DE10217870B4 - Non-volatile memory and method for reading the same - Google Patents

Abstract

Non-volatile memory with at least one memory cell (SZ) that can be addressed by means of word, bit and source lines for writing, reading and erasing, and with at least one evaluation device (AW) that is coupled to the memory cell (SZ) and when one is created Reading voltage to the bit line by detecting the current flowing through the memory cell (SZ) evaluates the content of the memory cell (SZ), characterized in that the evaluation device (AW) has a device (SE) through which the reading of the memory cell (SZ) in two steps are carried out so that the reading voltage is only present during the reading process.

Description

Non-volatile memory and method for reading the same The present invention relates to a nonvolatile Memory with at least one memory cell that is word, bit and source lines for writing, reading and erasing can be addressed and with at least one evaluation device which is connected to the memory cell is coupled and when applying a read voltage to the bit line by detecting the current flowing through the memory cell the content of the Evaluates memory cell. The invention further relates to a method to read this non-volatile Memory.

Non-volatile memories and methods to operate the same to write, read and delete Data has been known for a long time and is being used increasingly.

A conventional non-volatile Memory has a plurality of arranged in a memory cell array Memory cells that can be addressed by means of respective word, bit and source lines. Each memory cell has a selection transistor and a memory transistor on. The selection transistor is a "normal" field effect transistor, whose mode of action and function are known and no other explanation require. The memory transistor is a floating (connectionless) gate with a tunnel window field effect transistor, the Mode of operation and function due to widespread use are also known in memory cells and consequently none further explanation require. From the selection transistor is the source connection with a bit line, the Gate connection with a selection line and the drain connection with the drain connection of the memory transistor connected. From the memory transistor, the source connection is with a Source line, the control connection with a control line and the Drain  With the drain of the selection transistor connected. The selection line and the control line form together a so-called word line.

The state of a memory cell will represented by the threshold voltage of the memory transistor. The memory cell can have two different states, namely "programmed" or "deleted". In order to read out the state of the memory cell, the gate terminal of the selection transistor is brought up to a defined voltage. In the case of a programmed memory cell flows a drain current in the memory transistor, in the case of an erased memory cell no drain current can be measured in the memory cell. Any read access to a memory cell is therefore connected to a current flow.

This referred to as the cell stream Electricity essentially determines the reading speed and gives thus the necessary access time. Typical values are currently at approx. 20-30 μA.

Depending on the bit width of the Memory cell array increased the current consumption of the non-volatile memory in the case a read access. With a high bit width, e.g. B. 64 bit, dominates the Reading current even the total current consumption of the non-volatile Memory.

When reading a memory area sequentially the read voltages on the memory cell are held so long until the switch to the next Address takes place. This also applies if the reading process is already in progress before moving to the next one Address is complete. The one caused by the reading process In this case, current consumption remains constant, regardless of at what speed each individual memory cell is read becomes. The read voltage is the voltage that is applied to the control connection of the selection transistor is created. The term "sequential reading of a storage area" means several memory cells located in a word line in succession be read out.

Especially in the field of chip cards, where the energy and data transmission often contactless there are use cases in which the power consumption is strictly limited. To the power consumption To limit the maximum value, the clock frequency is targeted reduced. Since the current consumption caused by a reading process at the previous readout methods compared to the clock frequency does not vary, but the current caused by the reading process represents a significant proportion of the total power consumption this procedure for the area of contactless chip cards not suitable.

From the DE 196 00 288 A1 a semiconductor memory is known in which the reading current of a non-volatile memory cell is interrupted as soon as the reading result is available at the data output.

The object of the present invention therefore consists of a non-volatile memory as well Specify method for reading the same, which during a read operation has a reduced power consumption.

This task is accomplished by a non-volatile Memory with the features of claim 1 solved. The procedure for reading out of the non-volatile Memory is given in claim 10. Advantageous configurations each result from the dependent Claims.

In the non-volatile memory according to the invention, a memory cell is read out in two phases. In a first phase, the so-called precharge phase, the memory cell is not yet selected, during which the bit line is switched off value device is charged up to the reading voltage. In a second phase, the so-called read phase, the memory cell to be read is then selected so that the evaluation device can read out the content stored in the memory cell by detecting the read current. The evaluation device is deactivated immediately after the content has been read out.

The advantage of this procedure is in that the Reading voltage is only applied for exactly as long as the actual one Reading takes place. So the cell current only flows as long as is absolutely necessary for reading out. The charge consumption per read access is therefore constant and minimal. The non-volatile memory according to the invention is suitable is therefore particularly interested in use in chip cards, where the data and energy transfer done in a contactless manner.

To avoid an incorrectly read out date will during the precharging phase deactivates the evaluation device. This procedure avoids a while the precharging phase flowing charging current for charging a bit line capacitance as the date of the memory cell is interpreted. As long as the memory cell is not selected during the precharge phase is flowing No static even in the case of a programmed memory cell Current because the charging current after charging the bit line capacity up to "0" subsides.

It is also advantageous if deactivating the evaluation device immediately after reading, d. H. after recognizing the programmed state, the content the memory cell. By deactivating the evaluation device is the disconnection of the electrical connection to the at least to understand a memory cell. By disconnecting the electrical Connection becomes namely after the programmed state has been recognized, the flow of the Cell current prevented.

Deactivation is preferably carried out the evaluation device independently on the duration of the readout process. Deactivation takes place preferably only if the memory cell has a first logic Condition, e.g. Has "1". To deactivate the evaluation device independent of to be able to do the duration of the read-out process is preferably signal present at the output of the evaluation device as a control signal for the Deactivation used. As soon as the evaluation device determines has that Memory cell has a programmed state is on her Output connector on corresponding signal can be tapped. This in turn can again can be used to deactivate the evaluation device. Deactivation takes place regardless of how long the time period from the start of the reading process until the signal is picked up on Output port is.

The evaluation device preferably has a Sense Amplifier on. The device by which the reading of the memory cell in two steps or phases, is preferably between the sense amplifier and interconnect the memory cell and by the applied to the output terminal Controllable signal. The device can be in a switching element exist, which as a field effect transistor or any other Semiconductor switch can be formed.

In a preferred embodiment the invention provides that each bit line of the non-volatile Exactly one evaluation device is assigned to the memory.

The memory cell contains one Selection transistor and a memory transistor, their drain sections are interconnected. A memory cell is for storage exactly one data bit.

Using the following figures the invention becomes closer explained. Show it:

1 an embodiment of a non-volatile memory according to the invention,

2 one too 1 proper signal flow diagram,

3 a non-volatile memory known from the prior art and

4 one too 3 proper signal flow diagram.

A method known from the prior art for reading out a non-volatile memory is intended to be based on 3 and 4 are explained in more detail below.

3 shows a non-volatile memory with a memory cell and an evaluation device. The memory cell consists of a selection transistor T1, which is connected in series with a memory transistor T2. The drain connections of the selection and storage transistor are connected to one another. The source terminal of the selection transistor T1 is connected to a reference potential terminal BP in the exemplary embodiment shown. A control signal SGL can be applied to a control terminal ST1 of the selection transistor T1. The control connection ST1 is connected to a control line (not shown) and, together with a selection line connected to a control connection ST2 of the memory transistor T2, forms the aforementioned word line. The source connection of the memory transistor T2 is connected to the evaluation device AW, which is designed, for example, as a so-called “sense amplifier SA”. The evaluation device AW has an output connection AA. The data signal read from the memory cell can be tapped at this later. An in 3 shown charge memory C, which is connected between the memory cell and the evaluation device AW and a reference potential, sets parasitic component.

For the following explanations it is assumed that the erased State of the memory cell is represented by a cell current of 0μA, while the programmed state is represented by a cell current greater than 0μA becomes. A common one in practice Cell current is 30μA.

In the reading process customary in the prior art, the memory cell to be read in each case is selected until the next change of address. This means that a first logic state, V _SGL = high, is present at the control connection ST1. When reading sequentially via a word line, the control line connected to the control connection ST1 therefore remains permanently selected.

The sense amplifier SA applies a read voltage V _{BL to} the bit line for the entire duration of a readout period. At the beginning of the readout period (ZI2 in 4 ) a relatively high charge current I _{BL flows} until the charge store C, which is referred to as the bit line capacitance, is charged to the value of the read voltage V _BL .

In the case of a programmed cell, the charging current I _{BL changes} into the cell current and remains constant until the end of the readout period (end of the interval ZI3). Since the charging current is already interpreted by the sense amplifier SA as a cell current, the sense amplifier SA interprets the determined date during the entire readout period ZI2, ZI3 as a first logical value, here "1" or "high".

In the case of a deleted memory cell (ZI4, ZI5), the charging current, which is initially relatively high again at the beginning of the readout period (ZI4) until the bit line capacitance C is charged to the value of the read voltage, finally decays to 0μA. Only when the charging current has a reference value that is in 4 is denoted by the dashed line I _ref , _falls below the correct data "0" or "low" from the sense amplifier SA.

The access time, i.e. the time from Beginning of the readout period until reliable detection of the in the memory cell stored date, is consequently by reading out a deleted memory cell certainly.

1 shows a non-volatile memory according to the invention. In 1 a single memory cell with a selection transistor T1 and a memory transistor T2 is shown merely by way of example. The construction corresponds to that 3 , so that no further description is given here. The path formed by the load paths of the selection transistor T1 and memory transistor T2 is referred to as the bit line. The source connection of the memory transistor T2 is connected to an evaluation device AW.

The evaluation device AW has a sense amplifier which is basically identical to that in FIG 1 shown arrangement can be. Furthermore, a switching element SE is provided, which is located between the sense amplifier SA and the source terminal of the memory transistor T2. The switching element SE can be used as a semiconductor switch, for. B. as a field effect transistor.

The evaluation device AW has an output terminal AA which is identical to the output of the sense amplifier: On the output terminal AA a DATA signal can be tapped. This signal DATA gives after reading out a memory cell, the value stored in it again.

With the output connector is AA a control connection of the Switching element SE connected. The one present at the output connection AA Signal DATA thus determines whether the switching element SE is closed or open condition.

Between a reference potential connection BP and a node between the source of the memory transistor T2 and the switching element SE is connected to a charge storage C, the just a parasitic Representing device and is referred to as bit line capacitance.

The reading of the non-volatile according to the invention Storage takes place in two phases: The first phase is called the precharge phase or Precharge phase, the second phase as a read or sense phase.

The memory cell is not yet selected in the precharge phase. The signal SGL present at the control connection ST1 of the selection transistor T1 thus has a first state "0". During the precharge phase (in 2 denoted by ZI2), the sense amplifier SA charges the bit line up to the read voltage V _BL . The output of the sense amplifier SA is deactivated, so that no signal can be tapped at the output connection AA. By deactivating the sense amplifier, a misinterpretation of the charging current as the date of the memory cell is avoided. Since the memory cell is not selected during the precharge phase, no static current flows through the sense amplifier even in the case of a programmed memory cell. This means that after the charge store C has been charged to the read voltage V _BL , the charge current I _BL decays to the value “0”. The switching element is closed for the entire duration of the precharge phase, ie there is an electrical connection between the sense -Amplifier SA and the memory cell.

In the read phase, the memory cell is selected by applying a control signal SGL to the control terminal ST1 of the selection transistor T1. The reading phase is in 2 designated with the time intervals ZI3, ZI5, ZI7. In the case of a deleted cell (ZI5), the cell current remains “0”. In the case of a programmed cell (ZI3), a cell current I _{BL flows} and the sense amplifier SA supplies the correct data “1”. This data can be tapped at the output connection AA ,

Immediately after the concern of this Da At the output connection AA, that is to say after the cell state has been recognized, the sense amplifier SA is deactivated by opening the switching element SE, that is to say disconnected from the bit line. The read data "1" at the output connection AA is thus directly the indicator for the completed reading process and causes the respective sense amplifier SA to be switched off individually for each bit line. This process is therefore completely self-controlling and independent of physical parameters such as bit line capacity, temperature, etc.

Since switching off immediately after the programmed state of the memory cell is recognized, the current flow through the memory cell is limited to the minimum necessary time. This is, as from the above emerges independently on the duration of the reading. The procedure according to the invention has the advantage on that the average power consumption by choosing the clock frequency now is scalable and can be reduced to arbitrarily small values.

AW

evaluation

SA

Sense Amplifier

T1

Auwahltransistor

T2

memory transistor

ST1

control terminal

ST2

control terminal

SE

switching element

C

(Parasitic) charge storage

AA

output terminal

IBL

electricity

VBL

tension

DATA

output

SGL

control signal

SZ

memory cell

BP

Reference potential connection

Claims (14)

Non-volatile memory with at least one memory cell (SZ) that can be addressed by means of word, bit and source lines for writing, reading and erasing, and with at least one evaluation device (AW) that is coupled to the memory cell (SZ) and when one is created Reading voltage to the bit line by detecting the current flowing through the memory cell (SZ) evaluates the content of the memory cell (SZ), characterized in that the evaluation device (AW) has a device (SE) through which the reading of the memory cell (SZ) in two steps are carried out so that the reading voltage is only present during the reading process. Memory according to claim 1, characterized in that the evaluation device (AW) the length of time during controls the reading voltage itself. Memory according to claim 1 or 2, characterized in that the evaluation device (AW) an output connector (AA) on which the content of the read-out memory cell (SZ) corresponding signal can be tapped, and the device (SE) with the output connector (AA) is coupled. Memory according to one of the preceding claims, characterized in that the Evaluation device (AW) has a sense amplifier (SA). Memory according to claim 4, characterized in that the device (SE) between the sense amplifier (SA) and the memory cell (SZ) is interconnected and by the applied to the output connection (AA) Signal can be controlled. Memory according to one of the preceding claims, characterized in that device (SE) is a switching element. Memory according to one of the preceding claims, characterized in that everybody An evaluation device (SA) is assigned to the bit line. Memory according to one of the preceding claims, characterized in that the Memory cell (SZ) a selection transistor (T1) and a memory transistor (T2) contains whose drain sections are connected to each other. Memory according to one of the preceding claims, characterized in that a Memory cell is designed for storing a data bit. Method for reading a non-volatile memory after a of the preceding claims, in which - in a precharge phase (ZI2, ZI4, ZI6) the bit line through the evaluation device (AW) is charged up to the read voltage, the memory cell to be read out (SZ) remains unselected, - in a read phase (ZI1, ZI3, ZI5, ZI7) the memory cell to be read (SZ) is selected so that the evaluation device can read the content stored in the memory cell (SZ), - the evaluation device (AW) is deactivated after reading the content. A method according to claim 10, characterized in that the deactivation the evaluation device (AW) during the precharge phase (ZI2, ZI4, ZI6) takes place. A method according to claim 10 or 11, characterized in that this Deactivate the evaluation device (AW) immediately after reading the content of the memory cell (SZ). Method according to one of the preceding claims, characterized characterized that the Deactivating the evaluation device (AW) regardless of the duration of the Readout takes place. Method according to one of the preceding claims 10, characterized in that the deactivation the evaluation device (AW) only takes place if the memory cell has a first logic state.