DE10213545B4 - Method for producing an SOI field effect transistor and SOI field effect transistor - Google Patents

Abstract

A method of fabricating a fully depleted thin film SOI field effect transistor having predetermined transistor characteristics, wherein
A laterally limited layer sequence with a gate insulating layer and a gate region is formed on an approximately undoped body of a thickness of less than 20 nm;
A spacer layer with a predetermined thickness is formed on at least a part of the side walls of the laterally limited layer sequence;
• by introducing dopant into two surface areas next to the approximately undoped body, to which the spacer layer adjacent, two source / drain regions are formed with a given dopant concentration profile, wherein the layer sequence and the spacer layer so arranged are that they form a shading structure for avoiding the introduction of dopant into the approximately undoped body between the two source / drain regions;
Wherein preset transistor properties of the fully depleted thin film SOI field effect transistor are adjusted by adjusting the thickness of the spacer layer and adjusting the dopant concentration profile.

Description

The The invention relates to a method for producing an SOI field effect transistor and an SOI field effect transistor.

For many Applications of silicon microelectronics become field effect transistors needed.

In circuit technology, it is often desirable to have several different n-MOS transistors and several different p-MOS transistors with different threshold voltages in modern CMOS processes (so-called multi-V _T technique, where V _T for the threshold voltage of the transistor stands). For certain applications, it may be necessary to have transistors with a particularly high switching speed, whereas in other applications a minimum leakage current of the transistor is desired. If the multi-V _T technique is combined with the use of different supply voltages V _{DD of} an integrated circuit (multi-V _DD / V _T technique), then depending on the switching activity of a particular transistor of an integrated circuit, the optimum voltage swing can be selected To achieve the largest possible increase in the gate voltage V _DD -V _T. Examples of transistors with such requirements are transistors in clock circuits with high switching activity, low voltage swing and a low threshold voltage. For a transistor in a clock circuit, due to the high activity, the leakage current is of less relevance, whereas the minimization of the dynamic power dissipation (which depends on the square of the supply voltage V _DD ) is of primary interest. In contrast, in logic circuits with lower activity (for example, less than 30%), the static power dissipation due to electrical leakage currents in the off state of greater relevance, so that here transistors with higher threshold voltage are advantageous. In order not to degrade the switching speed in the active state (the switching time t _D is proportional to 1 / [V _DD -V _T ]) and to avoid an undesirable reduction of the gate voltage overshoot, the supply voltage V _{DD of} the logic block is increased accordingly ,

An overview of the multi-V _DD / V _T circuit technology, in particular with regard to conventional CMOS technology, can be found, for example, in [1].

One central problem is conventional integrated circuits the increasing degradation of the electrical properties of MOS transistors ("Metal-Oxide-Semiconductor") with increasing Structural fineness, that is Miniaturization. Cause for this are for example the punch-through effect, the latch-up effect as well as in proportion to transistor size disproportionately strong growing parasitic capacity between the drain / source region and the substrate. As punch-through effect is an unwanted current penetration between adjacent transistors of a transistor arrangement. As a latch-up effect is the phenomenon known that a p-type transistor and a transistor of the n-type conductivity when falling below a minimum distance from each other a parasitic Can form a thyristor, at which a high ignition current can flow a local destruction can cause an integrated semiconductor device.

at the SOI technology ("Silicon-on-Insulator"), in which a silicon layer on a silicon oxide layer on a silicon substrate as a base material are used to form an integrated circuit are alleviated the problems described. Especially when using a silicon thin film (for example, a thickness of 20nm) on an electrically insulating silicon oxide layer, the be alleviated problems described.

Further may be the problem when using a doped substrate that due to technologically conditioned local variations of the dopant concentrations a variation of the threshold voltage at different transistors an integrated circuit occurs. This problem is with Use of an undoped substrate avoided.

used but a thin one undoped silicon layer as a base layer for forming a Field effect transistor, so it is not possible, the threshold voltage the field effect transistor by adjusting the doping of Change channel area. In this case, the threshold voltage of a field effect transistor by setting the work function of the material of the gate region become. In this case is for Each type of transistor (low-power transistor or high-power transistor, p-MOS transistor or n-MOS transistor) each require a separate gate material, wherein by means of selecting of the gate material, the threshold voltage of the respective transistor is defined.

However, for technological reasons, the free choice of materials of the gate regions of different transistors of an integrated circuit may be restricted. Furthermore, it is complex and therefore expensive, in a method for producing an integrated circuit with different transistors different gate Ma materials.

Especially in a CMOS technology with dimensions below 50nm Thin-film SOI transistors ("Silicon-on-Insulator") interesting. As For example, in [2] are addressed, given the high component diversity several different types of transistors for the logic in existing ones Processes of 130nm technology required. In the case of three different transistor types with different threshold voltages (high threshold voltage, medium threshold voltage, low threshold voltage) as well as with two different types of charge carriers (n-type MOS transistor, p-MOS transistor) result in a total of six different Materials for the gate area. An associated Thin-film SOI-CMOS process required therefore a very high process cost.

In current CMOS technologies, the threshold voltage of the field effect transistors used there is usually adjusted by doping the channel region. Such implantations include forming light-doped-drain (LDD) regions, performing pocket doping (localized doping of the region between the source / drain regions and in the channel region, respectively, thereby increasing the sensitivity of the device) Transistors to technologically induced variations in the length of the gate region is reduced as well as the formation of a retrograde well (vividly a highly doped region in the interior of the substrate between the source / drain regions.) However, these implants are subject to technological variations, which is undesirable Furthermore, especially with completely depleted thin-film SOI transistors, especially with technology nodes with structural dimensions of less than 50 nm, this method for setting the threshold voltage is no longer applicable because the doping-dependent contribution to the threshold voltage V _T ^{dot is} proportional to q · N _A t _Si . In this case, t _Si denotes the thickness of the silicon layer, N _A denotes the dopant concentration in the channel region, and q denotes the electrical elementary charge. For t _Si <20nm and N _A <10 ¹⁶ cm ^-3 , V _T ^dot hardly has any influence on the threshold voltage.

The Alternative for setting the threshold voltage by means of targeted Doping involves the use of multiple different gate materials for transistors with different threshold voltages as well as different conductivity types. However, there are currently no thin-film SOI-CMOS processes, the formation of MOS transistors allow with different threshold voltages.

A possibility for adjusting the transistor properties in SOI technology is the use of transistors with different lengths of the Gate area, as well as the length of the gate area a significant Influence on the threshold voltage of a field effect transistor has. A sufficiently precise adjustability of the threshold voltage of transistors by adjusting the length of the gate region sets a sufficiently good resolution Masking technique ahead.

In 1A is an SOI field effect transistor 100 a technology with a minimum achievable structural dimension of F = 150nm shown. The SOI transistor 100 has a silicon substrate 101 , one on the silicon substrate 101 arranged silicon dioxide layer 102 and one on the silicon dioxide layer 102 arranged undoped silicon layer 103 on. The layers 101 to 103 form an SOI layer. In a first surface area of the undoped silicon layer 103 is a first source / drain region 106 implanted in a second surface area of the undoped silicon layer 103 is a second source / drain region 107 implanted. An area between the two source / drain areas 106 . 107 the undoped silicon layer 103 forms the channel area 108 , In 1A is the lateral extent of the gate region 104 determined by the smallest structure dimension F = 150nm achievable in the technology generation. A typical value for inaccuracy in structuring is in 1A denoted by ΔF. With the currently existing best structuring methods (electron beam lithography), an accuracy of approximately ΔF = ± 20 nm can be achieved.

In 1B is a field effect transistor 110 a technology generation in which the minimum achievable structural dimension F = 50nm. Assuming the currently best achieved triggering ΔF = 20nm, it can be seen that with conventional masking techniques at target technology generations of 50nm and less, the uncertainty in the mask's accuracy is too great to adequately control the gate area length or accuracy. to set the length of the channel area. The relative accuracy in setting the length of the gate region in a technology generation with F = 50nm and uncertainty ΔF = 20nm is 40%.

Therefore, as the structure dimensions of conventional masking techniques continue to decrease, the threshold voltage of a transistor can not be adjusted by adjusting the length of the gate region with satisfactory accuracy. In addition, the cost of using masks is very large. Furthermore, the manufacturing time of transistors in fine becoming masks in more to.

[3] discloses a method for adjusting a threshold voltage for a semiconductor device on an SOI substrate in which after the formation of a gate structure a threshold voltage adjustment implantation is performed, to reduce the diffusion of implanted dopant.

[4] discloses an overview of silicone-on-insulator devices and theirs Special features, taking, inter alia, the properties of completely impoverished and partially depleted SOI field effect transistors is received. It is further stated that the threshold voltage of SOI transistors, for example by a on the back applied voltage or by driving auxiliary transistors can be influenced.

[5] discloses a semiconductor device in which at an edge portion a field shield gate electrode under a sidewall oxide layer a field shield gate oxide layer is thicker. Furthermore, a Procedure for the production of a semiconductor device with a field shield insulation structure discloses in which an SOI layer in an NMOS transistor generation region and a PMOS transistor generation region is divided.

[6] discloses an SOI device and a method for its manufacture, where the effect of a potential-free body is reduced is. While of the method become a first gate electrode on a semiconductor layer for an NMOS transistor and a second gate electrode for a PMOS transistor is formed, wherein the gate electrodes made of doped polysizilium become.

[7] discloses a method of fabricating bipolar transistors and MOS transistors on a thin film SOI substrate. at The method is an SOI wafer in a bipolar transistor region and dividing a MOS transistor region becomes a bipolar transistor formed in the bipolar transistor region, and MOS transistors are formed in the MOS transistor region.

Of the The invention is based on the problem of creating a possibility Transistor property of an SOI field effect transistor with sufficient accuracy and reasonable effort to adjust.

The Problem is solved by a method of fabricating a fully depleted thin film SOI field effect transistor with definable transistor properties and by a completely depleted Thin-film SOI field effect transistor with definable transistor characteristics with the features according to the independent claims.

According to the inventive method for Make a complete depleted thin film SOI field effect transistor with definable transistor properties becomes a laterally limited layer sequence with a gate insulating layer and a gate region on one nearly undoped body formed a thickness of less than 20 nm. Furthermore, at least on a part of the side walls of the laterally limited Layer sequence a spacer layer with a predetermined thickness educated. About that In addition, by incorporating dopant into two surface areas next to the approximate undoped body to which the spacer layer abuts, two source / drain regions formed with a given dopant concentration profile, wherein the layer sequence and the spacer layer are set up in this way are that they have a shading structure to avoid the introduction of dopant in the approximate Undoped body between the two source / drain areas form. By adjusting the thickness of the spacer layer and by means Adjusting the dopant concentration profile will be default Transistor properties of the fully depleted thin film SOI field effect transistor set.

Of the Fully depleted thin film SOI field effect transistor according to the invention with definable transistor properties has a laterally limited Layer sequence with a gate insulating layer and a gate region on an approximate undoped body of a thickness of less than 20 nm. Furthermore, the Completely depleted thin film SOI field effect transistor a spacer layer of a predetermined thickness on at least one Part of the side walls the laterally limited layer sequence and two source / drain regions in two surface areas next to the almost undoped Body, which adjoins the spacer layer, with a predeterminable Dopant concentration profile. The layer sequence and the spacer layer are arranged to provide a shading structure for Avoiding the introduction of dopant in the approximately undoped Body between the two source / drain areas during the Manufacturing the complete depleted thin film SOI field effect transistor form. By adjusting the thickness of the spacer layer and by means Adjusting the dopant concentration profile will be default Transistor properties of the fully depleted thin film SOI field effect transistor set.

A basic idea of the invention is to specify a transistor characteristic (eg, the threshold voltage) of an SOI field effect transistor by adjusting the thickness of a sidewall spacer layer and adjusting the dopant concentration profile of the source / drain regions. According to the invention, it is possible to define the length of the gate region by means of a deposition method with an accuracy in the Angstrom range. Problems known from the prior art (eg fluctuations in the dopant concentration in the substrate, complicated use of a multiplicity of different gate materials, etc.) are avoided.

It is possible according to the invention to form a circuit arrangement on an SOI substrate at the different transistors with different transistor properties (e.g., different threshold voltages for high power and low power applications, respectively) are formed by placing a spacer layer on a lateral limited layer sequence of gate region and gate insulation Layer are applied. In a subsequent doping acts the Arrangement of laterally limited layer sequence and spacer layer as shading structure and prevents doping of the area between the source / drain regions. Because the length of the channel area is immediate depends on the thickness of the spacer layer is an exact setting of transistor properties associated with these geometric properties correlated allows.

Especially It should be noted that using a deposition process (e.g. Atomic Layer Deposition) for forming the spacer layer whose thickness is set with an accuracy of a few Angstrom whereas the accuracy of a masking technique in the orders of magnitude of 20nm lies. This is a much improved adjustability the gate length realized according to the invention. The range of underdiffusion of dopant in the undoped Channel area is by adjusting the thickness of the spacer layer and the parameter of doping (type of dopant, selecting and setting the parameter of the doping method) controllable.

The Depositing a spacer is more cost effective than using a finer one Masks.

at the method according to the invention is using more than two different materials (p-type, n-type) for avoided the gate areas. For any desired Thickness of a spacer layer is merely an additional mask required to form a field effect transistor with a given Establish threshold voltage. When using an impoverished, that means undoped silicon layer, in which the transistor is integrated, are complex implants in the channel area (LDD areas, pocket doping, retrograde trough) dispensable.

An undoped substrate is used so that the problems associated with conventional CMOS technologies are avoided due to a statistically varying dopant concentration. Also, a complex doping process is avoided. A (substantially) undoped substrate may also be considered as having a dopant concentration that is significantly less than a dopant concentration typically 10 ¹⁹ cm ^-3 used in conventional CMOS technology.

preferred Further developments of the invention will become apparent from the dependent claims.

The given transistor property can be the length of the channel area between the two source / drain regions, the threshold voltage, the leakage current characteristic, be the maximum current or a transistor characteristic. The transistor property can according to the invention by means Adjusting the dopant concentration profile or by adjusting the thickness of the spacer layer can be adjusted.

The Thickness of the spacer layer can be adjusted by the spacer layer using a chemical vapor deposition method (CVD method, "Chemical Vapor Deposition ") or an atomic layer deposition method (ALD method) becomes. In particular, in the ALD method, it is possible a Thickness of a layer to be deposited to the accuracy of one Atomic layer that means set exactly to a few Angstrom. The high accuracy in adjusting the thickness of the spacer layer causes a high accuracy in setting the transistor characteristic.

The both source / drain regions are preferably used an ion implantation process or a diffusion process, wherein the dopant concentration profile is selected by selecting the Type, concentration and / or diffusion properties of Dopants is set.

The Transistor characteristics of the SOI field effect transistor may alternatively by selecting the Material of the gate area, the dopant concentration of the substrate and / or the dopant profile of the substrate.

As a result, other parameters are available, by means of which the transistor properties are adjustable.

Especially For example, the dopant profile of the substrate can be determined using a Pocket doping and / or Retrograde tub can be adjusted.

Further a second SOI field effect transistor according to the inventive method for Producing the SOI field effect transistor be formed on and / or in the substrate, wherein the transistor properties of the second SOI field effect transistor different from those of the SOI field effect transistor can be adjusted. Such a necessity can be e.g. in a semiconductor memory, given the requirements to transistors in the logic region of a memory or in the Memory area of a memory are very different.

The different transistor properties of the SOI field effect transistor and the second SOI field effect transistor preferably result solely from a different thickness the spacer layer. In other words, for the transistors in particular the same with different transistor properties Gate material can be used, resulting in significantly simplified processing entails.

Further For example, a third SOI field effect transistor according to the method of manufacturing of the SOI field effect transistor formed in and / or on the substrate be, wherein the transistor characteristics of the third SOI field effect transistor be set analogous to those of the SOI field effect transistor. The line types of the SOI field effect transistor and the third SOI field effect transistor complementary to each other. In other words, according to the invention, both a p-MOS transistor and an n-MOS transistor can be formed.

This wear that needs the silicon microelectronics bill, transistors of both conductivity types to have an integrated circuit.

The Gate regions of the SOI field effect transistor and the second SOI field effect transistor or the SOI field effect transistor, the second SOI field effect transistor and the third SOI field effect transistor can be made of the same material. This simplifies the Litigation and reduces costs.

The material of the gate regions preferably has a work function value substantially equal to the arithmetic mean of the work function values of highly p-doped polysilicon (p ⁺ polysilicon) and heavily n-doped polysilicon (n ⁺ polysilicon) , In this case, one speaks of a so-called "mid-gap" gate. N ⁺ polysilicon has a work function of about 4.15 eV (electron volts), p ⁺ polysilicon has a work function of about 5.27 eV Therefore, a n-type field-effect transistor as well as a p-type field-effect transistor is suitable as a gate material with a band gap between the two mentioned values, for example tungsten, tantalum, titanium nitride or p ⁺ -doped germanium.

Further Preferably, the material of the gate region has a work function between 4.45eV and 4.95eV.

Preferably become the transistor properties of the SOI field effect transistor and the second SOI field effect transistor set such that one of the two SOI field effect transistors to a low leakage current and the other to a low threshold voltage is optimized. So it is for advantageously allows a transistor in a clock circuit that this on one. high switching speed and therefore to one low threshold voltage is optimized. In contrast to simple Way a transistor in a memory area set up such be that he sustained stored information permanently and therefore has a lower leakage current.

Further can according to the method of the invention at least one SOI field effect transistor as a vertical transistor, as a transistor with at least two gate terminals (double gate transistor) or be designed as Fin-FET (fin field effect transistor). The principle of the invention is basically applicable to all types of transistors.

According to the inventive method can Furthermore, the second SOI field effect transistor during the formation of the source / drain regions of the SOI field effect transistor by means of a protective layer in front of a Doping protected become. Alternative or supplementary For example, the SOI field effect transistor may be formed during formation of the source / drain regions of the second SOI field effect transistor be protected by a protective layer from doping.

At least one of the SOI field-effect transistors can be at least one additional Spacer layer on the spacer layer have. In other words, it is possible form a plurality of spacer layers on each other, wherein the properties of the associated Transistors essentially by the total thickness of the majority of defined spacer layers is defined.

The inventive method is both applicable to gate-connected thin-film lateral SOI transistors as well as to dual-gate MOSFETs, planar transistors, vertical transistors, or fin-FET type transistors.

Furthermore, the method can be easily applied to a technology with different thicknesses of gate insulating layers. In this case, the component diversity is extended by transistors with different thickness gate-insulating layers (thickness t _ox ) (so-called multi-V _DD - / V _T - / t _ox -Technik).

According to the invention is at a given source / drain doping (predefinable is the doping method, the dopant concentration, the dopant, etc.) and a fixed metallurgical length of the Gate area, the thickness of the spacer layer varies. takes a source / drain doping profile with a spatial Decrease ΔN / Δy of the dopant concentration N depending on Dop point y of 5nm per decade (logarithmic), so is the effective Length of the Channel area in the SOI field effect transistor with undoped Silicon substrate of length of the undoped silicon region, by adjusting the Length of Source / drain doping foothills adjustable. With a thin one Spacer layers protrude sufficiently well into the source / drain dopant tails Channel area, which shortens the effective channel length. This has different electrical properties of the transistors As a result, the sub-threshold voltage and other short-channel effects such as the off-current dominant gate induced drain leakage (GIDL) are influenced. A transistor with a thicker spacer has therefore unchanged metallurgical gate length a higher one Threshold voltage and lower leakage current (off-current) and a lower maximum current (on-current) than a transistor with a thinner spacer.

A essential idea of the invention is the simplified setting and optimization of transistor parameters by means of precise definition a spacer layer laterally independent of the gate region the quality an optical mask. Also the setting of the doping properties has a significant Influence on the threshold voltage.

It It should be noted that embodiments of the method for forming an SOI field effect transistor with specified transistor properties also for the inventive SOI field effect transistor be valid.

embodiments The invention is illustrated in the figures and will be discussed below explained in more detail.

It demonstrate:

1A a field effect transistor according to the prior art, whose transistor properties are defined by means of setting a mask,

1B another field effect transistor according to the prior art, whose transistor properties are defined by means of setting a mask,

2A 12 is a schematic view showing the relationship between gate length, channel length, spacer layer thickness and dopant profile of a field effect transistor for a low power application;

2 B 12 is a schematic view showing the relationship between gate length, channel length, spacer layer thickness and dopant profile of a field effect transistor for a high power application;

3A a diagram showing input characteristics of a field effect transistor for low-power applications,

3B a diagram showing output characteristics of a field effect transistor for low-power applications,

4A a diagram showing input characteristics of a field effect transistor for high power applications,

4B a diagram showing output characteristics of a transistor for high power applications,

5A to 5D Layer sequences at different times during a method for producing an SOI field effect transistor with predeterminable transistor properties according to a first exemplary embodiment of the invention,

6A to 6D Layer sequences at different times during a method for producing a SOI field effect transistor with predeterminable transistor properties according to a second embodiment of the invention,

7 a layer sequence according to an alternative for forming spacer Schich according to the invention,

8A a double gate field effect transistor,

8B a fin field effect transistor,

8C a vertical field effect transistor.

in the Further components are those in different embodiments are identical, provided with the same reference numerals.

In the following, reference is made to 2A . 2 B the relationship between the length of the channel region of a field effect transistor, the length of the gate region or the gate insulating layer, the thickness of a spacer layer and the dopant concentration profile described.

In 2A For example, for a field effect transistor for low power applications (high threshold voltage, low leakage current) along the horizontal axis, an array of layer components is shown, whereas along the vertical axis in logarithmic representation the location dependence of dopant concentration is shown. It is believed that in a surface region of a silicon layer in which the source / drain regions of the field effect transistor are implanted, the dopant concentration decreases exponentially from the outside of the spacer layer into the channel region. It is assumed that the dopant concentration decreases continuously from outside to inside at intervals of 5 nm each by one order of magnitude. Under this premise, a 25nm spacer layer is required to produce a drop in doping concentration of the source / drain region of 10 ²¹ cm ^-3 to a concentration of 10 ¹⁶ cm ^-3 (this corresponds to an approximately undoped substrate).

In 2A are the spacer layers 201 . 202 at the left or right side edge of the gate area 203 shown. The two spacer layers 210 . 202 have a thickness of 25nm each. The gate area is in the uppermost representation of 2A a width G = 100nm. As a result of the adjusted spatial dependence of the dopant concentration, the length of the channel region L = 100 nm is equal to the length of the gate region G = 100 nm. The first source / drain region 204 and the second source / drain region 205 are each formed from those areas of the silicon layer 206 located below the corresponding spacer layer 201 . 202 lie, and by the left or right of it arranged area with a high dopant concentration.

As in 2A show the first source / drain region 204 and the second source / drain region 205 two subsections each. In this case, the respective outer section corresponds to a region of the substrate 206 that by covering with one of the spacer layers 201 respectively. 202 is free and has a substantially homogeneous dopant concentration. By contrast, that of one of the spacer layers 201 respectively. 202 covered first and second source / drain portion of a highly location-dependent (according to the schematic representation of 2A exponentially location-dependent) dopant concentration.

As in the diagrams 210 . 220 . 230 . 240 By selecting a correspondingly smaller length of the gate region G, a smaller length of the channel region L can also be achieved. However, the length of the channel region L is also dependent on the thickness of the spacer layers 201 . 202 as well as the spatial decrease of the dopant concentration (here by a decade per 5nm) dependent. Therefore, in particular, by selecting the dopant concentration and the thickness of the spacer layers 201 . 202 a low energy field effect transistor with desired length of the channel region and a correspondingly high value of the threshold voltage can be formed. In other words, with a 25nm thick spacer layer, with a drop in dopant concentration of 5nm per decade, a field effect transistor for low power applications is achievable where the length of the gate region is the length of the channel region.

In contrast, it is in the in 2 B schematically shown transistor for high performance applications, that the length of the channel region is sufficiently low to achieve a small threshold voltage and therefore a short switching time. The thickness of the spacer layers 201 . 202 are in the diagrams 250 . 260 . 270 . 280 out 2 B each chosen with a thickness of 10nm. For the decrease of the dopant concentration the same assumption is made as in 2A , Like in diagram 250 shown results due to the under-diffusion at both edge regions of the gate region 203 a region of 15nm thickness below the gate region where there is a dopant concentration greater than 10 ¹⁶ cm ^-3 . The length of the channel region L is therefore in the cases of the diagrams 250 . 260 . 270 . 280 compared to the length of the gate region L by 2 · 15nm = 30nm reduced. By choosing the width of the spacer layers 201 . 202 Therefore, for a given length of the gate region, the length of the channel region is adjustable.

Out 2R . 2 B In particular, it can be seen that the under-diffusion at smaller who Denden gate lengths G increasingly strongly affects the transistor properties, so that in particular in future technology generations a very sensitive possibility for influencing transistor properties is created.

In the following, reference is made to 3A . 3B Characteristics of a field effect transistor for low-power applications with a gate length of 100nm and a channel length of 100nm described. This corresponds to a configuration as shown in the diagram 200 out 2A equivalent.

In diagram 300 out 3A is along the abscissa 301 the voltage between the gate region and the source region (first source / drain region) is plotted in volts. Along the ordinate 302 is plotted in a logarithmic representation of the electric current I _D in amperes at the drain region (second source / drain region). In 3A is a first turn 303 plotted corresponding to a voltage V _DS between the two source / drain regions of 1.2V. Furthermore, the curve corresponds 304 a voltage V _DS = 0.6V. It should be noted that both plotted curves 303 . 304 By way of example only, any other voltage may be applied between the source / drain regions. In the 3A Plotted curves are referred to as input characteristics of the field effect transistor.

The in the diagram 310 out 3B drawn third and fourth curves 313 . 314 are output characteristics of the field effect transistor for low power applications with a gate length of 100nm and a channel length of 100nm. Along the abscissa 311 For example, the voltage between the two source / drain regions V _{DS is} plotted in volts, whereas along the ordinate 312 in 3B the electric current is applied to one of the source / drain regions (drain region) I _D in amperes. The third turn 313 corresponds to a voltage between the first source / drain region (source region) and the gate region V _GS of 1.2V. In contrast, the fourth curve corresponds 314 a voltage V _GS = 0.6V.

In the following, reference is made to 4A Input characteristics and referring to 4B Output characteristics of a field effect transistor for high performance applications with a gate length of 100nm and a channel length of 70nm described.

In diagram 400 out 4A transistor characteristics are plotted for different electrical voltages between the two source / drain regions V _DS . Along the abscissa 401 For example, the voltage between the source region (first source / drain region) and the gate region is plotted in volts, whereas along the ordinate 402 of the diagram 400 the electric current is applied logarithmically to one of the two source / drain regions (drain region) I _D in amperes. A first turn 403 corresponds to a voltage between the two source / drain regions V _DS = 1.0V, whereas a second curve 404 a voltage V _DS = 0.3V corresponds.

In 4B are output characteristics of the field effect transistor off 4A applied. Along the abscissa 411 of the diagram 410 the voltage between the two source / drain regions V _{DS is} plotted in volts, whereas. along the ordinate 412 the current is applied to one of the two source / drain regions I _D in amperes. A third turn 413 shows a characteristic corresponding to a voltage between the gate region and the first source / drain region (source region) V _GS = 1.0V, whereas the fourth curve 414 a voltage V _GS = 0.3V corresponds.

Like a comparison between 3A and 4A or between 3B and 4B shows, the transistor characteristics as transistor properties by application of different thickness spacer layers are sensitive adjustable. The shown input and output characteristics of the transistor with 100nm gate length as a low energy variant with a channel length of 100nm (spacers of thickness 25nm) and once as a high performance variant with a channel length of 70nm (spacers of thickness 10nm) shows significant differences. All other parameters of these transistors are identical.

The dopant concentration of the silicon layer 206 each is 10 ¹⁶ cm ^-3 , the thickness of the gate insulating layer is 2nm (silicon dioxide), the vertical thickness of the silicon layer 206 is 10nm and the gate material is p ⁺ -doped germanium.

In the following, reference is made to 5A to 5D a method for producing an SOI field effect transistor with predetermined transistor characteristics according to a first embodiment of the invention described. In 5A to 5D For example, on the left side, a low-threshold, high-leakage, high-performance field effect transistor is shown, and on the right-hand side, a high-threshold, low-leakage transistor, low power low-power transistor.

In 5A are layer sequences 500 . 510 shown that correspond to a partially manufactured transistor in SOI technology. The layer sequences 500 . 510 are on the same SOI substrate 501 out a silicon substrate 502 , a silicon dioxide layer 503 and a silicon layer 504 processed. One in the left half of 5A shown first laterally limited layer sequence is made of a first gate insulating layer 505 and from a first gate area 506 built up. Furthermore, a first TEOS protective layer is on the side walls of the first laterally limited layer sequence 507 (Tetra Ethyl Ortho Silicate) applied. This serves for the electrical and mechanical decoupling of the first laterally limited layer sequence from the environment. One in the right half of 5A shown second laterally limited layer sequence is made of a second gate insulating layer 511 , a second gate area 512 and a second TEOS protective layer 513 built up.

To the in 5B shown layer sequences 520 . 530 to receive, according to 5B right area with a photoresist layer 531 in order to further process only the in 5B to enable the layer sequence shown on the left. In a further process step, n-type conductivity doping atoms are formed into two surface areas of the silicon layer using an ion implantation process 504 implanted around two source / drain areas 521 . 522 in the left half of 5B to obtain shown transistor with low threshold voltage. Implantation ions are due to photoresist coverage 531 before entering the surface area of the SOI substrate 501 protected in the right half of 5B is shown.

To the in 5C shown layer sequences 540 respectively. 550 is first obtained using a suitable etching method of photoresist 531 away. In a further step, a spacer layer is respectively formed on the side walls of the first and second laterally delimited layer sequences 541 respectively. 551 formed with a predetermined thickness, which is done using the ALD method (Atomic Layer Deposition). With the ALD method, the thickness of the spacer layer "d" to a precision of an atomic layer, that is, down to a few Angstrom, specifiable.

To the in 5D shown layer sequences 560 . 570 to receive, first on the layer sequence 540 another photoresist layer 561 deposited to shield the associated surface area of the SOI substrate from further processing. The following will be in that of the further photoresist layer 561 free surface area of the SOI layer sequence 501 by introducing dopant atoms of the n-type conductivity into two surface regions of the silicon layer 504 near the sidewalls of the second spacer layer 551 a third and a fourth source / drain region 571 . 572 formed with a given dopant concentration profile. The second laterally limited layer sequence and the second spacer layer 551 are arranged to have a shading structure for avoiding introducing the n-type conductivity dopant into surface areas of the silicon layer 504 between the third and fourth source / drain regions 571 . 572 form. By adjusting the thickness "d" of the second spacer layer 551 and by adjusting the dopant concentration profile in forming the third and fourth source / drain regions 571 . 572 be the transistor properties of the right in the area of 5D defined SOI field effect transistor defined. As a method of implanting the dopant atoms in the third and fourth source / drain regions 571 . 572 the ion implantation method is used. By adjusting the Dotierstoffatomart, the energy of the doping atoms and other process parameters, the dopant concentration profile of the third and fourth source / drain region 571 . 572 be specified.

The SOI field effect transistor in the left part of 5D has a channel region with a smaller length than that in the right part of 5D shown SOI field effect transistor. The length of the channel region of the left SOI field effect transistor is approximately 2d smaller than in the case of the right SOI field effect transistor, since in the penetration of dopant atoms in the according to 5D right field effect transistor the additionally applied second spacer layer 551 serves as a shading structure.

It should also be noted that the first TEOS protective layer 507 or the second TEOS protective layer 513 have a thickness of about 10 nm in order to allow a sufficiently good insulation effect for the layer stack of gate insulating layer and gate region. In contrast, the thickness "d" of the second spacer layer 551 adjusted so that the right SOI field effect transistor is designed as a low-energy field effect transistor. The functionalities of the TEOS protective layers 507 . 513 one hand, and the spacer layers 541 . 551 are fundamentally different.

In the following, reference is made to 6A to 6D A second preferred embodiment of the method according to the invention for producing an SOI field-effect transistor with predetermined transistor properties is described.

In the 6A shown layer sequences 600 . 610 correspond to the in 5A shown layer sequences 500 . 510 ,

To the in 6B shown layer sequences 620 . 630 to receive, both on the according to 6B left as well as on the right surface area of the layer sequences a spacer layer 621 This is done by using a CVD method ("Chemical Vapor Deposition") .The thickness "1" of this spacer layer 621 is an authoritative parameter for setting the length of the channel area of the according to 6B right SOI field effect transistor. The spacer layer 621 is made of silicon nitride.

To the in 6C shown layer sequences 640 . 650 to receive, according to 6C right surface area with a TEOS hardmask 651 (Tetra Ethyl Ortho Silicate) covered to protect this surface area in a further process step from etching. In a further method step is in the according to 6C left surface area the spacer layer 621 removed from silicon nitride using a wet chemical etching process. For this purpose, such a wet-chemical etching method is used, which is suitable for etching silicon nitride, whereas silicon dioxide (ie also the TEOS hard mask 651 ) is protected from etching. This will only make the spacer layer 621 removed from the left surface area.

To the in 6D shown layer sequences 660 . 670 First, the TEOS layer is obtained 651 removed using a suitable etching process. As in 6C The left laterally delimited layer stack is approximately 2 * 1 narrower than the right layer stack, where 1 is the thickness of the spacer layer 621 is. Subsequently, both the left layer stack and the right layer stack are subjected to an ion implantation process, so that a first source / drain region 661 , a second source / drain region 662 , a third source / drain region 663 and a fourth source / drain region 664 be formed. By means of the first and second source / drain region 661 . 662 are the source / drain regions of according to 6C left SOI field effect transistor formed, whereas by means of the source / drain regions 663 . 664 the source / drain regions of according to 6C right SOI Feldeffektransistors are formed. Due to the functionality of the spacer layer 621 as part of a shading structure, the distance between the two source / drain regions, by which the length of the channel region is defined, is in the layer sequence 670 by about 2 · l greater than in the layer sequence 660 , Therefore, the SOI field effect transistor 660 a lower threshold voltage than the SOI field effect transistor 670 , Furthermore, the SOI field effect transistor has 670 a lower leakage current than the SOI field effect transistor 660 ,

Referring to 6A to 6D In particular, the method described has the advantage that a single common implantation method for forming the source / drain regions of both SOI field-effect transistors is sufficient.

Analogous to the reference to 5A to 5D respectively. 6A to 6D described manufacturing method in a CMOS process, a p-channel SOI field effect transistor and an n-channel SOI field effect transistor can be produced. Furthermore, a multiple application of the procedure is conceivable to produce a still wide range of different components, in particular SOI field effect transistors.

After carrying out the reference to 5A to 5D respectively. 6A to 6D described method steps, further, in particular for the thin-film SOI technology specific process steps can be performed, such as the generation of "elevated" source / drain regions, silicidation or the formation of a conventional back-end region. When using a gate region of a metallic material instead of a p ⁺ -doped poly-silicon-germanium gate, this is replaced by a metallic gate region.

In 7 is a layer sequence 700 shown similar to that in the left pane of 5C shown layer sequence 540 is.

An essential difference between the layer sequence 700 out 7 and the layer sequence 540 out 5C is that at the stratigraphy 700 instead of the first spacer layer 541 a spacer sidewall 701 is provided. This can be obtained, for example, by the spacer layer 541 out 5C is etched back. The spacer sidewall 701 performs essentially the same functionality as the spacer layer 541 ,

Further, referring to 5A to 7 also describes how to make different types of transistors (low energy transistor, high power transistor) using a variable thickness spacer also applicable to other MOSFET variants. Embodiments of this are in the 8A to 8C shown.

In 8A is a double gate transistor 800 shown where a channel area 801 vertically on both sides of a first gate area 802 and from a second gate area 803 is controllably surrounded. The gate insulating regions between the first gate region 802 and the channel area 801 on the one hand and between the second gate area 803 and the channel area 801 on the other hand are in 8A Not shown. Furthermore, the double gate transistor 800 a first source / drain region 804 and a second source / drain region 805 on. In addition, a silicon substrate 806 and a silicon dioxide layer 807 on the silicon substrate 806 intended. Further, a first spacer area 808 silicon nitride and a second spacer region 809 provided by silicon nitride, by means of which according to the invention the length of the channel region is adjustable.

Furthermore, in 8A a fin field effect transistor (Fin-FET) is shown. According to the Fin-FET technology, the flow of current through the channel region is controlled from two sides. A kind of "fork-shaped" design of the gate region significantly reduces leakage currents through the channel region. In 8B are in particular a first, a second, a third and a fourth spacer area 821 to 824 shown by adjusting the thickness of the spacer layers 821 to 824 the length of the channel area is adjustable.

In 8C is a vertical field effect transistor 840 shown a bulk silicon area 841 having. A first spacer area 842 or a second spacer area 843 are so on the first and second gate area, respectively 802 . 803 designed such that thereby the length of the channel region is adjustable.

• [1] Hamada, M, Ootaguro, Y, Kuroda, T (2001) "Utilizing Surplus Timing for Power Reduction", Proceedings of the IEEE Custom Integrated Circuits Conference 2001
• [2] Schiml, T, Biesemans, S, Brase, G, Burrell, L, Cowley, A, Chen, KC, Ehrenwall, A, Ehrenwall, B, Felsner, P, Gill, J, Grellner, F, Guarin, F, Han, LK, Hoinkis, M, Hsiung, E, Kaltalioglu, E, Kim, P, Knoblinger, G, Kulkarni, S, Leslie, A, Mono, T, Schafbauer, T, Schroeder, P, Schruefer, K, Spooner, T, Towler, F, Warner, D, Wang, C, Wong, R, Demm, E, Leung, P, Stetter, M, Wann, C, Chen, JK, Crabbe, E (2001) "A 0.13μm CMOS Platform with Cu/Low-k Interconnects for System On Chip Applications" 2001 Symposium on VLSI Technology, Digest of Technical Papers
• [3] US 5,532,175
• [4] D.M. Nuernbergk, M. Lange, S. Richter, W. Göttlich, "Manche mögen's heiß – Silicon on Insulator Bauelemente und ihre Besonderheiten", in: "Mikroelektronik und Fertigung", Seiten 61 bis 64, 1999.
• [5] DE 198 23 212 A1
• [6] DE 198 57 059 A1
• [7] US 5,273,915

This document cites the following publications:

• [1] Hamada, M, Ootaguro, Y, Kuroda, T (2001) Utilizing Surplus Timing for Power Reduction, Proceedings of the IEEE Custom Integrated Circuits Conference 2001
• [2] Schiml, T, Biesemans, S, Brase, G, Burrell, L, Cowley, A, Chen, KC, Ehrenwall, A, Ehrenwall, B, Felsner, P, Gill, J, Grellner, F, Guarin, F , Han, LK, Hoinkis, M, Hsiung, E, Kaltalioglu, E, Kim, P, Knoblinger, G, Kulkarni, S, Leslie, A, Mono, T, Sheepmaker, T, Schroeder, P, Schruefer, K, Spooner , T, Towler, F, Warner, D, Wang, C, Wong, R, Demm, E, Leung, P, Stetter, M, When, C, Chen, JK, Crabbe, E (2001) "A 0.13μm CMOS Platform with Cu / Low-k Interconnects for System On-Chip Applications "2001 Symposium on VLSI Technology, Digest of Technical Papers
• [3] US 5,532,175
• [4] DM Nuernbergk, M. Lange, S. Richter, W. Göttlich, "Some like it hot - Silicon on Insulator components and their peculiarities", in: "Microelectronics and Manufacturing", pages 61 to 64, 1999.
• [5] DE 198 23 212 A1
• [6] DE 198 57 059 A1
• [7] US 5,273,915

100

SOI field effect transistor

101

Silicon substrate

102

Silicon dioxide layer

103

undoped Silicon layer

104

Gate region

105

Gate-insulating layer

106

first Source / drain region

107

second Source / drain region

108

Channel region

110

SOI field effect transistor

200

diagram

201

left Spacer layer

202

right Spacer layer

203

Gate region

204

first Source / drain region

205

second Source / drain region

206

Silicon layer

210

diagram

220

diagram

230

diagram

240

diagram

250

diagram

260

diagram

270

diagram

280

diagram

300

diagram

301

abscissa

302

ordinate

303

first Curve

304

second Curve

310

diagram

311

abscissa

312

ordinate

313

third Curve

314

fourth Curve

400

diagram

401

abscissa

402

ordinate

403

first Curve

404

second Curve

410

diagram

411

abscissa

412

ordinate

413

third Curve

414

fourth Curve

500

layer sequence

501

SOI substrate

502

Silicon substrate

503

Silicon dioxide layer

504

Silicon layer

505

first Gate insulating layer

506

first Gate region

507

first TEOS-protective layer

510

layer sequence

511

second Gate insulating layer

512

second Gate region

513

second TEOS-protective layer

520

layer sequence

521

first Source / drain region

522

second Source / drain region

530

layer sequence

531

photoresist

540

layer sequence

541

first Spacer layer

550

layer sequence

551

second Spacer layer

560

layer sequence

561

Another photoresist

570

layer sequence

571

third Source / drain region

572

fourth Source / drain region

600

layer sequence

610

layer sequence

620

layer sequence

621

Spacer layer

630

layer sequence

640

layer sequence

650

layer sequence

651

TEOS layer

660

layer sequence

661

first Source / drain region

662

second Source / drain region

663

third Source / drain region

664

fourth Source / drain region

670

layer sequence

700

layer sequence

701

Spacer side wall

800

Dopple gate transistor

801

Channel region

802

first Gate region

803

second Gate region

804

first Source / drain region

805

second Source / drain region

806

Silicon substrate

807

Silicon dioxide layer

808

first Spacer region

809

second Spacer region

820

Fin field effect transistor

821

first Spacer region

822

second Spacer region

823

third Spacer region

824

fourth Spacer region

840

Vertical field effect transistor

841

Bulk silicon

842

first Spacer region

843

second Spacer region

Claims (17)

Method of producing a completely depleted Thin-film SOI field effect transistor with given transistor properties, in which • one lateral limited layer sequence with a gate insulating layer and a gate area on an approximate undoped body is formed to a thickness of less than 20 nm; • at least a part of the side walls the laterally limited layer sequence a spacer layer is formed with a predetermined thickness; • by introducing dopant in two surface areas next to the nearly undoped body adjacent to the spacer layer, two source / drain regions formed with a given dopant concentration profile wherein the layer sequence and the spacer layer are set up so that they have a shading structure for Avoiding the introduction of dopant in the approximately undoped Form body between the two source / drain regions; • by means of Adjusting the thickness of the spacer layer and adjusting the Dopant concentration profile given transistor properties completely depleted thin film SOI field effect transistor be set. The method of claim 1, wherein as predetermined transistor property • the Length of the Channel region between the two source / drain regions, The threshold voltage, • the leakage current characteristic • the maximum current and or • one Transistor characteristic is set. The method of claim 1 or 2, wherein the thickness the spacer layer is adjusted by the spacer layer under use • one Chemical vapor deposition method or • an atomic Layer deposition process is formed. Method according to one of claims 1 to 3, wherein the two Source / drain areas using • an ion implantation procedure with following Diffusion, or • one Diffusion method are formed, wherein the dopant concentration profile by selecting the Type, concentration and / or diffusion properties of Dopant atoms is adjusted. Method according to one of claims 1 to 4, wherein the transistor properties of the completely impoverished Thin film SOI field effect transistor further by selecting of the material of the gate area. Method according to one of claims 1 to 5, wherein a second completely depleted thin film SOI field effect transistor according to the method for producing the fully depleted thin film SOI field effect transistor on or in an approximately undoped body layer is formed, wherein the transistor properties of second completely depleted thin-film SOI field effect different from those of the fully depleted thin film SOI field effect transistor. The method of claim 6, wherein the different Transistor properties of the fully depleted thin film SOI field effect transistor and the second completely depleted thin film SOI field effect transistor solely resulting from a different thickness of the spacer layers. A method according to claim 6 or 7, wherein a third Completely depleted thin film SOI field effect transistor according to the method for making the complete depleted thin film SOI field effect transistor on or in the approximate undoped body layer is formed, the transistor properties of the third completely depleted thin film SOI field effect transistor be set in the same way as that of the completely depleted thin-film SOI field-effect transistor, wherein the conductivity types of the fully depleted thin film SOI field effect transistor and the third completely depleted thin film SOI field effect transistor complementary to each other are. The method of claim 8, wherein the gate regions completely depleted thin film SOI field effect transistor and the second completely depleted thin film SOI field effect transistor and the third completely depleted thin film SOI field effect transistor be made of the same material. Method according to one of claims 6 to 9, wherein the material the gate regions have a work function value that is in the Essentially equal to the arithmetic mean of the work function values of heavily p-doped poly-silicon and heavily n-doped poly-silicon. Method according to one of the preceding claims, in the material of the gate areas Germanium, • tungsten, • Tantalum and or • titanium nitride is. The method of claim 11, wherein the material of the gate region has a work function between 445 electron volts and 495 electron volts. Method according to one of claims 6 to 12, wherein the transistor properties completely depleted thin film SOI field effect transistor and the second completely depleted thin film SOI field effect transistor be set such that one of the two fully depleted thin-film SOI field effect transistors to a low leakage current and the other to a low threshold voltage is optimized. Method according to one of claims 1 to 13, wherein at least a complete one depleted thin film SOI field effect transistor when Vertical transistor, • transistor with at least two gate connections or • Fin-FET educated becomes. Method according to one of claims 6 to 14, in which • the second Completely depleted thin film SOI field effect transistor while forming the source / drairt regions completely depleted thin film SOI field effect transistor protected by a protective layer from doping, and / or • the completely impoverished Thin-film SOI field effect transistor while forming the source / drain regions the second completely depleted thin film SOI field effect transistor is protected by a protective layer from doping. Method according to one of claims 6 to 15, wherein at least one of the most complete depleted thin film SOI field effect transistors at least one additional one Spacer layer has on the spacer layer. Completely depleted thin-film SOI field-effect transistor with predeterminable transistor properties, comprising: a laterally delimited layer sequence with a gate-insulating layer and a gate region on an approximately undoped body having a thickness of less than 20 nm; A spacer layer of a predeterminable thickness on at least a part of the side walls of the laterally delimited layer sequence; Two source / drain regions in two surface regions next to the approximately undoped body, to which the spacer layer adjoins, with a predeterminable dopant concentration profile, wherein the layer sequence and the spacer layer are set up in such a way that they form a shading structure to prevent the introduction of dopant into the approximately undoped body between the two source / drain regions during the fabrication of the fully depleted thin film SOI field effect transistor; Wherein, by adjusting the thickness of the spacer layer and adjusting the dopant concentration profile, predetermined transistor characteristics of the fully depleted thin layer SOI field effect transistor are set.