DE10211909B4 - Circuit for generating a first and a second clock signal - Google Patents

Abstract

Circuit for generating a first and a second clock signal from an input signal, the first and the second clock signal being shifted from one another by a predetermined phase angle, which comprises:
a reference signal input (1) at which a reference signal is present,
a first clock signal output (2), at which the first clock signal (9) is tapped,
a second clock signal output (3), at which the second clock signal (12) is tapped,
marked by
a first delay line (4) which is connected at a first end to the reference signal input (1) and at a second end to the first clock signal output (2),
a second delay line (5) which is connected at a first end to the second end of the first delay line (4), and
a comparison device (7) for comparing the signal at the reference signal input (1) and the signal at a second end of the second delay line (5) and for outputting the second clock signal (12) depending on the ...

Description

The invention relates to a circuit for generating a first and a second clock signal after the Preamble of claim 1.

The JP55042427A describes a phase branching filter, the circuit being provided for generating a first and a second signal for an input signal. The first and second signals are shifted from one another by a predetermined phase angle of 90 °. The input signal is present at a reference signal input. A first signal output and a second signal output are provided for the two phase-shifted output signals.

In the essay “A New Active Phase Shifter Using a Vector Sum Method "in IEEE Microwave and guided wave letters, Volume 10; No. 6, June 2000, Pages 233 to 235 by Kim S.J. and Myung N.H. becomes a phase shifter described in which a phase-shifted to the input signal Output signal is generated. The input signal is two Split signal paths with variable amplifier stages. The phase difference between the signals of the two signal paths at the output of the variable amplifier stages results in dependence from the set gain. One of the two signals goes through a 180 ° phase shifter in the form of a delay line, which results in a sign reversal for this signal. The Signals are vectorially added at the output of the two signal paths. Taking into account the Sign reversal of a difference or a comparison to Formation of a phase-shifted output signal.

Phase detectors in PLL (Phased Locked Loop) circuits need Clock signals that are 90 degrees out of phase with the original clock are. The provision of these out-of-phase signals requires huge Passive components such as capacities, inductors and resistors and their dimensioning.

Tolerances and the parasitic components of these components lead to deviations from the desired 90 degree phase shift. Passive circuits can be used with the corresponding expenditure on component area and layout this problem minimize but not solve. aggravating Added to this is the fact that the effective values of the components depend on the temperature depend. Further previously used circuits only work frequency-selective, what entails changes are associated with deviations from the desired 90 degrees in the clock frequency.

From "Continuously variable gigahertz phase-shifter IC covering more than one frequency decade "by Schmidt, L., and Rein, H.-J., in IEEE Journal of Solid-State Circuits, Vol. 27, No. 6, June 1992, a monolithic silicon integrated circuit is known in which a phase shift of an arbitrarily shaped clock signal around 0 to -2π in a frequency range from 60 MHz to 1.8 GHz is possible. The phase can be with a potentiometer or with an external voltage can be set. The circuit works essentially digitally. The temperature coefficient of the phase can be within a given Intervals can be set.

Such a circuit requires however, an elaborate one Logic circuit. It also has a potentiometer for setting the Phase an additional Inaccuracy and another temperature sensitive parameter result.

Object of the present invention is to provide a simple circuit that reliably two Clock signals are generated that have a predetermined phase angle have each other, in particular a phase angle of 90 degrees.

This task is solved by the features issued in the characterizing part of claim 1. Preferred embodiments the invention are the subject of the dependent claims.

The invention uses for providing two phase-shifted signals have the effect of two sinusoidal signals with a tolerance of + ΔT or of –ΔT at Cut 90 degrees or 270 degrees of the original signal. The value of ΔT is arbitrary.

The inventive circuit for generating a first and a second clock signal from an input signal, wherein the first and the second clock signal by a predetermined Phase angles are shifted from each other, includes: a reference signal input, at which a reference signal is present, a first clock signal output, at which the first clock signal is tapped, a second clock signal output, at which the second clock signal is tapped is marked through a first delay line, which is connected to the reference signal input at a first end and connected to the first clock signal output at a second end is a second delay line, that at a first end with the second end of the first delay line is connected, and a comparison device for comparing the Signal at the reference signal input and the signal at a second End of the second delay line and for outputting the second clock signal depending on the comparison.

The comparison device is preferably a differential amplifier with an inverting and a non-inverting input, at one input of which the reference signal is present and at the other input of which the signal is present at the second end of the second delay line and the second clock signal is tapped at its output. As a result, the two signals are subtracted from one another or added together, so that the difference or sum of the two signals is output as the second clock signal.

Around the first and second delay line to match one another, a phase shifter can be provided.

To delay delays by the comparison device To compensate is in a further preferred embodiment the invention a delay line provided before the second clock output.

In particular, the first and the second delay line the same transit time, so that the specified phase angle between the first and the second clock signal is ± 90 °.

The invention leads to several advantages over the State of the art. This is the effort involved in applying the invention relatively low, it will be next to two delay elements a differential amplifier needed being the delay elements can be easily implemented using a defined wiring length. The phase shift is constant at all frequencies, in particular it has a constant one Value of 90 degrees. Signals are not attenuated, they are instead generated further signals. The error of the phase shift between the first and the second clock signal are determined solely by the runtime delay error in the two delay elements, he is no longer through the many when designing the circuit to be considered Tolerances exist, which are due to the many components. It is easy to correct the phase shift from the outside. The solution according to the invention independently of temperature and voltage.

Other features and advantages of Invention result from the description of exemplary embodiments, reference is made to the accompanying drawings.

1 shows the basic structure of a circuit for realizing the inventive concept.

2 shows a timing diagram of the signals in the circuit after 1 ,

3 shows an embodiment of a switching element 1 ,

In 1 An inventive clock signal generating circuit for generating a first and a second clock signal from an input signal is shown. The first and the second clock signal should be shifted from one another by a predetermined phase angle. The clock signal generating circuit includes a reference signal input 1 to which the reference signal is present, which is, for example, an external (master) clock. The first clock signal generated by the clock signal generating circuit is at a first clock signal output 2 tapped. The second clock signal generated by the clock signal generating circuit is at a second clock signal output 3 tapped.

The clock signal generating circuit according to the invention comprises a first delay line 4 between the reference signal input 1 and the first clock signal output 2 , More specifically, the first delay line is 4 at one end directly with the reference signal input 1 connected between its second end and the first clock signal output 2 but yet another switching element is arranged, which will be explained further below. A second delay line 5 follows after the first delay line 4 so that at the end of the second delay line 5 receives a twice-delayed signal. The total delay of the twice-delayed signal is the sum of the delays in the two preceding individual sections, namely T1 and T2, T1 being the delay in the first section 4 and T2 is the delay of the second route 5 is.

The twice delayed signal is sent together with the (original) reference signal at the input 1 the circuit of a comparison device 7 fed. The two signals are compared in this comparison device, which means that they are added, subtracted, multiplied or divided, depending on which form of the output signal is required. In practice, the easiest way to realize the sum or difference. In 1 is therefore the comparison device 7 marked by a "+ -", and in the following description it is assumed that the difference of the reference signal at the input 1 and the twice-delayed signal at the end of the second delay line 5 is formed.

The output signal of the comparison device 7 is the second clock signal, which thus depends on the comparison or the combination of the two signals at the input of the comparison device.

The comparison facility 7 can in turn cause a certain delay between the application of the two input signals and the formation of the output signal. This undesirable delay can only be compensated for by the fact that the first clock signal is also delayed to the same extent. Therefore, the circuit is after 1 another delay element 8th intended. This delay element 8th is located between the node between the two delay lines 4 and 5 and the first clock output 2 ,

The temporal development of the signals at the input and at the output of the comparison device 7 in 1 is in 2 shown. The delay is caused by switching elements such as the comparison device 7 or the delay element 8th not considered Untitled.

The reference signal is the "earliest" or "leading" signal found in 2 With 9 is designated and shown in dash-dotted lines. After its delay in the route 4 you get that with 10 designated signal shown with a solid line, which is the first clock signal, which is by the circuit in 1 is generated and at the output 2 is issued. After delaying this second signal in the route 5 that results with 11 designated "trailing" signal, which is shown in dashed lines. In 2 have the leading and trailing signal 9 and 11 compared to the first clock signal 10 the same amount of phase shift, which differs in sign. The two signals 9 and 11 are therefore symmetrical to the signal 10 , In this case, the two delay lines are 4 and 5 identical, in the simplest case they can consist of wiring.

The comparison facility 7 forms from the leading signal 9 and the trailing signal 11 a difference signal that in 2 With 12 is designated. This difference signal 12 is the second of the circuit after 1 generated clock signal at the output 3 ,

How out 2 can be seen - because of the same phase shift of the signals 9 and 11 opposite signal 10 - the first clock signal 10 and the difference signal 12 shifted by 90 ° to each other. This becomes clear on the vertical lines in 2 where the first clock signal 10 has an extremum while the second clock signal 12 has a zero crossing at this point.

At the intersection of the curves 9 and 11 that lead or lag by + ΔT and –ΔT changes the sign of the difference 12 , This change of sign can be used by means of a differential amplifier to form the original signal shifted by 90 degrees.

In 3 is an embodiment of the comparison device 7 shown. The circuit consists of a differential amplifier with a first input 13 and a second entrance 14 , The leading signal is at one of the two inputs 9 , i.e. the reference signal, and the trailing signal is located at the other of the two inputs 11 from the end of the second delay line 5 , The two signal inputs are designated accordingly with -ΔT and + ΔT. The differential amplifier comprises a first transistor in a manner known per se 15 and a second transistor 16 with a first collector resistor 17 or a second collector resistor 18 , The two transistors are above their emitter 15 and 16 with a power source 19 connected. The supply voltage of the circuit is the potential difference between VCC on the collector and VEE on the emitter side. The output voltage is tapped between the collector and the collector resistor.

So the non-inverted output signal (difference signal) is at an output 20 , the inverted output signal (sum signal) is at an output 21 , Depending on your needs, one of the outputs 20 and 21 with the exit 3 in 1 connected for the second clock signal.

With the circuit described above, any phase shifts can be set. The invention is not limited to a phase shift of ± 90 °. In order to enable a variable phase shift or to enable a comparison to a desired phase shift (in particular 90 °), the following is therefore in the circuit 1 a phase shifter 6 provided, which is represented by a double arrow.

1

Reference signal input

2

first Clock out

3

second Clock out

4

first delay line

5

second delay line

6

Delay adjustment device

7

comparator

8th

Output delay element

9

leading end Signal, reference signal

10

first clock signal

11

trailing signal

12

Difference signal, second clock signal

13

signal input for leading signal

14

signal input for trailing signal

15

first transistor

16

second transistor

17

first collector resistance

18

second collector resistance

19

power source

20

output for second clock signal

21

output for inverted second clock signal

Claims (5)

Circuit for generating a first and a second clock signal from an input signal, the first and the second clock signal being shifted from one another by a predetermined phase angle, which comprises: a reference signal input ( 1 ), to which a reference signal is present, a first clock signal output ( 2 ) on which the first clock signal ( 9 ) is tapped, a second clock signal output ( 3 ) on which the second clock signal ( 12 ) is tapped, characterized by a first delay line ( 4 ) connected at a first end to the reference signal input ( 1 ) is connected and at a second end to the first clock signal output ( 2 ) is connected, a second delay line ( 5 ) which at a first end with the second end of the first delay distance ( 4 ) and a comparison device ( 7 ) to compare the signal at the reference signal input ( 1 ) and the signal at a second end of the second delay line ( 5 ) and for outputting the second clock signal ( 12 ) depending on the comparison. Circuit according to claim 1, characterized in that the comparison device ( 7 ) a differential amplifier with a first input ( 13 ) and a second entrance ( 14 ), at one input of which the reference signal ( 1 ) is present and at its other input the signal at the second end of the second delay line ( 5 ) is present and at its output ( 20 . 21 ) the second clock signal is tapped. Circuit according to claim 1 or 2, characterized in that a phase shifter ( 6 ) to adjust the first (4) and the second delay line ( 5 ) is provided. Circuit according to one of the preceding claims, characterized in that a delay line ( 8th ) between the second, end of the first delay line ( 4 ) and the first clock signal output ( 2 ) is provided for delay delays by the comparison device ( 7 ) to compensate. Circuit according to one of the preceding claims, characterized in that the first ( 4 ) and the second delay line ( 5 ) have the same runtime, so that the specified phase angle between the first ( 9 ) and the second clock signal ( 12 ) Is ± 90 °.