DE10210160A1 - Process for fixing integrated circuits to a circuit board comprises placing an elastic film having vertical wires arranged in the film between the circuits and the circuit board - Google Patents

Process for fixing integrated circuits to a circuit board comprises placing an elastic film having vertical wires arranged in the film between the circuits and the circuit board

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Publication number
DE10210160A1
DE10210160A1 DE10210160A DE10210160A DE10210160A1 DE 10210160 A1 DE10210160 A1 DE 10210160A1 DE 10210160 A DE10210160 A DE 10210160A DE 10210160 A DE10210160 A DE 10210160A DE 10210160 A1 DE10210160 A1 DE 10210160A1
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circuit board
elastic film
film
integrated circuits
chip
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DE10210160A
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German (de)
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Stefan Geyer
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10378—Interposers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

Process for fixing integrated circuits to a circuit board comprises placing an elastic film having vertical wires arranged in the film between the circuits and the circuit board.

Description

Die Erfindung betrifft eine Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten. The invention relates to a method for fastening integrated circuits on printed circuit boards.

Ein integrierter Schaltkreis (Chip) muss auf einer Leiterplatte elektrisch absolut zuverlässig angebracht sein. Des weiteren soll die Anordnung möglichst stabil, möglichst klein, möglichst flach und möglichst leicht sein. Es müssen weiterhin genügend Eingänge/Ausgänge am Chip möglich sein, der Chip mit einer hohen Taktfrequenz bei guter Signalqualität arbeiten können und der Chip muss seine Wärme gut abführen können. An integrated circuit (chip) must be absolutely reliable on a circuit board to be appropriate. Furthermore, the arrangement should be as stable as possible, as small as possible, as possible be flat and as light as possible. There must still be enough inputs / outputs on the chip be possible, the chip can work with a high clock frequency with good signal quality and the chip must be able to dissipate its heat well.

Das wichtigste ist, dass all die Eigenschaften nur mit minimalen Herstellungskosten verbunden sein dürfen. The most important thing is that all of the properties are associated with minimal manufacturing costs may be.

Eine elektrisch absolut zuverlässige Verbindung von Chip und Leiterplatte zu realisieren ist kompliziert, da Chip und Leiterplatte bedingt durch die unterschiedlichen Ausdehnungskoeffizienten und Aufwärm- und Abkühlvorgänge und die damit verbundenen Ausdehn- und Zusammenziehvorgänge "gegeneinander arbeiten". An electrically absolutely reliable connection of the chip and the circuit board can be realized complicated because the chip and circuit board are due to the different Expansion coefficients and heating and cooling processes and the associated expansion and Contractions "work against each other".

Dieses "gegeneinander Arbeiten" führt bei einer starren elektrischen Verbindung von Chip und Leiterplatte im Laufe der Zeit unweigerlich zum Reißen der elektrischen Verbindung zwischen Chip und Leiterplatte und damit zum Ausfall des Bauteils. This "working against each other" leads to a rigid electrical connection of the chip and PCB over time inevitably breaks the electrical connection between Chip and circuit board and therefore failure of the component.

Um das zu verhindern, sind alle funktionierenden Verbindungen von Chip und Leiterplatte so gestaltet, dass sie das "gegeneinander Arbeiten" ermöglichen. To prevent this, all working connections between chip and circuit board are like this designed to enable "working against each other".

Bedingt durch starken Preisdruck ist man weltweit bemüht, die Fertigung zu vereinfachen, und die Entwicklung in Richtung "möglichst klein, möglichst flach, möglichst leicht, genügend Eingänge/Ausgänge, hohe Taktfrequenz, guter Signalqualität, gute Wärmeabführung" zu treiben, und wenn möglich, vor allem auf das Zeit- und kostenintensive Bonden zu verzichten. So wurden in den vergangenen Jahren neben dem klassischen SOJ- und TSOP-Packaging eine breite Palette von neuen Packagingmethoden entwickelt. Due to strong price pressure, efforts are being made worldwide to simplify production, and the development towards "as small as possible, as flat as possible, as light as possible, sufficient Inputs / outputs, high clock frequency, good signal quality, good heat dissipation "too drive, and if possible, especially to forego the time-consuming and costly bonding. In addition to classic SOJ and TSOP packaging, a developed a wide range of new packaging methods.

Zur Zeit sind weltweit ca. 50 Packagingmethoden kommerziell verfügbar und einige hundert in Entwicklung. Einen guten Überblick über die Breite der weltweiten Aktivitäten bieten John H. Lau und S. W. Ricky Lee in "Chip Scale Package (CSP) Design, Materials, Processes, Reliability and Applications", McGraw-Hill, New York, 1999, ISBN 047-038304 sowie über die neusten Entwicklungen P. Garrou in "Wafer-Level Packaging Has Arriveed", SEMICONDUCTOR INTERNATIONAL, October 2000, p. 119-128. Around 50 packaging methods are currently commercially available and several hundred in Development. John H. offers a good overview of the breadth of global activities. Lau and S. W. Ricky Lee in "Chip Scale Package (CSP) Design, Materials, Processes, Reliability and Applications ", McGraw-Hill, New York, 1999, ISBN 047-038304 and the latest Developments P. Garrou in "Wafer-Level Packaging Has Arriveed", SEMICONDUCTOR INTERNATIONAL, October 2000, p. 119-128.

Beim Analysieren der zahlreichen Packagingmethoden kommt man zu dem Schluß, dass sehr kostengünstige Packagingmethoden, die ganz auf die Bondverbindung verzichten, nicht genügend zuverlässig sind und sehr zuverlässige Packagingmethoden, die die Bondverbindung weiterhin nutzen, nicht genügend kostengünstig sind. When analyzing the numerous packaging methods, one comes to the conclusion that very much Inexpensive packaging methods that do without the bond connection entirely are sufficiently reliable and very reliable packaging methods that the Continue to use bond connection, are not sufficiently cost-effective.

So nimmt das klassische Packaging, mit metallischem Leadframe und gebondeten und verkapselten Chips immer noch einen bedeutenden Platz ein. So takes the classic packaging, with metallic leadframe and bonded and encapsulated chips still occupy a significant place.

Ziel der Erfindung ist es, eine extrem kostengünstige und extrem zuverlässige Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten zu finden. The aim of the invention is to provide an extremely inexpensive and extremely reliable method for Fastening integrated circuits to find on printed circuit boards.

Dieses Ziel wird erreicht, indem das Prinzip der Bondverbindung - ein längerer dünnerer Draht verbindet zwei Punkte elektrisch sicher, lässt dabei aber Ortsveränderungen der zwei Punkte in gewissem Maße zu - beibehalten aber technisch völlig anders realisiert wird. This goal is achieved by using the principle of bond connection - a longer, thinner wire connects two points electrically securely, but leaves the two points in place changes to a certain extent - retained but implemented technically completely different.

Dazu wird, wie bei anderen Packagingmethoden ebenfalls üblich, sehr kostengünstig auf Waferebene ein System an Redistributionsleitbahnen hergestellt, bevor die Chips aus dem Wafer gesägt werden. Das System an Redistributionsleitbahnen hat dabei die Aufgabe, die elektrische Verbindung von den sehr engen und nicht sicher lötfähigen Pondpads, zu sicher lötfähigen Lötpunkten in lötfähiger Größe und lötfähigem Abstand zu gewährleisten. Die vorzugsweise runden Lötpunkte haben dabei einen Durchmesser von vorzugsweise 0,4 mm, einen Abstand von vorzugsweise 0,4 mm und der Abstand von Lötpunkzentrum zu Lötpunktzentrum beträgt vorzugsweise 0,8 mm. As with other packaging methods, this is very inexpensive A system of redistribution interconnects is produced at the wafer level before the chips are removed from the Wafers are sawn. The system of redistribution channels has the task of electrical connection from the very tight and not securely solderable Pondpads, too safe To ensure solderable solder points in a solderable size and solderable distance. The preferably round solder points have a diameter of preferably 0.4 mm, a distance of preferably 0.4 mm and the distance from the soldering point center Soldering point center is preferably 0.8 mm.

Auf der Leiterplatte existiert dazu das spiegelverkehrte Lötpunktbild. For this purpose, there is the mirror-image solder point image on the circuit board.

Nun wird der ausgesägte Chip aber nicht direkt auf die Leiterplatte gelötet, denn das wäre ja aus den erwähnten Gründen der thermischen Ausdehnung nicht elektrisch zuverlässig, sondern zwischem Chip und Leiterplatte wird eine elastische Folie mit senkrechten in der elastischen Folie angeordneten Drähten eingelötet, sodass die senkrechten Drähte die Lötpunkte auf der Leiterplatte mit den Lötpunkten auf dem Chip verbinden (siehe Figur). Direkt auflötbar sind nur sehr kleine Chips mit DNP's (ball distance from neutral point) bis ca. 2 mm und auch mit Unterfüllung bleibt die Direktanlötung in Anbetracht der gewaltigen möglichen Kräfte zwischen Chip und Leiterplatte ein Zuverlässigkeitsproblem. Now the sawn-out chip is not soldered directly onto the circuit board, because that would be so not electrically reliable due to the thermal expansion reasons mentioned, but between the chip and the circuit board is an elastic film with vertical in the Elastic foil arranged wires soldered so that the vertical wires the Connect solder points on the circuit board to the solder points on the chip (see figure). Only very small chips with DNP's (ball distance from neutral point) up to approx. 2 mm can be soldered on directly and even with underfill, the direct soldering remains in view of the enormous possible forces between the chip and the circuit board pose a reliability problem.

Nach Anlötung der elastischen Folie an Chip und Leiterplatte kann der Spalt zwischen Chip und elastischer Folie sowie zwischen elastischer Folie und Leiterplatte mit einem dünnflüssigen Epoxydharz unter Ausnutzung der Kapillarwirkung verfüllt werden bzw. es kann auch die gesamte Anordnung umhüllt werden. After soldering the elastic film to the chip and the printed circuit board, the gap between the chip can and elastic film and between elastic film and circuit board with one thin epoxy resin can be filled using the capillary effect or it can the entire arrangement can also be encased.

Die erfindungsgemäße Methode hat folgende Vorteile:

  • 1. Die elastische Folie mit den senkrechten Drähten gestattet analog der Bondverbindung dem Chip und der Leiterplatte ein Höchstmass an thermischem, dehnungsmäßigem Eigenleben ohne dass die Gefahr des Abreißens der elektrischen Verbindung besteht. Das bedeutet ein Höchstmaß an Zuverlässigkeit des fertigen Bauteiles.
  • 2. Durch die Wahl der Dicke der elastischen Folie mit den senkrechten Drähten können auch ungewöhnlich große Chips oder mehrere Chips in einem Stück Silizium auf der Leiterplatte montiert werden. Man braucht dazu nur die Dicke der elastischen Folie entsprechend groß wählen. Bei entsprechend großer Foliendicke ist praktisch jede Chipgröße und jede DNP ohne Zuverlässigkeitseinschränkungen beherrschbar. Das kann in naher Zukunft eine große Bedeutung erlangen, da man mit Chipstrukturbreiten zwischen 0,15 und 0,10 µm an einem Punkt angelangt ist, wo der wirtschaftliche Nutzen den technischen Aufwand kaum noch rechtfertigt. Das bedeutet: Will man mehr Funktionen auf einem Chip integrieren, muss man gezwungenermaßen den Chip größer machen.
  • 3. Die Methode ist für nahezu alle Chiptypen geeignet und die elastische Folie mit den senkrechten Drähten lässt sich hervorragend auf bestimmte Drahtrasterabstände und Foliendicken standardisieren, und hat damit das Potenzial, eine Standardmethode zur Chipmontage zu werden.
  • 4. Da die Redistributionsleitbahnen keinen mechanischen Stress abzufangen haben, d. h. aller mechanischer Stress in der elastischen Folie mit den senkrechten Leitbahnen abgebaut bzw. aufgefangen wird, werden an sie auch keine besonderen Anforderungen gestellt. Sie müssen sich nur möglichst kostengünstig und möglichst mit den vorhandenen Anlagen der jeweiligen Chipfabrik herstellen lassen. Das Prozessende der Chipfabrik sind dann nicht mehr Pondpads, wie bisher üblich, sondern Lötpunkte in definierter Anordnung, z. B. im quadratischen 0,8 mm-Raster.
  • 5. Die elastische Folie mit den senkrechten Drähten lässt sich als Meterware kostengünstig und hochproduktiv außerhalb der eigentlichen Chipindustrie herstellen.
  • 6. Die Methode ist gleichzeitig "Wafer Level Packaging" (WLP), "Wafer Scale Assemly" (WSA), "Wafer Level Burn In" (WLBI), "Wafer Level Testing" (WLT) und "Chip Size Packaging" (CSP) mit all den wirtschaftlichen Vorteilen.
The method according to the invention has the following advantages:
  • 1. Analogous to the bond connection, the elastic film with the vertical wires allows the chip and the printed circuit board to have a high degree of thermal, expansional life without the risk of the electrical connection being torn off. This means the highest degree of reliability of the finished component.
  • 2. By choosing the thickness of the elastic film with the vertical wires, unusually large chips or several chips can be mounted in one piece of silicon on the circuit board. You only need to choose the thickness of the elastic film accordingly large. With a correspondingly large film thickness, practically every chip size and every DNP can be managed without any reliability restrictions. This can become very important in the near future, since chip structure widths between 0.15 and 0.10 µm have reached a point where the economic benefits hardly justify the technical effort. That means: If you want to integrate more functions on a chip, you have to make the chip bigger.
  • 3. The method is suitable for almost all types of chips and the elastic film with the vertical wires can be standardized perfectly to certain wire spacing and film thicknesses, and thus has the potential to become a standard method for chip assembly.
  • 4. Since the redistribution guideways do not have to absorb mechanical stress, ie all mechanical stress is reduced or absorbed in the elastic film with the vertical guideways, no special requirements are placed on them. You only have to be able to manufacture them as cost-effectively as possible and if possible with the existing systems of the respective chip factory. The process end of the chip factory is then no longer Pondpads, as was previously the case, but soldering points in a defined arrangement, e.g. B. in a square 0.8 mm grid.
  • 5. The elastic film with the vertical wires can be produced inexpensively and highly productively by the meter outside the actual chip industry.
  • 6. The method is simultaneously "Wafer Level Packaging" (WLP), "Wafer Scale Assemly" (WSA), "Wafer Level Burn In" (WLBI), "Wafer Level Testing" (WLT) and "Chip Size Packaging" (CSP ) with all the economic advantages.

Am folgenden Ausführungsbeispiel soll die Methode näher erläutert werden:
Die Bearbeitung auf Waferebene erfolgt folgendermaßen:
Ein Wafer mit DRAM's verlässt das Frontend wie üblich nach PAD OPEN.
Anschließend erfolgt wie ebenfalls üblich der PARAMETRIC TEST, der PREFUSE TEST, das LASER REPAIR und der POSTFUSE TEST. The method will be explained in more detail using the following exemplary embodiment:
Processing at the wafer level is as follows:
A wafer with DRAMs leaves the front end as usual after PAD OPEN.
This is followed by the PARAMETRIC TEST, the PREFUSE TEST, the LASER REPAIR and the POSTFUSE TEST as usual.

Jetzt wird der Wafer aber nicht wie beim herkömmlichen Packaging gesägt, sondern es geht auf Waferebene mit nach dem Stand der Technik üblichen Prozessschritten zur Erzeugung von Redistributionsleitbahnen weiter. Die zum Schluss vorliegenden runden Lötpunkte haben einen Durchmesser von 0,4 mm, einen Abstand von 0,4 mm und der Abstand von Lötpunkzentrum zu Lötpunktzentrum beträgt 0,8 mm. Die Lötpunkte sind ca. 0,15 mm hoch mit aufgeschmolzenem Lot versehen welches zuvor als Lötpaste im Siebdruckverfahren aufgebracht wurde. Now the wafer is not sawn like in conventional packaging, it works at the wafer level with process steps customary in the prior art for producing Redistribution channels. Have the round soldering points at the end a diameter of 0.4 mm, a distance of 0.4 mm and the distance of Soldering point center to soldering point center is 0.8 mm. The solder points are approx. 0.15 mm high with melted solder which was previously used as a solder paste using the screen printing process was applied.

Nach diesen Prozessschritten erfolgt auf Waferebene mit elastischen Kontakten, die sich in das Lot pressen (z. B. Formfaktor-Mikrospring-Kontakten), der FINAL TEST-HOT, das BURN-IN (125°C) und der FiNAL TEST-COLD. Danach erfolgt das Sägen womit man die einzelnen Chips erhält. After these process steps, elastic contacts are made at the wafer level, which are located in press the plumb (e.g. form factor microspring contacts), the FINAL TEST-HOT, the BURN-IN (125 ° C) and the FiNAL TEST-COLD. Then the sawing takes place with which the individual chips receives.

Die Herstellung der elastischen Folie mit den senkrechten Drähten erfolgt folgendermaßen:
Durch Extrusion von Vinylsilikonkautschuk wird eine lötemperaturbeständige, hochelastische Silikonkautschukfolie von 0,5 mm Dicke hergestellt. The elastic film with the vertical wires is produced as follows:
Extrusion of vinyl silicone rubber produces a soldering temperature resistant, highly elastic silicone rubber film with a thickness of 0.5 mm.

In die Folie werden anschließend mit Nähtechnik Kupferdrähte von 50 µm Durchmesser im quadratischen Rasterabstand von 0,8 mm eingestochen. Copper wires with a diameter of 50 µm are then sewn into the film using sewing technology square pitch of 0.8 mm.

Danach werden aus der Folie chipgroße Folienstücke so ausgeschnitten, dass sie exakt auf das Lötpunktraster des Chips sowie das spiegelverkehrte Lötpunktraster der Leiterplatte passen. Then chip-sized pieces of film are cut out of the film so that they fit exactly the solder grid of the chip and the mirrored grid of the PCB fit.

Die Montage der Chips auf der Leiterplatte erfolgt folgendermaßen:
Die ausgesägten Chips werden im MODUL ASSEMBLY jetzt nicht direkt auf die Leiterplatte gelötet, sondern über die elastische Zwischenschicht angebracht. The chips are mounted on the circuit board as follows:
The sawn-out chips in the MODUL ASSEMBLY are now not soldered directly onto the circuit board, but rather attached over the elastic intermediate layer.

Zuerst wird Lötpaste mit der üblichen Sieb- und Rakeltechnik auf die elastische Folie gebracht, dann der Chip aufgesetzt, erhitzt und abgekühlt. Der mit der elastischen Folie ausgerüstete Chip wird dann genau so - d. h. Lötpaste aufbringen, Chip aufsetzen, erhitzen und abkühlen - auf die Leiterplatte gelötet. First, solder paste is applied to the elastic film using the usual sieve and doctor blade technology, then the chip is put on, heated and cooled. The one equipped with the elastic film Chip is then exactly the same - d. H. Apply solder paste, put on chip, heat and cool - on soldered the circuit board.

Zum Schluß erfolgt der MODULE FINAL TEST. Finally, the MODULE FINAL TEST is carried out.

Claims (7)

1. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten, dadurch gekennzeichnet, dass zwischen integriertem Schaltkreis und Leiterplatte eine elastische Folie mit senkrechten in der elastischen Folie angeordneten Drähten platziert ist. 1. Method for fastening integrated circuits on printed circuit boards, characterized in that an elastic film with vertical wires arranged in the elastic film is placed between the integrated circuit and the printed circuit board. 2. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten nach Anspruch 1, dadurch gekennzeichnet, dass die elastische Folie eine Dicke von 0,05-5,0 mm besitzt. 2. Method for mounting integrated circuits on printed circuit boards according to claim 1, characterized characterized in that the elastic film has a thickness of 0.05-5.0 mm. 3. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten nach Anspruch 1 und 2, dadurch gekennzeichnet, dass die elastische Folie löttemperaturbeständig ist. 3. Method for mounting integrated circuits on printed circuit boards according to claim 1 and 2, characterized in that the elastic film is resistant to soldering temperature. 4. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten nach Anspruch 1, 2 und 3 dadurch gekennzeichnet, dass die in der elastischen Folie angeordneten Drähte Kupfer-, Silber- oder Golddrähte mit 5-500 µm Durchmesser sind. 4. Method for mounting integrated circuits on printed circuit boards according to claim 1, 2 and 3 characterized in that the wires arranged in the elastic foil copper, Silver or gold wires with a diameter of 5-500 µm are. 5. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten nach Anspruch 1, 2, 3 und 4 dadurch gekennzeichnet, dass die in der elastischen Folie angeordneten Drähte Volldrähte oder Hohldrähte sind. 5. Method for mounting integrated circuits on printed circuit boards according to claim 1, 2, 3 and 4 characterized in that the wires arranged in the elastic film are solid wires or are hollow wires. 6. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten nach Anspruch 1, 2, 3, 4 und 5 dadurch gekennzeichnet, dass die Drähte sowohl an der Leiterplatte wie auch am integrierten Schaltkreis angelötet sind. 6. Method for mounting integrated circuits on printed circuit boards according to claim 1, 2, 3, 4 and 5 characterized in that the wires on both the circuit board and on integrated circuit are soldered. 7. Methode zur Befestigung integrierter Schaltkreise auf Leiterplatten nach Anspruch 1, 2, 3, 4, 5 und 6 dadurch gekennzeichnet, dass sowohl der Spalt zwischen integriertem Schaltkreis und elastischer Folie wie auch der Spalt zwischen elastischer Folie und Leiterplatte mit einem temperaturbeständigen Polymer gefüllt sein kann. 7. Method for mounting integrated circuits on printed circuit boards according to claim 1, 2, 3, 4, 5 and 6 characterized in that both the gap between the integrated circuit and elastic film as well as the gap between the elastic film and the circuit board with one temperature-resistant polymer can be filled.
DE10210160A 2002-03-07 2002-03-07 Process for fixing integrated circuits to a circuit board comprises placing an elastic film having vertical wires arranged in the film between the circuits and the circuit board Withdrawn DE10210160A1 (en)

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DE10210160A DE10210160A1 (en) 2002-03-07 2002-03-07 Process for fixing integrated circuits to a circuit board comprises placing an elastic film having vertical wires arranged in the film between the circuits and the circuit board

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6264476B1 (en) * 1999-12-09 2001-07-24 High Connection Density, Inc. Wire segment based interposer for high frequency electrical connection
DE10105920A1 (en) * 2000-02-10 2001-08-16 Nitto Denko Corp Semiconducting component has anisotropically conductive film connecting semiconducting element to circuit board, film substrate of insulating resin with mutually insulated conducting tracks

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6264476B1 (en) * 1999-12-09 2001-07-24 High Connection Density, Inc. Wire segment based interposer for high frequency electrical connection
DE10105920A1 (en) * 2000-02-10 2001-08-16 Nitto Denko Corp Semiconducting component has anisotropically conductive film connecting semiconducting element to circuit board, film substrate of insulating resin with mutually insulated conducting tracks

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM Technical Disclosure Bulletin, 1992, Vol. 35, Nr. 3, S. 130-131 *
IBM Technical Disclosure Bulletin, 1994, Vol. 37, Nr. 04B, S. 105-106 *

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