DE102011082715A1 - Die package used for a semiconductor device comprises a leadframe containing a die attach pad, a conductive layer on a portion of the die attach pad, a boundary feature comprising a bond wire, and a die on the conductive layer - Google Patents

Abstract

Die package for a semiconductor device comprises: (a) a leadframe containing a die attach pad; (b) a conductive layer on a portion of the die attach pad, where the conductive layer has a thickness ranging up to 30 mil; (c) a boundary feature comprising a bond wire partially surrounding the conductive layer, where both ends of the bond wires are attached to the die attach pad; and (d) a die on the conductive layer. Independent claims are included for: (1) a semiconductor device comprising: (a) a leadframe; (b) a conductive layer; (c) a boundary; and (d) a die on the conductive layer; and (2) a method for making a semiconductor device.

Description

TERRITORY

This application relates generally to semiconductor devices and to methods of fabricating semiconductor devices. More particularly, the application relates to chip attachment methods used in the fabrication of semiconductor devices and the chip assemblies and semiconductor devices resulting from those methods.

BACKGROUND

Often, during the fabrication of semiconductor devices, one or more chips comprising the integrated circuit may be bonded or attached to a chip mounting pad (or paddle) of a leadframe. The method of bonding the chip to the leadframe is generally referred to as a die attach method. The die attach process may be performed using an electrically conductive material, such as an adhesive or solder, that mechanically and electrically connects the die to the leadframe. The thickness of this conductive material is often referred to as the Bond Line Thickness (BLT).

In the mounting method, the conductive material must allow the bonding between the chip and the leadframe to occur while minimizing the formation of voids in the bond. The die attaching process must also provide a consistent bond strength across the top of the die, thereby minimizing punctiform stresses that can cause breakage or other defects of the semiconductor devices. Any voids and non-uniform ribbon thickness in the bond increase on-chip stress and stress, which can lead to tears and defects in the semiconductor device. In addition, cavities can result in inefficient electrical or thermal conductivity, possibly causing defects in the semiconductor device. The conductive material should therefore have a sufficiently low viscosity to allow effective bonding by avoiding these two problems.

1 and 2 make an example chip 110 which is on the chip pad 120 through a conductive material 130 is attached to a chip mounting assembly 100 to build. As in 1 t _{1 is} the BLT between the chip 110 and the chip mounting pad 120 , An increase in BLT by increasing the thickness of the conductive material 130 reduces the shear stress on the chip, making a larger thickness more desirable. However, the low viscosity required to ensure no voids normally limits the thickness to less than 3 mils. However, increasing the amount of conductive material used during chip attachment with the effort to increase the BLT may lead to the flow of conductive material to other parts of the leadframe or the chip, potentially causing moisture, short circuits and problems causes wire bonding and often results in failure of the semiconductor device.

To avoid these problems, some chip attachment methods use a "spanner" to flatten the conductive material during the die attach process. However, the use of the chip requires additional steps that extend the manufacturing process of the device, making it less productive and more expensive. In addition, if too much conductive material is used to attempt to achieve a large BLT, the conductive material may be displaced by the chip from the die attach pad to other portions of the leadframe, possibly causing short circuits and other problems ,

SUMMARY

This application describes the mounting methods used in manufacturing semiconductor devices and the chip packages resulting from those methods and the semiconductor devices. The methods include providing a leadframe with a die attach pad, using constraining means (s) comprising a bonding wire to define a perimeter on the die attach pad, depositing a conductive material (such as solder), within the perimeter, and then attaching a chip comprising an integrated circuit device to the die attach pad by the conductive material. The clipping device (s) allow increased layer thickness of the conductive material to be used, resulting in increased adhesive layer thickness and increase in durability and performance of the resulting semiconductor package.

BRIEF DESCRIPTION OF THE DRAWINGS

The following description may be better understood in light of the figures, wherein:

1 FIG. 12 illustrates a perspective view of a prior art chip package having a die bonded to a die attach pad of a leadframe. FIG.

2 represents another view of the in 1 shown chip assembly.

3 FIG. 12 illustrates a top view of an exemplary chip package having a limiting device comprising a bonding wire. FIG.

4 represents a sectional drawing of the 3 shown chip assembly is; and

5 FIG. 12 shows a top view of some embodiments of a chip mounting pad including limiting devices formed on top thereof; FIG.

6 FIG. 12 illustrates a top view of some embodiments of a die attach pad with a conductive material formed between the restraints; FIG.

7a and 7b 12 show perspective views of some embodiments of a chip attached to the chip mounting pad with different arrangements of the bonding wire connection points of the limiting device; and

characters 8a and 8b represents details of the bond used to attach the constraining device bonding wire to the die attach pad.

The figures depict certain embodiments of the semiconductor devices and associated methods of making and using such devices. Together with the following description, the figures illustrate and explain the principles of semiconductor devices and related methods. In the drawings, the thickness of layers and regions is exaggerated for clarity. It should also be noted that if one layer is referred to as being "on top" of another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present , The same reference numerals in different drawings represent the same elements and thus their description will not be repeated.

DETAILED DESCRIPTION

The following description provides specific details to provide a thorough understanding. However, it will be understood by those skilled in the art that the apparatus and associated methods of using the apparatus may be employed and used without using these specific details. However, the devices and associated methods may be practiced by varying the illustrated devices and associated methods, and may be used in conjunction with any other devices and techniques conventionally used in the industry. For example, although the following description focuses on chip attachment methods for semiconductor devices and assemblies, the devices and associated methods could also be used for any method or device where a chip is connected to a die attach pad. such as a printed circuit board, MEMS devices, and the like.

An exemplary chip package that is formed using the methods described herein is disclosed in U.S. Patent Nos. 5,496,074, 5,729,877, 5,377,359, and 3,701,635 3 and 4 shown. In 3 includes the chip assembly 200 a chip 210 holding a chip attachment pad 220 through a conductive material 230 is bonded. Limiting devices 240 comprising a bonding wire form a circumference on the chip mounting pad 220 around the chip 210 and the conductive material 230 around. As in 4 shown, the conductive material 230 between the chip 210 and the chip mounting pad 220 with a bond layer thickness (BLT) represented by a thickness t ₂ .

The chip 210 may comprise any type of semiconductor chip known in the art. In some embodiments, the chip comprises a silicon-based substrate comprising any integrated circuit device known in the art. However, in other embodiments, the chip may also be made of GaAs, SiC, GaN, or any other suitable semiconductor material. The substrate and the integrated circuit device may have any desired and required structure to perform any desired function. For example, the chip 210 comprise one or more discrete transistors, diodes or other known integrated circuit device. Thus, the chip can 210 be designed to perform any number of functions, such as current regulation, memory, processing, or any other integrated circuit (IC) function. The chip 210 can be any size required for these functions. For example, in some embodiments, the size of the chip may range from about 100 μm by 100 μm to about 20,000 μm by 20,000 μm.

The chip attachment pad 220 may be part of any lead frame known in the art or may be a separate paddle. Likewise, the chip attachment pad 220 a single chip-mounting pad of a leadframe may be one of a plurality of die attach pads on a leadframe or a plurality of connected leadframes used in semiconductor fabrication. When a leadframe is used, it is formed so as to be in the area of the chip-mounting pad 220 is relatively flat. The leadframe serves as part of the I / O connection system and also provides a heat conduction path for dissipating most of the heat generated by the integrated circuit device in the chip 210 is produced.

The material of the leadframe may comprise any metal, such as copper or a copper alloy. In some examples, if desired, the leadframe may include a metallization layer (not shown). The metallization layer may include an adhesive underlayer, a conductive underlayer and / or an oxidation resistant layer. For example, the leadframe may include a leadframe coating comprising an adhesive underlayer and a wettable / protective underlayer.

The chip 210 and the chip attachment pad 220 can through a conductive material (which forms a layer) 230 be connected to each other. The conductive material 230 may be any conductive material that can bond these two components together. In some embodiments, the conductive material 230 a solder adapted to be used in a chip mounting method. The conductive material 230 may be, for example, a PB-Sn, Au-Sn or other solder. Other solders that can be used as a conductive material can be made from Sn, Ag, and / or PB-Sn-Ag. In some embodiments, the conductive material 230 be an adhesive designed to be used in a chip attachment process. An adhesive conductive material 230 may be a non-conductive or a conductive epoxy such as silver-epoxy.

As in 4 shown includes the chip assembly 200 wire-shaped limiting devices 240 holding an enclosure on the chip mounting pad 220 Form around the area surrounding the conductive material 230 includes. The limiting devices 240 serve to allow for an increased amount of conductive material 230 can be used in the chip mounting process, resulting in a larger BLT. In other words, the limiting devices 240 a raised surface with a sufficient height to make it a boundary for the conductive material 230 form.

4 represents an example of the BLT that can be obtained and is designated by t ₂ . In some embodiments, t ₂ may be up to 30 mils. in other embodiments, this thickness can range from about 4 to 30 mils.

The size of the enclosure, by the limiting devices 240 is determined depends on the size of the chip, and thus on the type of semiconductor device to be manufactured. In some embodiments, the enclosure may have a size of about 100 μm by about 100 μm to about 20,000 μm by about 20,000 μm. And while the enclosure is shown as being substantially rectangular in shape, the shape also becomes of the shape of the chip 210 and thus may be substantially square, circular, triangular or polygonal.

The limiting devices 240 can form a complete or partial boundary. In some embodiments and as in 3 and 4 As shown, the wire bond of the limiting means may be provided to allow complete encasement on the chip mounting pad 220 to build. In further embodiments, the limiting devices 240 be provided to form a partial enclosure, so that about 75% or even 50% or more of the enclosure by the wire bond of the limiting devices 240 is determined.

In some embodiments, the limiting devices may 240 have one or more bond wires connected to the die attach pad 220 can be bonded. In some arrangements and as in 7b 4 bonding wires (such as the wires known to be used to attach a chip to a lead finger) can be attached to the die attach pad 220 be bonded to form the enclosure containing the conductive material 230 will include. In other arrangements, as in 7a shown, a single segment of a bonding wire to different points of the wire are bonded to form the enclosure. In addition, any number of segments of a wire may be bonded to form the wire, as appropriate or necessary to form the enclosure.

Each bonding wire can be attached to the chip mounting pad 220 be attached using any method known in the art. In some embodiments, the bond wire (- (wires) to the die attach thread 220 by a stitch and / or wedge bond to each end as in 8a and 8b shown to be attached. Where longer bond wires are used, one or more stitch and / or wedge bonds may be provided between the ends of the bond wires as needed.

These arrangements described above may be formed using any known method with which the above-described arrangements can be formed. In some embodiments, the chip may be 210 by providing the various electronic components (ie, the transistors) in a semiconductor substrate as known in the art. In further embodiments, the integrated circuits are fabricated, separated, tested, and chip bonded to a substrate, as known in the art.

Next, a leadframe may be formed by any known method, for example, any sheet metal stamping and etching methods. If desired, a metallization layer may be formed on the base metal used in the leadframe by methods such as electroless plating, sputtering or electroplating. Instead, a previously coated leadframe can also be used. The leadframe is made with the chip-pad formed as part of the leadframe 220 produced.

Next, the bonding wire may be attached to the die attach pad 220 be fastened using any known technique. In some embodiments, the limiting devices may 240 be attached using a known in the art bonding wire stitching technique. The bonding wire of the limiting devices 240 Can with the chip attachment pad 220 using any number of connection points (ie, by a stitch or wedge bond 250 , as in 8a and 8b shown). In an example and as in 7b As shown, the bounding device is along the enclosure using a stitch and / or wedge bond 250 connected with several attachment points along the enclosure. In another example, as in 7a As shown, any side of the enclosure may have as many connection points as necessary, including from 4 to 40 stitch and / or wedge bonds.

8a and 8b Figure 11 shows a detailed view of a bond wire stitch that may be used to connect the brad wire of the restrictor to the die attach pad. As is known in the art of wedgewire / stitch wire bonding, the wire will become attached to the die attach pad as shown in FIG 8a shown deformed. 8b shows a sectional view of the bonding wire and its Stichbondbefestigung. The one with the limiting devices 240 The wedge / stitching bond used may be used at any point (s) along the enclosure to provide the required bond for the bond wire.

Next, in the attachment process as in 6 represented the conductive material 230 on the chip mounting pad 220 within through the limiting devices 240 fixed enclosure are deposited. The conductive material may be deposited using any known method until the desired level at which the desired BLT can be provided is achieved. In some embodiments, a chip may be used to seal the conductive material 230 flatten. However, in other embodiments, no chip is used due to the possibility of conductive material 230 out of the by the limiting devices 240 displaced or sprayed out.

Then the chip 210 on the conductive material 230 using any method known in the art. The resulting assembly may then be heated at a sufficient time and temperature that the conductive material 230 melt without the shape of the in the limiting devices 240 used to modify bond wire. During the reflow process, the conductive material becomes 230 forced in by the limiting device 240 to remain established. After the reflow process is completed, the chip becomes 210 on the chip mounting pad 220 through the molten conductive material 230 attached, which has the desired height, but has substantially no voids.

Once the chip package has been formed in this manner, further processing may be performed to produce a semiconductor device. For example, electrical connections may be formed between parts of the integrated circuit device on the chip and parts of the lead fingers using wires, generally a wire bonding method. According to the wire bonding method, a resin body may be formed to shed the chip and the wire bonds. The resulting assembly can then be singulated (and optionally tested) to create a leaded semiconductor package. The assembly leads may then be connected to another electrical device, such as a printed circuit board (or PCB), so that it is electrically connected to the integrated circuit of the chip.

The chip assemblies described above have several advantages. First, higher BIT allows more stable chip assemblies, which reduces the mechanical errors of the chip 210 due to cracking and voids in the conductive material 230 limited. The higher BLT can also lead to increased thermal performance, which is the error rate of the chip 210 limited.

In addition to any changes noted above, numerous other changes and alternative arrangements may be devised by those skilled in the art without departing from the spirit and scope of this specification, and the appended claims are intended to cover such changes and arrangements. Although the information has been carefully described in detail in conjunction with what is presently believed to be the most practical and preferred embodiments, it will be apparent to those skilled in the art that numerous changes, including, but not limited to, form, function, effect and use without departing from the principles and concepts set forth herein. Likewise, the examples used herein are for illustration only and should not be construed as limiting in any way.

Claims (25)

A chip assembly for a semiconductor device, comprising: a leadframe comprising a chip mounting pad; a conductive layer on a portion of the die attach pad, the conductive layer having a layer thickness of up to about 30 mils; a limiting device comprising a bonding wire partially surrounding the conductive layer, both ends of the bonding wires being fixed to the chip mounting pad; and a chip on the conductive layer. The chip package of claim 1, wherein the limiting means completely surrounds the conductive layer. The chip package of claim 1, wherein the limiting means surrounds at least half of the conductive layer. The chip package of claim 1, wherein the conductive layer has a layer thickness ranging from about 4 mils to about 30 mils. The chip package of claim 1, wherein the conductive layer is substantially free of voids between the chip and the die attach pad. The chip package of claim 1, wherein both ends of the bond wire have been attached to the die attach pad using a wedge or stitch bond. The chip package of claim 6, wherein the bonding wire has been affixed to the die attach thread in more than two locations. The chip package according to claim 1, wherein four bonding wires are used to form the limiting means, and both ends of each bonding wire are fixed to the chip mounting pad. Semiconductor device comprising: a leadframe comprising a chip mounting pad; a conductive layer on a portion of the die attach pad, the conductive layer having a layer thickness of up to about 30 mils; a limiting device comprising a bonding wire partially surrounding the conductive layer, both ends of the bonding wires being fixed to the chip mounting pad; and a chip on the conductive layer. The device of claim 9, wherein the limiting means completely surrounds the conductive layer. The device of claim 9, wherein the limiting means surrounds at least half of the conductive layer. The device of claim 9, wherein the conductive layer has a layer thickness ranging from about 4 mils to about 30 mils. The device of claim 9, wherein the conductive layer is substantially free of voids between the chip and the die attach pad. The device of claim 9, wherein both ends of the bond wire have been attached to the die attach pad using a wedge or stitch bond. The device of claim 9, wherein the bonding wire has been secured to the die attach pad at more than two locations. The device of claim 9, wherein four bonding wires are used to form the confining means, and both ends of each band wire are fixed to the chip mounting pad. A method of manufacturing a semiconductor device, comprising: Providing a leadframe comprising a chip mounting pad; Forming a confining means comprising a bonding wire such that both ends of the bonding wire are attached to the chip mounting pad, the limiting means defining a perimeter; Depositing a conductive layer on the die attach pad within the perimeter, the conductive layer having a layer thickness ranging up to about 30 mils; Placing a chip on the conductive layer; and fusing the conductive layer to secure the chip to the die attach pad. The method of claim 17, wherein the fused conductive layer is substantially free of voids between the chip and the die attach pad. The method of claim 17, wherein the conductive layer comprises a material based on a solder. The method of claim 17, wherein the periphery of the restrictor surrounds at least half of the conductive layer. The method of claim 20, wherein the perimeter of the restrictor completely surrounds the conductive layer. The method of claim 17, wherein both ends of the ribbon wire have been secured to the die attach pad using a wedge or stitch bond. The method of claim 17, further comprising attaching the tape to the die attach pad at more than two locations. The method of claim 17, wherein four bonding wires are used to form the confining means, and both ends of each band wire are secured to the chip mounting pad. The method of claim 17, wherein the conductive layer has a layer thickness ranging from about 4 mils to about 30 microns.

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