DE10205706B4 - Control circuit for a switch in a switching power supply - Google Patents

Abstract

Drive circuit for a switch (T1) in a switched-mode power supply,
a supply input (A1) for applying a supply voltage (VCC), a separate control input (A2) for applying a dependent of an output voltage (Vs) of the switching power supply control signal (Vr) and an output terminal (OUT) for providing drive pulses (AI) .
which generates drive pulses (AI) depending on the supply voltage (VCC) and the control signal (Vr) and
which assumes a high power state or a low power state during operation,
characterized in that the
A power supply voltage (VCC) voltage control circuit assumes a low power state between a first threshold value (from) and a second threshold value (Vuv) depending on the supply voltage (VCC) and the control signal (Vr).

Description

The present invention relates to a drive circuit for driving a switch in a switched-mode power supply, in particular in a free-running switched-mode power supply, which has a functionality for reducing the power output at low load, according to the preamble of claim 1 (US Pat. US Pat. No. 5,689,407 ).

The basic function of such a drive circuit, which is, for example, an integrated circuit of the type TDA 16846 of the Applicant, will be described below for better understanding with reference to FIG 1 explained.

1 shows the basic structure of a switching power supply with a drive circuit CON, which drives a connected in series with a primary coil Lp of a transformer TR, formed in the example as a MOSFET switch T1. A secondary-side coil Ls of the transformer TR is usually followed by a rectifier arrangement Ds, Cs, which takes over the supply of a load Rl with an output voltage Vs, wherein the load in 1 is formed by an ohmic resistor R1.

The task of the switching power supply, it is in a well-known manner, a primary side available supply voltage Vp, in the example according to 1 is generated by a bridge rectifier BR and the bridge rectifier BR downstream capacitor C1 from an AC voltage to convert into an approximately load-independent output voltage VS.

Lots Consumers supplied by such switching power supplies can a high power consumption state (normal operation) and a State of low power consumption (stand-by mode) assume. Examples of this are television sets and other devices the consumer electronics but also household appliances.

Of the completeness it should be mentioned, that with high power consumption of the consumer and with steady Operation of the switching power supply the frequency with which the switch T1 is respectively turned on and / or the time duration for which the switch T1 remains actuated, varies depending on the load, over the from the primary side transmitted to the secondary side Power to regulate the output voltage Vs. The energy that the primary coil Lp with the switch T1 is closed and then opened Switch T1 to the secondary side is, is given by the predetermined by the drive signal AI Duty cycle of the switch T1 dependent, the power consumption increases with time, for which the switch T1 remains closed. The switching frequency of the switch T1 and the duration of the drive periods of the drive pulses is during the steady state depending on a control signal Vr supplied to the drive circuit CON, and that of the output voltage Vs dependent is.

The Power supply of the drive circuit CON is during the steady state over taken over an auxiliary winding Lr of the transformer TR, with the switch open T1 a part of the previously absorbed by the primary coil Lp energy over a Diode D1 is supplied to a capacitor C2, which is connected to a supply voltage terminal A1 supplied to the drive circuit is.

To turning on the switching power supply when the power supply capacitor C2 is uncharged and because of a lack of supply voltage still no control of the switch T1 can be done to the capacitor C2 about the Charge auxiliary winding Lr, there is a charging of the capacitor C2 directly through the primary voltage Vp over a resistor R1. A permanent power supply over this Opposition R1 is, however, because of the occurring high losses undesirable.

The known drive circuit CON is adapted to first drive pulses for the switch T1 to produce when the supply voltage is an upper threshold achieved, for which purpose the drive circuit CON in a high state Power consumption passes, around the internal to the generation of the drive pulses AI circuit components sufficient to provide. The current consumption in the state of high power consumption exceeds while the over the starting resistor R1 supplied power, so that the above the storage capacitor applied supply voltage VCC initially drops until over the Primary coil Lp and the auxiliary winding Lr enough energy to the capacitor C2 transmitted becomes.

After reaching the upper threshold value of the supply voltage VCC, drive pulses are generated in the burst mode by the known drive circuit CON, that is to say drive pulses which are each equally long and evenly spaced. This burst mode is maintained until the secondary side a certain output voltage Vs ereicht and the above-explained control of the output voltage Vs starts in the steady state. If the output voltage Vs exceeds a predetermined maximum value, for example, if no load or a Load is connected with only low power consumption, so the further generation of drive pulses is interrupted by the control signal Vr, in the illustrated example, the maximum output voltage Vs is given by the breakdown voltage D2 a Zener diode in the breakdown through an optocoupler to a control input A2 connected capacitor C3 discharges, over which the control voltage Vr is applied. This control voltage Vr is evaluated in the drive circuit CON in a manner not shown in order to prevent the generation of drive pulses in burst mode when falling below a predetermined threshold value.

moreover is the drive circuit CON designed to be a lower state To accept power consumption when the supply voltage VCC is below has dropped a lower threshold at which a supply the circuit components generating the drive pulses are not more guaranteed is, wherein the current consumption of the drive circuit CON in the state low line overhead the resistor R1 from the primary voltage Vp can be covered.

These properties of the drive circuit CON, namely the generation of drive pulses in the burst mode after reaching an upper threshold value of the supply voltage VCC and the associated transition to a high power state, the prevention of the generation of drive pulses when falling below a lower threshold of the control signal Vr and the Transition to a state of low power consumption falls below a lower threshold of the supply voltage VCC are used in known drive circuits for the power supply of loads with low power consumption, in particular of loads in stand-by mode, as in 2 is explained with reference to temporal profiles of the supply voltage VCC, the drive pulses and the control signal.

First, will assumed that the capacitor C2 uncharged and the supply voltage VCC is zero accordingly. The supply voltage VCC increases after providing the primary voltage Vp slowly by the capacitor C2 is charged via the resistor R1. Over a Power source connected to the power supply terminal A1 CS1 is also the capacitor C3 charged at the control input A2, this capacitor is usually a lower capacity as the capacitor C2 and to a lower voltage when this capacitor is charged, so that the control voltage Vr quickly reaches an upper value.

Reached the supply voltage VCC at time t10 has an upper threshold V1, the drive circuit increases its power consumption a lower value to an upper value and starts drive pulses to generate in burst mode. The supply voltage VCC begins decrease, since the current consumption of the drive circuit CON is higher as the over the resistor R1 delivered power and initially only a little energy over the Auxiliary winding Lr is provided. In the example shown the power transferred to the secondary side in burst mode is greater than the power absorbed by the load RL, so that the output voltage increases until the breakdown voltage of the Zener diode reaches D2 and the capacitor C3 discharged at the control input via the optocoupler OC1 becomes. In this case, the control voltage Vr reaches a point at time t20 lower threshold, so will the generation of drive pulses AI finished. The power supply of the drive circuit then takes place exclusively about the resistance R1. Since the drive circuit, the state of high power consumption however, it keeps decreasing the supply voltage continues because the delivered power is not sufficient to cover the power consumption.

The Supply voltage VCC decreases until it is at the time t30 reaches a lower threshold V2 and the drive circuit goes into a low power state for which the power supplied through the resistor sufficient so that the supply voltage VCC starting from the time t30 rises again until it reaches the upper threshold again.

This Cycle continues until the power consumption of the load RL increases, for example, when the load switches from stand-by mode to normal mode and while transmitted in burst mode Power is insufficient to adjust the output voltage Vs to a value above the breakdown voltage of the zener diode D2.

A disadvantage of this known drive circuit is that the time that elapses between the times when the drive circuit CON goes into the high power state to generate drive pulses in the burst mode, and to which energy is transferred to the secondary side to the variable load RL, depending on the primary voltage Vp can be very long, resulting in a strong ripple of the output voltage Vs. A shortening of this period of time can be achieved if the charging resistor R1 is reduced, but this leads to increased power loss in continuous operation. If one increases the value of the supply voltage at which the drive circuit returns to the state of low power consumption and the Voltage V2 in 2 corresponds, there is a risk that the drive circuit switches off again even with small fluctuations in the supply voltage.

In the publication "The TOP210, TOPSwitch ^® Family, Three-terminal Off-line PWM Switch" Power Integrations, February 1996, an integrated control circuit for a switching power supply is described which includes a power transistor and a control circuit for this power transistor. This drive circuit controls the power transistor clocked when their supply voltage reaches or exceeds an upper threshold. The clocked control of the power transistor is interrupted again as soon as the supply voltage has dropped below a lower threshold.

In the US 5,689,407 A a drive circuit for a switching power supply is described, which can be operated in a standby mode. In standby mode, the drive circuit begins to generate drive pulses for a power transistor when the supply voltage of the drive circuit has reached an upper threshold while the drive of the power transistor is interrupted when the supply voltage has dropped to a lower threshold value. The transition of the drive circuit in the standby mode is carried out in accordance with an externally applied to the control circuit standby signal.

Of the The present invention is based on the object, a drive circuit and a driving method for To provide a switch in a switching power supply, which has a functionality for reduction the power output at low to an output of the power supply connected load and at the ripple of the output voltage reduced at a low connected to the switching power supply load is.

These The object is achieved by a drive circuit according to the features of claims 1 and 16 and a method according to claim 14 solved. Advantageous embodiments The invention are the subject of the dependent claims.

The Drive circuit according to the invention for a Switch in a switching power supply includes a supply input for applying a supply voltage, a control input for creating a from an output voltage of the switching power supply dependent control signal and an output terminal for providing drive pulses, wherein the drive circuit dependent from the supply voltage and the control signal drive pulses for the Switch generated and while of operation, a high power consumption state or a state low power consumption. According to the invention Drive circuit adapted to be dependent on the supply voltage and the control signal, the high power state or the State of low power consumption adopts.

The Drive circuit according to the invention in particular designed such that it depends on the value of the supply voltage and the control signal generates drive pulses whose duration is determined by the Value of the control signal dependent or whose duration is independent of the value of the control signal, the latter mode of operation hereinafter referred to as burst mode becomes. The generation of drive pulses whose duration depends on the value independent of the control signal is (burst mode), begins when the supply voltage reaches a first threshold has reached the supply voltage, and the generation of drive pulses, whose duration is independent of the value of the control signal, d. H. the burst mode ends when the control signal reaches a first threshold of the Has reached control signal.

The Drive circuit is also, for example, designed such that upon reaching a first threshold, in particular an upper threshold Threshold, the supply voltage, the state of high power consumption assumes that they reach a second threshold, in particular a lower threshold, the supply voltage a state low power consumption, and that it is a condition low power consumption when the control signal is a first threshold, usually has reached a lower threshold, and the supply voltage a third, between the first and second threshold of the supply voltage lying threshold has reached.

The drive circuit is thus already in the state of low power consumption, in which an increase in the supply voltage until the generation of the next drive pulses or until the next transition to a state of high power consumption, if it is clear from the control signal that a small load on the secondary side connected. The difference between the first threshold value and the third threshold value of the supply voltage is preferably substantially smaller than the difference between the first threshold value and the second threshold value of the supply voltage, so that, in the case of the switched-mode power supply according to the invention, the time periods, during which no drive pulses are generated in the burst mode, are significantly shorter, which contributes to a reduction in the ripple of the output voltage.

The inventive drive circuit has according to one embodiment a pulse generating circuit coupled to the output; an on and off signal is supplied, that of the supply voltage and the control signal dependent is, and that the pulse generating circuit on and off or for the generation of drive pulses releases. Is the pulse generation circuit switched on, the drive circuit is in the high state Power consumption, the pulse generating circuit is switched off, the drive circuit is in the state of low power consumption. The on and off signal switches in one embodiment the pulse generating circuit for the generation of drive pulses when the rising supply voltage reached an upper value of the supply voltage, and the input and OFF signal switches the pulse generation circuit for generation of drive pulses when the supply voltage is at the lower threshold the supply voltage is reached or if the supply voltage reaches the middle threshold of the supply voltage and the control signal reaches the lower threshold of the control signal.

Of the Pulse generation circuit is still the one in one embodiment Control signal and a selection signal supplied, wherein the selection signal the pulse generating circuit for the generation of drive pulses whose duration depends on the control signal dependent is or whose duration is independent of the control signal releases. The release signal thus puts the pulse generating circuit in burst mode or normal operation. The selection signal switches the Pulse generation circuit from burst mode to normal operation, if the control signal for a predetermined period of time after the supply voltage to the upper Threshold has reached the lower threshold of the control signal did not fall below.

Preferably the drive circuit further has a supply input coupled current overflow circuit on, which continues to be a terminal for a supply potential is connected and which limits the increase of the supply voltage, so independent from the primary voltage to achieve a constant increase in the supply voltage.

The The present invention will be described below in exemplary embodiments with reference to FIG Figures explained in more detail. In the figures shows

1 a basic structure of a free-running switching power supply with a drive circuit for controlling a switch,

2 Time profiles of a supply voltage, of drive pulses and of a control signal in a drive circuit according to the prior art,

3 Circuit components of a drive circuit according to the invention, which serve to regulate the power consumption of the drive circuit and to generate drive pulses,

4 exemplary temporal courses of the in 3 designated signals,

5 First embodiment of a current overflow circuit for a drive circuit according to the invention,

6 Second embodiment of a current overrun circuit for a drive circuit according to the invention.

In denote the figures, unless otherwise indicated, like reference numerals same parts with the same meaning.

With regard to the basic structure of a switching power supply and the function of a drive circuit for driving a switch in a switching power supply is to the description 1 referenced, which can also be used for the following description, since the external circuitry of the drive circuit does not differ from known drive circuits.

3 shows an embodiment of a drive circuit according to the invention, in particular the components are shown, which are available for a power supply of a low load, in particular a load in stand-by mode. The external circuit of the drive circuit corresponds to the drive circuit according to 1 so that the terminals are labeled accordingly and in this regard to the description 1 is referenced.

The in the embodiment according to 3 A driving circuit CON comprises a pulse generating circuit LR which controls the control signal Vr applied to the input terminal A2, an ON / OFF ON / OFF signal and a selection signal BURST is supplied. An output OUT 'of the pulse generating circuit LR is coupled via an AND gate G3 to be explained and an output driver AT to the output OUT of the drive circuit CON.

Of the Structure and operation of the pulse generating circuit LR can the structure and operation of a conventional pulse generating circuit of this kind, for example, in the drive circuit of the type TDA 16846 of Applicant correspond.

The Pulse generating circuit LR generates in accordance with the selection signal BURST Drive pulses AI ', their duration and / or mutual time interval in normal operation dependent on the control signal Vr is or drive signals in the burst mode, preferably each have the same duration and in which two temporally adjacent drive pulses each have the same time interval. drive pulses, their time interval and / or their duration from the Control signal Vr dependent is, be for the steady state of the switching power supply or supply greater Loads needed. Drive pulses in burst mode are used during the start-up phase and during the Supply of small loads, especially loads in stand-by mode generated.

at the drive circuit according to the invention the delivery of drive pulses AI at the output OUT is prevented, when the control signal Vr is smaller than a lower threshold Vru of the control signal Vr becomes. For this purpose, a first comparator K1 is present, the voltage applied to the input terminal A1 control signal Vr with the lower threshold Vru, which exemplifies a Value of 2V is assumed. If the control signal Vr falls below the Value of the lower threshold Vru, so is the output of the first Comparator K1 is a logic high level available to the comparator K1 downstream RS flip-flop FF3 sets. An output signal of this Flip-flops FF3 will be an inverting input of the already above mentioned And G3 gates fed.

Regardless of whether the drive pulses AI 'are pulses during the burst mode or during the steady state, the drive pulses AI' amplified by the output driver AT are output as output pulses AI, if the RS flip-flop FF3 is not set, ie when the control signal Vr is greater than the lower threshold Vru. As already explained above, a control signal Vr falling below the lower threshold value Vru indicates a secondary voltage Vs greater than a maximum allowable value, this permissible value referring to FIG 1 is given by the breakdown voltage of the zener diode D2. In this case, no further drive pulses Ai are to be generated in order to prevent a further power output to the secondary side and thus a possible further increase of the output voltage Vs.

The On and off signal ON / OFF is determined by the output signal another RS flip-flop FF2. This flip-flop FF2 is set by a second one Comparator K2, whose plus input is applied to the input A1 supply voltage VCC and its minus input an upper threshold signal from is supplied. The flip-flop FF2 is thus set when the supply voltage VCC the value of the upper threshold signal from, for example 12V is reached, thereby obtaining the pulse generating circuit Turn on LR, wherein the drive circuit CON when turned on Pulse generating circuit LR a state of high power consumption accepts. This results from the increased power consumption, the the pulse generating circuit LR in the on state for generation the drive pulses AI 'needed.

The Pulse generating circuit LR is turned off when the RS flip-flop FF2 reset becomes. On the one hand, this happens when the supply voltage VCC is at or below the value of a lower threshold signal Vuv, that is assumed in the example to 8V, has dropped. These are the supply voltage VCC a minus input and the lower threshold signal Vuv, which is assumed to be 8V by way of example, a positive input of a supplied to another comparator K4, wherein the output of this further comparator K4 via a Or gate G2 the reset input R of the RS flip-flop FF2 supplied is.

The On the other hand, RS flip-flop FF2 is then reset to the pulse generating circuit LR off when the flip-flop FF3 is set when the control signal Vr is below the value of lower threshold signal Vru has dropped and if the supply voltage VCC below the value of a mean threshold signal Voff, the in the example it is assumed to be 11.9V and that between the upper one Threshold signal From and the lower threshold signal Vuv lies, has sunk. This is the reset input of the flip-flop FF2 is supplied to an output signal of an AND gate G1 whose an input, the output signal of the flip-flop FF3 is supplied and the other input an output signal of another comparator K3 supplied is, wherein at the plus input of the further comparator K3 the middle Threshold signal Voff of the supply voltage VCC and at the Minus input of the other comparator K3 the supply voltage VCC is applied.

The Difference between the first threshold signal Von and the middle one Threshold signal Voff is much smaller than the difference between the first threshold signal of and the lower threshold signal Vuv and amounts in the example only 12.5% of the difference between the upper one and lower threshold signal Von or Voff.

The Selection signal BURST, which determines whether drive pulses AI 'in burst mode or in Normal mode, so dependent from the control signal Vr, is determined by the output signal another RS flip-flop FF1. This flip-flop FF1 is connected via an edge detector ED1 set when the on and off signal a logic high level assumes, therefore, if the RS flip-flop FF2 is set, because the supply voltage VCC has reached the value of the upper threshold signal Von. The RS flip-flop FF1 is reset, to the pulse generating circuit LR in the normal operation - in which the drive pulses AI 'depending on the control signal Vr are generated - to switch after the On and off signal for maintain a logical high level for a predetermined period of time Has. For this purpose, the on and off signal is an input TEN one counter T supplied, with the presence of a rising edge, the on and off signal each starts counting at one output value and then one logical high level outputs at its output TO to the flip-flop Reset FF1, if the signal present at the input TEN until reaching a Counter end value has maintained a high level.

The operation of the drive circuit according to the invention 3 is described below by means of 4 explained in which 4 temporal courses of selected signals according to 3 are shown. 4 shows the time courses for two different external circuits of the drive circuit namely in the left part for a secondary side voltage reduction in stand-by mode, in which the secondary voltage Vs is limited to an upper threshold value Vse of 8V, for example, and in the right part for operation without secondary side Voltage drop, in which the secondary-side voltage Vs is limited to an upper threshold value Vse of example 16V. The voltage reduction can be realized in a manner not shown in that depending on the power consumption of the connected load different maximum output voltages Vs are allowed until a lowering of the control signal Vr, ie a discharge of the control capacitor C3 takes place. The basic mode of operation of the drive circuit according to the invention is independent of whether a voltage reduction is to be achieved by the external wiring or not, only the time courses of the occurring signals change.

First of all the operation with secondary voltage reduction shown in the left part:
If the RS flip-flop FF2 is reset and thus the pulse generating circuit LR is switched off, the current taken from the supply capacitor C2 is lower than the current supplied downstream via a starting circuit to the supply capacitor VCC, this starting circuit, which is in 1 shown start-up circuit with a resistor R1 or one in the 5 and 6 can still correspond to start-up circuit to be explained. Power supply inputs of the individual components in 3 , which take power from the supply capacitor C2 are, for reasons of clarity in 3 not shown. After the current supplied to the supply capacitor C2 is larger than the extracted current, the supply margin VCC increases as long as the pulse generation circuit LR is off with the RS flip-flop FF2 reset. If the supply voltage VCC reaches the value of the upper threshold signal at a time t1, the RS flip-flop FF2 is set via the output signal K2out of the comparator K2, so that the output signal QFF2 of this flip-flop FF2 assumes a high level to turn on the pulse generating circuit LR. The current consumption of the processing circuit CON is now greater than that supplied downstream in the supply capacitor C2 via the starting circuit, so that the supply voltage VCC drops.

With the switching on of the pulse generating circuit LR, these drive pulses AI 'are generated in the burst mode, ie comparatively short drive pulses which are evenly spaced. The RS flip-flop FF1, which sets the burst mode of the pulse generating circuit LR in the set state, has already been set at the first rising edge of the on and off switching signal ON / OFF or the signal QFF2. The RS flip-flop FF3 is reset to the turn-on of the pulse generating circuit LR by the low state of the output signal QFF2 of the RS flip-flop FF2 and set at time t2 to prevent the delivery of drive pulses AI at the output terminal OUT At time t2, the control signal Vr has dropped to the value of the lower threshold signal Vru. The decrease of this control signal Vr results with reference to FIG 1 from the fact that with the activation of the switch T1 in the burst mode, energy is transmitted from the primary side to the secondary side and the power absorbed on the secondary side by the load Rl is lower than the power transmitted during the burst mode. The secondary-side voltage Vs increases until it reaches a maximum value Vse, which is determined for example by the breakdown voltage of the zener diode D2. At this time, the control capacitor C3 is discharged across the optocoupler OC1, so that the control voltage Vr, which was previously maintained via a current source CS1 coupled to the supply input A1, decreases.

To the time t2 at which the control signal Vr the lower threshold Vru, the RS flip-flop FF2 is reset to the pulse generating circuit LR off. The flip-flop FF2 is now reset because already before Time t2, the supply voltage VCC below the value of the middle Threshold signal Voff had dropped.

at the drive circuit according to the invention the pulse generating circuit LR is then already turned off or the drive circuit CON goes into a low power state as soon as the control signal Vr reaches a predetermined lower threshold and once the supply voltage reaches a threshold between a high threshold and a lower threshold, the upper threshold being the turning on of the pulse generating circuit LR or the state of high power consumption recording of the drive circuit certainly. The time periods between which drive pulses in burst mode in the drive circuit according to the invention be produced, is thus much shorter than conventional such drive circuits, in which with the turn off the pulse generating circuit exclusively depending on the supply voltage VCC Waiting until the supply voltage VCC except for the lower threshold Vuv has dropped. The lower threshold essentially serves as undervoltage protection in the event of an overload at the output terminals of the power supply.

Now on the time course with external wiring without secondary voltage reduction, in the right part of 4 is shown:
The pulse generating circuit LR is turned on at the time t3 when the supply voltage VCC reaches the value of the upper threshold signal Von. Due to previously occurring clock cycles is on the secondary side Vs to a voltage that is initially greater than the supply voltage VCC, so with reference to 1 the supply capacitor C2 rises abruptly to a higher value via the auxiliary winding LR of the transformer TR, wherein the supply capacitor C2 is charged further with each further clock cycle of the burst mode, so that the supply voltage VCC and the output voltage Vs with each clock cycle of the drive pulses in the BURST Mode continues to increase. At time t4, the secondary-side voltage Vs reaches a maximum value Vse, which is assumed to be 16V in the example, so that at this time the control capacitor C3 is discharged and the control signal Vr drops to the lower threshold Vru, whereby the flip-flop FF3 the further Dispensing of drive pulses to the output terminal OUT prevented. The pulse generating circuit LR remains turned on, so that the drive circuit CON remains in the high power state, whereby the supply voltage VCC decreases, since the supply capacitor C2 now exclusively via a drive circuit, for example via the resistor R1 according to FIG 1 , and no longer charged via the auxiliary winding Lr. The pulse generating circuit LR is turned off when the output voltage Vcc reaches the value of the middle threshold signal Voff at time t5. In contrast to the example with a secondary-side voltage reduction shown on the left, in this example the supply voltage VCC reaches the value of the average threshold signal Voff only after the time when the control signal Vr has dropped to the value of the lower threshold signal Vru.

Of the next Clock cycle begins at time t6 when the supply voltage VCC again increased to the value of the upper threshold signal Von is after the drive circuit CON at time t5 the state low power consumption.

From At time t6, it is now assumed that the output side the switching power supply connected load is so large that the transmitted during the burst mode Power is insufficient to quickly raise the output voltage VS the value of the maximum allowed Output voltage Vse increase. At time t7 sets the counter T the RS flip-flop FF1 back and switches the pulse generating circuit LR to the normal mode, in which the drive pulses AI are generated, the duration of dependent on the control signal Vr is.

The operation of the counter T is also in 4 where Tout represents the output of the counter and Tcount represents an internal counter signal. This internal counter signal assumes a high level each time the RS flip-flop FF2 is set to turn on the pulse generating circuit LR. However, the output signal Tout assumes a high level only when the internal signal Tcount has maintained a high level for a sufficiently long time.

After switching is in the example according to 1 , in which, as previously explained, the An Control circuit CON a conventional drive circuit, but also an inventive with reference to the 3 and 4 can be explained drive circuit, the voltage supply of the drive circuit during start-up ensured by a resistor R1, which is connected between the supply terminal A1 and a capacitor C1, to which the primary voltage Vp applied.

As already explained, is the speed at which capacitor C2 is charged is, from the value of the primary voltage Vp dependent. Of this, therefore, the time is dependent, the minimum between two clock cycles in burst mode.

At an in 5 illustrated embodiment of the drive circuit CON according to the invention, a current overflow circuit is provided which limits the current flowing to the supply capacitor C2 current to a maximum value. In the embodiments according to the 5 and 6 only these overcurrent circuits are shown on the in 3 illustrated circuit components, of course, in a corresponding manner between the in the 5 and 6 Plotted connections are connected, is omitted for reasons of clarity.

The overflow circuit according to 5 includes a resistor R2 connected to the supply terminal, which drives the base-emitter path of a PNP bipolar transistor T2. The bipolar transistor T2 limits the maximum current flowing to the supply capacitor C2 charging current Ich and derives the excess current via a transistor connected as a diode T3 to reference potential GND.

Resistor R2 is preferably connected to an input A3 for a primary current replica, which is usually present anyway in such drive circuits CON, where the external wiring of this input A3 has a resistor R3 between the input A3 and the primary voltage Vp and a capacitor C4 between the input A3 and reference potential GND provides. For the evaluation of the voltage applied to the input A3 primary current simulation signal an evaluation PCM is present, but will not be discussed in more detail below. Since an external resistor R3 is required anyway for the primary current simulation, when using the overflow current circuit according to the invention according to 5 to an external resistor (R1 in 1 ) can be omitted as a start-up circuit.

6 shows a further embodiment of an overflow current circuit according to the invention, in addition to the resistor R2 comprises an operational amplifier OA1, which compares the voltage across the resistor R2 voltage with a reference voltage VS1 and the part of the current flowing in the supply line I3 via a driven by the operational amplifier OA1 transistor T3 to reference potential GND derives when the charging current I has reached a dependent on the reference voltage VS1 maximum value.

A1, A2

input terminals

AT

output driver

BR

Bridge rectifier

C1, C2, C3

capacitors

C4

capacitor

CON

drive circuit

Cs

capacitor

CS1

power source

D1

diode

D2

Zener diode

ds

diode

FF1, FF2, FF3

RS flip-flop

G1, G3

And gate

G2

OR gate

GND

reference potential

I

charging current

K1, K2, K3, K4

comparators

Lp

primary coil

Lr

auxiliary winding

LR

Pulse generating circuit

ls

secondary coil

OA1

operational amplifiers

OC1

optocoupler

OUT

output terminal the drive circuit

R1

resistance

R2, R3

resistance

rl

load

T1

Switch / transistor

T2

PNP bipolar transistor

T3, T4

NPN bipolar transistor

TR

transformer

VCC

supply voltage

vp

primary voltage

Vr

control signal

vs

secondary voltage

VS1

Reference voltage source

Claims (17)

Control circuit for a switch (T1) in a switched-mode power supply having a supply input (A1) for applying a supply voltage (VCC), a separate control input (A2) for applying a control signal (Vr) dependent on an output voltage (Vs) of the switched-mode power supply and an output terminal (OUT) for providing drive pulses (AI), which generates drive pulses (AI) as a function of the supply voltage (VCC) and the control signal (Vr) and which assumes a high power or low power state during operation, characterized in that the supply voltage (VCC) control circuit (CON) ) assumes the low power state between a first threshold value (from) and a second threshold value (Vuv) depending on the supply voltage (VCC) and the control signal (Vr). Drive circuit according to claim 1, which upon reaching a first threshold value (Von) of the supply voltage (VCC) assumes the state of high power consumption when reaching a second Threshold value (Vuv) of the supply voltage (VCC) a state low power consumption and low power consumption assumes when the control signal (Vr) has a first threshold (Vru) has reached and the supply voltage (VCC) a third, between the first and second thresholds (From, Vuv) threshold (Voff) has reached. Drive circuit according to one of claims 1 or 2, the dependent from the value of the supply voltage (VCC) and the control signal (Vr) generates control pulses (AI) whose duration depends on the value of the Control signal (Vr) dependent or whose duration is independent of the value of the control signal. A drive circuit according to claim 3, which is the generation of drive pulses (AI) whose duration depends on the value of the control signal (Vr) independently is, when the supply voltage (VCC) starts the first threshold (From) the supply voltage is reached, and the generation of Driving pulses whose duration depends on the value of the control signal (Vr) independently is finished when the control signal (Vr) to the first threshold (Vru) of the control signal has dropped. A drive circuit according to claim 3 or 4, which is the Generation of drive pulses whose duration depends on the value of the control signal dependent is, starts when the control signal (Vr) for a predetermined period of time has not reached the first threshold after the rising threshold Supply voltage (VCC) the first threshold value (of) the supply voltage has reached. Drive circuit according to one of the preceding claims, which a pulse generating circuit (LR) coupled to the output (OUT) having an on and off signal is supplied (on / off), which depends on the supply voltage (VCC) and the control signal (Vr), and the pulse generating circuit (LR) for generating drive pulses (AI) releases. Drive circuit according to Claim 6, in which the input and turn-off signal (on / off), the pulse generating circuit (LR) for the Generation of drive pulses (AI) releases when the supply voltage (VCC) reaches the first supply voltage threshold (VCC). Drive circuit according to claim 6 or 7, wherein the on and off signal (On / Off) the pulse generating circuit (LR) for generating driving pulses (AI) turns off when the supply voltage (VCC) exceeds the second threshold of the Supply voltage (VCC) reached or when the supply voltage (VCC) reaches the third threshold (Voff) and the control signal (Vr) reaches the first threshold. Drive circuit according to one of claims 6 to 8, in which the pulse generating circuit (LR) the control signal (Vr) and a selection signal (BURST) are supplied, wherein the selection signal (BURST) the pulse generation circuit (LR) for the generation of drive pulses (AI) whose duration depends on the control signal (Vr) or whose duration depends on independent of the control signal is free. A drive circuit according to claim 9, wherein the selection signal (BURST) the pulse generation circuit (LR) for the generation of drive pulses (AI), the duration of which depends on the control signal, releases if the Control signal (Vr) for a predetermined period of time after the supply voltage (VCC) reaches the first supply voltage threshold (VCC) has not reached the first threshold (Vru) of the control signal. Drive circuit according to one of the preceding claims at an output signal (AI ') of the Pulse generating circuit (LR) depending on the control signal (Vr) on the output (OUT) of the drive circuit is coupled. Drive circuit according to one of claims 2 to 5, at which the first threshold value (Von) of the supply voltage (VCC) is an upper threshold at which the second threshold (Vuv) of the supply voltage (VCC) is a lower threshold and wherein the first threshold value (Vru) of the control signal (Vr) is a lower threshold. A drive circuit according to any one of the preceding claims, comprising a current override circuit coupled to the supply input (A1) and further connected to a terminal for a supply supply potential (Vp) is coupled. Method for controlling a switch (T1) by means of a drive circuit (CON) in a switching power supply depending on a supply voltage (VCC) and a separate control signal (Vr), wherein the drive circuit (CON) a high power consumption state or assumes a low power state by characterized in that the drive circuit (CON) for values the supply voltage (VCC) between a first threshold (From) and a second threshold (Vuv) depending on the supply voltage (VCC) and the control signal (Vr) in the low power state is switched. The method of claim 14, wherein the drive circuit (CON) upon reaching a first threshold value (Von) of the supply voltage (VCC) is switched to the high power state when it reaches a second threshold value (Vuv) of the supply voltage (VCC) is switched to the low power state, and is switched to a low power state when the control signal (Vr) has reached a first threshold value (Vru) and the supply voltage (VCC) a third, between the first and second threshold (Von, Vuv) threshold (Voff) has reached. Control circuit for a switch (T1) in one Switching power supply, the one supply input (A1) for applying a supply voltage (VCC), a separate control input (A2) for applying one of an output voltage (Vs) of the switching power supply dependent Control signal (Vr) and an output terminal (OUT) to provide of drive pulses (AI), depending on the supply voltage (VCC) and the control signal (Vr) generates drive pulses (AI), the while operation, a high power consumption state or a state low power consumption, and the on reaching a first threshold value (of) the supply voltage (VCC) the high power state and when a second threshold is reached (Vuv) assumes the state of low power consumption, thereby marked that the Control circuit (CON) for values the supply voltage (VCC) between a third threshold (Voff) and the second threshold (Vuv) depending on the control signal (Vr) the State of low power consumption adopts. A drive circuit according to claim 16, suitable for values the supply voltage (VCC) between the second and third threshold (Vuv, Voff) assumes the state of low power consumption when the control signal (Vr) has reached a first threshold value (Vru).