DE102022209804A1 - Method for producing semiconductor components, and a semiconductor component - Google Patents

Abstract

Method for producing a plurality of vertical semiconductor components (104), in particular power semiconductor components, from a wafer (100), wherein the wafer (100) in the initial state has a vertical layer structure (108) made of a substrate layer (61), a compensation layer (13), in particular to compensate for different crystal lattices and/or thermal expansion coefficients of the layer structure (108), and at least one semiconductor layer (110), wherein the wafer (100) can be divided along separating sections (106) for producing the large number of individual semiconductor components (104).

Description

Technical area

The invention relates to a method for producing a large number of semiconductor components from a wafer and a semiconductor component according to the invention. In the initial state, the wafer has a vertical layer structure consisting of a substrate layer, a compensation layer, in particular for compensating for different crystal lattices and/or thermal expansion coefficients of the layer structure, and at least one semiconductor layer. The wafer can be divided along separating sections in order to produce the large number of individual semiconductor components.

State of the art

It is generally known that semiconductor components can be manufactured on a large scale using wafer substrates using known manufacturing processes from clean room or microsystem technology. In order to reduce manufacturing costs, ever larger wafers are being used, with silicon (Si) wafers being particularly suitable for this purpose and also being suitable for standardized use in automated manufacturing systems.

Preferred semiconductor components, in particular diodes or transistors, are based on gallium nitride (GaN) as a preferred material system or substrate material, which offer the possibility of producing components with lower on-resistances and at the same time higher breakdown voltages than comparable components based on silicon or Silicon carbide.

Components with a vertical layer structure in which the current flows from a front to a back of the component are particularly advantageous, since these enable an improved breakdown voltage, a small size and an improved electrical field distribution inside the component. For a vertical heteroepitaxial growth of GaN layers on a cost-effective Si substrate, compensating layers, in particular insulating intermediate layers or so-called buffer layers, are necessary to adapt lattice mismatches between GaN and Si layers, as well as to reduce substrate curvature due to internal stresses. The compensation layer itself is mechanically designed in such a way that at room temperature it just compensates for the tension in the layer structure through different thermal expansion coefficients.

To make contact on the rear side of the semiconductor component, in particular a drift zone, the mostly insulating compensation layer is partially removed together with the Si substrate layer through depressions, so-called trenches. The semiconductor layers are partially detached from the substrate layer and thus form a thin membrane with limited stability. Such vertical semiconductor components are known in particular as trench MOSFETs. For example, such a vertical semiconductor component is used in the DE 10 2020 215 006 A1 described by the applicant.

However, the previously mentioned rear processing can lead to the effect of the compensation layer being lost and residual stresses leading to deformation and damage to the semiconductor layers. In particular, in a subsequent separation process of the semiconductor components by sawing or laser dicing processes, further damage, in particular to the thin exposed membrane, can occur and/or a negative influence on operating parameters.

Disclosure of the invention

The method according to the invention for producing a large number of semiconductor components from a wafer with the features of claim 1 has the advantage that the method prevents or at least reduces stresses within the semiconductor layer and thus enables distortion-free backside processing of the wafer, in particular at elevated temperatures, and thus prevents damage to the semiconductor layer. For this purpose, the teaching of the invention in its most general form suggests that in separating sections between individual semiconductor components, vertical first depressions are created in a front side of the wafer, which penetrate the at least one semiconductor layer, and preferably the compensation layer, before the wafer is processed on a back side becomes.

The invention has recognized that by introducing the first depressions during a first method step, the at least one semiconductor layer on the front side of the wafer is divided and as a result there is no longer a coherent, strained semiconductor layer. This means that internal stresses within the layer structure or temperature-dependent tensions can be avoided or at least reduced. For example, distortion can also be avoided if the substrate material is structured on the back in a subsequent second process step and the compensation layer can therefore no longer compensate for internal stresses. The method according to the invention thus enables a particularly cost-effective production of semi-lead terbauelemente on Si substrates, whereby known clean room manufacturing processes, especially for Si substrates, can still be used.

Advantageous developments of the method according to the invention for producing a large number of semiconductor components from a wafer are listed in the subclaims.

• In einer bevorzugten Ausführungsform werden die ersten Vertiefungen zusätzlich zu der zumindest einen Halbleiterschicht in der Ausgleichsschicht und angrenzend an die Ausgleichsschicht in der Substratschicht eingebracht.

With regard to the specific implementation of the method, there are a variety of options, some of which are preferred variants are listed below:

• In a preferred embodiment, the first depressions are introduced in the substrate layer in addition to the at least one semiconductor layer in the compensation layer and adjacent to the compensation layer.

Preferably, the first depressions are produced by wet and/or dry etching processes using an etching mask, in particular a resist mask. A chlorine-based dry etching process is particularly preferably used to produce the first depressions, in particular partially in the substrate layer, along the separating sections. Etching processes have the advantage of known clean-room processing techniques on a wafer level, in particular compared to mechanical abrasive or sawing processes, which are limited to straight-line separating contours in a horizontal plane of the wafer and can also lead to damage to the at least one semiconductor layer, especially in an exposed state Semiconductor layer.

The etching process is particularly preferably carried out in the vertical direction with respect to the front side of the wafer, with a ratio between a depth and a width of the first depressions preferably being between 1:40 and 1:5.

In this context, it may further be particularly preferred that the first depressions are produced in the front of the wafer in combination with a functional structuring of the at least one semiconductor layer. This means that wafer processing steps can be combined and the manufacturing process can be accelerated.

Preferably, after introducing the first depressions, in particular after the first step and particularly preferably before processing on the back in the second step, a reinforcing wafer, in particular a carrier wafer made of glass material, with a, in particular detachable, connecting layer is applied to the front of the wafer. In this way, the at least one semiconductor layer can be stabilized, protected from damage and isolated semiconductor components can be temporarily held in position. The connecting layer is preferably a temporary adhesive layer, which can particularly preferably be dissolved by the action of temperature, in particular in the case of a wax layer, or by chemical action.

During a preferred second method step, after the first depressions have been introduced, in particular after the reinforcing wafer has been applied, the substrate layer and/or the compensation layer is removed at least in the separating sections from the back of the wafer in order to separate the semiconductor components from one another. In other words, a rear breakthrough is created up to the first depressions that were previously made. Advantageously, the semiconductor components can be separated without material-removing processes, in particular sawing processes, and thus prevent damage caused by a separation process.

In a preferred development, during the second step, second depressions are introduced into the back of the wafer vertically along the separating sections and additional recesses are introduced into the rear contact areas of the semiconductor components, recesses within the substrate layer and/or the compensation layer. The recesses are particularly preferably made in the substrate layer and the compensating layer, especially if the compensating layer has an insulating effect. Particularly for very large wafers, the aforementioned reinforcement wafer is advantageously used in this process step.

Through the recesses, membrane-like semiconductor layers can be formed which are surrounded by substrate sections, with the semiconductor components being able to be separated from one another advantageously by means of the second depressions without damaging the thin membranes.

Preferably, the second depressions and/or the recesses in the back of the wafer are also produced by means of wet and/or dry etching processes using an etching mask, with the second depressions and the recess preferably being introduced in a common process step in a time-saving manner.

Preferably, the compensation layer acts as an etch stop layer during the second step and a backside etching process of the substrate layer. In particular, if the first depressions do not already penetrate the compensation layer, the compensation layer is also removed from the back, at least in the area of the second depressions and/or the recesses for the rear contact.

Furthermore, in this context, it may be preferred that after the introduction of the first depressions, and preferably after the introduction of the second depressions and / or recesses, the substrate layer of the wafer is partially ground and / or etched in a vertical direction and over the entire surface in a horizontal plane to reduce a vertical depth of the recesses. This makes it easier to apply rear contact layers or to make contact with the semiconductor component itself. In particular in this method step, the previously introduced first depressions advantageously bring about a reduction in distortion effects induced by internal stress in connection with the removal of the substrate layer.

Very particularly preferably, after the second method step, a contact electrode is applied to the back of the structured wafer, in particular a drain electrode of the semiconductor component, which can preferably consist of several metallic layers or a thickened metal. In a further embodiment, the recess on the back can be completely filled with metal.

In an alternative embodiment of the second method step, after the first depressions have been introduced, the substrate layer and/or the compensating layer of the wafer are ground and/or etched over the entire surface in a horizontal plane in order to completely remove the substrate layer and/or the compensating layer and so in conjunction with the first recesses to separate the semiconductor components in the separating sections. In particular, the aforementioned reinforcement wafer is preferably used here too.

The at least one semiconductor layer preferably forms a vertical power semiconductor component based on epitaxially grown GaN, wherein the substrate layer is made of silicon and the compensating layer is made of an insulating material, in particular comprising aluminum nitride and gallium-aluminum nitride, and wherein the compensating layer enables the epitaxial growth of the GaN layers on the substrate layer. In particular, the substrate layer made of silicon has the advantage that particularly large wafers can be produced cost-effectively and using known manufacturing processes.

The invention further relates to a semiconductor component, in particular a vertical power semiconductor component, with a vertical layer structure consisting of a substrate layer, a compensating layer, in particular for compensating for different crystal lattices and/or thermal expansion coefficients of the layer structure, and at least one semiconductor layer, wherein the substrate layer and/or the compensating layer has a recess for rear contacting which has at least one semiconductor layer. In this case, a first vertical outer surface of the semiconductor component is produced at least in the region of the at least one semiconductor layer in a first wet and/or dry etching process and a second vertical outer surface of the semiconductor component in the compensation layer and/or the substrate layer in a second wet and/or Dry etching process is produced, whereby the two different outer surfaces form a separating transition.

The invention further relates to a semiconductor component which is produced using an aforementioned method.

In particular, the aforementioned first depressions in the front of the wafer in a manufactured semiconductor component can be seen on its side surfaces. Etching processes differ from mechanical abrasive separation processes in particular in that surfaces produced in the etching process can have repeating and regular notches in the vertical direction and the side surface also has a characteristic angle to the vertical direction. In particular, mechanical separation processes show irregular side surfaces, in particular with irregular notches and/or projections.

The aforementioned semiconductor component is preferably used for applications in electric drive trains for electric or hybrid-electric vehicles, in particular converters and/or inverters. Other preferred applications include charging stations, especially for the automotive sector, and inverters in household appliances.

Further advantages and details of the invention emerge from the following description of preferred embodiments of the invention and from drawings which are shown only schematically.

Brief description of the drawings

• 1 shows a top view of a front side of a wafer with a large number of semiconductor components,
• 2 a cross-sectional view of the wafer with a layer structure consisting of a substrate layer, a compensation layer and semiconductor layers,
• 3 a cross-sectional view of the wafer according to 2 with a recess on the back,
• 3 a cross-sectional view of the wafer according to 2 with first depressions in a front side of the wafer,
• 4 a cross-sectional view of the wafer according to 3 with a reinforcement wafer,
• 5 a cross-sectional view of the wafer according to 4 with second recesses and recesses on the back,
• 6 a cross-sectional view of the wafer according to 4 with substrate layer removed on the back.

Embodiments of the invention

The same elements or elements with the same function are provided with the same reference numbers in the figures.

In the 1 a wafer 100 is shown in a horizontal plane HL in an initial state, with a large number of semiconductor components 104 being arranged on the front side 102 of the wafer 100 shown. Separating sections 106, shown in dashed lines, are shown schematically between the individual semiconductor components along a longitudinal direction L and a transverse direction H, along which the wafer can be divided into individual semiconductor components.

In the 2 is a section of the wafer 100 in a transverse plane VH with several adjacent semiconductor components 104 and an exemplary layer structure 108 shown along a vertical direction V. The layer structure 108 preferably has a substrate layer 61 made of silicon, in particular a carrier substrate, with a compensating layer 13, in particular an insulating layer, onto which at least one semiconductor layer 110, here several semiconductor layers, can be grown epitaxially. The semiconductor layers 110 preferably have a lowermost highly doped contact semiconductor layer with n-conductivity 14, a low-doped conductive drift layer 15, a P-conductive body layer 16, and a highly doped n-conductive source contact layer 17. The source contact layer 17 and the body layer 16 are preferably pierced by a trench, a so-called trench, the side walls and base of which are separated from a gate electrode 21 by a gate dielectric 22. The source contact layer 17 and the body layer 16 are preferably contacted by a source electrode 41 applied from the outside, which are separated from the gate electrode 21 by a more preferred insulation layer 31. The aforementioned layer structure 108 forms the one in the 2 three cells 65, in particular transistor cells, shown for illustrative purposes, preferably a large number of such parallel-connected cells 65 being integrated in the layer structure 108 in order to reduce the resistance of the component and increase the current-carrying capacity.

This is done in the 2 So a preferred layer structure 108 is shown in the vertical direction V, which can have different layers with different thermal expansion coefficients and / or lattice structures. The compensation layer 13 preferably serves, on the one hand, as a base layer for epitaxial growth of the semiconductor layers and, on the other hand, to compensate for mechanical stresses between the substrate layer 61 and the semiconductor layers 110.

For rear-side contacting of the vertical semiconductor component 104, it is necessary that the substrate layer 61 is at least partially removed.

In the 3 A disadvantageous first method step from the prior art is shown, wherein a recess 51 is introduced into the back 112 of the wafer 100 in each of a semiconductor component 104 in order to expose the semiconductor layer 110 in a contacting area 118 on the back and to apply a drain electrode 52 for contacting . The substrate layer 61 and the compensation layer 13 are preferably removed. However, this results in the disadvantage that the compensating layer 13 can no longer have a compensating effect, at least in sections, and the semiconductor layer 110 can be distorted, particularly if the substrate layer 61 is reduced in its vertical extent. Furthermore, very thin membrane structures are formed by the rear recesses 51, which can be easily damaged in a further process step, especially since the exposed membrane preferably has a thickness in the range of micrometers in the vertical direction and a width in the range of millimeters in the transverse direction H . In particular, in the prior art, mechanically abrasive saw cutting processes are used to separate the semiconductor components 104, which can damage the thin membrane.

In the 4 An advantageous first method step according to the present invention is shown, wherein first depressions 102 are introduced vertically into the front side 102 of the wafer 100 along the separating sections 106 between individual semiconductor components 104, which are at least penetrate the semiconductor layers 110 shown here. These first depressions 102 are contrary to the previously mentioned exemplary embodiment 3 introduced in a second step before processing the back of the wafer 100. Particularly preferably, the first depressions 64 penetrate the compensating layer 13 completely, and very particularly preferably partially penetrate the substrate layer 61 in an area adjacent to the compensating layer 13. It is further clearly shown that the semiconductor layers 110 of the wafer 100 can be separated, but the substrate layer 61 remains, with the first depressions 64 allowing tensions along the transverse direction H within the layer structure 108 to be avoided or at least reduced. In further steps, the back side 112 of the wafer 100 can be processed, in particular in thermal processes and/or processes that at least partially remove the substrate layer 61, without the semiconductor layer being distorted.

To introduce the first depressions, wet and/or dry etching processes using an etching mask are preferably used, in particular no cutting separation processes, in order to avoid damage to the semiconductor layers 110. It can be further preferred that the first depressions 64 take place together with a structuring of the semiconductor layers 110 themselves, for example a structuring of the source electrode 41. It is conceivable that the in the 1 Separating sections 106 shown can have any complex, even curved, courses.

In the 5 A preferred further method step is shown, wherein after the introduction of the first depressions 64, in particular before processing the back of the wafer 100 in a second step, a reinforcing wafer 63 is applied to the front side 102 of the wafer 100 with a connecting layer 62. The connecting layer 62 is preferably designed as a temporary adhesive layer, which can preferably be dissolved thermally and/or chemically.

In the 6 and the 7 Two exemplary embodiments of a second method step are shown, wherein the substrate layer 61 and/or the compensating layer 13 are removed at least along the separating sections 106 in order to separate the individual semiconductor components 104 from one another. The back side 112 of the wafer 100 is removed until the previously introduced first depressions 64 are reached and a continuous depression is formed along the separating sections 106.

In a first embodiment of the second step 6 second depressions 51a are introduced into the back 112 of the wafer 100 until they reach the previously introduced first depressions 64. In addition, recesses 51 are each introduced into a semiconductor component 104 in order to be able to contact the semiconductor layers 110 on the back.

Preferably, the compensation layer 13 can act as an etching stop layer for removing the substrate layer 61 during the second step, with this also being removed at least in the area of the second depressions 51a and/or the recesses 51.

More preferably, after the recess 51 and the second recesses 51a have been introduced, the substrate layer 61 is etched and/or ground over the entire surface in the horizontal plane HL in order to reduce a depth t of the subsequently or previously produced recesses 51 in the vertical direction V and thus a later one To facilitate contacting from the back 112 of the semiconductor layers 110. Next is in the 6 It can be seen that the aforementioned drain electrode 52 can preferably be applied after the recess 51 has been introduced.

It should also be noted that the separated semiconductor components 104 can be distinguished in particular by characteristic vertical outer surfaces 114, 116 of semiconductor components, which are divided using an exciting separation process. In particular, surfaces produced using the etching process have a regular structure, in particular with notches corresponding to the various etching steps or a characteristic etching angle to the vertical direction V. In particular, a transition between the etching processes of the first depressions 116 and the second depressions 51a can be seen in the outer surface 114, 116.

In the 7 an alternative embodiment of the second method step for producing and separating the semiconductor components 104 is shown, the substrate layer 61 and the compensation layer 13 being etched and/or ground over the entire surface in the horizontal plane HL, with the removal of these layers down to the previously introduced first depressions 64 he follows.

As additionally in the 6 and the 7 is shown, the reinforcement wafer 63 is preferably separated after the separation of the semiconductor components 104 in the separation sections 106 by loosening the connection layer 62 in order to separate the semiconductor components 104.

QUOTES INCLUDED IN THE DESCRIPTION

This list of documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102020215006 A1 [0005]

Claims (10)

Method for producing a plurality of vertical semiconductor components (104), in particular power semiconductor components, from a wafer (100), wherein the wafer (100) in the initial state has a vertical layer structure (108) made of a substrate layer (61), a compensation layer (13), in particular to compensate for different crystal lattices and/or thermal expansion coefficients of the layer structure (108), and at least one semiconductor layer (110), wherein the wafer (100) can be divided along separating sections (106) for producing the large number of individual semiconductor components (104), characterized in that During a first step, vertical first depressions (64) are created in a front side (102) of the wafer (100) in the separating sections (106) between individual semiconductor components (104), which contain the at least one semiconductor layer (110), and preferably also the compensation layer (13), penetrate before the wafer (100) is processed on a back side (112) during a second step. Procedure according to the Claim 1 , characterized in that the first depressions (64) are generated by wet and/or dry etching processes using an etching mask, wherein preferably the first depressions (64) are introduced in combination with a functional structuring of the at least one semiconductor layer (110). Procedure according to the Claim 1 or 2 , characterized in that after the first depressions (64) have been introduced, in particular after the first step and before the second step, a reinforcing wafer (63) with a, in particular detachable, connecting layer (62) is placed on the front side (102) of the wafer (100) is applied. Procedure according to one of the Claims 1 until 3 , characterized in that after the introduction of the first depressions (64), the substrate layer (61) and / or the compensation layer (13) during the second step at least along the separating sections (106) from the back (112) of the wafer (100). be removed to separate the semiconductor components (104) from each other. Procedure according to the Claim 4 , characterized in that during the second step, second depressions (51a) in the back (112) of the wafer (100) vertically along the separating sections (106) and additionally in the rear contact areas (118) of the semiconductor components (104) recesses (51) within the substrate layer (61) and/or the compensation layer (13) are introduced. Procedure according to the Claim 5 , characterized in that during the second step, preferably after the introduction of the second depressions (51a) and / or recesses (51), the substrate layer (61) of the wafer (100) is partially in a vertical direction (V) and over the entire surface in a horizontal direction Level (LH) is ground and / or etched to reduce a vertical depth (t) of the recesses (51). Procedure according to the Claim 4 , characterized in that after the introduction of the first depressions (64) and during the second step, the substrate layer (61) and / or the compensation layer (13) of the wafer (13) is ground and / or etched over the entire surface in a horizontal plane (LH). to completely remove the substrate layer (61) and/or the compensation layer (13). Procedure according to one of the Claims 3 until 7 , characterized in that after the semiconductor components (104) have been separated, the reinforcement wafer (63) is removed, in particular by thermally and/or chemically dissolving a connecting layer (62). Procedure according to one of the Claims 1 until 8th , characterized in that the semiconductor layer (110) forms at least one vertically epitaxially grown GaN layer, the substrate layer (61) being made of silicon and the compensating layer (13) being made of an insulating material, in particular comprising aluminum nitride and gallium-aluminum nitride, and where the compensation layer (13) enables the epitaxial growth of the at least one GaN layer. Semiconductor component, in particular produced by a method according to Claim 5 , in particular a vertical power semiconductor component, with a vertical layer structure (108) consisting of a substrate layer (61), a compensation layer (13), in particular for compensating for different crystal lattices and / or thermal expansion coefficients of the layer structure (108), and at least one semiconductor layer (110), where the substrate layer (61) and/or the compensating layer (13) has a recess (51) for rear-side contacting of the at least one semiconductor layer (110), characterized in that a first vertical outer surface (114) of the semiconductor component (104) at least in the area of at least one semiconductor layer (110) is produced in a first wet and/or dry etching process and wherein a second vertical outer surface (116) of the semiconductor component (104) in the compensation layer (13) and/or the Substrate layer (61) is produced in a second wet and/or dry etching process, wherein the two different outer surfaces (114, 116) form a separating transition.

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