DE102022114918A1 - IMMERSION COOLING CASING - Google Patents

Abstract

Implementations of a semiconductor package may include one or more semiconductor dies embedded in a substrate; at least three pin fin terminals coupled to the substrate; at least one signal lead wire connector and a receiving portion coupled to the substrate; and include a coating directly coupled to all surfaces of the substrate that are exposed to coolant during operation. The receptacle portion may be configured to attach to a receptacle in an immersion cooling chamber that may contain coolant.

Description

OVERREFERENCE TO RELATED APPLICATIONS

This document claims the benefit of the filing date of the provisional U.S. Patent Application 63/202,561 entitled "Immersion Cooling Package" by Im et al., filed June 16, 2021, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

1. Technical field

Aspects of this document relate generally to semiconductor packages, such as packages for semiconductor devices. Other specific implementations include packages for power semiconductor devices.

2. Background

Semiconductor packages are used to make electrical connections between a semiconductor die and other electrical components in a system. Semiconductor packages were also designed to protect a semiconductor die from physical forces (impact, thermal stress, mechanical stress) and environmental variables such as moisture or light.

EXECUTIVE SUMMARY

Implementations of a semiconductor package may include one or more semiconductor dies embedded in a substrate; at least three pin fin terminals coupled to the substrate; at least one signal lead wire connector and a receiving portion coupled to the substrate; and include a coating directly coupled to all surfaces of the substrate that are exposed to coolant during operation. The receptacle portion may be configured to attach to a receptacle in an immersion cooling chamber that may contain coolant.

• Das eine oder die mehreren Halbleiter-Dies können parallel gekoppelt werden, wenn sie in das Substrat eingebettet sind.

Semiconductor package implementations may include any, all, or any of the following:

• The one or more semiconductor dies can be coupled in parallel when embedded in the substrate.

The one or more semiconductor dies can be stacked when embedded in the substrate.

The at least three pin fin connections can be a P-connection, N-connection and an output connection.

The N-terminal and the P-terminal can be coupled to opposite sides of the substrate.

In various implementations of packages, only one substrate may be enclosed.

The at least three pin-rib terminals may be six pin-rib terminals, and the six pin-rib terminals may be a P-terminal, an N-terminal, a U-out terminal, a V-out terminal, and a W-out terminal.

The housing can be a traction converter module.

Implementations of an immersion cooling system may include an immersion cooling chamber enclosing a coolant coupled to a cooling heat exchanger; wherein a semiconductor package is immersed in the coolant. The semiconductor package may include one or more semiconductor dies embedded in a substrate; at least one pin fin terminal coupled to the substrate; at least one signal lead wire connector; a receiving portion coupled to the substrate; and include a coating directly coupled to all surfaces of the substrate that are exposed to coolant during operation.

• Der Aufnahmeabschnitt kann dazu konfiguriert sein, an einer mit der Immersionskühlkammer gekoppelten Aufnahme befestigt zu werden.

Implementations of an immersion cooling system may include any, all, or any of the following:

• The receptacle portion can be configured to be attached to a receptacle coupled to the immersion cooling chamber.

The one or more semiconductor dies can be coupled in parallel when embedded in the substrate.

The one or more semiconductor dies can be stacked when embedded in the substrate.

The at least one pin-rib terminal may be three pin-rib terminals, and the three pin terminals may be a P-terminal, N-terminal, and an output terminal.

The N-terminal and the P-terminal can be connected to opposite sides of the substrate be coupled systems, wherein only one substrate can be included in the semiconductor package.

The at least (one) pin-rib terminals may be six pin-rib terminals and wherein the six pin-rib terminals may be a P-terminal, an N-terminal, a U-out terminal, a V-out terminal, and a W-out terminal.

The semiconductor package can be a traction converter module.

Implementations of a method of forming a semiconductor package may include embedding one or more semiconductor dies in a substrate; coupling at least one pin fin terminal directly to a side of the substrate using a bonding process; coupling at least one signal lead wire connector and a receiving portion coupled to the substrate; and applying a coating directly over all surfaces of the substrate that are exposed to coolant during operation.

• Das Einbetten des einen oder der mehreren Halbleiter-Dies kann ferner das Stapeln von zwei oder mehr Halbleiter-Dies einschließen.

Implementations of a method of forming a semiconductor package may include one, all, or any of the following:

• Embedding the one or more semiconductor dies may further include stacking two or more semiconductor dies.

Embedding the one or more semiconductor dies may further include electrically coupling two or more semiconductor dies in parallel.

The above and other aspects, features and advantages will be apparent to those skilled in the art from the DESCRIPTION and DRAWINGS, as well as from the CLAIMS.

character list

• 1 ist eine perspektivische Ansicht einer Implementierung eines Halbleitergehäuses, das in einer Immersionskühlkammer platziert ist;
• 2 ist eine Querschnittsansicht einer Implementierung eines Halbleitergehäuses, das in einer Immersionskühlkammer platziert ist;
• 3 ist eine Querschnittsansicht einer Implementierung eines Halbleitergehäuses mit parallel gekoppeltem Halbleiter-Die;
• 4 ist eine Querschnittsansicht einer Implementierung eines Halbleitergehäuses mit aufeinander gestapelten Halbleiter-Dies;
• 5 ist eine seitliche Querschnittsansicht einer Implementierung eines Substrats nach dem Einbetten der Halbleiter-Dies darin;
• 6 ist eine Querschnittsansicht der Substratimplementierung von 5 nach dem Koppeln von drei Stiftrippenanschlüssen unter Verwendung eines Fügeprozesses;
• 7 ist eine Querschnittsansicht der Gehäuseimplementierung von 7 nach dem Koppeln von Anschlüssen mit den drei Stiftrippenanschlüssen; und
• 8 ist eine Querschnittsansicht der Gehäusesausführung von 7 nach dem Aufbringen einer Beschichtung auf die freiliegenden Substratoberflächen.

Implementations are described below in conjunction with the accompanying drawings, wherein like reference numbers denote like elements and the following applies:

• 1 Figure 12 is a perspective view of an implementation of a semiconductor package placed in an immersion cooling chamber;
• 2 Figure 12 is a cross-sectional view of an implementation of a semiconductor package placed in an immersion cooling chamber;
• 3 Fig. 12 is a cross-sectional view of an implementation of a parallel-coupled semiconductor die semiconductor package;
• 4 Figure 12 is a cross-sectional view of an implementation of a semiconductor package with stacked semiconductor dice;
• 5 Figure 12 is a cross-sectional side view of an implementation of a substrate after embedding the semiconductor dies therein;
• 6 FIG. 12 is a cross-sectional view of the substrate implementation of FIG 5 after coupling three pin fin terminals using a joining process;
• 7 FIG. 12 is a cross-sectional view of the package implementation of FIG 7 after mating connectors to the three pin fin connectors; and
• 8th 12 is a cross-sectional view of the housing embodiment of FIG 7 after applying a coating to the exposed substrate surfaces.

DESCRIPTION

This disclosure, its aspects, and implementations are not limited to the specific components, assembly procedures, or method elements disclosed herein. Many other components, assembly methods, and/or method elements known in the art that are compatible with the desired semiconductor package will become apparent from this disclosure for use with particular implementations. Accordingly, for example, although particular implementations are disclosed, these implementations and implementing components can be any shape, size, make, type, model, version, dimension, concentration, material, quantity, process element, process step, and/or the like known in the art these semiconductor packages and implementing components and methods that are consistent with the intended operation and methods.

With reference to 1 Figure 1 illustrates an implementation of a semiconductor package 2 placed within an immersion cooling chamber 4 containing a coolant 6 therein. As illustrated, in this implementation, immersion cooling chamber 4 contains both liquid phase coolant 8 and vapor phase coolant 10. However, in other implementations, coolant 6 may exist in immersion cooling chamber 4 only as a liquid phase. As used herein, "immersion cooling" includes at least a portion of the semiconductor package being immersed in a liquid phase of the coolant and closing thus, situations where a single-phase or two-phase coolant is employed in an immersion cooling chamber. In various implementations, the immersion cooling chamber 4 is included as part of an electronic system, such as, by way of non-limiting example, a car battery, an electric motor, a vehicle, or any other electronic system that uses a semiconductor die. The immersion cooling chamber 4 can be self-supporting and a closed system without an outlet that relies on ambient or external forced convection cooling of the outer surface of the chamber to remove heat transferred from the coolant 6 (both for two-phase and single-phase coolant situations). will. In other implementations, the immersion cooling chamber 4 may be coupled to a cooling heat exchanger that receives heated coolant 6 from inside the chamber 4, removes heat therefrom, and then returns the cooled coolant to the immersion cooling chamber. As in 1 1, a refrigeration heat exchanger 12 is illustrated that receives vaporized refrigerant 10 and then condenses it using heat exchanger 14 to return liquid refrigerant 8 to chamber 4. FIG. However, in other implementations, the cooling heat exchange may only receive and cool liquid coolant from the immersion cooling chamber, even if two phases of the coolant are present in the chamber. A wide variety of chamber types and cooling heat exchange types can be constructed with the principles disclosed in this document. In certain implementations, the coolant used can be a chemically inert coolant. In other implementations, the coolant used can be a dielectric fluid. In some implementations, the coolant may be any of the inert and dielectric coolants sold under the tradename FLUORINERT by 3M of St. Paul, Minnesota.

As in 1 As illustrated, the semiconductor package illustrated is a traction inverter configured to convert direct current from a battery to alternating current used to power an electric motor. However, the principles disclosed herein can be used to form semiconductor packages for many other types of electronic devices. Included in this housing implementation are at least six pin fin terminals that correspond to the electric motor terminals: P-terminal 16, N-terminal 18, U-terminal 20, V-terminal 22 and W-terminal 24. Signal lead wire connectors 26 are also enclosed in this housing. During operation, related electrical cables (not for illustration purposes in 1 shown) connected to each of the terminals and signal lead wire connectors to allow the housing to be electrically connected to an electric motor. The pin-fin leads include a plurality of fins (pin-fins in this case) that extend into the coolant and correspondingly increase the surface area of each lead to increase heat transfer from the semiconductor package to the coolant. While the use of straight ribs 28 with the pin rib terminals in 1 As illustrated, various implementations can include a wide variety of ribs and other projection types such as, as non-limiting examples, pins, cones, frusto-conical shapes, rectangular guards, curved protrusions, or any other three-dimensional rib or pin shape.

Referring to 2 1, a cross-sectional side view of a semiconductor package 30 in an immersion cooling chamber 32 is illustrated. The immersion cooling chamber 32 operates in a two-phase mode with coolant 34 in conjunction with the cooling heat exchanger 36, which is similar to that in FIG 1 illustrated implementation works. Illustrated here is the internal structure of the semiconductor package 30 showing the N-pin fin connection 38, the P-pin fin connection 40 and the output pin fin connection 42. FIG. Each of the pin fin terminals 38,40,42 includes terminal portions 44,46,48 adapted to be coupled to an electrical cable coupled to fin portions 50,52,54. The fin portions 50, 52, 54 are directly coupled to the substrate 56 by a joint/bond (which includes the associated bonding material). The substrate 56 includes four semiconductor dies 58, 60, 62, 64 embedded in the material of the substrate itself along with respective conductive traces 66, 68 connecting the dies 58, 60, 62, 64 to each of the respective fin portions 50 , 52, 54 electrically couple. An additional signal pigtail connector 70 is coupled at one end of the substrate 56 adjacent the receiving portion 72 that is configured to allow the entire housing 30 to be coupled into a mount within the immersion cooling chamber 32 . The particular shapes of the various terminal portions 44, 46, 48, signal pigtail connector 70 and receptacle portion 72 are determined by the particular electrical cable connector that is used or the receptacle structure that is used to couple to the receptacle portion 72. A wide variety of connector types and receptacle coupling structures may be used in various implementations, and those of ordinary skill in the art will readily determine the appropriate terminal, lead wire connector, and receptacle section types and structures using the principles disclosed in this document.

In one set of implementations, the substrate 56 material may be any of a wide variety of material types used for printed circuit boards, including, by way of non-limiting example, FR1, FR2, FR4, FR5, FR6, G-10, G- 11, alumina, glass reinforced epoxy laminate, laminates, insulated metal substrates, polyimide film or any other type of circuit board material in which semiconductor dies can be embedded. In another set of implementations, the material of the substrate may be a Direct Bonded Copper (DBC) substrate. In still other implementations, the substrate may be an insulated metal substrate (IMS). In still other implementations, the substrate may be a ceramic substrate. Because portions of the substrate 56 are exposed even after the pin fin terminals 38, 40, 42 are coupled thereto, a coating 74 is coupled to the outer surface of the substrate 56. FIG. The coating 74 can provide a large number of effects such as, by way of non-limiting example, anti-corrosion; ion getters for lifetime extension; physical protection during assembly; mechanical protection against coolant flow over the surface; Particle/flake protection from particles from the chamber, housing and/or assembly debris; and other beneficial effects resulting from the protection of the substrate 56 material from the coolant 34.

While the coating is 74 in 2 As illustrated as being applied to all exposed surfaces of the substrate 56, in other implementations one, all, or any number of the surfaces/sides of the substrate 56 may be coated. The use of the coating 74 may also allow for protection of the wire bonds formed on the substrate 56 as the coating may completely cover the wire bonds and mechanically and physically protect them from coolant flow and particulate matter. The use of the coating can also aid in the repair of all components of the case during assembly as components can be individually tested prior to full assembly. while in 2 Where a single layer of coating material is illustrated, multiple layers of coating material(s) may be applied in different implementations, each made of the same or different materials. The coating 74 may be formed from a wide variety of materials including, as a non-limiting example, epoxies, novolak resins, polymeric films, alumina, titanium nitride, molding compound, any combination thereof, or any other material capable of being adhered to Substrate to be applied and is resistant to the coolant. In certain implementations, the ability to use alumina and/or titanium nitride as a coating can result in a thin foil that provides adequate protection in the vicinity of the immersion cooling chamber while facilitating additional heat transfer from the substrate itself. For example, when the film is formed of alumina and/or titanium nitride, the film thickness may be less than about 5 microns, between about 1 micron and about 5 microns, between about 1.5 microns and about 3 microns, as a non-limiting example.

A wide variety of configurations and types of semiconductor dies and traces can be used in different substrate implementations. With reference to 3 Illustrated is a semiconductor package 76 including a substrate 78 containing a first pair of integrated gate bipolar transistors (IGBT) 80 and a diode 82 electrically connected in parallel with a second pair of IGBT 84 and diode 86 by conductive traces 88 is coupled to the output port 90 . Here the emitter and anode of the first IGBT/diode pair 80,82 are coupled through the center trace of the traces 88 to the collector and cathode of the second IGBT/diode pair 84,86. The ability to electrically couple the die in parallel allows the package to be made more compact and the first IGBT/diode pair 80,82 to be sandwiched between two heatsinks in the form of pin fin connectors 92,94. This may allow for increased heat transfer for the first IGBT/diode pair 80,82 compared to the heat transfer from the second IGBT/diode pair 84,86. This configuration may be desirable when increased heat transfer is required for one or more of the semiconductor dies relative to another die in the substrate and/or where a particular form factor is desired for the semiconductor package.

4 1 illustrates an implementation of a semiconductor device 96 in which a first IGBT/diode pair 98,100 is coupled in a stacked configuration over a second IGBT/diode pair 102,104. Electrically, the collector and cathode of the first IGBT/diode pair 98,100 are coupled to the emitter and anode of the second IGBT/diode pair 102,104 via the central conductor track 106. In this configuration, the first IGBT/diode pair 98, 100 and the second IGBT/diode pair 102, 104 are electrically coupled in series. Here this design places all of the semiconductor dies embedded in the substrate 108 between t between the two pin fin connectors 110, 112, thereby ensuring that the cooling effect available from each is substantially equivalent, including the cooling effect of the center trace 106, which can act as a heat conductor to the output pin fin connector 114.

Both at the in 3 as well as in 4 In the illustrated implementation, a coating 116,118 is applied over the exposed portions of the substrates 78,108. These coatings 116, 118 can be any coating material disclosed in this document. A wide variety of embedded die configurations can be constructed in combination with the structure of the pin fin terminations using the principles disclosed in this document. Any of a wide variety of semiconductor dies may also be used, including, as a non-limiting example, power semiconductor dies, processors, memories, IGBTs, diodes, rectifiers, metal oxide field effect transistors (MOSFETs), gallium arsenide devices, high electron mobility -Transistors (HEMTs), passive components (capacitors, resistors, inductors, etc.), or any other semiconductor device or component. This process of embedding the dies and forming the traces also works to couple the different dies in parallel or to stack the dies on top of each other. In various method implementations, one die may be embedded, or more than one die may be embedded.

Various methods of forming semiconductor packages, such as those disclosed in this document, involve processes of forming substrates and attaching components thereto. With reference to 5 Illustrated is a cross-sectional view of a substrate 120 implementation after the process of embedding four semiconductor dies 122 therein and forming conductive traces 124 to connect the dies 122 together. The process of embedding the dies and forming the conductive traces may include, by way of non-limiting example, any of the following steps: laminating the dies into one or more layers of circuit board material, laminating the conductive traces, patterning and etching the conductive traces, shaping the dies with the circuit board material, or any other processing step for embedding the dies and related components and/or forming the conductive traces in the material of the circuit board. The ability to embed the die in the substrate 120 material allows the semiconductor package to be used in an immersion cooling chamber since the die is not separately exposed to the coolant but is protected by the substrate material. This technique can ensure that the housing has a desired level of reliability and/or longevity in the immersion cooling chamber.

Referring to 6 is the substrate 120 of 5 after the coupling of three rib sections 126, 128, 130 to opposite sides of the substrate 120 is illustrated. The rib sections are pin ribs as disclosed in this document, but the rib sections can be any other type disclosed in this document. The process of coupling the rib portions may involve a wide variety of techniques including, as a non-limiting example, soldering, bonding, brazing, gluing, thermocompression bonding, joining using a solder, joining using an attachment film, joining using an adhesive or a other method of coupling two materials together to facilitate heat transfer/electricity passage. As in 6 As can be seen, the three rib portions 126, 128, 130 make electrical contact with the conductive traces 124. FIG. In this way, the fin sections can perform dual functions as electrical connectors as well as heat transfer devices. The use of an immersion cooling chamber with a dielectric coolant ensures that during operation these electrically energized fin sections do not have the ability to short out or otherwise conduct electricity to unwanted structures/persons. The materials used for the three fin sections can be any of a wide variety of thermally conductive materials including, by way of non-limiting example, metals, metal alloys, alumina, copper, copper alloys, aluminum, aluminum alloys, or any other thermally conductive material.

6 also illustrates the coupling of the signal lead wire connector 138 into the material of the substrate 120, whereby the trace connections (not shown in the cross-sectional view of FIG 6 illustrated) are mechanically and electrically coupled to the signal lead wire connector 138 . Multiple signal wire connectors may be coupled to the substrate 120 in various implementations depending on the number of trace connections included in the substrate. Additionally, the receiving portion 140 is illustrated as being coupled to/around/into the end 142 of the substrate 120 . The particular signal lead wire connectors and receptacle portions coupled to the substrate at this point may be any of those disclosed in this document depending on the type of electrical connector for the electrical cables and receptacle type used. to support the housing in the immersion cooling chamber.

With reference to 7 is the substrate 120 of 6 after coupling the terminals 132,134,136 into the three rib sections 126,128,130. The coupling can be accomplished using a wide variety of methods including, as a non-limiting example, soldering, screwing, bonding, gluing, clamping, riveting, or any other method of coupling two pieces of metal together. in the in 7 In the illustrated implementation, port 132 is an N-port, port 134 is a P-port, and port 130 is an output port. The particular shape and type of each of the terminals 132, 134, 136 is dependent on the type of electrical cable used to make the connection to each terminal, which may be any of those disclosed in this document.

With reference to 8th A view of the completed housing 144 after the application of the coating 146 over the exposed portions of the substrate 120 is illustrated. The material used for the coating 146 can be any of those disclosed in this document. In certain process implementations where the coating has two or more layers, multiple application steps may be performed sequentially (along with a corresponding number of curing/drying steps). For example, a gel-like material can be applied in a first coating process, followed by application of a molding compound through a molding process to form a two-layer coating material. In some implementations, the application process for the coating may be a printing process. In other implementations, the deposition process can be a molding process. In other implementations, the coating may be applied using, as a non-limiting example, spraying, dipping, dispensing, chemical vapor deposition, sputtering, physical vapor deposition, film deposition, or other method to form a layer of material over a substrate.

In various semiconductor package implementations, while the pin-fins illustrated herein are illustrated as being suspended in the coolant, one or more of the pin-fin leads may contact the wall(s) of the immersion cooling chamber. In some, the pin fin connectors can be coupled directly to/across the wall(s) by screws/floor; in others, the pin fin connector(s) may merely be in physical contact with the wall(s) of the immersion cooling chamber. In such implementations, where sufficient mechanical support is available through/against the walls of the immersion cooling chamber using the pin fins, a receptacle may not be used to further secure the semiconductor package therein. In such implementations, a receiving portion may not be included/coupled to the substrate. Additionally, additional conductive heat transfer to the wall(s) of the immersion cooling chamber is possible in such implementations. A wide variety of pin fin termination configurations for various semiconductor package implementations that include contact/bonding to the wall(s) of the immersion cooling chamber can be developed using the principles disclosed in this document.

Implementations of a semiconductor package may include the at least three pin fin terminals being a P-terminal, N-terminal, and an output terminal.

Implementations of a semiconductor package may include only one substrate being included.

Implementations of a semiconductor package may include where the at least three pin-fin terminals are six pin-fin terminals and the six pin terminals are a P-terminal, an N-terminal, a U-out terminal, a V-out terminal, and a W-out terminal.

Implementations of a semiconductor package may include the package being a traction converter module.

Implementations of a semiconductor package may include the N-terminal and the P-terminal coupled to opposite sides of the substrate.

It will be readily understood that where the foregoing description refers to particular implementations of semiconductor packages and implementing components, sub-components, methods and sub-methods, a number of modifications can be made without departing from the essence and that these implementations, implementing Components, sub-components, methods and sub-methods can also be applied to other semiconductor package types.

QUOTES INCLUDED IN DESCRIPTION

This list of the documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63202561 [0001]

Claims (10)

A semiconductor package comprising: one or more semiconductor dies embedded in a substrate; at least three pin fin terminals coupled to the substrate; at least one signal lead wire connector and a receiving portion coupled to the substrate; and a coating directly coupled to all surfaces of the substrate exposed to coolant during operation; wherein the receptacle portion is configured to be attached to a receptacle in an immersion cooling chamber containing the coolant. housing after claim 1 wherein the one or more semiconductor dies are either coupled in parallel when embedded in the substrate or stacked when embedded in the substrate. housing after claim 1 wherein two of the at least three pin fin terminals are coupled to opposite sides of the substrate. Immersion cooling system comprising: an immersion cooling chamber including a coolant coupled to a cooling heat exchanger; a semiconductor package immersed in the coolant, the semiconductor package comprising: one or more semiconductor dies embedded in a substrate; at least one pin fin terminal coupled to the substrate; at least one signal lead wire connector and a receiving portion coupled to the substrate; and a coating directly coupled to all surfaces of the substrate exposed to coolant during operation; system after claim 4 , wherein the receptacle portion is configured to be attached to a receptacle coupled to the immersion cooling chamber. system after claim 4 , wherein the one or more semiconductor dies are coupled in parallel when embedded in the substrate. system after claim 4 , wherein the one or more semiconductor dies are stacked when embedded in the substrate. A method of forming a semiconductor package, comprising: embedding one or more semiconductor dies in a substrate; coupling at least one pin fin terminal directly to a side of the substrate using a bonding process; coupling at least one signal lead wire connector and a receiving portion coupled to the substrate; and Applying a coating directly over all surfaces of the substrate that are exposed to coolant during operation. procedure after claim 8 , wherein embedding the one or more semiconductor dies further comprises stacking two or more semiconductor dies. procedure after claim 8 , wherein embedding the one or more semiconductor dies further comprises electrically coupling two or more semiconductor dies in parallel.

Images