DE102021203863A1 - Gate driver component for controlling a topological semiconductor switch for power electronics - Google Patents

Abstract

A gate driver module is proposed for driving at least two power semiconductors, which form a topological switch and are formed from different semiconductor materials and/or semiconductor types. The gate driver module has: an output for each power semiconductor, a conversion unit with a first input to which a state variable or a state variable vector can be applied, in the conversion unit the state variable or the state variable vector being converted into logical information that indicates , which is to be controlled by the power semiconductor and output as an operand. In addition, a selection unit with a second input is provided, to which an input pattern vector can be applied, which has control information for one of the power semiconductors, comprising at least information about a dead time and a control frequency. In the selection unit, the input pattern vector is compared with the operand in such a way that it is determined whether the power semiconductor specified by the input pattern vector should actually be driven, and if this is the case, a corresponding output pattern vector is generated. A unit for generating a control matrix is also provided, in which the output pattern vector and the operand are linked in such a way that it is determined which of the outputs is to be controlled, with a control signal being output at the output associated with the power semiconductor determined.

Description

The present invention relates to the field of electromobility, in particular a gate driver component and a method for controlling at least two power semiconductors made from different semiconductor materials and/or semiconductor types, which form a topological semiconductor switch for power electronics.

Semiconductor transistors are used in many areas as electronic switches and are referred to as semiconductor switches. This is possible because a semiconductor switch can switch back and forth between two states. A first state is an on state. In this state, the solid state switch can conduct current and behave analogously to a low resistance or diode in the forward biased state. The other state is the lock state. In this state, the semiconductor switch is able to absorb an applied voltage, e.g. 400V or 800V.

A semiconductor switch is characterized in that it can switch back and forth between the two states mentioned very quickly and efficiently. This switching back and forth between the conducting and the blocking state of the semiconductor switch is the basis for many electronic circuits such as power packs, inverters, rectifiers, drive inverters.

So that the semiconductor switch can switch back and forth between these two states, it has a control connection, the so-called gate driver, via which the semiconductor switch is controlled. When driving the semiconductor switch, a general distinction is made between two types of driving. Voltage controlled semiconductor switches and current controlled semiconductor switches. With voltage-controlled semiconductor switches, the control voltage must be above or below a defined level, e.g. +5V or -3V, so that the semiconductor switch changes its state (conducting or blocking). In the case of current-controlled semiconductor switches, a defined control current must be exceeded or fallen short of in order for the semiconductor switch to change its state.

A control circuit is required for both variants, which implements the control of the semiconductor switch.

Previously known control circuits or control arrangements (gate drivers) have an input side and an output side. The input side has at least one signal variable that carries the information as to whether the semiconductor switch is to be switched on (conducting state) or off (blocking state). Furthermore, the control arrangement can have potential isolation between the input and output sides. The output side has at least one output signal, which is processed by the drive arrangement in terms of voltage level, current strength, etc., so that the semiconductor switch can be driven directly with this signal.

In addition, the applicant has already proposed an arrangement for a topological switch which has at least two power semiconductors, in particular power transistors, the topological semiconductor switch of which has at least one first power semiconductor with a first semiconductor material and at least one second power semiconductor with a second semiconductor material.

However, the control arrangements described above can only be used for topological semiconductor switches that consist of semiconductor switches of the same type. In the case of a topological switch consisting of a parallel connection of different semiconductor switch materials with a large band gap such as SiC, GaN, Si, etc. and/or different semiconductor types such as MOSFET (metal-oxide-semiconductor field effect transistor), IGBT (bipolar transistor with insulated gate electrode or Insulated Gate Bipolar Transistor), JFET (Junction FET) etc., it is not possible to control the different semiconductor types separately with this arrangement, since each semiconductor type must have a separate control signal.

It is an object of this invention to overcome this problem. According to the invention, this object is achieved by the features of the independent patent claims. Advantageous configurations are the subject matter of the dependent claims.

A gate driver component for driving at least two power semiconductors, which form a topological switch and are formed from different semiconductor materials and/or semiconductor types, is proposed as a solution. The gate driver module has: an output for each power semiconductor, a conversion unit with a first input to which a state variable or a state variable vector can be applied, in the conversion unit the state variable or the state variable vector being converted into logical information that indicates , which is to be controlled by the power semiconductor and output as an operand. In addition, a selection unit is provided with a second input to which an input pattern vector can be applied that has control information for one of the power semiconductors, comprising at least information about a dead time and a control frequency. In the selection unit, the input pattern vector is compared with the operand in such a way that it is determined whether the power semiconductor specified by the input pattern vector should actually be driven, and if this is the case, a corresponding output pattern vector is generated. A unit for generating a control matrix is also provided, in which the output pattern vector and the operand are linked in such a way that it is determined which of the outputs is to be controlled, with a control signal being output at the output associated with the power semiconductor determined.

The speed of the switching process depends on which semiconductor materials and/or semiconductor types are used, i.e. the control patterns of the low-side switch and the high-side switch of the topological switch can differ in terms of dead time and control frequency. With the proposed gate driver component, different power semiconductors can be controlled depending on the state and in an optimized manner, in that different control patterns can be provided for each output without requiring additional hardware.

In one embodiment, the first output is set up to drive the first power semiconductor with a first dead time T _D,1 and a first drive frequency f _S,1 , and each additional output is designed to drive each additional power semiconductor with an additional dead time T _{D,n+ 1} and a further drive frequency f _S,n+1 , where the following applies: T _D,n+1 ≧T _D,n and f _S,n+1 ≦f _S,n , where n corresponds to the number of outputs.

In one embodiment, a first power semiconductor is a SiC MOSFET and a second power semiconductor is a Si IGBT.

In one embodiment, which input pattern vector is present at the second input is determined cyclically.

In one embodiment, the comparison between the input pattern vector and the operand is based on a specified truth table. In one embodiment, the link between the output pattern vector and the operand is based on a specified truth table. The advantage here is that the comparison or linking is very fast and can also be implemented using hardware.

In one embodiment, at least one of the outputs can be driven with at least two different input patterns. This is advantageous when power semiconductors with switching processes that switch at different speeds are to be controlled, since the faster-switching power semiconductor can also be controlled with the control pattern of the slower-switching power semiconductor.

In one embodiment, the state values are detected on the input side and/or on the output side of the semiconductor switch. In one embodiment, state values include at least one or a combination of physical values that are used to control the power semiconductors. In one embodiment, the input signal includes one or more physical values that are used to control the power semiconductors, in particular the input signal corresponds to a degree of modulation. Depending on the application and performance requirements, as many parameters as possible can be taken into account that influence the choice of the right power semiconductor.

Furthermore, an electronic module for controlling an electric drive of a vehicle is proposed, the electronic module having an inverter with a described gate driver module. Furthermore, an electric drive of a vehicle with the electronics module and a vehicle with the electric drive are proposed.

In addition, a method for state-dependent control of a topological semiconductor switch for power electronics with at least two power semiconductors connected in parallel, which are formed from different semiconductor materials and/or semiconductor types, is provided by means of a gate driver module, which has an output for each power semiconductor. The control is carried out by detecting a state variable or a state variable vector as the first input signal, with the state variable or the state variable vector being converted into logical signal information which indicates which of the power semiconductors is to be controlled and output as an operand, as well as detecting an input pattern vector as second input signal, which has control information, comprising at least information about a dead time and a control frequency, for one of the power semiconductors. The input pattern vector is compared with the operand in such a way that it is determined whether the power semiconductor specified by the input pattern vector should actually be driven, and if this is the case, a corresponding output pattern vector is generated. In addition, the output pattern vector and the operand are linked to form a control matrix, which is used to determine wel cher of the outputs is to be controlled. Finally, a control signal is output to the output associated with the determined power semiconductor.

Further features and advantages of the invention result from the following description of exemplary embodiments of the invention, with reference to the figures of the drawing, which show details according to the invention, and from the claims. The individual features can each be implemented individually or together in any combination in a variant of the invention.

• 1 zeigt eine Schaltungsanordnung des Gate-Treiber-Bausteins 1 gemäß einer Ausführung der vorliegenden Erfindung.
• 2 zeigt eine Detailansicht der Selektionseinheit E2 aus 1.

Preferred embodiments of the invention are explained in more detail below with reference to the attached drawing.

• 1 FIG. 1 shows a circuit arrangement of the gate driver chip 1 according to an embodiment of the present invention.
• 2 shows a detailed view of the selection unit E2 1 .

In the following descriptions of the figures, the same elements or functions are provided with the same reference symbols.

Inverters, also known as power converters, require a power module or semiconductor package to convert direct current from a battery into alternating current. The power module has topological switches with semiconductor transistors as the power transistors (also referred to as power semiconductors) used to control the currents and generate the AC power. Different configurations of power transistors are known. Among other things, it is known to use semiconductor types such as MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) or IGBTs (Insulated Gate Bipolar Transistors). The semiconductor material used can be silicon (Si), silicon carbide (SiC), gallium nitride (GaN) or any other semiconductor material. Materials with a wide band gap are preferred.

In the field of electromobility, it is necessary to increase the efficiency of the inverter through the use of new semiconductor technologies, such as SiC MOSFETs, in order to comply with strict fleet efficiency targets (set by legislators). However, the semiconductor area for normal, i.e. average, driving operation is oversized, since the operating point relevant to the design is rarely reached. The problem is that the semiconductor area of newer technologies (Wide-Bandgab-Semiconductors = WBG), which have a higher inherent efficiency (such as SiC or GaN), is expensive compared to conventional silicon. Conventional systems with semiconductors made of a cheaper material (e.g. silicon) can be dimensioned with safety margins in relation to the design-relevant operating point, since the costs per semiconductor area are low compared to WBG materials. When using WBG semiconductors in a conventional design, not only is space wasted, but there is also a price disadvantage. It is therefore necessary to find an optimum between the best possible technology and the lowest possible costs.

For this purpose, the power semiconductors to be controlled (hereinafter also referred to as semiconductors for short) are designed by selecting the semiconductor type and the semiconductor material according to the application, i.e. the target specification. For example, silicon semiconductor transistors exhibit better conductivity at larger currents, while silicon carbide semiconductor transistors exhibit this property at smaller currents. In this way, for example, the power supply can be realized in a consumption-optimized manner.

In order to control different, parallel-connected power semiconductors HL1, HL2, ..., HLn, which are formed from different semiconductor materials and/or different semiconductor types, using a single topological semiconductor switch, the gate driver module 1 described below and a control method for the power semiconductors are used HL1, HL2, ..., HLn suggested. Semiconductor materials used can be Si, SiC, GaN etc. Semiconductor materials with a large band gap are advantageously used. Actively switchable transistors such as MOSFETs, IGBTs, JFETs etc. can be used as semiconductor types.

As already mentioned, the speed of the switching process depends on which semiconductor materials and/or semiconductor types are used, ie the control patterns of the low-side switch and the high-side switch of the topological switch can differ in terms of dead time T _D12 , ... , T _D,n , and driving frequency f _S,1 , ..., f _S,n differ. For example, a SiC-MOSFET is able to carry out a switching process much faster, for example within approx. 100 ns, than a Si-IGBT, which requires approx. 500 ns, with the same voltage and current values.

When driving half-bridges, low-side switches and high-side switches are driven in a complementary manner. To avoid bridge short circuits, the conductive switch must always be switched off first before the complementary switch is switched on. However, you always have to wait until the switch-off process is complete. During this time both topological switches must be switched off. The time in which both topological switches are switched off is referred to as the dead time T _D and usually corresponds to around 2-5 times the duration of a switching process. Furthermore, it is possible to carry out more switching processes in the same time by switching a SiC semiconductor more quickly. This enables higher control frequencies fs.

The control patterns can therefore differ in terms of dead time T _D and control frequency fs. A SiC MOSFET can be driven with a pattern with a smaller T _D and higher fs compared to a Si IGBT. Here, an output designed for a SiC MOSFET can also be operated with a drive pattern for a Si IGBT. The reverse is not possible.

In order to provide an optimized control of power semiconductors HL1, HL2, ..., HLn, which are formed from different semiconductor materials and/or different semiconductor types, the following is based on 1 and 2 described gate driver module 1 proposed. In addition, a method for state-dependent control of a topological semiconductor switch for power electronics with at least two power semiconductors HL1, HL2, . . . , HLn connected in parallel and formed from different semiconductor materials and/or different semiconductor types is proposed.

The gate driver module 1 has the advantage that it has a number of outputs S1, . . . , Sn, which can be driven using different drive patterns. Each of the outputs S1, . . . , Sn is assigned to a power semiconductor HL1, HL2, . Another advantage is that no additional, space-consuming hardware is required.

In 1 a gate driver module 1 with two inputs M _E and X and a plurality of outputs S1, ..., Sn is shown. Each output S1, ..., Sn is used to control a power semiconductor HL1, HL2, ..., HLn. As already mentioned several times, the power semiconductors HL1, HL2, . . . , HLn can be formed from different semiconductor materials and/or different semiconductor types, which makes separate activation necessary. The power semiconductors HL1, HL2, . . . HLn always form a topological switch with a high-side switch and a low-side switch.

A state vector X or a state variable is applied to one of the inputs of the gate driver module 1 . A state vector X is advantageous when several physical variables are used to describe the state.

State values of the state variable or the state vector X include physical values that are used to control the power semiconductors HL1, HL2, ..., HLn, i.e. variables for the control or regulation and/or the monitoring of power electronics. Such a variable is e.g. the current, the effective value of the current or the temperature, whereby the variables can be subdivided further. For example, the cooling water inlet temperature or the cooling water outlet temperature and/or semiconductor temperatures can be used as the temperature. Furthermore, phase currents or battery currents, the battery state of charge, the voltage in the intermediate circuit, the accelerator pedal position and thus the current power requirement can be used as a state variable or as a state vector, i.e. if several variables are considered.

The state values of the state variable or the state vector X can be recorded both on the input side of the semiconductor switch, e.g. a cooling water temperature, and on the output side of the semiconductor switch, e.g. the temperature of the power semiconductors HL1, ..., HLn.

The state variable or the state vector X is then processed in a conversion unit E1 to form logical information which indicates which of the power semiconductors HL1, HL2, ..., HLn is to be controlled, and is made available as an operand vector An which contains as many elements how there are exits.

In one embodiment, normalization to a maximum value takes place, which can mean, for example, that the power electronics must deliver their maximum power. The logical information output as the operand An or as the operand vector can have 2 ⁿ logic level patterns. This means that if the topological switch consists of two (n=2) semiconductor types and/or materials, four different patterns can be output (2 ² =4), which can be defined in terms of different, given level heights Ln. These level heights Ln can, for example, correspond to different ranges of a required power output. Depending on the required power output, a lookup table can be created, for example, which defines which power semiconductors HL1, HL2, . . . , HLn are to be controlled. This can be read out by means of a corresponding arithmetic unit, for example a control unit, which is provided for carrying out the method.

Various input pattern vectors M _E can be applied to the second input of the gate driver module 1, which always have control information of the power semiconductor HL1, ..., HLn to be controlled and are identified as input pattern vectors M _E1 , M _E2 , ..., M _En . At least they have information about the dead time T _D and the drive frequency f _S . The dead time T _D and the drive frequency fs are chosen in such a way that their parameters are suitable for driving a specific semiconductor type or material.

For example, in the case of two different power semiconductors HL1 and HL2 to be controlled, one of them is a SiC MOSFET (HL1) in which, for example, the dead time T _D,1 can be defined as 500 ns and the control frequency f _S,1 as 20 kHz. The other is a Si-IGBT (HL2), in which, for example, the dead time T _D,2 can be defined as 2.5 µs and the control frequency f _S,2 as 10 kHz. This results in two input pattern vectors M _E1 and M _E2 . In this case, M _E1 with the parameters T _D,1 and f _S,1 is intended for driving the power semiconductor HL1 and M _E2 with the parameters T _D,2 and f _S,2 for driving the power semiconductor HL2.

The input pattern vectors M _E are adjusted (or compared) with the operand An in a selection unit E2 in order to generate an output pattern vector M _A . This determines which M _E is present at the input. In the case described above, this is either M _E1 or M _E2 . The determination can take place cyclically. Furthermore, a comparison is made with the operand An using a truth table. If the determined input pattern vector M _E1 , M _E2 matches the operand An (check by comparison in E21), or reflects an entry in the truth table, the ME (M _E1 or M _E2 ) is transmitted to the output and used as the output pattern vector M _A passed on. This means that a verification takes place in the selection unit E2 that the power semiconductor HL1 or HL2 specified by the input pattern vector M _E1 , M _E2 should actually be driven.

The structure of the selection unit E2 is in 2 shown in detail. As already shown, the input pattern vector M _E and the operand An enter the selection unit E2 as input variables, and the output pattern vector M _A exits as an output. The selection unit E2 determines (block E21) which input pattern vector M _E is present, ie M _E1 , M _E2 , . . . , M _En , depending on the number n of power semiconductors HL1, HL2, . This result is then compared to the operand An using a truth table. If the match is successful, the output pattern vector M _A is output.

In the case of two power semiconductors HL1, HL2, the truth table (T1) can look like this: On _{ME MA} 0 0 0 0 1 M _E1 M _E1 1 0 M _E2 M _E2 1 1 M _E2 M _E2

In the further course, the output pattern vector M _A and the operand An are linked to one another, more precisely, conjunctively linked, in a unit for generating a control matrix E3.

A control matrix E3 is generated by conjunctively linking (logical AND) the output pattern vector M _A with the operand An, ie M _A ∩ An in accordance with a predetermined truth table. Thus, each of the power semiconductors HL1, HL2, . . . , HLn to be controlled can be controlled separately. The actual control signal G1, G2, ..., Gn is output from the gate driver module 1 via the outputs S1, S2, ..., Sn to an impedance network Z1, ..., Zn and processed there signal generated.

In the case of two power semiconductors HL1, HL2, the truth table (T2) can look like this: On _ME S ₂ p ₁ 0 0 0 0 0 0 1 M _E1 0 M _E1 1 0 M _E2 M _E2 0 1 1 M _E2 M _E2 M _E2

From this it can be seen that the output S2 can be operated exclusively with the input pattern vector M _E2 and the output S1 with both M _E1 and M _E2 .

The control arrangement can also have a potential separation P between the input and output sides, which is 1 is indicated as a dashed line. This is used, for example, for galvanic isolation of a high-voltage circuit or the (signal-related) output side OUT from a low-voltage circuit or the (signal-related) input side IN in the vehicle.

Output signals are thus output at the outputs S1, ..., Sn, which ultimately serve to control one of the power semiconductors HL1, HL2, ..., HLn, with each output S1, ..., Sn a power semiconductor HL1, HL2, . .., HLn is assigned.

In the example above, the output S1 is designed to drive a power semiconductor HL1 (SiC-MOSFET) with a specified (small) dead time T _D,1 and a specified (high) drive frequency f _S,1 . The second output S2 is designed to drive a power semiconductor HL2 (Si-IGBT) with a dead time of T _D,2 >T _D,1 and a drive frequency of f _S,2 <f _S,1 .

In the event that further power semiconductors HL3, ..., HLn and thus further outputs S3, ..., Sn are present, these are T _D,n+1 > T _d,n and f _s,n+1 <f _s,n designed. This means that the first output S1 is designed in such a way that it can basically control all power semiconductors HL1, HL2, ..., HLn, with the second and further outputs S2, ..., Sn having fewer power semiconductors HL1, HL2, ... . , HLn can drive (the second output S2 can drive more than the third output S3, etc.).

This results in the possibility that the output S1 does not have to be driven automatically with T _D,1 and f _S,1 , but also with drive patterns with longer dead times and lower drive frequencies, as can be seen in the truth table T2.

The control method can be implemented using software, hardware or a combination thereof. The advantage of the proposed gate driver module 1 and the control method lies in the linking of the input signal, i.e. the input pattern vectors M _E or M _E1 , M _E2 ,..., M _En for each semiconductor type or type, with state variables or State vectors X for generating separate, direct control signals for each power semiconductor HL1, HL2, ..., HLn of the topological semiconductor switch. The proposed method is used with inverters in the field of electromobility, i.e. for controlling an electric drive or other electric machine.

Reference List

1

gate driver device

On

operand

E1

conversion unit

E2

selection unit

E21

Comparison with operand

E3

Unit for generating a control matrix

G1, ..., Gn

Control signal power semiconductor

HL1, ..., HLn

power semiconductors

MA

exit pattern vector

ME ,ME1, ...MEn

input pattern vector

S1, ..., Sn

exits

X

state vector

Z1, ..., Zn

impedance network

P

electrical isolation

IN

Input side / low-voltage side

OUT

Output side / high-voltage side

Claims (10)

Gate driver module (1) for driving at least two power semiconductors (HL1, HL2, ..., HLn), which form a topological switch and are formed from different semiconductor materials and/or semiconductor types, the gate driver module ( 1) has: - an output (S1, S2, ..., Sn) per power semiconductor (HL1, HL2, ..., HLn), - a conversion unit (E1) with a first input to which a state variable or a state variable vector (X) can be applied, the state variable or the state variable vector (X) being converted into logic information in the conversion unit (E1), which indicates which of the power semiconductors (HL1, HL2, ..., HLn) is to be controlled, and output as an operand (An), - a selection unit (E2) with a second input to which an input pattern vector (M _E ; M _E1 , M _E2 , ..., M _En ) can be applied, which contains control information for one of the power semiconductors ( HL1, HL2, ..., HLn), comprising at least at least information on a dead time (T _D ) and an activation frequency (fs), with the input pattern vector (M _E ; M _E1 , M _E2 ,..., M _En ) is compared with the _operand (An) in such a _way that it is determined _{whether the} power semiconductors (HL1, HL2, ..., HLn) is actually to be driven, and if this is the case, a corresponding output pattern vector (M _A ) is generated, - a unit for generating a drive matrix (E3), in which the output pattern vector ( M _A ) and the operand (An) are linked in such a way that it is determined which of the outputs (S1, S2,..., Sn) is to be controlled, with a Control signal (G1, G2, ..., Gn) is output to the output (S1, S2, ..., Sn) associated with the determined power semiconductor (HL1, HL2, ..., HLn). Gate driver chip (1) after claim 1 , wherein - the first output (S1) is set up to control the first power semiconductor (HL1) with a first dead time (T _D,1 ) and a first control frequency (f _S,1 ), - each additional output (S2, ... , Sn) for driving each additional power semiconductor (HL2, ..., HLn) with a further dead time (T _D,2 , ..., T _D,n ) and a further control frequency (f _S,2 , ... , f _S,n ), where: T _D,n+1 ≥ T _D,n and f _S,n+1 ≤ f _S,n , where n corresponds to the number of outputs. Gate driver chip (1) after claim 1 or 2 , wherein a first power semiconductor (HL1) is a SiC MOSFET and a second power semiconductor (HL2) is a Si-IGBT. Gate driver module (1) according to one of the preceding claims, a determination as to which input pattern vector (M _E ; M _E1 , M _E2 ,..., M _En ) is present at the second input takes place cyclically. Gate driver module (1) according to one of the preceding claims, wherein the comparison between the input pattern vector (M _E ; M _E1 , M _E2 ,..., M _En ) and the arithmetic variable ormation (An) takes place using a predetermined truth table, and/ or wherein the link between the output pattern vector (M _A ) and the operand (An) is based on a predetermined truth table. Gate driver module (1) according to one of the preceding claims, wherein at least one of the outputs can be driven with at least two different input patterns (M _E ; M _E1 , M _E2 ,..., M _En ). Electronics module for controlling an electric drive of a vehicle, the electronics module having an inverter with a gate driver component (1) according to one of the preceding claims. Electric drive of a vehicle, having the electronic module claim 7 . Vehicle having an electric drive with the electronic module claim 8 . Method for state-dependent control of a topological semiconductor switch for power electronics with at least two power semiconductors (HL1, HL2, ..., HLn) connected in parallel, which are formed from different semiconductor materials and/or semiconductor types, by means of a gate driver module (1), which has an output (S1, S2, ..., Sn) for each power semiconductor (HL1, HL2, ..., HLn), the control being carried out by - detecting a state variable or a state variable vector (X) as the first input signal, wherein the state variable or the state variable vector (X) is converted into logical signal information which indicates which of the power semiconductors (HL1, HL2, ..., HLn) is to be controlled and is output as an operand (An), and - a detection having control information, comprising at least information about a dead time (T _D ) and a control frequency (f _S ), for one of the power semiconductors (HL1, HL2, ..., HLn). n input pattern vector (M _E ; M _E1 , M _E2 ,..., M _En ) as the second input signal, the input pattern vector ( _ME ; M _E1 , M _E2 ,..., M _En ) being compared with the operand (An) in such a way that it is determined , whether the power semiconductor (HL1, HL2, ..., HLn) specified by the input pattern vector (M _E ; M _E1 , M _E2 ,..., M _En ) should actually be driven, and if this is the case, a corresponding one Output pattern vector (M _A ) is generated, and - a combination of the output pattern vector (M _A ) and the operand (An) to form a control matrix (E3), which determines which of the outputs (S1, S2,..., Sn) is to be controlled, and outputting a control signal (G1, G2, ..., Gn) to the output (S1, S2, ..., Sn) associated with the determined power semiconductor (HL1, HL2, ..., HLn).

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