DE102021108872A1 - SEMICONDUCTOR DEVICE AND METHOD - Google Patents

Abstract

Methods for improving the sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed thereby are disclosed. In one embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant, a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature includes; a second contact material over the first contact material, the second contact material comprising a material different than the first contact material, a first portion of the second contact material further comprising the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, wherein a first portion of the dielectric liner includes the first dopant.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority from U.S. Provisional Application No. 63/082,045 , filed September 23, 2020, which is hereby incorporated herein by reference.

BACKGROUND

Semiconductor devices (components) are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating/dielectric material layers, conductive material layers, and semiconductor layers over a semiconductor substrate and patterning the various layers using lithography to form circuit components and elements thereon.

The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, thereby allowing more components to be integrated in a given area.

character list

• 1 veranschaulicht ein Beispiel eines Halbleiterbauelements mit Fin-Feldeffekttransistoren (FinFETs) in einer dreidimensionalen Ansicht, gemäß einigen Ausführungsformen.
• 2, 3, 4, 5, 6A, 6B, 7A, 7B, 7C, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 10D, 11A, 11B, 12A, 12B, 13A, 13B, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 18C, 18D, 19A, 19B, 19C, 19D, 19E, 19F, 20A, 20B, 20C, 20D, 21A, 21B, 22A und 22B sind Querschnittsansichten von Zwischenstufen bei dem Herstellen von Halbleiterbauelementen, gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

• 1 1 illustrates an example of a semiconductor device with fin field effect transistors (FinFETs) in a three-dimensional view, according to some embodiments.
• 2 , 3 , 4 , 5 , 6A , 6B , 7A , 7B , 7C , 8A , 8B , 8C , 9A , 9B , 9C , 10A , 10B , 10C , 10D , 11A , 11B , 12A , 12B , 13A , 13B , 14A , 14B , 14C , 15A , 15B , 15C , 16A , 16B , 16C , 17A , 17B , 17C , 18A , 18B , 18C , 18D , 19A , 19B , 19C , 19D , 19E , 19F , 20A , 20B , 20c , 20D , 21A , 21B , 22A and 22B 12 are cross-sectional views of intermediate stages in the fabrication of semiconductor devices, according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments for implementing different features of the invention. In order to simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in face-to-face contact, and also include embodiments in which additional features are so intermediate between the first and the second feature may be formed that the first and second features may not be in direct contact. Also, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like may be used herein for ease of description to indicate the relationship of an element or feature to other element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The item may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly as well.

Various embodiments provide a method for improving interfaces between dielectric layers and contacts, and semiconductor devices formed by these methods. The method includes forming an opening in a dielectric layer, depositing a first contact material in the opening, depositing a second contact material over the first contact material, around the contact and performing an ion implantation process on the dielectric layer. The dielectric layer may include silicon oxide, silicon nitride, or the like; the first contact material may include cobalt or the like; and the second contact material may include tungsten, ruthenium, or the like. The ions implanted by the ion implantation process may include germanium, xenon, argon, silicon, arsenic, nitrogen, combinations thereof, or the like. The implantation of the ions into the dielectric layer can cause the volume of the dielectric layer to expand, creating a seal between the dielectric layer and the second contact material. A planarization process, such as chemical mechanical polishing (CMP), planarizes the dielectric layer and the second contact material. The seal prevents chemicals used in the planarization process, such as CMP slurry, from penetrating between the second contact material and the dielectric layer and removing material from the first contact material. This reduces the formation of cracks between the contact and the dielectric layer, reduces device defects, and improves device performance.

1 12 illustrates an example of FinFETs, according to some embodiments. The FinFETs include fins 55 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation regions (STI) 58 are disposed in substrate 50 and fins 55 protrude over and between adjacent STI regions 58 . Although STI regions 58 are described/illustrated as being separate from substrate 50, the term "substrate" as used herein can be used to refer to a semiconductor substrate alone or to a semiconductor substrate having STI regions. Additionally, although fins 55 are illustrated as a single material continuous with substrate 50, fins 55 and/or substrate 50 may comprise a single material or a plurality of materials. In this context, the fins 55 refer to the portions that extend between the adjacent STI regions 58 .

Gate dielectric layers 100 are located along sidewalls and over a top surface of fins 55, and gate electrodes 102 are located over gate dielectric layers 100. Source/drain epitaxial regions 92 are on opposite sides of fins 55 , the gate dielectric layers 100 and the gate electrodes 102 are arranged. 1 further illustrates reference cross-sections used in subsequent figures. The cross sections AA′ are along a longitudinal axis of the gate electrode 102 and in the direction perpendicular to the direction of current flow between the epitaxial source/drain regions 92 of the FinFETs, for example. Cross-section BB' is perpendicular to cross-section AA' and runs along the longitudinal axis of a fin 55 and, for example, in a direction of current flow between the epitaxial source/drain regions 92 of the FinFETs. Cross section CC' is parallel to cross section AA' and extends through the epitaxial source/drain regions 92 of the FinFETs. For the sake of clarity, subsequent figures refer to these reference cross-sections.

Some of the embodiments discussed herein are discussed in the context of fin field effect transistors (FinFETs) fabricated with gate-last (gate-last) processes. In some embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects used in planar devices (e.g., planar field effect transistor), nanostructure field effect transistors (e.g., nanosheet, nanowire, gate all around field effect transistors, or the like) (NSFETs), or the like .

2 until 22B 12 are cross-sectional views of intermediate stages in manufacturing FinFETs, according to some embodiments. 2 until 5 , 6A , 7A , 8A , 9A , 10A , 11A , 12A , 13A , 14A , 15A , 16A , 17A , 18A , 19A , 20A , 21A and 22A are along the in 1 illustrated reference cross-section AA'. 6B , 7B , 8B , 9B , 10B , 11B , 12B , 13B , 14B , 14C , 15B , 16B , 17B , 18B , 18D , 19B , 19D , 20B , 20D , 21B and 22B are along a similar, in 1 illustrated cross-section BB'. 7C , 8C , 9C , 10C and 10D are along the in 1 illustrated reference cross-section CC'. 15C , 16C , 17C , 18C , 19C , 20c , 20E and 20F are top-down views.

In 2 a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, which is doped (e.g., with a p-type or an n-type dopant). or may be undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be a buried one, for example Oxide layer (BOX layer - buried oxide layer), a silicon oxide layer or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as a multilayer or a gradient substrate can also be used. In some embodiments, the semiconductor material of the substrate 50 may be silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; or combinations thereof.

The substrate 50 has a region 50N and a region 50P. Region 50N may be used to form n-type devices such as NMOS transistors, e.g. B. n-FinFETs. Region 50P may be used to form p-type devices such as PMOS transistors, e.g. B. p-FinFETs. Region 50N may be physically separate from region 50P (as illustrated by divider 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be located between region 50N and region 50P can be arranged.

In 3 fins 55 are formed in the substrate 50 . The fins 55 are semiconductor strips. In some embodiments, the fins 55 may be formed in the substrate 50 by etching trenches into the substrate 50 . The etch may be any acceptable etch process, such as reactive ion etch (RIE), neutral beam etch (NBE), or the like, or combinations thereof. The etch can be anisotropic.

The fins 55 can be patterned by any suitable method. For example, the fins 55 may be patterned using one or more photolithographic processes, including double or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithographic and self-aligned processes, allowing for the fabrication of structures with smaller dimensions than achievable, for example, using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the fins 55. In some embodiments, the mask (or other layer) may remain on the fins 55.

In 4 shallow trench isolation (STI) regions 58 are formed adjacent to fins 55 . STI regions 58 may be formed by forming an insulating material (not separately illustrated) over substrate 50 and between adjacent fins 55 . The insulating material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system with post-curing to convert the deposited material to another material such as an oxide) or the like, or a combination thereof. Other insulation materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. After the insulating material is formed, an annealing process can be performed. In some embodiments, the insulation material is formed such that excess insulation material covers the fins 55 . The insulation material may comprise a single layer or use multiple layers. For example, in some embodiments, a liner (not separately illustrated) may be formed along the surfaces of the substrate 50 and the fins 55 first. Thereafter, a fill material such as those discussed above may be formed over the liner.

A removal process is then applied to the insulation material to remove excess insulation material over the fins 55 . In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, combinations thereof, or the like may be used. The planarization process can planarize the insulating material and the fins 55 . The planarization process exposes the fins 55 such that the top surfaces of the fins 55 and the insulating material are flush after the planarization process is complete.

The insulating material is then recessed to form the STI regions 58 as shown in FIG 4 illustrated. The insulating material is recessed such that top portions of the fins 55 and substrate 50 protrude between adjacent STI regions 58 . Furthermore, the upper surfaces of the STI regions 58 can have flat surfaces as illustrated, convex surfaces, concave surfaces (e.g., by dishing), or a combination thereof. The top surfaces of the STI regions 58 can be formed flat, convex, and/or concave by an appropriate etch. The STI regions 58 may be deepened using any acceptable etch process, such as an etch process that is selective to the material of the insulating material (e.g., which etches the material of the insulating material at a faster rate than the material of the fins 55 and the substrate 50). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) may be used.

The one related to 2 until 4 The process described is just one example of how the fins 55 may be formed. In some embodiments, the fins 55 may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of substrate 50 and trenches can be etched through the dielectric layer to expose underlying substrate 50 . Homoepitaxial structures can be epitaxially grown in the trenches and the dielectric layer can be deepened such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, heteroepitaxial structures may be used for the fins 55 in some embodiments. For example, the fins can be 55 in 4 recessed and a material other than the fins 55 may be epitaxially grown over the recessed fins 55. In such embodiments, the fins 55 include the recessed material and the epitaxially grown material disposed over the recessed material. In some embodiments, a dielectric layer may be formed over a top surface of substrate 50 and trenches may be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate 50 and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins 55 . In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, thereby avoiding prior and subsequent implants, but in situ and implant doping may also be used together.

Still further, it may be advantageous to epitaxially grow a different material in region 50N (e.g., an NMOS region) than the material in region 50P (e.g., a PMOS region). In some embodiments, upper portions of the fins 55 may be made of silicon germanium (Si _x Ge _1-x , where x can range from 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II- VI compound semiconductors or the like can be formed. Materials available for forming III-V compound semiconductors include, but are not limited to, for example, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

Furthermore, in 4 appropriate wells (not separately illustrated) may be formed in fins 55 and/or substrate 50. In some embodiments, a p-well may be formed in region 50N and an n-well in region 50P. In some embodiments, a p-well or an n-well is formed in both the n-type region 50N and the p-type region 50P.

In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist or other masks (not illustrated separately). For example, a photoresist may be formed over fins 55 and STI regions 58 in region 50N. The photoresist is patterned to expose area 50P of substrate 50, such as a PMOS area. The photoresist can be formed using a spin-on technique and patterned using acceptable photolithographic techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in region 50P and the photoresist can serve as a mask that substantially prevents n-type impurities from being implanted in region 50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like, ranging in concentration equal to or less than 1 x 10 ¹⁸ atoms/cm ³ , such as between about 1 x 10 ¹⁶ atoms/cm ³ and about 1 x 10 ¹⁸ atoms/cm ³ . After implantation, the photoresist is removed, for example by an acceptable ashing process.

Following the implantation of region 50P, a photoresist is formed over fins 55 and STI regions 58 in region 50P. The photoresist is patterned to expose area 50N of substrate 50, such as the NMOS area increase The photoresist can be formed using a spin-on technique and patterned using acceptable photolithographic techniques. Once the photoresist is patterned, a p-type impurity implantation can be performed in region 50N and the photoresist can serve as a mask that substantially prevents p-type impurities from being implanted in region 50P, such as a PMOS region. The p-type impurities may be boron, boron fluoride, indium, or the like, contained in the range at a concentration equal to or less than 1×10 ¹⁸ atoms/cm ³ , such as between about 1×10 ¹⁶ atoms/cm ³ and about 1×10 16 atoms/cm 3 10 ¹⁸ atoms/cm ³ . After implantation, the photoresist can be removed, for example by an acceptable ashing process.

After the region 50N and region 50P implants, an annealing step may be performed to repair implant damage and activate the implanted p-type and/or n-type impurities. In some embodiments, the grown materials of epitaxial fins can be in situ doped during growth, which can avoid the implants, but in situ and implant doping can also be used together.

In 5 dummy dielectric layers 60 are formed on the fins 55 and the substrate 50 . The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to any acceptable technique. A dummy gate layer 62 is formed over dummy dielectric layers 60 and a mask layer 64 is formed over dummy gate layer 62 . The dummy gate layer 62 may be deposited over the dummy dielectric layers 60 and then planarized by a process such as CMP. Mask layer 64 may be deposited over dummy gate layer 62 . The dummy gate layer 62 can be made of conductive or non-conductive materials and can be selected from a group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic includes oxides and metals. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used to deposit a selected material. The dummy gate layer 62 may be fabricated from other materials that have a higher etch selectivity than the STI region 58 material. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over regions 50N and 50P. It should be noted that the dummy dielectric layers 60 are shown covering only the fins 55 and the substrate 50 for purposes of illustration only. In some embodiments, dummy dielectric layer 60 may be deposited such that dummy dielectric layer 60 covers STI regions 58 , extending between dummy gate layer 62 and STI regions 58 .

6A until 22B 12 illustrate various additional steps in manufacturing devices according to embodiments. 6A until 22B illustrate features in either the 50N range or the 50P range. For example, the in 6A until 22B illustrated structures may be applicable to both region 50N and region 50P. Differences between the structures of area 50N and those of area 50P (if any) are described in the text that accompanies each figure.

In 6A and 6B the mask layer 64 (see 5 ) may be patterned to form masks 74 using acceptable photolithography and etching techniques. An acceptable etching technique can be used to transfer the pattern of the masks 74 to the dummy gate layer 62 to form dummy gates 72. FIG. In some embodiments, the structure of the masks 74 can also be transferred to the dummy dielectric layers 60 . The dummy gates 72 cover respective channel regions 68 of the fins 55. The structure of the masks 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The dummy gates 72 can also have a longitudinal direction that runs substantially perpendicular to the longitudinal direction of the respective fins 55 . The dummy dielectric layers 60, dummy gates 72, and masks 74 may collectively be referred to as a "dummy gate stack."

In 7A until 7C a first spacer layer 80 and a second spacer layer 82 over the in 6A and 6B illustrated structures formed. In 7A until 7C For example, first spacer layer 80 is formed on top surfaces of STI regions 58, top surfaces and sidewalls of fins 55 and masks 74, and sidewalls of dummy gates 72 and dummy dielectric layers 60. FIG. The second spacer layer 82 is deposited over the first spacer layer 80 . The first spacer layer 80 can be formed by thermal oxidation or by CVD, ALD or the like are deposited. The first spacer layer 80 can be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer 82 can be deposited by CVD, ALD, or the like. The second spacer layer 82 can be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

In 8A until 8C the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83 . The first spacer layer 80 and the second spacer layer 82 may be etched using any suitable etch process, such as an anisotropic etch process (e.g., a dry etch process) or the like. The first spacers 81 and the second spacers 83 may be arranged on the sidewalls of the fins 55, the dummy dielectric layers 60, the dummy gates 72 and the masks 74. FIG. The first spacers 81 and the second spacers 83 may have different heights near the fins 55 and the dummy gate stacks as well as different heights of the fins 55 due to the etching processes used to etch the first spacer layer 80 and the second spacer layer 82 and the dummy gate stack. As in 8B and 8C As illustrated, in some embodiments, the first spacers 81 and the second spacers 83 may partially pull up on the sidewalls of the fins 55 and dummy gate stacks. In some embodiments, the first spacers 81 and the second spacers 83 may extend to top surfaces of the dummy gate stacks.

After the first spacers 81 and the second spacers 83 are formed, implantations for lightly doped source/drain regions (LDD regions) (not illustrated separately) can be performed. In embodiments with different component types, similar to the above in 4 discussed implantations, a mask, such as photoresist, may be formed over region 50N while region 50P is exposed, and impurities of the appropriate type (e.g., p-type) may enter the exposed fins 55 and substrate 50 in region 50N 50P are implanted. The mask can then be removed. A mask, such as photoresist, can then be formed over region 50P while exposing region 50N, and impurities of the appropriate type (e.g., n-type) can enter the exposed fins 55 and substrate 50 in region 50N to be implanted. The mask can then be removed. The n-type impurities can be any of the n-type impurities previously discussed, and the p-type impurities can be any of the p-type impurities previously discussed. The lightly doped source/drain regions may have an impurity concentration of about 1×10 ¹⁵ atoms/cm ³ to about 1×10 ¹⁹ atoms/cm ³ . An anneal step can be used to repair implant damage and activate the implanted impurities.

It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacers 81 may be formed prior to forming the second spacer layer 83, additional spacers may be formed and removed, and/or the like). Also, the n-type and p-type devices can be formed using different structures and steps.

In 9A until 9C the substrate 50 and the fins 55 are etched to form first recesses 86 . As in 9C As illustrated, the top surfaces of the STI regions 58 may be flush with the top surfaces of the fins 55 . In some embodiments, bottom surfaces of first depressions 86 are located above or below top surfaces of STI regions 58 . The substrates 50/fins 55 are etched using anisotropic etching processes such as RIE, NBE or the like. The first spacers 81, the second spacers 83 and the masks 74 mask portions of the substrate 50/fins 55 during the etch processes used to form the first recesses 86. FIG. A single etch process or multiple etch processes may be used to form the first recesses 86 . Timed etch processes may be used to stop etching the first pits 86 after the first pits 86 reach a desired depth.

In 10A until 10D For example, epitaxial source/drain regions 92 are formed in the first recesses 86 to place stress on the channel regions 68 of the fins 55 and thereby improve performance. As in 10B As illustrated, the source/drain epitaxial regions 92 are formed in the first recesses 86 such that each dummy gate 72 is disposed between respective adjacent pairs of source/drain epitaxial regions 92 . In some embodiments, the first spacers 81 are used to separate the source/drain epitaxial regions 92 by an appropriate lateral width distance from the dummy gates 72 so that the epitaxial source/drain regions 92 are not shorted to the gates of the resulting FinFETs that are subsequently formed.

The epitaxial source/drain regions 92 in region 50N, e.g. the NMOS region, by masking the region 50P, e.g. B. the PMOS area are formed. Then the epitaxial source/drain regions 92 are epitaxially grown in the first recesses 86 . The source/drain epitaxial regions 92 may comprise any acceptable material, such as that appropriate for n-type FinFETs. For example, when the fins 55 are silicon, the epitaxial source/drain regions 92 may include materials that apply tensile stress to the second nanostructures 55, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. Epitaxial source/drain regions 92 may have surfaces raised from respective surfaces of fins 55 and may have facets.

The epitaxial source/drain regions 92 in region 50P, e.g. the PMOS region, by masking the region 50N, e.g. B. the NMOS area are formed. Then the epitaxial source/drain regions 92 are epitaxially grown in the first recesses 86 . The source/drain epitaxial regions 92 may comprise any acceptable material, such as that appropriate for p-type NSFETs. For example, when the fins 55 are silicon, the epitaxial source/drain regions 92 may include materials that apply compressive stress to the second nanostructures 55, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like. The epitaxial source/drain regions 92 may also have surfaces raised from respective surfaces of the fins 55 and may have facets.

The epitaxial source/drain regions 92, fins 55 and/or substrate 50 may be implanted with dopants to form source/drain regions similar to the process for forming lightly doped source/drain regions previously discussed , followed by an annealing step. The source/drain regions may have an impurity concentration between about 1×10 ¹⁹ atoms/cm ³ and about 1×10 ²¹ atoms/cm ³ . The n- and/or p-type impurities for source/drain regions can be any of the impurities previously discussed. In some embodiments, the source/drain epitaxial regions 92 may be in situ doped during growth.

As a result of the epitaxial processes used to form epitaxial source/drain regions 92 in region 50N and region 50P, top surfaces of epitaxial source/drain regions 92 have facets that extend laterally outward over the Side walls of the fins 55 extend away. In some embodiments, these facets cause adjacent source/drain epitaxial regions 92 of the same FinFET to grow together, as through 10C illustrated. In some embodiments, the adjacent source/drain epitaxial regions 92 remain separate after the epitaxial growth process is complete, as illustrated by FIG 10D is illustrated. In 10C and 10D In the illustrated embodiments, the first spacers 81 may be formed to cover portions of the sidewalls of the fins 55 that extend over the STI regions 58, thereby blocking epitaxial growth. In some embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 58 .

The epitaxial source/drain regions 92 may include one or more layers of semiconductor material. For example, the source/drain epitaxial regions 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the source/drain epitaxial regions 92 . Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed from different semiconductor materials and/or doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a lower dopant concentration than the second semiconductor material layer 92B and a higher dopant concentration than the third semiconductor material layer 92C. In embodiments where the epitaxial source/drain regions 92 include three layers of semiconductor material, the first layer of semiconductor material 92A may be deposited, the second layer of semiconductor material 92B may be deposited over the first layer of semiconductor material 92A, and the third layer of semiconductor material 92C may be deposited over the second layer of semiconductor material 92B will.

In 11A and 11B a first interlayer dielectric (ILD) 96 over the in 10A or. 10B illustrated structure deposited. The first ILD 96 may be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. In some embodiments, the dielectric materials for the first ILD 96 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. Other insulation materials formed by any acceptable process can be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the source/drain epitaxial regions 92 , the masks 74 , and the first spacers 81 . The CESL 94 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like that has a different etch rate than the overlying first ILD 96 material silicon nitride are formed.

In 12A and 12B For example, a planarization process, such as CMP, may be performed to cause the top surface of the first ILD 96 to be flush with the top surfaces of the dummy gates 72 or the masks 74. The planarization process may also remove the masks 74 on the dummy gates 72 and portions of the first spacers 81 along sidewalls of the masks 74. FIG. After the planarization process, the top surfaces of the dummy gates 72, the first spacers 81 and the first ILD 96 are flush. Accordingly, the top surfaces of the dummy gates 72 are exposed through the first ILD 96 . In some embodiments, masks 74 may remain, in which case the planarization process causes the top surface of first ILD 96 to be flush with the top surface of masks 74 and first spacers 81 .

In 13A and 13B the dummy gates 72 and the masks 74, if present, are removed in an etch step(s), whereby a second recess 98 is formed. Portions of the dummy dielectric layers 60 in the second recesses 98 may also be removed. In some embodiments, only the dummy gates 72 are removed and the dummy dielectric layers 60 remain and are exposed through the second recesses 98 . In some embodiments, the dummy dielectric layers 60 are removed from second recesses 98 in a first area of a die (e.g., a core logic area) and remain in second recesses 98 in a second area of the die (e.g., an input/output area). output area). In some embodiments, the dummy gates 72 are removed by an anisotropic dry etch process. The etch process may include, for example, a dry etch process using a reactive gas(es) that etch the dummy gates 72 at a faster rate than the first ILD 96 or the first spacers 81 . Each second depression 98 exposes and/or covers a channel region 68 of a respective fin 55 . Each channel region 68 is located between adjacent pairs of epitaxial source/drain regions 92 . During removal, the dummy dielectric layer 60 can be used as an etch stop layer when etching the dummy gates 72 . The dummy dielectric layer 60 can optionally be removed after removing the dummy gates 72 .

In 14A and 14B gate dielectric layers 100 and gate electrodes 102 are formed for replacement gates. 14C Figure 10 illustrates a detailed view of area 103 14B . The gate dielectric layers 100 may be formed by depositing one or more layers in the second recesses 98, e.g. B. on the top surfaces and sidewalls of the fins 55 and the first spacers 81 and on the top surfaces of the STI regions 58, the first ILD 96, the CESL 94 and the second spacers 83. The gate dielectric layers 100 can a or multiple layers of silicon oxide, silicon nitride, metal oxides, metal silicates, or the like. In some embodiments, the gate dielectric layers 100 include, for example, an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, or the like. Gate dielectric layers 100 may include a dielectric layer having a k value greater than about 7.0. The gate dielectric layers 100 may be deposited by molecular beam deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layer 60 remain in the second recesses 98, the gate dielectric layers 100 may comprise a dummy dielectric layer 60 material (eg, SiO ₂ ).

The gate electrodes 102 are deposited on the gate dielectric layers 100 and fill the remaining portions of the second recesses 98. The gate electrodes 102 can be a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten , combinations thereof or more layers of it. For example, although in 14B FIG. 12 illustrates a single layer gate electrode 102, the gate electrodes 102 include any number of liner layers 102A, any number of work function adjusting layers 102B, and a fill material 102C, as illustrated by FIG 14C illustrated. After filling the second recesses 98, a planarization process, such as a CMP, is performed to remove excess portions of the gate dielectric layers 100 and the gate electrodes 102, which excess portions overlie the top surface of the first ILD 96. The remaining portions of the gate electrodes 102 and the gate dielectric layers 100 form substitute gates of the resulting FinFETs. The gate electrodes 102 and the gate dielectric layers 100 may collectively be referred to as a “gate stack”. The gate stacks can extend along the sidewalls of the channel regions 68 of the fins 55 .

The formation of the gate dielectric layers 100 in regions 50N and 50P may occur simultaneously such that the gate dielectric layers 100 in each region are formed from the same materials. The formation of the gate electrodes 102 can be done simultaneously such that the gate electrodes 102 are formed from the same materials in each region. In some embodiments, the gate dielectric layers 100 may be formed by different processes in each region such that the gate dielectric layers 100 may be of different materials. The gate electrodes 102 in each region can be formed by different processes such that the gate electrodes 102 can be made of different materials. If different processes are used, different masking steps can be used to mask/uncover appropriate areas.

In 15A until 15C the first ILD 96 and the CESL 94 are etched to form third recesses 104 that expose surfaces of the epitaxial source/drain regions 92. FIG. The third recess can be formed using acceptable photolithographic and etching techniques. The etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Etching can be anisotropic.

In 16A until 16C a liner 106 such as a diffusion barrier layer, an adhesive layer or the like is formed in the third depressions 104 . The liner 106 may include titanium, titanium nitride, tantalum, tantalum nitride, silicon nitride, or the like. The liner 106 may be deposited by a conformal process such as CVD, ALD, or the like. The liner 106 may be along the top surfaces of the gate electrodes 102, the gate dielectric layers 100, the first spacers 81, the second spacers 83, and the epitaxial source/drain regions 92, as well as along the top surfaces and sidewalls of the first ILD 96 and the CESL 94 are deposited. The liner 106 may then be etched with a suitable etch process, such as an anisotropic etch process (e.g., a dry etch process) or the like, to remove lateral portions of the liner 106 and expose surfaces of the epitaxial source/drain regions 92 . Etching the liner 106 may also remove portions of the liner 106 over the top surfaces of the gate electrodes 102, the gate dielectric layers 100, the first spacers 81, the second spacers 83, the first ILD 96, and the CESL 94 . The liner 106 may have a thickness ranging from about 1 nm to about 2 nm.

In 17Abis 17C, a first contact material 108 is formed in the third recesses 104 over the source/drain epitaxial regions 92 and the liner 106. FIG. The first contact material 108 may be a conductive material such as cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), combinations thereof, or the like. The first contact material 108 may be deposited by a deposition process such as sputtering, chemical vapor deposition, atomic layer deposition, electro-deposition, electroless plating, or the like. In some embodiments, the first contact material 108 may be deposited to fill or overfill the third recesses 104 . The first contact material 108 can be planarized with the top surfaces of the first ILD 96 , the CESL 94 , the liner 106 , the gate electrodes 102 , the gate dielectric layers 100 , the first spacers 81 , and the second spacers 83 . The first contact material 108 can then be recessed to a level below the top surfaces of the first ILD 96, the CESL 94, the liner 106, the gate electrodes 102, the gate dielectric layers 100, the first spacers 81 and the second spacers 83 will. In one embodiment, the first contact material 108 is recessed using a wet or dry etch process using one or more etchants selective to the material of the first contact material 108 (e.g., cobalt or the like) without affecting the material of the first contact material first ILD 96, the CESL 94, the liner 106, the gate electrodes 102, the gate dielectric layers 100, the first spacers 81 and the second spacer 83 to remove substantially. The first contact material 108 may be recessed a first distance D ₁ between about 18 nm and about 25 nm. However, any suitable spacing can be used. An annealing process may be performed to form a silicide at the interface between the source/drain epitaxial regions 92 and the first contact material 108 . The first contact material 108 is physically and electrically coupled to the source/drain epitaxial regions 92 .

In 18A until 18D a second contact material 110 is formed over the first contact material 108 in the third cavities 104 . The second contact material 110 may be a conductive material such as tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu), molybdenum (Mo), combinations thereof, or the like. The second contact material 110 may be deposited by a deposition process such as sputtering, chemical vapor deposition, atomic layer deposition, electro-deposition, electroless plating, or the like. In some embodiments, the second contact material 110 may be deposited to fill or overfill the third recesses 104 . in the in 18B In the illustrated embodiment, the second contact material 110 may be deposited by a plating process or the like, and after deposition, the top surfaces of the second contact material 110 may be positioned over the top surfaces of the first ILD 96, the CESL 94, the liner 106, the gate electrodes 102, of the gate dielectric layers 100, the first spacers 81 and the second spacers 83 may be arranged. In some embodiments, the second contact material 110 may be formed from a material that differs from the material of the first contact material 108 . Using different materials for the second contact material 110 and the first contact material 108 lowers contact resistance, which improves device performance.

18D FIG. 11 illustrates an embodiment in which the top surfaces of the first contact material 108 and the second contact material 110 are non-planar. As in 18D As illustrated, the top surfaces of the first contact material 108 and the second contact material 110 may be W-shaped or M-shaped in a cross-sectional view. The top surfaces of the first contact material 108 and the second contact material 110 may include one or more dimples. However, any suitable shapes for the first contact material 108 and the second contact material 110 are possible depending on the deposition and etching processes used to form the first contact material 108 and the second contact material 110 . In some embodiments, the first contact material 108 and the second contact material 110 may be deposited by CVD at a temperature ranging from about 300°C to about 500°C, by PVD at room temperature, or the like. The deposition process may be followed by an annealing process at a temperature from about 300°C to about 600°C. Dry etching processes, e.g. B. based on halogen, can be used. In some embodiments, the second contact material 110 may be deposited by a plating process or the like. After the deposition, the top surfaces of the second contact material 110 can be over the top surfaces of the first ILD 96, the CESL 94, the liner 106, the gate electrodes 102, the gate dielectric layers 100, the first spacers 81 and the second spacers 83 can be arranged.

The materials of the second contact material 110 and the liner 106 may not have good adhesion to each other such that subsequent processes may form cracks or other defects between the second contact material 110 and the liner 106 . For example, during a subsequent process to planarize the second contact material 110, cracks may form between the second contact material 110 and the liner 106 (hereinafter referred to as FIG 20A until 20D discussed). The cracks allow process fluids, such as a CMP slurry, to enter between the second contact material 110 and the liner 106, and the process fluids can remove material from the second contact material 110 and the first contact material 108, introducing further device defects and reducing device performance.

In 19A until 19E Formed are second contact material 110 doped contact portions 110a, liner 106 doped liner portions 106a, first ILD 96 doped ILD portions 96a and CESL 94 doped CESL portions 94a. 19E and 19F illustrate detail views of a portion 111 of 19C . Doping the liner 106, the first ILD 96, and the CESL 94 to form the doped liner sections 106a, the doped ILD sections 96a, and the doped CESL sections 94a, respectively, can result in the materials of the liner 106, of the first ILD 96 and the CESL 94, which improves the sealing between the doped contact portions 110a and the doped liner portions 106a. The improved sealing between the doped liner sections 106a and the doped contact sections 110a prevents prevents process liquids, such as a CMP slurry, from penetrating between the doped liner sections 106a and the doped contact sections 110a. This prevents materials of the doped contact portions 110a, the second contact material 110, and the first contact material 108 from being undesirably removed by the process liquids or the like, reducing device defects and improving device performance.

The outer surfaces of each of the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may extend outwardly a distance of from about 1 nm to about 10 nm, or from about 1 nm to about 5 nm. Extending the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a by at least this amount improves the sealing between the doped contact portions 110a and each of the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL- Sections 94a, preventing process liquids from penetrating between the doped contact sections 110, the second contact materials 110 and the first contact materials 108 and each of the doped liner sections 106a, the doped ILD sections 96a and the doped CESL sections 94a. This prevents unwanted material removal from each of the doped contact portions 110a, the second contact material 110, and the first contact material 108, reduces device defects, and improves device performance.

The dopants in each of the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may increase to a depth of from about 1 nm to about 15 nm, or from about 1 nm to about 10 nm extend. Although the bottom extents of each of the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a are illustrated as being aligned at the same depth, each of the bottom surfaces of the doped contact portions 110a, the doped liner sections 106a, the doped ILD sections 96a and the doped CESL sections 94a may be misaligned with one another and extend to different depths. in the in 19A until 19D In the illustrated embodiment, the first contact material 108 is free of the dopants. However, in some embodiments, the dopants may extend through a partial or full thickness of the second contact material 110 and the dopants may extend into the first contact material 108 .

In some embodiments, the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may include the same dopants that are germanium (Ge), silicon (Si), argon (Ar), xenon ( Xe), arsenic (As), nitrogen (N), combinations thereof, or the like. In some embodiments, the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may further include hydrogen (H), which may be implanted along with the ambient air dopants or the like. The doped contact portions 110a, the doped CESL portions 94a, the doped liner portions 106a, and the doped ILD portions 96a may be formed by ion implantation. The dose for ion implantation can range from about 1×10 ¹⁴ atoms/cm ² to about 1×10 ¹⁶ atoms/cm ² and the tilt angle for ion implantation can range from about 0 degrees to about 60 degrees. The ion implantation can be performed at a temperature ranging from about -100°C to about 500°C with an applied energy ranging from about 2 keV to about 50 keV. In some embodiments, performing the ion implantation at a temperature in the range of about -100°C to about 25°C may provide for greater expansion of the doped liner portions 106a, the doped ILD portions 96a, and/or the doped CESL portions 94a. which can further improve the sealing between the doped contact portions 110a and the doped liner portions 106a. In some embodiments, the concentrations of the dopants in each of the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may range from about 1×10 ²⁰ atoms/cm ³ to about 2×10 ²² atoms/cm ³ to lie. In some embodiments, the concentrations of the dopants in the doped contact regions 110a may range from about 1×10 ¹⁸ atoms/cm ³ to about 1×10 ²¹ atoms/cm ³ .

The distribution of the dopants may vary in each of the doped contact regions 110a, the doped liner regions 106a, the doped ILD regions 96a, and the doped CESL regions 94a. A distribution of the dopants in the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a is given as that in FIG 19B and 19D illustrated curve 109 illustrates. In some embodiments, a peak in the distribution 109 may lie near the center of the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a in a direction perpendicular to a major surface of the substrate 50, but the disclosure is not limited thereto. In some embodiments, the peak of the distribution curve 109 may be near the top surfaces of the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a.

19E and 19F 12 illustrate the stress placed on the doped contact portions 110a by the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a, according to some embodiments. in the in 19E In the illustrated embodiment, the first contact material 108 (not separately illustrated), the second contact material 110 (not separately illustrated), and the doped contact portions 110a may have a rectangular shape in a top-down view. The stress S _x1 applied to the doped contact portions 110a in a first direction may be proportional to a width b ₁ of the doped contact portions 110a in the first direction and the stress S _y1 applied to the doped contact portions 110a in a second direction exerted perpendicular to the first direction may be proportional to a width a ₁ of the doped contact portions 110a in the second direction. The stress S _x1 and the stress S _y1 may also depend on the CESL 94 and first ILD 96 materials. Width a ₁ and width b ₁ can range from about 5 nm to about 200 nm, and the ratio of width a ₁ to width b ₁ can range from about 1 to about 40. In embodiments where the CESL 94 and the first ILD 96 are formed from the same materials (e.g., silicon oxide, silicon nitride, or the like), the stress S _x1 and the stress S _y1 may be equal when the widths a ₁ and the width b ₁ are the same, the stress S _x1 can be greater than the stress S _y1 when a ₁ is less than bi and the stress S _x1 can be less than the stress S _y1 when a ₁ is greater than b ₁ . In embodiments where the CESL 94 and the first ILD 96 are formed from different materials, the stress S _x1 and the stress S _y1 may be equal if one of the widths a ₁ or b ₁ is greater and one of the stresses S _x1 or the stress S _y1 may be larger when the widths a ₁ and b ₁ are equal or when one of the widths a ₁ or b ₁ is larger.

in the in 19F In the illustrated embodiment, the first contact material 108 (not separately illustrated), the second contact material 110 (not separately illustrated), and the doped contact portions 110a may have round shapes (e.g., elliptical shapes) in a top-down view. The stress S _x2 applied to the doped contact portions 110a in a first direction may be proportional to a width b ₂ of the doped contact portions 110a in the first direction and the stress S _y2 applied to the doped contact portions 110a in a second direction exerted perpendicular to the first direction may be proportional to a width a ₂ of the doped contact portions 110a in the second direction. The stress S _x2 and the stress S _y2 may also depend on the CESL 94 and first ILD 96 materials. Width a ₂ and width b ₂ can range from about 5 nm to about 200 nm, and the ratio of width a ₂ to width b ₂ can range from about 1 to about 40. In embodiments where the CESL 94 and the first ILD 96 are formed from the same materials (e.g., silicon oxide, silicon nitride, or the like), the stress S _x2 and the stress S _{y2 may be} equal when the widths a ₂ and the width b ₂ are equal, the stress S _x2 can be greater than the stress S _y2 when a ₂ is less than b ₂ , and the stress S _x2 can be less than the stress S _y2 when a ₂ is greater than b ₂ is. In embodiments where the CESL 94 and the first ILD 96 are formed from different materials, the stress S _x2 and the stress S _{y2 may be} equal if one of the widths a ₂ or b ₂ is greater and one of the stresses S _x2 or the stress S _y2 may be larger when the widths a ₂ and b ₂ are equal or when one of the widths a ₂ or b ₂ is larger.

Although the dopants have been described as being implanted only into the second contact material 110, the liner 106, the first ILD 96, and the CESL 94, in some embodiments the dopants may also be implanted into the first spacers 81, the second spacers 83, the gate Dielectric layers 100 and the gate electrodes 102 are implanted. The implantation of the dopants into one of the first spacers 81, the second spacers 83, the gate dielectric layers 100 and the gate electrodes 102 may result in additional stress being placed on the doped contact portions 110a, which compromises the seal between the doped Can improve contact portions 110a and the doped liner portions 106a. Additionally, in some embodiments, the dopants may be implanted across the entire thickness of the second contact material 110 and into the first contact material 108 .

In 20A until 20D For example, a planarization process, such as a CMP, can be performed to cause the top surfaces of the doped contact portions 110a to be flush with the top surfaces of the doped liner portions 106a, the doped ILD portions 96a, the doped CESL portions 94a, the first spacers 81, the second spacer 83, the gate dielectric layers 100 and the gate electrodes 102 is. The planarization process may use process liquids, such as a CMP slurry and the like, which may remove materials of the first contact material 108, the second contact material 110, and the doped contact portions 110a when the process liquids are in contact with the first contact material 108, the second contact material 110, and the doped contact portions 110a. Performing the ion implantation process to form the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a improves the sealing between the doped contact portions 110a and the doped liner portions 106a, preventing the process fluids from leaking between the doped liner portions 106a and each of the doped contact portions 110a, the second contact material 110 and the first contact material 108 penetrate. This prevents unwanted material removal from the doped contact portions 110a, the second contact material 110, and the first contact material 108, reduces device defects, and improves device performance.

After planarization, the distribution of dopants in the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may peak near the center of the doped contact portions 110a, the doped liner portions 106a, the doped ILD -portions 96a and the doped CESL portions 94a lie in a direction perpendicular to a major surface of the substrate 50. In some embodiments, the peak of the distribution of the dopants in the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a may peak near the top surfaces of the doped contact portions 110a, the doped liner portions 106a, of the doped ILD sections 96a and the doped CESL sections 94a.

In 21A and 21B A second ILD 114 is formed over the doped contact portions 110a, the doped liner portions 106a, the doped ILD portions 96a, the doped CESL portions 94a, the first spacers 81, the second spacers 83, the gate dielectric layers 100, and the gate -Electrodes 102 deposited. In some embodiments, the second ILD 114 becomes a flowable film formed by FCVD. In some embodiments, the second ILD 114 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, which may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, the dielectric materials for the second ILD 114 may include silicon oxide, silicon nitride, silicon oxynitride, or the like. In some embodiments, the gate stack (including the gate dielectric layers 100 and the corresponding overlying gate electrodes 102) is recessed prior to the formation of the second ILD 114 such that a recess is formed directly over the gate stack and between opposing portions of the first spacers 81 . A gate mask 112 comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like is filled into the recess, followed by a planarization process to remove excess portions of the dielectric material overlying the doped contact portions 110a, the doped liner sections 106a, the doped ILD sections 96a, the doped CESL sections 94a, the first spacers 81 and the second spacers 83 extend. Subsequently formed gate contacts (such as those below with reference to 22A and 22B gate contacts 116 discussed) penetrate the gate mask 112 to contact the top surface of the recessed gate electrodes 102. FIG.

In 22A and 22B the gate contacts 116 are formed by the second ILD 114 and the gate masks 112 and source/drain contacts 118 are formed by the second ILD 114 .

Openings for the source/drain contacts 118 are formed through the second ILD 114 and openings for the gate contacts 116 are formed through the second ILD 114 and the gate mask 112 . The openings can be formed using acceptable photolithographic and etching techniques. A liner, such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the openings. The liner may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD 114 . The remaining liner and conductive material form the sour ce/drain contacts 118 and the gate contacts 116 in the openings. The source/drain contacts 118 are physically and electrically coupled to the epitaxial source/drain regions 92 via the first contact material 108, the second contact material, and the doped contact portions 110a, and the gate contacts 116 are physically and electrically coupled to the Gate electrodes 102 coupled. The source/drain contacts 118 and the gate contacts 116 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that the source/drain contacts 118 and the gate contacts 116 can be formed in different cross-sections, thereby avoiding shorting of the contacts.

Embodiments can achieve various benefits. For example, doping the liner 106, the first ILD 96, and the CESL 94 to form the doped liner portions 106a, the doped ILD portions 96a, and the doped CESL portions 94a, respectively, may result in the materials of the The liner 106, the first ILD 96 and the CESL 94 expand, which improves the sealing between the doped contact portions 110a and the doped liner portions 106a. The improved sealing between the doped liner sections 106a and the doped contact sections 110a prevents process liquids, such as a CMP slurry, from penetrating between the doped liner sections 106a and the doped contact sections 110a. This prevents materials of the doped contact portions 110a, the second contact material 110, and the first contact material 108 from being undesirably removed by the process liquids or the like, reducing device defects and improving device performance.

The disclosed FinFET embodiments could also be applied to nanostructured devices such as nanostructured field effect transistors (e.g., nanosheet, nanowire, gate all around field effect transistors, or the like) (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the embodiments described above. After the dummy gate stack is removed, the sacrificial layers in channel areas can be partially or fully removed. The replacement gate structures are formed in a manner similar to the embodiments described above, the replacement gate structures may partially or completely fill openings left by the removal of the sacrificial layers, and the replacement gate structures may fill the channel layers partially or completely surrounded in the channel regions of the NSFET devices. The ILDs and the contacts to the replacement gate structures and the source/drain regions can be formed in a manner similar to the embodiments described above. A nanostructure device can be used as described in US patent application publication no. 2016/0365414, which is incorporated herein by reference in its entirety.

According to one embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, wherein a first portion of the first dielectric layer includes a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature comprising a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material comprising a material different than the first contact material, a first portion of the second contact material further comprising the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, wherein a first portion of the dielectric liner includes the first dopant. In one embodiment, the first dopant includes germanium (Ge). In one embodiment, the first contact material includes cobalt (Co) and the second contact material includes tungsten (W). In one embodiment, the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner each extend to depths of 1 nm to 15 nm. In one embodiment, the top surfaces of the first dielectric layer are the metal feature and the dielectric liner are flush with each other. In one embodiment, the semiconductor device further comprises a second dielectric layer over the conductive feature, a first portion of the second dielectric layer being doped with the first dopant, the first dielectric layer and the second dielectric layer each contacting sidewalls of the dielectric liner, and wherein the first dielectric layer and the second dielectric layer each comprise different materials. In one embodiment, the first dielectric layer includes silicon oxide and the second dielectric layer includes silicon nitride. In one embodiment, there is a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, first portion of the second contact material, and first portion of the dielectric liner at a top surface of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner, respectively. In one embodiment, a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the first dielectric layer is below a top surface of the first portion of the first dielectric layer, the first Section of the second contact material or the first section of the first dielectric layer.

According to another embodiment, a semiconductor device includes a first dielectric layer over a substrate and a conductive feature; a first doped dielectric layer over the first dielectric layer; a first portion of metal in the first dielectric layer electrically coupled to the conductive feature; a doped metal portion overlying the first metal portion, the first metal portion and the doped metal portion comprising a same metal material; a dielectric liner between the first dielectric layer and the first metal section; and a doped liner over the dielectric liner and between the first doped dielectric layer and the doped metal portion, wherein the first doped dielectric layer, the doped liner, and the doped metal portion each include first dopants. In one embodiment, the first dopants include xenon (Xe). In one embodiment, the semiconductor device further includes a second metal portion between the first metal portion and the conductive feature, wherein the second metal portion electrically couples the first metal portion to the conductive feature, and the second metal portion includes a different metal than the first metal portion. In one embodiment, the second metal portion includes cobalt (Co) and the first metal portion includes ruthenium (Ru). In one embodiment, the dielectric liner contacts the sidewalls of the first metal portion and the second metal portion, and the doped liner contacts the sidewalls of the first metal portion. In one embodiment, bottom extents of the first doped dielectric layer, the doped metal portion, and the doped liner are aligned with one another.

According to another embodiment, a method includes depositing a first dielectric layer over a conductive feature; etching the first dielectric layer to form an opening exposing the conductive feature; forming a dielectric liner in the opening, the dielectric liner lining sidewalls of the first dielectric layer; forming a first metal section in the opening over the conductive feature; forming a second metal portion over the first metal portion and filling the opening, the second metal portion comprising a material different than the first metal portion; and performing an ion implantation on the first dielectric layer, the dielectric liner, and the second metal portion, wherein the ion implantation causes the material of the first dielectric layer and the dielectric liner to expand toward the second metal portion. In one embodiment, forming the first metal portion includes depositing a first metal material in the opening; and etching back the first metal material, the first metal material comprising cobalt. In one embodiment, the ion implantation is performed at a temperature of -100°C to 25°C. In one embodiment, the ion implantation is performed with germanium dopants at a dosage of 1×10 ¹⁴ atoms/cm ² to 1×10 ¹⁶ atoms/cm ² and the ion implantation causes the material of the first dielectric layer and the dielectric liner to change extends toward the second metal section by at least 1 nm. In an embodiment, the method further includes planarizing the second metal portion, the dielectric liner, and the first dielectric layer after performing the ion implantation.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and/or achieve the same advantages of the embodiments presented herein. It should also be appreciated by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions and modifications can be made thereto without departing from the spirit and scope of the present disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63/082045 [0001]

Claims (20)

A semiconductor device comprising: a first dielectric layer over a conductive feature, a first portion of the first dielectric layer comprising a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature comprising: a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material comprising a material different than the first contact material, a first portion of the second contact material further comprising the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, wherein a first portion of the dielectric liner includes the first dopant. semiconductor device claim 1 , wherein the first dopant comprises germanium (Ge). semiconductor device claim 1 or 2 , wherein the first contact material comprises cobalt (Co) and the second contact material comprises tungsten (W). A semiconductor device as claimed in any preceding claim, wherein the first portion of the first dielectric layer, the first portion of the second contact material and the first portion of the dielectric liner each extend to depths in the range 1 nm to 15 nm. A semiconductor device as claimed in any preceding claim, wherein the top surfaces of the first dielectric layer, the metal feature and the dielectric liner are flush with one another. The semiconductor device of any preceding claim, further comprising a second dielectric layer over the conductive feature, a first portion of the second dielectric layer being doped with the first dopant, the first dielectric layer and the second dielectric layer each contacting sidewalls of the dielectric liner, and wherein the first dielectric layer and the second dielectric layer each comprise different materials. semiconductor device claim 6 , wherein the first dielectric layer comprises silicon oxide and the second dielectric layer comprises silicon nitride. Semiconductor component according to one of the preceding patent claims 1 until 7 wherein a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the dielectric liner is at a top surface of the first portion of the first dielectric layer, the first portion of the second Contact material or the first portion of the dielectric lining is located. Semiconductor component according to one of the preceding Claims 1 until 7 , wherein a maximum concentration of the first dopant in each of the first portion of the first dielectric layer, the first portion of the second contact material, and the first portion of the first dielectric layer is below a top surface of the first portion of the first dielectric layer, the first portion of the second contact material or the first portion of the first dielectric layer is located. A semiconductor device comprising: a first dielectric layer over a substrate and a conductive feature; a first doped dielectric layer over the first dielectric layer; a first portion of metal in the first dielectric layer electrically coupled to the conductive feature; a doped metal portion overlying the first metal portion, the first metal portion and the doped metal portion comprising a same metal material; a dielectric liner between the first dielectric layer and the first metal section; and a doped liner over the dielectric liner and between the first doped dielectric layer and the doped metal portion, wherein the first doped dielectric layer, the doped liner, and the doped metal portion each include first dopants. semiconductor device claim 10 , wherein the first dopants comprise xenon (Xe). semiconductor device claim 10 or 11 , further comprising a second metal portion between the first metal portion and the conductive feature, wherein the second metal portion electrically couples the first metal portion to the conductive feature and the second metal portion comprises a different metal than the first metal portion. semiconductor device claim 12 wherein the second metal portion comprises cobalt (Co) and the first metal portion comprises ruthenium (Ru). semiconductor device claim 12 or 13 wherein the dielectric liner contacts the sidewalls of the first metal portion and the second metal portion, and wherein the doped liner contacts the sidewalls of the first metal portion. Semiconductor component according to one of the preceding Claims 10 until 14 , wherein bottom extents of the first doped dielectric layer, the doped metal portion, and the doped liner are aligned with one another. Procedure, which includes: depositing a first dielectric layer over a conductive feature; etching the first dielectric layer to form an opening exposing the conductive feature; forming a dielectric liner in the opening, the dielectric liner lining sidewalls of the first dielectric layer; forming a first metal section in the opening over the conductive feature; forming a second metal section over the first metal section and filling the opening, the second metal section comprising a different material than the first metal section; and performing an ion implantation on the first dielectric layer, the dielectric liner, and the second metal portion, wherein the ion implantation causes the material of the first dielectric layer and the dielectric liner to expand toward the second metal portion. procedure after Claim 16 , wherein forming the first metal portion comprises: depositing a first metal material in the opening; and etching back the first metal material, the first metal material comprising cobalt. procedure after Claim 16 or 17 , wherein the ion implantation is performed at a temperature of -100 °C to 25 °C. Method according to any of the preceding Claims 16 until 18 , wherein the ion implantation is performed with germanium dopants at a dosage of 1×10 ¹⁴ atoms/cm ² to 1×10 ¹⁶ atoms/cm ² , and wherein the ion implantation causes the material of the first dielectric layer and the dielectric liner to change extends towards the second metal section by at least 1 nm. Method according to any of the preceding Claims 16 until 19 , further comprising planarizing the second metal portion, the dielectric liner, and the first dielectric layer after performing the ion implantation.

Images