DE102021100438B3 - Device for simultaneous delta-sigma analog-to-digital conversion of multiple input signals - Google Patents

Abstract

The invention relates to a device and a method for converting input signals (Uin1, Uin2, Uin3, ...Uinj, ...Uinn) into digitized output signals (out1, out2, out3, ...outk, ...outm). The input signals are assumed to be quasi-static. Each channel is shifted into a channel-specific frequency band with a specific chopper frequency. The storage effect of the delta-sigma integrator leads to a frequency band-specific phase shift during digitization. When mixing down the individual frequency bands, the phase shift is taken into account if necessary. One then obtains the digitized values that are unmixed compared to the other channels. If the phase shift is not taken into account, the signals will be mixed.

Description

field of invention

The invention relates to a method and an associated device for converting a plurality of at least n input signals (U _in1 , U _in2 , U _in3 , ... U _inj , ... U _inn ) into m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...outm).

General introduction

In many applications, delta-sigma analog-to-digital converters are used as analog-to-digital converters (ADC). Often the voltage values of different input signals, for example of n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _in,n ) are to be recorded. Let n be a positive integer greater than 1 and j a positive integer with 1≤j≤n. This is preferably done in time-division multiplex by means of an analog multiplexer (MUX), which is controlled by a control signal (SEL) of the analog multiplexer (MUX). We explain the state of the art (SdT) based on the 1 and 2 . The figures of this document are simplified and shown schematically for the sake of clarity.

Depending on the control signal (SEL), the analog multiplexer (MUX) preferably connects precisely one of its n input signals, for example (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _{in ,n} ) with the input signal (S1) of the analog-to-digital converter (ADC). To explain this, we assume that the analog multiplexer (MUX) currently mixes an arbitrarily selected jth input signal (U _in,j ) with the input signal (S1) of the analog-to-digital converter ( ADC) connects. As already mentioned, the number j is a positive integer with 1≤j≤n. The analog-to-digital converter (ADC) acquires the value of the selected j-th input signal (U _in,j ) and outputs the value thus digitized as a digitized output signal (out) of the analog-to-digital converter (ADC). . This prior art situation is in 1 shown.

A problem arises when delta-sigma analog-to-digital converters are used as analog-to-digital converters (ADC), since these typically have a storage element, for example an integrating filter (INT), which stores the measured values when switching between the n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _in,n ) by means of the control signal (SEL) due to the storage effect.

For this example on the 2 referred. 2 FIG. 12 shows an exemplary implementation of the prior art analog-to-digital converter (ADC) as a simple delta-sigma converter.

The analog multiplexer (MUX) of the 2 connects again depending on a control signal (SEL) preferably again exactly one of its e.g. n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _in,n ) , for example a jth input signal (U _in,j ) with 1≤j≤n, with the input signal (S1) of the analog-to-digital converter (ADC), which is now an exemplary delta-sigma analog-to- digital converter is. A subtractor (Sub) subtracts the value of a feedback signal (S5) in the example of FIG 2 from the input signal (S1) of the analog-to-digital converter (ADC) and thus forms the difference signal (S2). A filter (INT), which is preferably an integrator or a filter with integrating properties, filters the difference signal (S2) to form the filter output signal (S3). A quantizer or another analog-to-digital converter (eg a simple inverter) (QNT) quantizes the filter output signal (S3) to the quantized intermediate signal (S4). A decimation filter (LPF/DEZ), which is preferably a low-pass filter, converts the intermediate signal (S4) to the output signal (out) and outputs the digitized value as the digitized output signal (out) of the analog-to-digital converter (ADC). A digital-to-analog converter (DAC) forms the analog feedback signal (S5) from the digitized intermediate signal (S4), which is fed back to the subtractor (SUB). This closes the control loop.

The analog multiplexer (MUX) preferably comprises a transconductance amplifier, which transmits the voltage value at its input signal (U _in,j ) selected by means of the control signal (SEL) of its, for example, n input signals (U _in,1 , U _in,2 , U _in,3 , . ..U _in,j , ...U _in,n ) into an electrical current, which it feeds into the input signal (S1) of the analog-to-digital converter (ADC). Said digital-to-analog converter (DAC) preferably converts the intermediate signal (S4) into an electrical current which corresponds to the value of the intermediate signal (S4) with a preferably negative sign. The sign is important for the stability of the control loop. It can also be inserted elsewhere in the control loop. The intermediate signal (S4) can have a bit width of one bit or else a bit width of several bits. The output of the quantizer (QNT) can be followed by a digital filter that reduces the bit width of the output of the quantizer (QNT) compared to the bit width of the intermediate signal (S4). For example, the quantizer (QNT) can be a special inverter whose output accordingly only has a bit width of 1. The filter connected downstream of the output of the quantizer (QNT) can then, for example, generate an intermediate signal (S4) with an arbitrary exemplary bit width of six from the one-bit-wide output signal of the quantizer (QNT). This downstream filter can also be regarded as part of the quantizer (QNT), that is to say it can be integrated into it, which is why it is not shown in the drawings. If necessary, another digital filter can be connected between the output signal of the quantizer (QNT) and the input of the digital-to-analog converter (DAC) that adapts the bit width of the intermediate signal (S4) to the bit width of the digital-to-analog converter. converter (DAC) adjusts. This filter can possibly also be understood as part of the digital-to-analog converter (DAC) and is therefore not shown in the figures for the sake of clarity. Since the digital-to-analog converter (DAC) preferably converts the intermediate signal (S4) into an electrical current which corresponds to the value of the intermediate signal (S4) with a negative sign, the subtractor (SUB) can then simply be replaced by an electrical connecting nodes are replaced. Such a connection node is therefore a possible realization of a subtractor (Sub). The digital-to-analog converter (DAC) and the transconductance amplifier of the multiplexer (MUX) then each inject a current into this node of the subtractor (SUB). The subtraction then comes about through the negative sign of the current of the digital-to-analog converter (DAC). The sum current formed in this sum node of the subtractor (Sub) is then fed into the filter (INT) as a difference signal (S2). In this case, the difference signal (S2) is a current signal. In the example, the filter (INT) is then preferably a capacitor, for example, which is connected to a first terminal of the capacitor with the difference signal (S2) and which is connected to the other, second terminal of the capacitor with a reference potential line at reference potential, for example ground (GND ), connected is. For the sake of simplicity, the supply voltage line and the reference potential line (GND) are not shown in the figures. The current signal of the difference signal (S2) then charges this capacitor depending on the current value difference of the current value of the input signal (S1) of the analog-to-digital converter (ADC) minus the current value magnitude of the feedback signal (S5) of the digital-to-analog converter (DAC) on or off. In the example of a capacitor as an exemplary filter (INT), the filter output signal (S3) is preferably connected directly to the first connection of the exemplary capacitor and thus directly to the difference signal (S2). The quantizer (QUNT) preferably evaluates the potential of the first connection of the exemplary capacitor against the reference potential of the reference potential line (GND). For the sake of simplicity, we assume that the quantizer (QNT) is a simple inverter. If the voltage between the first terminal of the exemplary capacitor of the exemplary filter (INT) and the reference potential crosses the threshold level of the quantizer (QNT) in the form of a simple inverter, the output signal of the exemplary quantizer (QNT) switches, and the charging direction of the charging current of the exemplary filter capacitor (INT) changes direction. Since the digital-to-analog converter (DAC) and the entire controlled system have a control time constant (t _delay ), in the stable state the value of the intermediate signal (S4) oscillates at a frequency (1/T _delay ) around the true value. This frequency is usually inherent in the design and therefore predictable. A decimation filter (LPF/DEZ) of the exemplary analog-to-digital converter (ADC) designed as a delta-sigma converter 2 removes this oscillation from the intermediate signal (S4) and forms the digitized output signal of the analog-to-digital converter (ADC). It is typically a digital low-pass filter. Typically, the decimation filter also changes the bit width of the output signal (out) compared to the bit width of the intermediate signal (S4).

The problem in question, which the technical solution proposed here aims to avoid, is caused by the integrating properties of the filter (INT) in which the past measurements are stored. The analog multiplexer (MUX) now switches, for example, from a first connection configuration of a connection between a jth input signal (U _in,j ) to the input signal (S1) of the analog-to-digital converter (ADC) to a second connection configuration of a connection a p-th input signal (U _in,p ) with the input signal (S1) of the analog-to-digital converter (ADC), where p≠j and 1≦j≦n and 1≦p≦n should apply immediately after switching, the value of the integrator still has a value which corresponds to the j-th input signal (U _in,j ) and which does not, as it should, correspond to the p-th input signal (U _in,p ). . As a result, massive erroneous measurements occur for a short time, which only occur after the controller has stabilized, namely when the value of the integrator again corresponds to the pth input signal (U _in,p ) and thus displays a correct value again. Thus, the switching speed between the input channels, ie between the n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _in,n ) is limited.

Exemplary state of the art

A number of documents relating to delta-sigma converters are known from the prior art. We name the scriptures here as an example EP 3 413 466 A1 , EP 3 579 419 A1 , U.S. 10,135,459 B2 , US 2003 0 146 786 A1 , U.S. 6,707,409 B1 , U.S. 6,985,030 B2 , U.S. 7,193,545 B2 , U.S. 7,227,481 B2 , U.S. 7,477,178 B1 , U.S. 7,551,110 B1 , U.S. 7,999,710 B2 , U.S. 8,004,444 B2 , U.S. 8,097,853 B2 , U.S. 8,421,660 B1 , U.S. 8,471,744 B1 , U.S. 8,553,827 B2 , U.S. 8,576,002 B2 , U.S. 8,836,553 B2 , U.S. 9,154,155 B2 , U.S. 9,300,319 B2 , U.S. 9,379,731 B1 , U.S. 9,455,733 B1 , U.S. 9,685,967 B1 .

The devices have the disadvantages described above, particularly when combined with an input multiplexer.

From the 5 the U.S. 10,348,530 B1 a transmitter in the form of an OFDM transmitter and a receiver in the form of an OFDM receiver are known, which are part of a multi-carrier transmission system. According to the technical teachings of U.S. 10,348,530 B1 a multiplication of input currents with different modulation frequencies takes place in the transmitter. The recipient of the 5 the U.S. 10,348,530 B1 points in the lower part of the 5 the U.S. 10,348,530 B1 an analogue/digital conversion and a subsequent fast Fourier transformation. the 5 the U.S. 10,348,530 B1 represents the baseband distribution of the OFDM transmission system U.S. 10,348,530 B1 also has the disadvantages described above.

From the U.S. 2012/0 288 034 A1 discloses a method and system for performing complex signal sampling using two or more sampling channels and calculating time delays between these channels. The device of U.S. 2012/0 288 034 A1 uses an analog-to-digital converter for each channel (see 2 the U.S. 2012/0 288 034 A1 ) and thus does not solve the problem, but circumvents it with increased effort.

From the DE 10 2018 119 278 A1 a method and a device for processing an OFDM radar signal are known. Like them U.S. 2012/0 288 034 A1 also uses the DE 10 2018 119 278 A1 one analog-to-digital converter for each channel (see 1A below the DE 10 2018 119 278 A1 ) and thus does not solve the problem, but circumvents it with increased effort.

From the U.S. 2018/0 358 979 A1 a delta-sigma modulator is known, which also does not solve the problem.

task

The object of the proposal is therefore to create a solution that does not have the above disadvantages of the prior art and has other advantages. In particular, rapid switching between the n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _in,n ) should be made possible.

This object is achieved by a device according to claim 6 and a method according to claim 1.

solution of the task

To solve the technical problem, a method is first proposed, which corresponds to a device that will be presented later.

In the following, n is always a positive integer greater than 1.

In the following, j always denotes a positive integer with 1≤j≤n.

In the following, m always denotes a positive integer with 1≤m≤n.

In the following, k always denotes a positive integer with 1≤k≤m and j≠k.

In the following, p always denotes a positive integer with 1≤p≤n.

We propose a method for converting a plurality of at least n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _in,j , ...U _in,n ) into m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...outm).

The basic idea can be realized with the help of the 3 and 4 be explained.

In the exemplary system of 3 the j-th input signal (U _in,j ) is converted into a j-th summand signal (SO _j ) using a j-th input multiplier (M _1,j ). For this purpose, the j-th input multiplier (M _1,j ) multiplies the j-th input signal (U _in,j ) by a j-th modulation signal (MX _j ) to form the j-th summand signal (SO _j ). A generator (G) produces the jth modulation signal (MX _j ). The analog-to-digital converter (ADC) generates the digitized intermediate signal (S4) from the j-th summand signal (SO _j ). In the steady state, the value of the digitized intermediate signal (S4) is typically proportional to the value of the j-th summand signal (SO _j ). In the simplest case, however, the analog-to-digital converter (ADC) typically has a low-pass characteristic. In other words, a frequency-dependent phase shift typically occurs between the time profile of the digitized intermediate signal (S4) and the time profile of the j-th summand signal (SO _j ). This is exactly said storage effect, which leads to said problems, for example, in delta-sigma converters, such as the 2 , caused by the memory element of the integrating filter (INT).

We now assume for the purpose of explanation that the j-th input signal (U _in,j ) is constant in time or has signal components with frequencies that are so low compared to the center frequencies introduced later that they can be assumed to be approximately constant . Due to the construction of the analog-to-digital converter (ADC), which is generally known, the distortion of the intermediate signal (S4) compared to the j-th summand signal (SO _j ) can be predicted. As a rule, this can be described by a mathematical function that is typically bijective in certain areas. In the case of analog-to-digital converter (ADC) attenuation or amplification coupled with a phase shift, this can easily be done by suitably advancing the generation of the j-th modulation signal (MX _j ) in time by the generator (G) and corrected by an amplitude adjustment of the j-th modulation signal (MX _j ) or the k-th analysis signal (MY _k ) described later.

A k-th output multiplier (M _2,k ) multiplies the intermediate signal (S4) by the k-th analysis signal (MY _k ) to form the k-th decimation preliminary signal (S6 _k ). Ideally, the j-th modulation signal (MX _j ), which is generated by the generator (G), is designed in such a way that its corresponding signal component in the intermediate signal (S4) after passage through the analog-to-digital converter (ADC) and after deformation in the analog-to-digital converter (ADC) is proportional to the k-th analysis signal (MY _k ). Ie the relationship between the k-th analysis signal (MY _k ) and the j-th modulation signal (MX _j ) by the deformation properties of the analog-to-digital converter (ADC) for a passage of the j-th modulation signal (MX _j ) through the analog-to-digital converter (ADC). The mathematical function describing the analog-to-digital converter (ADC) deformation properties for a passage of the j-th modulation signal (MX _j ) through the analog-to-digital converter (ADC) should preferably be bijective or for the purpose be approached bijectively during handling.

Assuming for the purpose of explanation that the jth modulation signal (MX _j ) is mono-frequency with a j-th center frequency (ω _mm,j ) and the k-th analysis signal (MY _k ) is mono-frequency with a k-th center frequency ( ω _mm,k ), this second mixing in the k-th output multiplier (M _2,k ) results in a first signal component in the k-th decimation preliminary signal (S6 _k ), which has a first mid-mixing frequency corresponding to the difference from the j-th mid-frequency ( ω _mm,j ) and k-th center frequency (ω _mm,k ). Furthermore, this second mixing in the k-th output multiplier (M _2,k ) results in a second signal component in the k-th decimation preliminary signal (S6 _k ), which has a second center mixing frequency corresponding to the sum of the j-th center frequency (ω _mm,j ) and k-th center frequency (ω _mm,k ).

In the ideal case, the j-th center frequency (ω _mm,j ) will be equal to the k-th center frequency (ω _mm,k ), since the k-th analysis signal (MY _k ) prefers the j-th modulation signal (MX _j ). Passage through the analog-to-digital converter (ADC) should be essentially proportional to a phase shift. This typically corresponds to a requirement for j=k for this case.

The first signal part then has a first mixed center frequency of essentially 0Hz, while the second signal part has a second mixed center frequency which is essentially twice the jth center frequency (ω _mm,j ) and thus essentially twice the kth center frequency (ω _mm,k ) corresponds.

A downstream k-th decimation filter (LPF _k /DEZ _k ) removes the second signal component, which has the second center mixing frequency, from the k-th decimation preliminary signal (S6 _k ) and thus forms the k-th output signal (out _k ). It is therefore preferably a digital low-pass filter that only lets through the first signal component with a center mixing frequency close to 0 Hz and blocks the second signal component with the second center mixing frequency. The low-pass filter preferably also blocks the j-th center frequency (ω _mm,j ) and the k-th center frequency (ω _mm,k ). Typically, the k-th decimation filter (LPF _k /DEZ _k ) changes the bit width of the k-th output signal (out _k ) compared to the bit width of the k-th decimation pre-signal (S6 _k ) as required.

With the help of 3 we have now adequately explained the basic, modified chopper method with a modulation signal (MX _j ) that is typically phase-shifted in relation to the analysis signal (MY _k ). The phase shift can also be 0. In this proposed modified chopper method, the k-th analysis signal (MY _k ) corresponds to the j-th modulation signal (MX _j ) only if the signal component of the j-th summand signal (SO _j ), which corresponds to the j-th modulation signal ( MX _j ) corresponds, is not deformed by the analog-to-digital converter (ADC), ie delayed, for example. In the method proposed here, the storage effect of the integrating filter (INT) within the analog-to-digital converter (ADC) is instead taken into account by, for example, comparing the k-th analysis signal (MY _k ) with the j-th modulation signal (MX _j ) is amplified (or possibly dampened) and possibly phase-shifted in a defined manner. This is a first difference from the prior art.

figure 4

If the reciprocal of the j-th center frequency (ω _mm,j ) and thus the k-th center frequency (ω _mm,k ) is small compared to the time delay (τ _ADC ) in the analog-to-digital converter (ADC), then the k- th analysis signal (MY _k ) equal to the j-th modulation signal (MX _j ), ie with a phase shift of 0, are chosen. In this case, logically, k=j preferably applies by way of example.

figure 5

In the example of 5 to simplify the description, a simple system with two modulation signals (MX ₁ , MX ₂ ) and two analysis signals (MY ₁ , MY ₂ ) will now be considered, which is thus slightly more complex than the system of FIG 3 is.

In the exemplary device of 5 For example, the first analysis signal (MY ₁ ) should be proportional to the first signal component of the intermediate signal (S4), which corresponds to that signal component of the first summand signal (S0 ₁ ) after passage through the analog-to-digital converter (ADC) that is associated with the first modulation signal (MX ₁ ) corresponds. As described above, this first signal component of the intermediate signal (S4) is typically deformed by the analog-to-digital converter (ADC) during its passage through the analog-to-digital converter (ADC), i.e. phase-delayed with a first phase delay, for example.

In the exemplary device of 5 the second analysis signal (MY ₂ ), for example, should be proportional to the second signal component of the intermediate signal (S4), which corresponds to that signal component of the second summand signal (S0 ₂ ) after passage through the analog-to-digital converter (ADC), which corresponds to the second modulation signal (MX ₂ ) corresponds. As described above, this second signal component is typically also deformed by the analog-to-digital converter (ADC) during its passage through the analog-to-digital converter (ADC), ie phase-delayed with a second phase delay, for example.

The first phase delay can be different than the second phase delay.

The first phase delay can be 0. The second phase delay can be 0.

In the exemplary system of 5 the first input multiplier (M _1,1 ) converts the first input signal (U _in,1 ) into a first summand signal (S0 ₁ ). To this end, the first input multiplier (M _1,1 ) multiplies the first input signal (U _in,1 ) by a first modulation signal (MX ₁ ) to form the first summand signal (S0 ₁ ).

The second input multiplier (M _1.2 ) converts the second input signal (U _in.2 ) into a second summand signal (S0 ₂ ). To this end, the second input multiplier (M _1,2 ) multiplies the second input signal (U _in,2 ) by a second modulation signal (MX ₂ ) to form the second summand signal (S0 ₂ ).

The generator (G) generates the first modulation signal (MX ₁ ) preferably leading with the amount of the first phase delay before the first analysis signal (MY ₁ ). The generator (G) generates the second modulation signal (MX ₂ ) preferably in advance with the amount of the second phase delay before the second analysis signal (MY ₂ ). The first modulation signal (MX ₁ ) and the second modulation signal (MX ₂ ) form the modulation signal bundle (MXB). The first analysis signal (MY ₁ ) and the second analysis signal (MY ₂ ) form the analysis signal bundle (MYB).

A summation and difference formation device (Σ) adds the instantaneous values of the first summand signal (S0 ₁ ) and the second summand signal (S0 ₂ ) to the instantaneous value of the difference signal (S2) and thus forms the difference signal (S2). The term difference signal has been retained here for clarity to ensure consistency with the previously described figures.

The analog-to-digital converter (ADC) generates the digitized intermediate signal (S4) from the difference signal (S2). In the steady state, the value of the digitized intermediate signal (S4) is typically proportional to the value of the typically analog differential signal (S2). We again assume that the analog-to-digital converter (ADC) again exhibits an exemplary low-pass characteristic. I.e. between the time profile of the digitized intermediate signal (S4) and the time profile of the difference signal (S2) there should again be a typically frequency-dependent phase shift as an example of distortion by the analog-to-digital converter (ADC).

The first center frequency (ω _mm,1 ) of the first modulation signal (MX ₁ ) should again deviate from the second center frequency (ω _mm,2 ) of the second modulation signal (MX ₂ ).

We assume, for example, that the first center frequency (ω _mm,1 ) of the first modulation signal (MX ₁ ) leads to a first phase shift of the signal component of the differential signal (S2), which corresponds to this first modulation signal (MX ₁ ), in analog-to- digital converter (ADC) leads.

We also assume, for example, that the second center frequency (ω _mm,2 ) of the second modulation signal (MX ₂ ) leads to a second phase shift of the signal component of the difference signal (S2), which corresponds to this second modulation signal (MX ₂ ), in the analog to digital converter (ADC) leads.

We therefore have good reason to assume that the first phase shift differs from the second phase shift because the first center frequency (ω _mm,1 ) of the first modulation signal (MX ₁ ) differs from the second center frequency (ω _mm,2 ) of the second modulation signal (MX ₂ ) differs.

Again, just for the purpose of simplifying the explanation, we assume that the first input signal (U _in,1 ) is essentially constant in time and that the second input signal (U _in,2 ) is essentially constant in time.

Due to the generally known construction of the analog-to-digital converter (ADC), the distortion of the intermediate signal (S4) compared to the first summand signal (S0 ₁ ) and compared to the second summand signal (S0 ₂ ) can be predicted.

As a rule, this can be described by a respective, preferably bijective, mathematical function.

1. a) durch eine geeignete zeitliche Vorverlegung der Erzeugung des ersten Modulationssignals (MX₁) entsprechend der ersten Phasenverschiebung und
2. b) ggf. durch eine Amplitudenanpassung des ersten Modulationssignals (MX₁)
3. c) durch eine geeignete zeitliche Vorverlegung der Erzeugung des zweiten Modulationssignals (MX₂) entsprechend der zweiten Phasenverschiebung und
4. d) ggf. durch eine Amplitudenanpassung des zweiten Modulationssignals (MX₂)

korrigiert werden.In the case of analog-to-digital converter (ADC) attenuation or gain paired with phase shift, this can easily

1. a) by a suitable advance in time of the generation of the first modulation signal (MX ₁ ) according to the first phase shift and
2. b) possibly by adjusting the amplitude of the first modulation signal (MX ₁ )
3. c) by suitably bringing forward the generation of the second modulation signal (MX ₂ ) in accordance with the second phase shift and
4. d) possibly by adjusting the amplitude of the second modulation signal (MX ₂ )

Getting corrected.

A first output multiplier (M _2.1 ) multiplies the intermediate signal (S4) by the first analysis signal (MY ₁ ) to form the first decimation pre-signal (S6 ₁ ).

A second output multiplier (M _2.2 ) multiplies the intermediate signal (S4) by the second analysis signal (MY ₂ ) to form the second decimation preliminary signal (S6 ₂ ).

In the ideal case, the first modulation signal (MX ₁ ), which is generated by the generator (G), is designed in such a way that its signal component in the intermediate signal (S4) after passage through the analog-to-digital converter (ADC) and after deformation in the analog to digital converter (ADC) is proportional to the first analysis signal (MY ₁ ). That is, the relationship between the first analysis signal (MY ₁ ) and the first modulation signal (MX ₁ ) is determined by the deformation properties of the analog-to-digital converter (ADC) for a passage of the first modulation signal (MX ₁ ) through the analog-to-digital converter (ADC). The mathematical function describing the deformation properties of the analog-to-digital converter (ADC) for a passage of the first modulation signal (MX ₁ ) through the analog-to-digital converter (ADC) should preferably be bijective, or bijective for handling purposes be approximated.

In the ideal case, the second modulation signal (MX ₂ ), which is generated by the generator (G), is designed in such a way that its signal component in the intermediate signal (S4) after passage through the analog-to-digital converter (ADC) and after deformation in the analog to digital converter (ADC) is proportional to the second analysis signal (MY ₂ ). That is, the relationship between the second analysis signal (MY ₂ ) and the second modulation signal (MX ₂ ) is determined by the deformation properties of the analog-to-digital converter (ADC) for a passage of the second modulation signal (MX ₂ ) through the analog-to-digital converter (ADC). The mathematical function describing the deformation properties of the analog-to-digital converter (ADC) for a passage of the second modulation signal (MX ₂ ) through the analog-to-digital converter (ADC) should preferably be bijective, or bijective for handling purposes be approximated.

Again, for purposes of explanation, we assume that the first modulation signal (MX ₁ ) is mono-frequency with a first center frequency (ω _mm,1 ) and that the first analysis signal (MY ₁ ) is mono-frequency with the first center frequency (ω _mm,1 ). .

Furthermore, again for the sake of explanation, we assume that the second modulation signal (MX ₂ ) is also mono-frequency with a second center frequency (ω _mm,2 ) and that the second analysis signal (MY ₂ ) is mono-frequency with the second center frequency (ω _{mm, 2} ) is.

Furthermore, again for the sake of explanation, we assume that the second center frequency (ω _mm,2 ) is different from the first center frequency (ω _mm,1 ).

The first output multiplier (M _2.1 ) multiplies the first analysis signal (MY ₁ ) by the intermediate signal (S4) to form the first decimation pre-signal (S6 ₁ ).

The second output multiplier (M _2.2 ) multiplies the second analysis signal (MY ₂ ) by the intermediate signal (S4) to form the second pre-decimation signal (S6 ₂ ).

The mixing in the first output multiplier (M _2,1 ) now produces a first signal component in the first decimation preliminary signal (S6 ₁ ) with a first center mixing frequency which is the difference between the first center frequency (ω _mm,1 ) and the first center frequency (ω _mm,1 ) corresponds and thus disappears. This first signal component of the first decimation preliminary signal (S6 ₁ ) is therefore a direct component which is proportional to the first input signal (U _in,1 ), which we have only assumed to be constant to simplify the explanation.

The mixing in the first output multiplier (M _2,1 ) now produces a second signal component in the first decimation preliminary signal (S6 ₁ ) with a second center mixing frequency which is the sum of the first center frequency (ω _mm,1 ) and the first center frequency (ω _mm,1 ) corresponds and thus corresponds to twice the first center frequency (ω _mm,1 ). This second signal component of the first decimation preliminary signal (S6 ₁ ) is therefore an alternating signal component which is proportional to the first input signal (U _in,1 ) and which has the center frequency magnitude of the second center mixing frequency of 2* |ω _mm,1 |.

The mixing in the first output multiplier (M _2,1 ) also creates a third signal component in the first decimation preliminary signal (S6 ₁ ) with a third center mixing frequency, which is the difference between the first center frequency (ω _mm,1 ) and the second center frequency (ω _mm,2 ) and thus does not disappear. This third signal component of the first decimation signal (S6 ₁ ) is therefore an alternating signal component which is proportional to the first input signal (U _in,1 ) and to the second input signal (U _in,2 ) and which is the center frequency absolute value of the third center mixing frequency of |ω _mm,1 -ω _mm,2 | having.

The mixing in the first output multiplier (M _2,1 ) also creates a fourth signal component in the first decimation preliminary signal (S6 ₁ ) with a fourth center mixing frequency, which is the sum of the first center frequency (ω _mm,1 ) and the second center frequency (ω _mm,2 ) and thus does not disappear. This fourth signal component of the first decimation preliminary signal (S6 ₁ ) is therefore an alternating signal component which is proportional to the first input signal (U _in,1 ) and to the second input signal (U _in,2 ) and which has the center frequency of the fourth center mixing frequency of |ω _mm,1 +ω _mm,2 | having.

The mixing in the second output multiplier (M _2,2 ) now also creates a fifth signal component in the second decimation preliminary signal (S6 ₂ ) with a fifth center mixing frequency, which is the difference between the second center frequency (ω _mm,2 ) and the second center frequency (ω _{mm ,2} ) and thus vanishes. The fifth center mixing frequency thus essentially corresponds to the first center mixing frequency. This fifth signal component of the second decimation preliminary signal (S6 ₂ ) is therefore also a DC component which is proportional to the second input signal (U _in,2 ), which we have also assumed to be constant only to simplify the explanation.

The mixing in the second output multiplier (M _2,2 ) also creates a sixth signal component in the second decimation preliminary signal (S6 ₂ ) with a sixth center mixing frequency, which is the sum of the second center frequency (ω _mm,2 ) and the second center frequency (ω _mm,2 ) corresponds and thus corresponds to twice the second center frequency (ω _mm,2 ). This second signal component of the second decimation preliminary signal (S6 ₂ ) is therefore an alternating signal component which is proportional to the second input signal (U _in,2 ) and which has the center frequency magnitude of the sixth center mixing frequency of 2* |ω _mm,2 | having.

The mixing in the second output multiplier (M _2,2 ) also creates a seventh signal component in the second decimation preliminary signal (S6 ₂ ) with a seventh center mixing frequency, which is the difference between the second center frequency (ω _mm,2 ) and the first center frequency (ω _mm,1 ) and thus does not disappear. The seventh center mixing frequency thus corresponds to the third center mixing frequency. This seventh signal component of the second decimation preliminary signal (S6 ₂ ) is therefore an alternating signal component which is proportional to the second input signal (U _in,2 ) and to the first input signal (U _in,1 ) and which has the center frequency of the seventh center mixing frequency of |ω _mm,2 -ωmm _,1 | having.

The mixing in the second output multiplier (M _2,2 ) also creates an eighth signal component in the second decimation preliminary signal (S6 ₂ ) with an eighth center mixing frequency, which is the sum of the second center frequency (ω _mm,2 ) and the first center frequency (ω _mm,1 ) and thus does not disappear. The eighth center mixing frequency thus corresponds to the fourth center mixing frequency. This eighth signal component of the second decimation preliminary signal (S6 ₂ ) is therefore an alternating signal component which is proportional to the second input signal (U _in,2 ) and to the first input signal (U _in,1 ) and which has the center frequency amount of the fourth center mixing frequency of |ω _mm,2 +ω _mm,1 |.

A downstream first decimation filter (LPF ₁ / DEZ ₁ ) removes the second signal component described immediately beforehand and the third signal component described immediately previously and the fourth signal component described immediately previously from the first decimation preliminary signal (S6 ₁ ) and thus forms the first output signal (out ₁ ) that preferably essentially only has the first signal component of the first decimation preliminary signal (S6 ₁ ). The first decimation filter (LPF ₁ /DEZ ₁ ) is therefore preferably a digital low-pass filter. Typically, the first decimation filter (LPF ₁ /DEZ ₁ ) changes the bit width of the first output signal (out ₁ ) compared to the bit width of the first decimation pre-signal (S6 ₁ ) as required.

A downstream second decimation filter (LPF ₂ / DEZ ₂ ) removes the sixth signal component described immediately beforehand and the seventh signal component described immediately previously and the eighth signal component described immediately previously from the second decimation preliminary signal (S6 ₂ ) and thus forms the second output signal (out ₂ ) that preferably essentially only has the fifth signal component of the second decimation preliminary signal (S6 ₂ ). The second decimation filter (LPF ₂ /DEZ ₂ ) is therefore preferably a digital low-pass filter. Typically, the second decimation filter (LPF ₂ /DEZ ₂ ) changes the bit width of the second output signal (out ₂ ) compared to the bit width of the second decimation pre-signal (S6 ₂ ) as required.

With the help of 3 until 5 we have now sufficiently explained the basic, modified chopper method. In this proposed modified chopper method, the k-th analysis signal (MY _k ) corresponds to the j-th modulation signal (MX _j ) only if the signal component of the j-th summand signal (SO _j ) corresponds to that with the j-th modulation signal (MX _j ) corresponds, is not deformed by the analog-to-digital converter, ie delayed, for example.

figure 6

In the following we describe in a generalized way with the help of the 6 and based on what has been described above, a system with n input signals (U _in1 , U _in2 , U _in3 ,...U _inj ,...U _in,n ) and m output signals (out ₁ , out ₂ , out ₃ , .. .out _k , ...outm).

In the case of the example here 6 In the proposed method, the memory effect of the integrating filter (INT) within the analog-to-digital converter (ADC) is again taken into account in that, for example, the signal component of the kth analysis signal (MY _k ) picked out arbitrarily here is preferred over the signal component of the here arbitrarily selected j-th modulation signal (MX _j ) by the analog-to-digital converter (ADC) amplified (or possibly attenuated) and possibly phase-shifted in a defined manner. This is a first difference from the prior art.

Precisely one kth digitized output signal (out _k ) is bijectively assigned to each j-th input signal (U _in,j ) in the generalized proposed method below. It is therefore preferably n=m and for each pair of input signal and output signal preferably k=j. Nevertheless, in the following we also describe n≠m to maximize the generality of the description.

Thus, m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...outm) are obtained from the at least n input signals (U _in1 , U _in2 , U _m3 , ...U _inj , .. .U _inn ) formed. n=m is preferably chosen. In a first step, the method begins with the provision of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) and with the provision of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _m ).

The signal of each j-th modulation signal (MX _j ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) has a j-th center frequency (ω _mm,j ) of the j-th modulation signal (MX _j ).

The signal of each k-th analysis signal (MY _k ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _m ) typically has the k-th center frequency (ω _mmk ) of the k-th analysis signal (MY _k ), which for j=k is preferably equal to the center frequency (ω _mm,k ) of the k-th modulation signal (MX _k ).

There are thus n center frequencies (ω _mm,1 , ω _mm,2 , ω _mm,3 , ... ω _mm,j , ... ω _mm,n ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ), which preferably all differ from one another.

The j-th center frequency (co _mmj ) of the j-th modulation signal (MX _j ) is preferred of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _{mm(j+ 1)} ,... ω _mmn ) of the other (n-1) modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _(j-1) ,MX _(j+i) ,... MX _n ) different and preferred for j≤m also from all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmm ) of the other (m -1) Analysis signals (MY ₁ , MY ₂ , MY ₃ ,... MY _(j-1) ,MY _(j+1) ,... MY _n ) different.

In the same way, the k-th center frequency (ω _mmk ) of the k-th analysis signal (MY _j ) is preferably of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(k-1) , ω _{mm( k+1)} ,...ω _mmn ) of the other (n-1) modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _(k-1) , MX _(k+1) ,... MX _n ) different and preferably also from all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmm ) of the other (m-1 ) Analysis signals (MY ₁ , MY ₂ , MY ₃ ,... MY _(k-1) , MY _(k+1) ,... MY _m ) differ.

ausdrücken. In einem folgenden Schritt erfolgt die Summation aller n Summandensignale (SO₁, SO₂, S0₃,... S0_j,... S0_n) in der Summations- und Differenzbildungsvorrichtung (Σ) zur Erzeugung eines Differenzsignals (S2). Als Formel ausgedrückt ergibt dies: $${\displaystyle \sum _{j=1}^{n}S{0}_j\left(t\right)}={\displaystyle \sum _{j=1}^n{U}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}$$

As a first step in the method, each of the j-th input signals (U _in,j ) is multiplied or mixed with exactly one associated j-th modulation signal (MX _j ) to generate an associated j-th summand signal (S0 _j ). There are thus n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n ) from the n input signals (U _in,1 , U _in,2 , U _in,3 , .. .U _in,j , ...U _in,n ). Each jth modulation signal (MX _j ) is thus preferably multiplied by exactly one jth input signal (U _in,j ). In this method step, each j-th modulation signal (MX _j ) is thus preferably used exactly once within the scope of this device, in that preferably exactly one respective input multiplier (M _{1, j} ) This j-th modulation signal (MX _j ) is multiplied with preferably exactly this associated j-th input signal (U _in,j ). If necessary, the signals outside of the device can still be used for others purposes are used. In this method step, each j-th input signal (U _in,j ) is thus also preferably used exactly once, by being multiplied by exactly said j-th modulation signal (MX _j ). We can do that by the formula $$u_{in,j}\left(t\right)\times M{X}_j\left(t\right)=S{0}_j\left(t\right)$$

to express. In a following step, all n summand signals (SO ₁ , SO ₂ , S0 ₃ ,... S0 _j ,... S0 _n ) are summed in the summation and difference formation device (Σ) to generate a difference signal (S2). Expressed as a formula, this gives: $${\displaystyle \sum _{j=1}^{n}S{0}_j\left(t\right)}={\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}$$

In the next step, the difference signal (S2) is filtered, in particular integrated, to form the filter output signal (S3) in the typically integrating filter (INT) within the analog-to-digital converter (ADC). For the clarity of the description, we approximate the filtering by an integration as an example, in order to continue the example of a delta-sigma converter: $${\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+C=S3\text{'}\left(t\right)}$$

After this filtering in the integrating filter (INT), the virtual filter output signal (S3') is quantized or analog-to-digital converted in the quantizer (QNT) to form the quantized intermediate signal (S4). (Here, C represents an integration constant.) The quantizer (QNT) adds a quantization error e(t) to the digitized intermediate signal (S4), which is undesirable. $${\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+C+e\left(t\right)=S4\left(t\right)}$$

The analog-to-digital converter (ADC) thus typically again causes a delay in the quantized intermediate signal (S4) compared to the difference signal (S2).

We now assume that all modulation signals (MX ₁ , MX ₂ , MX ₃ , ... MX _j , ... MX _n ) and all analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _k , ... MY _m ) have a common system period T _p . This means: after a time corresponding to this system period T _p , these signals are repeated in the same way as in the previously elapsed system period T _p .

For each k with 1≤k≤m, a k-th output multiplier (M _2,k ) multiplies the intermediate signal (S4) with the associated k-th analysis signal (MY _k ) to form the corresponding k-th decimation preliminary signal (S6 _k ), so that m output multipliers (M _2,1 , M _2,2 , M _2,3 ,... M _2,k ,... M _2,m ) m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) from the intermediate signal (S4). $${\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t\times M{Y}_k\left(t\right)+C\times M{Y}_k\left(t\right)+e\left(t\right)\times M{Y}_k\left(t\right)=\mathrm{<figure-callout\; id="6k"\; label="S"\; filenames="DE102021100438B3\_0043.png,DE102021100438B3\_0045.png"\; state="\{\{state\}\}">S</figure-callout>}{6}_k\left(t\right)}$$

We assume that the system period T _p is very short. Ie we assume that we can write: $${\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)+\left[C+e\left(t\right)\right]\times M{Y}_k\left(t\right)}=\mathrm{<figure-callout\; id="6k"\; label="S"\; filenames="DE102021100438B3\_0043.png,DE102021100438B3\_0045.png"\; state="\{\{state\}\}">S</figure-callout>}{6}_k\left(t\right)$$

Here, τ _j stands for the phase shift of the j-th analysis signal MY _j (t) compared to the j-th modulation signal MX _j (t).

A respectively associated kth decimation filter (LPF _k /DEZ _k ) of m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) filters the k-th decimation pre-signal (S6 _k ) of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) to the corresponding k-th output signal (out _k ) , so that the m decimation filters (LPF ₁ /DEC ₁ , LPF ₂ /DEC ₂ , LPF ₃ /DEC ₃ ,... LPF _k /DEC _k ,... LPF _m /DEC _m ) m Off output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...out _m ) from the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ). .

The respective kth filter function F _k [] of the respective kth decimation filter (LPF _k /DEZ _k ) used in this case is F _k [S6 _k (t)]. $$f_k\left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)+\left[C+e\left(t\right)\right]\times M{Y}_k\left(t\right)}\right]=O\mathrm{and}{t}_k\left(t\right)$$

We assume that the relevant kth decimation filters (LPF _k /DEZ _k ) are linear filters.

For any two signals S10(t) and S11(t) and a complex constant α, the kth filter function F _k [] of the relevant kth decimation filter (LPF _k /DEZ _k ) should have the following properties, essentially based on the have the intended parametric functional range of the relevant k-th decimation filter (LPF _k /DEZ _k ): $$\begin{array}{c}{f}_k\left[S10\left(t\right)+S11\left(t\right)\right]=f_k\left[S10\left(t\right)\right]+f_k\left[S11\left(t\right)\right]\\ f_k\left[a\times S10\left(t\right)\right]=a\times f_k\left[S10\left(t\right)\right]\end{array}$$

We then receive $${\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)f_k\left[M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]+f_k\left[\left[C+e\left(t\right)\right]\times M{Y}_k\left(t\right)\right]}=O\mathrm{and}{t}_k\left(t\right)$$

We now assume that, for simplification, the following essentially applies: $$\begin{array}{c}{f}_k\left[M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]=0\text{f}\ddot{\text{and}}\text{rk}\ne \text{j and}\\ f_k\left[M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]=\beta \text{f}\ddot{\text{and}}\text{rk}=\text{j and}\\ f_k\left[M{X}_j\left(t\right)\right]=0\end{array}$$

These are the orthogonality conditions.

und $$F_k\left[\left[C+e\left(t\right)\right]\times M{Y}_k\left(t\right)\right]\approx 0$$

We then get, simplifying: $${\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)f_k\left[M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]}=\beta \frac{1}{T_p{\omega }_{mm,k}}{u}_{in,k}\left(t\right)$$

and $$f_k\left[\left[C+e\left(t\right)\right]\times M{Y}_k\left(t\right)\right]\approx 0$$

lässt einen Signalanteil für j≠k durch verschwinden des AusdrucksNote that the expression [MX _j (t - τ _j ) × MY _k (t)] includes the jth complex phase shift τ _j . Only a compensation of this phase shift by the condition $$M{X}_j\left(t-{\tau }_j\right)=M{Y}_j\left(t\right)$$

leaves a signal component for j≠k by vanishing the expression

F _k [MX _j (t - -r _j ) × MY _k (t)] disappear completely and leads to a complete disentanglement of the output signal (out _j ) and input signal (U _in,j ) pairs, which is the essence of the proposal . The generation of the j-th modulation signal (MX _j (t)) by the generator (G) as a function of the j-th analysis signal (MY _j (t)) leads to a successful orthogonalization and to the compensation of the previous history. The j-th phase shift τ _j is constructed by the analog-to-digital converter as a function of the j-th center frequency ω _mm,j of the j-th modulation signal (MX _j (t)) and the j-th analysis signal ( MY _j (t)) determined.

The block of intermediate signal (S4), the output multipliers (M _2,1 , M _2,2 , M _2,3 , .... M _2,k , .... M _2,m ), the decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) and the digitized output signals can also be used in its function by a Fourier transformation unit (FFT ) will be realized. The prerequisite is that the input signals (U _in,1 , U _in,2 , U _in,3 , ... U _in,j , ... U _in,n ) can be viewed as quasi-static. With a suitable design, the Fourier transformation unit (FFT) then calculates Fourier coefficients from the intermediate signal (S4) in the form of the values of Fourier coefficient signals, which the digital output signals (out ₁ , out ₂ , out ₃ , ... out _k , ... out _m ) are. This transformation can preferably be carried out by a signal processor. Ie the Fourier transformation unit (FFT) can also be a signal processor which calculates a Fourier transformation of the value profile of the intermediate signal (S4) and calculates Fourier coefficients which, as representatives of the values of the input signals (U _in,1 , U _in,2 , U _in,3 , ... U _in,j , ... U _in,n ) can be used or kept ready.

figure 7

In 7 the analog-to-digital converter is now implemented as a delta-sigma converter by way of example.

ausdrücken. In einem folgenden Schritt erfolgt die Summation der Werte aller n Summandensignale (S0₁, SO₂, SO₃,... S0_j,... S0_n) in der Summations- und Differenzbildungsvorrichtung (Σ) nun unter Abzug des Werts des Rückkoppelsignals (S5)zur Erzeugung eines Differenzsignals (S2). Als Formel ausgedrückt ergibt dies: $${\displaystyle \sum _{j=1}^{n}S{0}_j\left(t\right)}=-S5\left(t\right)+{\displaystyle \sum _{j=1}^n{U}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}$$

As a first step in the method, each of the jth input signals (U _in,j ) is multiplied or mixed with exactly one associated jth modulation signal (MX _j ) to generate an associated jth summand signal (S0 _j ) using a respective associated j-th input multiplier (M _1,j ). The n input multipliers (M _1,1 , M _1,2 , M _1,3 , ... M _1,j , M _1,n ) thus form n summand signals (S0 ₁ , SO ₂ , SO ₃ ,.. S0 _j ,... S0 _n ) from the n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _inj , ...U _in,n ) and the n modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _j ,... MXn). Each j-th modulation signal (MX _j ) is thus preferably multiplied by exactly one j-th input signal (U _in,j ) by the j-th input multiplier (M _1,j ). In this method step, each j-th modulation signal (MX _j ) is thus preferably used exactly once within the scope of this device, in that preferably exactly one respective input multiplier (M _{1, j} ) This j-th modulation signal (MX _j ) is multiplied with preferably exactly this associated j-th input signal (U _in,j ). If necessary, the signals can also be used outside of the device for other purposes. In this method step, each j-th input signal (U _in,j ) is thus also preferably used exactly once by being multiplied by exactly said j-th modulation signal (MX _j ). We can do that by the formula $$u_{in,j}\left(t\right)\times M{X}_j\left(t\right)=S{0}_j\left(t\right)$$

to express. In a following step, the summation of the values of all _n summand signals (S0 ₁ , SO ₂ , SO ₃ , . . . S0 _j , (S5) to generate a differential signal (S2). Expressed as a formula, this gives: $${\displaystyle \sum _{j=1}^{n}S{0}_j\left(t\right)}=-S5\left(t\right)+{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}$$

In the next step, the difference signal (S2) is filtered, in particular integrated, to form the filter output signal (S3) in the typically integrating filter (INT) within the analog-to-digital converter (ADC). For the clarity of the description, we approximate the filtering by an integration as an example, in order to continue the example of a delta-sigma converter: $${\displaystyle \int \left[-S5\left(t\right)+{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+C=S3\text{'}\left(t\right)}$$

After this filtering in the integrating filter (INT), the virtual filter output signal (S3') is quantized or analog-to-digital converted in the quantizer (QNT) to form the quantized intermediate signal (S4). (Here, C represents an integration constant.) The quantizer (QNT) adds a quantization error e(t) to the digitized intermediate signal (S4), which is undesirable. $${\displaystyle \int \left[-S5\left(t\right)+{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+C+e\left(t\right)=S4\left(t\right)}$$

The analog-to-digital converter (ADC) thus typically again causes a delay in the quantized intermediate signal (S4) compared to the difference signal (S2). The digital-to-analog converter (DAC) delays the intermediate signal to the feedback signal (S5). We approximate this with a constant complex factor y.

We obtain: $$g{\displaystyle \int \left[-S5\left(t\right)+{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+gC+ge\left(t\right)=S5\left(t\right)}$$

We assume that the conversion in the analog-to-digital converter is linear. In our example, this means that we can use the sum rule of integration: $$-g{\displaystyle \int S5\left(t\right)\mathrm{i.e}t+g{\displaystyle \int \left[{\displaystyle {\sum }_{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]}\mathrm{i.e}t+gC+ge\left(t\right)=S5\left(t\right)}$$

From this we get: $$g{\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+gC+ge\left(t\right)=S5\left(t\right)}+g{\displaystyle \int S5\left(t\right)\mathrm{i.e}t}$$

We now assume again that all modulation signals (MX ₁ , MX ₂ , MX ₃ , ... MX _j , ... MX _n ) and all analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _k , ... MY _m ) have a common system period T _p . This means: after a time corresponding to this system period T _p , these signals are repeated in the same way as in the previously elapsed system period T _p .

We approximate the expression γ ∫ S5(t)dt by γ ∫ S5(t)dt = λS5(t) as damping.

We obtain: $$g{\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+gC+ge\left(t\right)=S5\left(t\right)}\left[1+\lambda \right]$$

This gives us for the intermediate signal S4(t): $$\frac{1}{1+\lambda }{\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t+\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }=S4\left(t\right)}$$

The analog-to-digital converter (ADC) thus typically again causes a delay in the quantized intermediate signal (S4) compared to the difference signal (S2).

We now assume that all modulation signals (MX ₁ , MX ₂ , MX ₃ , ... MX _j , ... MX _n ) and all analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _k , ... MY _m ) have a common system period T _p . This means: after a time corresponding to this system period T _p , these signals are repeated in the same way as in the previously elapsed system period T _p .

For each k with 1≤k≤m, a k-th output multiplier (M _2,k ) multiplies the intermediate signal (S4) with the associated k-th analysis signal (MY _k ) to form the corresponding k-th decimation preliminary signal (S6 _k ), so that m output multipliers (M _2,1 , M _2,2 , M _2,3 ,... M _2,k ,... M _2,m ) m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) from the intermediate signal (S4). $$\frac{1}{1+\lambda }{\displaystyle \int \left[{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t\right)}\right]\mathrm{i.e}t\times M{Y}_k\left(t\right)+\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }\times M{Y}_k\left(t\right)=\mathrm{<figure-callout\; id="6k"\; label="S"\; filenames="DE102021100438B3\_0043.png,DE102021100438B3\_0045.png"\; state="\{\{state\}\}">S</figure-callout>}{6}_k\left(t\right)}$$

We assume that the system period T _p is very short. Ie we assume that we can write: $$\frac{1}{1+\lambda }{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)+\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }\times M{Y}_k\left(t\right)}=\mathrm{<figure-callout\; id="6k"\; label="S"\; filenames="DE102021100438B3\_0043.png,DE102021100438B3\_0045.png"\; state="\{\{state\}\}">S</figure-callout>}{6}_k\left(t\right)$$

A respectively associated kth decimation filter (LPF _k /DEZ _k ) of m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) filters the k-th decimation pre-signal (S6 _k ) of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) to the corresponding k-th output signal (out _k ) , so that the m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) m output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...outm) from the m decimation advance signals (S6 ₁ , S6 ₂ , S6 ₃ , ... S6 _k , ... S6 _m ).

The respective kth filter function F _k [] of the respective kth decimation filter (LPF _k /DEZ _k ) used in this case is F _k [S6 _k (t)]. $$f_k\left[\frac{1}{1+\lambda }{\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)+\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }\times M{Y}_k\left(t\right)}\right]=O\mathrm{and}{t}_k\left(t\right)$$

We assume that the relevant k-th decimation filters (LPF _k /DEZ _k ) are linear filters.

For any two signals S10(t) and S11(t) and a complex constant α, the kth filter function F _k [] of the relevant kth decimation filter (LPF _k /DEZ _k ) should again have the following properties, essentially based on have the intended parametric functional range of the relevant k-th decimation filter (LPF _k /DEZ _k ): $$\begin{array}{c}{f}_k\left[S10\left(t\right)+S11\left(t\right)\right]=f_k\left[S10\left(t\right)\right]+f_k\left[S11\left(t\right)\right]\\ f_k\left[a\times S10\left(t\right)\right]=a\times f_k\left[S10\left(t\right)\right]\end{array}$$

We then receive $${\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)\times f_k\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]+f_k\left[\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }\times M{Y}_k\left(t\right)\right]}=O\mathrm{and}{t}_k\left(t\right)$$

We now assume that, for simplification, the following essentially applies: $$\begin{array}{c}{f}_k\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]=0\text{f}\ddot{\text{and}}\text{rk}\ne \text{j and}\\ f_k\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]=\beta \text{f}\ddot{\text{and}}\text{rk}=\text{j and}\\ f_k\left[M{X}_j\left(t\right)\right]=0\end{array}$$

These are the orthogonality constraints for the delta-sigma converter of FIG 7 . The feedback by the feedback signal S5(t) only leads to a slightly different phase shift in the form of a different prefactor, which can be predetermined in terms of design.

und $$F_k\left[\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }\times M{Y}_k\left(t\right)\right]\approx 0$$

We then get, simplifying: $${\displaystyle \sum _{j=1}^n{u}_{in,j}\left(t\right)f_k\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]}=\beta \frac{1}{T_p{\omega }_{mm,k}}{u}_{in,k}\left(t\right)$$

and $$f_k\left[\left[C+e\left(t\right)\right]\frac{1}{1+\lambda }\times M{Y}_k\left(t\right)\right]\approx 0$$

MY_k(t)] die j-te komplexe Phasenverschiebung τ_j mitumfasst. Erst eine Kompensation dieser Phasenverschiebung durch die Bedingung $$\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)=M{Y}_j\left(t\right)$$

lässt einen Signalanteil für j≠k durch verschwinden des Ausdrucks $F_k\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]$

komplett verschwinden und führt zu einer kompletten Entflechtung der Paare aus Ausgangssignal (out_j) und Eingangssignal (U_in,j), was der Kern des Vorschlags ist. Die Erzeugung des j-ten Modulationssignals (MX_j(t)) durch den Generator (G) in Abhängigkeit vom j-ten Analysesignal (MY_j(t)) führt zu einer erfolgreichen Orthogonalisierung und zur Kompensation der Vorgeschichte. Die j-te Phasenverschiebung τ_j wird dabei durch den Analog-zu-Digital-Wandler konstruktiv in Abhängigkeit von der j-ten Mittenfrequenz ω_mm,j des j-ten Modulationssignals (MX_j(t)) und des j-ten Analysesignals (MY_j(t)) bestimmt.Note that the expression $\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]$

MY _k (t)] which includes the j-th complex phase shift τ _j . Only a compensation of this phase shift by the condition $$\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)=M{Y}_j\left(t\right)$$

leaves a signal component for j≠k by vanishing the expression $f_k\left[\frac{1}{1+\lambda }M{X}_j\left(t-{\tau }_j\right)\times M{Y}_k\left(t\right)\right]$

disappear completely and leads to a complete disentanglement of the output signal (out _j ) and input signal (U _in,j ) pairs, which is the essence of the proposal. The generation of the j-th modulation signal (MX _j (t)) by the generator (G) as a function of the j-th analysis signal (MY _j (t)) leads to successful orthogonalization and compensation of the previous history. The j-th phase shift τ _j is constructed by the analog-to-digital converter as a function of the j-th center frequency ω _mm,j of the j-th modulation signal (MX _j (t)) and the j-th analysis signal ( MY _j (t)) determined.

7 thus shows a device for converting a plurality of at least n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _inn ) with n as a positive integer greater than 1 into n digitized output signals (out ₁ , out ₂ , out ₃ , ...out _j , ...out _n ). The device has n input multipliers (M _1,1 , M _2,1 , M _3,1 , ... M _j,1 , ... M _n,1 ), n modulation signals (MX ₁ , MX ₂ , MX ₃ , ... MX _j , ... MX _n ), n summand signals (SO ₁ , SO ₂ , S0 ₃ , ... S0 _j , ... S0 _n ), a summation and difference forming device (Σ), a difference signal (S2), a filter (INT), a filter output signal (S3), a quantizer or other analog-to-digital converter (QNT), an intermediate signal (S4), a digital-to-analog converter (DAC), a feedback signal (S5), m output multipliers (M _2,1 , M _2,2 , M _2,3 ,... M _2,k ,... M _2,m ), m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ), m decimation filter (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m / DEZ _m ) and m output signals (out ₁ , out ₂ , out ₃ ,... out _k ,... outm).

The signal of each j-th modulation signal (MX _j ) with 1≦j≦n has a j-th center frequency (ω _mm,j ) of the j-th modulation signal (MX _j ) in each case. The respective center frequency (ω _mm,j ) of such a j-th modulation signal (MX _j ) preferably differs from all other center frequencies (ω _mm,1 , ω _mm,2 , ω _mm,3 ,... ω _{mm,(j -1)} ,ω _mm,(j+1) ,...ω _mm,n ) of the other (n-1) modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _(j-1) ,MX _(j+1) ,... MX _n ). Preferably, each j-th input multiplier (M _1,j ) of the n input multipliers (M _1,1 , M _1,2 , M _1,3 , ... M _1,j , ... M _1,n ) multiplies this j-th input multiplier (M _j,1 ) bijectively assigned j-th input signal (U _in,j ) of the at least n input signals (U _in,1 , U _in,2 , U _in,3 , ...U _inj , .. . U _in,n ) with a j-th modulation signal (MX _j ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , also bijectively assigned to this j-th input multiplier (M _j,1 ) .... MX _n ) to a j-th addend signal (S0 _j ) of the n _addend signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n ). The summation and difference formation device (Σ) sums the values of the n summand signals (SO ₁ , SO ₂ , SO ₃ ,... S0 _j ,... S0 _n ) by subtracting the value of the feedback signal (S5) and thus forms the difference signal (S2) from the values determined in this way by outputting them as a differential signal (S2).

The filter (INT), which can in particular be an integrator or in particular comprises an integrator, filters the difference signal (S3) to form the filter output signal (S3).

The quantizer or the other analog-to-digital converter (QNT) quantizes the filter output signal (S3) to the quantized intermediate signal (S4).

The digital-to-analog converter (DAC) or a delay device delays the quantized intermediate signal (S4) to form the feedback signal (S5).

Preferably, every k-th output multiplier (M _2,k ) of the m output multipliers (M _2,1 , M _2,2 , M _2,3 , ... M _2,k , ... M _2,m ) multiplies the Intermediate signal (S4) with a respective _{k-th analysis signal (MY k )} of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , . _{. _ _ _ _ _ _} .. S6 _m ).

Preferably, every k-th decimation filter (LPF _k /DEZ _k ) of the m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m / DEZ _m ) filters this k-th decimation filter (LPF _k /DEZ _k ) of the m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,.. LPF _m /DEZ _m ) bijectively assigned kth decimation pre-signal (S6 _k ) of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) to this k-th decimation filter ( LPF _k /DEZ _k ) of the m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) bijectively assigned k- th output signal (out _k ) of the m output signals (out ₁ , out ₂ , out ₃ , ... out _k , ... out _m ).

If the distortion in the analog-to-digital converter is very low for certain modulation signals of the modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ), the associated analysis signals of the analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _m ) must be equal to these modulation signals.

figure 8

8th shows a device with a suppression of the 1'/f noise by means of a chopper method. In the example of 8th a j-th chopper multiplier (M _3,j ) multiplies an associated j-th summand signal (S0 _j ) with a chopper signal (CS) of very high frequency to form a choppered j-th summand signal (S0' _j ). The j-th choppered summand signal (SO' _j ) then feeds the summation and difference-forming device (Σ) instead of the j-th summand signal (S0 _j ). In other words, in this variant it is used as a j-th input signal of the summation and difference-forming device (Σ) instead of the j-th summand signal (S0 _j ). Thus, the n chopper multipliers (M _3,1 , M _3,2 , M _3,3 , ... M _3,j , ... M _3,n ) generate from the n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , . . . S0O _j , . . . S0 _n ) _{n choppered} summand signals (S0' ₁ , S0' ₂ , S0' ₃ , Chopper signal (CS).

A choppered difference signal (S2') then forms the output of the summation and difference formation device (Σ). A reverse multiplier (M ₄ ) multiplies the choppered differential signal (S2') by the chopper signal (CS) again to form the differential signal (S2). As a result, the signals of the n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _in,n ) are typically raised in the frequency spectrum to such an extent that the 1/f noise no longer dominates and only the white noise plays a role.

advantage

As shown above, the pre-calculated compensating specific pairwise phase shift of the thus leading n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) compared to m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _m ) to a decoupling of the multiplexed channels, which is the essence of the proposal. However, the advantages are not limited to this.

character list

• 1 shows a prior art analog-to-digital converter (ADC) with multiplexed input.
• 2 FIG. 12 shows an example prior art delta-sigma analog-to-digital converter (ADC) with multiplexed input.
• 3 serves to clarify the relationship between a j-th modulation signal (MX _j ) and a k-th analysis signal (MY _k ).
• 4 equals to 3 in case there is no phase shift in the analog-to-digital converter (ADC).
• 5 equals to 3 now with two measurement channels.
• 6 equals to 3 now with n measurement channels. (Preference is given to m=n.)
• 7 equals to 6 , where the analog-to-digital converter (ADC) is now implemented as a delta-sigma converter.
• 8th equals to 7 now the input stage with the summing and differencing device (Σ) is designed as a chopper amplifier stage with several inputs.

Reference List

a

complex constant;

ADC

analog to digital converters;

β

complex factor;

g

complex factor;

C

constant of integration;

CS

chopper signal;

DAC

digital to analog converter;

e(t)

quantization error;

F1[]

first filter function of the first decimation filter (LPF ₁ /DEZ ₁ );

F2[]

second filter function of the second decimation filter (LPF ₂ /DEZ ₂ );

F3[]

third filter function of the third decimation filter (LPF ₃ /DEZ ₃ );

Fk[]

kth filter function of the kth decimation filter (LPF _k /DEZ _k );

FM[]

mth filter function of the mth decimation filter (LPF _m /DEZ _m );

G

signal generator. The signal generator generates the n modulation signals (MX ₁ , MX ₂ , MX ₃ , ... MX _j , ... MX _n ) and the m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _k , .. MY _m ) and other signals, if applicable;

INT

Filter. The filter is preferably an integrator or a filter with properties that come close to the properties of an integrator, at least in certain operating ranges;

G

Generator;

GND

reference potential line to reference potential;

j

positive integer with 1≤j≤n;

k

positive integer with 1≤k≤m;

λ

complex factor;

LPF/DEC

Decimation filter of the exemplary analog-to-digital converter (ADC) designed as a delta-sigma converter 2 ;

LPF1/DEC1

first decimation filter of m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ , ... LPF _k /DEZ _k , ... LPF _m /DEZ _m );

LPF2/DEC2

second decimation filter of m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ , ... LPF _k /DEZ _k , ... LPF _m /DEZ _m );

LPF3/DEC3

third decimation filter of m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ , ... LPF _k /DEZ _k , ... LPF _m /DEZ _m );

LPFk/DECk

kth decimation filter of m decimation filters (LPF ₁ /DEC ₁ , LPF ₂ /DEC ₂ , LPF ₃ /DEC ₃ , ... LPF _k /DEC _k , ... LPF _m /DEC _m );

LPFm/DECm

mth decimation filter of m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ , ... LPF _k /DEZ _k , ... LPF _m /DEZ _m );

m

positive integer with 2≤m≤n. Preferably n=m;

M1,1

first input multiplier of n input multipliers (M _1,1 , M _2,1 , M _3,1 , ... M _j,1 , ... M _n,1 );

M1,2

second input multiplier of n input multipliers (M _1,1 , M _2,1 , M _3,1 , ... M _j,1 , ... M _n,1 );

M1,3

third input multiplier of n input multipliers (M _1,1 , M _2,1 , M _3,1 , ... M _j,1 , ... M _n,1 );

M1, j

j-th input multiplier of n input multipliers (M _1,1 , M _2,1 , M _3,1 , ... M _j,1 , ... M _n,1 );

M1,n

nth input multiplier of n input multipliers (M _1,1 , M _2,1 , M _3,1 , ... M _j,1 , ... M _n,1 );

M2.1

first output multiplier of m output multipliers (M _2,1 , M _2,2 , M _2,3 , ... M _2,k , ... M _2,m );

M2.2

second output multiplier of m output multipliers (M _2,1 , M _2,2 , M _2,3 , ... M _2,k , ... M _2,m );

M2.3

third output multiplier of m output multipliers (M _2,1 , M _2,2 , M _2,3 , ... M _2,k , ... M _2,m );

M2, k

k-th output multiplier of m output multipliers (M _2,1 , M _2,2 , M _2,3 , ... M _2,k , ... M _2,m );

M2, w

m-th output multiplier of m output multipliers (M _2,1 , M _2,2 , M _2,3 , ... M _2,k , ... M _2,m );

M3.1

first chopper multiplier. The first chopper multiplier multiplies the first summand signal (S0 ₁ ) to form the choppered first summand signal (S0' ₁ ). This is then instead of the first summand signal (S0 ₁ ) in the example 8th fed to the summation and difference forming device (Σ);

M3.2

second chopper multiplier. The second chopper multiplier multiplies the second addend signal (S0 ₂ ) to form the choppered second addend signal (S0' ₂ ). This is then in place of the second summand signal (S0 ₂ ) in the example 8th fed to the summation and difference forming device (Σ);

M3.3

third chopper multiplier. The third chopper multiplier multiplies the third addend signal (S0 ₃ ) to form the choppered third addend signal (S0' ₃ ). This is then in place of the third addend signal (S0 ₃ ) in the example 8th fed to the summation and difference forming device (Σ);

M3, j

j-th chopper multiplier. The j-th chopper multiplier multiplies the j-th addend signal (S0 _j ) to form the choppered j-th addend signal (S0' _j ). This is then instead of the j-th summand signal (S0 _j ) in the example 8th fed to the summation and difference forming device (Σ);

M3,n

nth chopper multiplier. The nth chopper multiplier multiplies the nth summand signal (S0 _n ) to form the choppered nth summand signal (S0' _n ). This is then instead of the nth summand signal (S0 _n ) in the example 8th fed to the summation and difference forming device (Σ);

M4

inverse multiplier;

MUX

analog multiplexer;

MX1

first modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MX2

second modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MX3

third modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MX(j-1)

(j-1)-th modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MXj

j-th modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MX(j+1)

(j+1)-th modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MXn

nth modulation signal of n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) where n is a positive integer;

MXB

modulation signal burst;

MY1

first analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) where m is a positive integer;

MY2

second analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) where m is a positive integer;

MY3

third analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) where m is a positive integer;

MY(k-1)

(k-1)-th analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) where m is a positive integer;

MYk

k-th analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) with m as a positive integer;

MY(k+1)

(k+1)th analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) where m is a positive integer;

MYn

nth analysis signal of m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _k , .... MY _n ) with m as a positive integer;

MYB

analysis signal bundle;

n

whole positive number;

ωmm1

first center frequency of the first modulation signal (MX ₁ ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the first analysis signal (MY ₁ ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m ) for mono-frequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... .MY _j , .... MY _k , .... MY _m );

ωmm2

second center frequency of the second modulation signal (MX ₂ ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the second analysis signal (MY ₂ ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m ) for mono-frequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... .MY _j , .... MY _k , .... MY _m );

ωmm3

third center frequency of the third modulation signal (MX ₃ ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the third analysis signal (MY ₃ ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m ) for mono-frequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... .MY _j , .... MY _k , .... MY _m );

ωmm(j-1)

(j-1)-th center frequency of the (j-1)-th modulation signal (MX _(j-1) ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the (j-1)-th analysis signal (MY _(j-1) ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _j , .... MY _k , .... MY _m ) for monofrequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

ωmmj

j-th center frequency of the j-th modulation signal (MX _j ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, ... . MX _n ) and the j-th analysis signal (MY _j ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ ,.... MY _j ,.... MY _k ,.... MY _m ) at ( MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

ωmm(j+1)

(j+1)-th center frequency of the (j+1)-th modulation signal (MX _(j+1) ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the (j+1)-th analysis signal (MY _(j+1) ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _j , .... MY _k , .... MY _m ) for monofrequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

ωmm(k-1)

(k-1)-th center frequency of the (k-1)-th modulation signal (MX _(k-1) ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the (k-1)-th analysis signal (MY _(k-1) ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _j , .... MY _k , .... MY _m ) for monofrequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

ωmmk

k-th center frequency of the k-th modulation signal (MX _k ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, ... MX _n ) and the k-th analysis signal (MY _k ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m ) at monofrequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and m monofrequency analysis signals (MY _1, MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

ωmm(k+1)

(k+1)-th center frequency of the (k+1)-th modulation signal (MX _(k+1) ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and the (k+1)-th analysis signal (MY _(k+1) ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , ... MY _j , .... MY _k , .... MY _m ) for monofrequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and monofrequency m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

ωmmn

nth center frequency of the nth modulation signal (MX _n ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, ... MX _n ) and the nth analysis signal (MY _n ) of the m analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m ) at monofrequency modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _k , .... MX _m, .... MX _n ) and m monofrequency analysis signals (MY ₁ , MY ₂ , MY ₃ , .... MY _j , .... MY _k , .... MY _m );

out

digitized output of prior art analog-to-digital converter (ADC);

out1

first digitized output signal of m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...out _m );

out2

second digitized output signal of m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...out _m );

out3

third digitized output signal of m digitized output signals (out ₁ , out ₂ , out ₃ , ...OUt _k , ...out _m );

outk

kth digitized output signal of m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...outm) with 1≤j≤n;

outm

mth digitized output signal of m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...out _m ), where n is a positive integer;

QNT

quantizer or other analog-to-digital converter;

Σ

summation and difference forming device;

S01

first summand signal of n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n )

S0'1

choppered first summand signal of n choppered summand signals (S0' ₁ , S0' ₂ , S0' ₃ , ... S0' _j , ... S0' _n )

S02

second summand signal of n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n )

S0'2

choppered second summand signal of n choppered summand signals (S0' ₁ , S0' ₂ , S0' ₃ , ... S0' _j ,... S0' _n )

S03

third summand signal of n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n )

S0'3

choppered third summand signal of n choppered summand signals (S0' ₁ , S0' ₂ , S0' ₃ , ... S0' _j , ... S0' _n )

S0j

j-th addend signal of n addend signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n )

S0'j

choppered j-th summand signal of n choppered summand signals (S0' ₁ , S0' ₂ , S0' ₃ , ... S0' _j , ... S0' _n )

S0n

nth addend signal of n addend signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n )

S0'n

choppered n-th summand signal of n choppered summand signals (S0' ₁ , S0' ₂ , S0' ₃ , ... S0' _j , ... S0' _n )

S1

analog-to-digital converter (ADC) input signal;

S2

differential signal;

S2'

choppered differential signal;

S3

filter output signal;

S4

intermediate signal;

S5

feedback signal;

S61

first decimation pre-signal of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,...S6 _k ,...S6 _m );

S62

second decimation pre-signal of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,...S6 _k ,...S6 _m );

S63

third decimation pre-signal of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,...S6 _k ,...S6 _m );

S6k

k-th decimation advance signal of the m decimation advance signals (S6 ₁ , S6 ₂ , S6 ₃ ,...S6 _k ,...S6 _m );

S6n

nth decimation pre-signal of the m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,...S6 _k ,...S6 _m );

510

first arbitrary signal;

511

second arbitrary signal;

SEL

analog multiplexer (MUX) control signal;

SUB

subtractor;

τ1

first phase shift of the first analysis signal MY ₁ (t) with respect to the first modulation signal MX ₁ (t);

τ2

second phase shift of the second analysis signal MY ₂ (t) with respect to the second modulation signal MX ₂ (t);

τ3

third phase shift of the third analysis signal MY ₃ (t) with respect to the third modulation signal MX ₃ (t);

τj

j-th phase shift of the j-th analysis signal MY _j (t) with respect to the j-th modulation signal MX _j (t);

τη

nth phase shift of the nth analysis signal MY _n (t) with respect to the nth modulation signal MX _n (t);

Tp

system period;

Uin,1

first input signal of n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _in,n );

uin,2

second input signal of n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _in,n );

uin,3

third input signal of n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _in,n );

Uin,j

j-th input signal of n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _in,n ) with 1≤j≤n;

Uin,n

nth input signal of n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _in,n ), where n is a positive integer;

List of cited writings

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Claims (10)

Method for converting a plurality of at least n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _inn ) into m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...out _m ), where n is a positive integer greater than 1 and where m is a positive integer with 2≤m≤n and where in the following j is a positive integer with 1≤j≤n and where im Following k is a positive integer with 1≤k≤m and with each jth input signal (U _inj ), with j as a positive integer with 1≤j≤n, exactly a jth digitized output signal (out _j ) bijective is assigned, with the steps of providing n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) and providing m analysis signals (MY ₁ , MY ₂ , MY ₃ , . ... MY _k , .... MY _m ), wherein the signal of each j th modulation signal (MX _j ) has a center frequency (ω _mm,j ) of the j th modulation signal (MX _j ) and wherein the signal of each k -th analysis signal (MY _k ) the center frequency (ω _mm,k ) of the k-th analysis signal (MY _k ), which for j≤k is preferably equal to the center frequency (ω _mm,k ) of the k-th modulation signal (MX _k ), and wherein the j-th center frequency (ω _mmj ) of the j-th modulation signal (MX _j ) of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmn ) of other (n-1) modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _(j-1) , MX _(j+1) ,... MX _n ) is different and for j≤m from all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmm ) of the other (m-1) analysis signals (MY ₁ , MY ₂ , MY ₃ ,... MY _(j-1) ,MY _(j+1) ,... MY _n ) different is; where the k-th center frequency (ω _mmk ) of the k-th analysis signal (MY _k ) is one of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(k-1) , ω _mm(k+1) ,... ω _mmn ) of the other (n-1) modulation signals (MX _1, MX ₂ , MX ₃ ,... MX _(k-1) , MX _(k+1) ,... MX _n ) is different and of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmm ) of the other (m-1) analysis signals (MY ₁ , MY ₂ , MY ₃ ,... MY _(k-1) ,MY _(k+1) ,... MY _m ) is different; Multiplication or mixing of each of the j-th input signals (U _in,j ) with exactly one assigned j-th modulation signal (MX _j ) to generate an associated j-th summand signal (S0 _j ) of n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , . . _{. S0 j} , _. Summation of all n summand signals (S0 ₁ , S0 ₂ , S0 ₃ ,... S0 _j ,... S0 _n ) to generate a differential signal (S2); Filtering of the difference signal (S2) to form the filter output signal (S3); Quantization or analog-to-digital conversion of the filter output signal (S3) to the quantized intermediate signal (S4); Multiplication of the intermediate signal (S4) with preferably each of the k-th analysis signals (MY _k ) of the _m analysis signals (MY ₁ , MY ₂ , MY ₃ , . . . MY _k , decimation advance signal (S6 _k ) of preferably m decimation advance signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ); Filtering of each k-th decimation preliminary signal (S6 _k ) of the preferably m decimation preliminary signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) generated in this way to produce a k-th digitized output signal (out _k ) in each case of preferably m digitized output signals (out ₁ , out ₂ , out ₃ , ... out _k , ... out _m ). procedure after claim 1 comprising the additional steps, summation of all n summand signals (S0 ₁ , S0 ₂ , S0 ₃ , ... S0 _j , ... S0 _n ) with subtraction of a feedback signal (S5) to generate a difference signal (S2); Digital-to-analog conversion of the quantized intermediate signal (S4) to the feedback signal (S5). procedure after claim 1 and/or 2, wherein an analysis signal (MY _k ) has the same center frequency (ω _mm,j ) as compared to a modulation signal (MX _j ) and wherein this analysis signal (MY _k ) has a non-zero phase shift compared to this modulation signal (MX _j ). , so that the analysis signal (MY _k ) lags behind the modulation signal (MX _j ). Method according to one or more of the Claims 1 until 3 , wherein the filtering of each k-th decimation pre-signal (S6 _k ) with a k-th filter function F _k[ S6k(t)] to a respective k-th digitized output signal (out _k ) takes place in such a way that the filtering has the property $${\text{f}}_{\text{k}}\left[{\mathrm{\lambda }}_{\text{j}}\times {\text{MX}}_{\text{j}}\left(\text{t}-{\mathrm{\tau }}_{\text{j}}\right)\times {\text{MY}}_{\text{k}}\left(\text{t}\right)\right]=0\text{f}\ddot{\text{and}}\text{rk}\ne \text{j and}$$

and $${\text{f}}_{\text{k}}\left[{\mathrm{\lambda }}_{\text{j}}\times {\text{MX}}_{\text{j}}\left(\text{t}-{\mathrm{\tau }}_{\text{j}}\right)\times {\text{MY}}_{\text{k}}\left(\text{t}\right)\right]={\mathrm{\beta }}_{\text{j}}\text{f}\ddot{\text{and}}\text{rk}=\text{j}$$

with τ _j as a temporal phase shift, λ _j as a complex factor and β _j as a constant complex value. Method according to one or more of the Claims 1 until 4 , where for a modulation signal (MX _j (t)) and an associated analysis signal (MY _j (t)) the equation MX _j (t-τ _j ) = η MY _k (t) with η as complex value and with τ _j as temporal phase shift applies. Device for converting a plurality of at least n input signals (U _in1 , U _in2 , U _in3 , ...U _inj , ...U _inn ) into m digitized output signals (out ₁ , out ₂ , out ₃ , ...out _k , ...out _m ), where n is a positive integer greater than 1 and where m is a positive integer with 2≤m≤n and where in the following j is a positive integer with 1≤j≤n and where im Following k is a positive integer with 1≤k≤m and with n input multipliers (M _1,1 , M _1,2 , M _1,3 , ... M _1,j , ... M _1,n ) and with n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j , .... MX _n ) and with n summand signals (S0 ₁ , S0 ₂ , S0 ₃ ,... S0 _j ,... S0 _n ) and with a summation and difference device (Σ) with a difference signal (S2) and with a filter (INT) and with a filter output signal (S3) and with a quantizer or another analog-to-digital converter (QNT) and with an intermediate signal (S4) and with m output multipliers (M _{2, 1} , M _2,2 , M _2,3 ,... M _2,k ,... M _2,m ) and with m decimation advance signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,.. . S6 _m ) and with m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m/ DEZ _m ) and with m output signals ( out ₁ , out ₂ , out ₃ , ... out _k , ... out _m ), wherein the signal of each j th modulation signal (MX _j ) has a center frequency (ω _mmj ) of the j th modulation signal (MX _j ). and wherein the signal of each k-th analysis signal (MY _k ) has the center frequency (ω _mmk ) of the k-th analysis signal (MY _k ), which for j≤k is preferably equal to the center frequency (ω _mmk ) of the k-th modulation signal (MX _k ) and where the j th center frequency (ω _mmj ) of the j th modulation signal (MX _j ) of all Center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmn ) of the other (n-1) modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _(j-1) ,MX _(j+1) ,... MX _n ) is different and for j≤m from all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... Mmm _(j-1) , ω _mm(j+1) ,...ω _mmm ) of the other (m-1) analysis signals (MY ₁ , MY ₂ , MY ₃ ,... MY _(j-1) ,MY _(j+1) ,... MY _n ) is different; where the k-th center frequency (ω _mmk ) of the k-th analysis signal (MY _k ) is one of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(k-1) , ω _mm(k+1) ,... ω _mmn ) of the other (n-1) modulation signals (MX ₁ , MX ₂ , MX ₃ ,... MX _(k-1) , MX _(k+1) ,... MX _n ) is different and of all center frequencies (ω _mm1 , ω _mm2 , ω _mm3 ,... ω _mm(j-1) , ω _mm(j+1) ,... ω _mmm ) of the other (m-1) analysis signals (MY ₁ , MY ₂ , MY ₃ ,... MY _(k-1) ,MY _(k+1) ,... MY _m ) is different; each j-th input multiplier (M _1,j ) of the n input multipliers (M _1,1 , M _1,2 , M _1,3 , ... M _1,j , ... M _1,n ) in this j -th input multiplier (M _1,j ) bijectively assigned j-th input signal (U _in,j ) of the at least n input signals (U _in,1 , U _in,2 , U _in,3 ,...U _in,j ,. ..U _in,n ) with a j-th modulation signal (MX _j ) of the n modulation signals (MX ₁ , MX ₂ , MX ₃ , .... MX _j ) bijectively assigned to this j-th input multiplier (M _1,j ), .... MX _n ) to a _{j-th summand signal (S0 j )} of the n summand signals (S0 ₁ , S0 ₂ , S0 ₃ ,... S0 _j ,. .. S0 _n ) and wherein the summation and difference formation device (Σ) sums the values of the n summand signals (S0 ₁ , S0 ₂ , S0 ₃ ,... S0 _j ,... S0 _n ) and thus the difference signal (S2 ) and where the filter (INT) filters the difference signal (S2) to form the filter output signal (S3) and where the quantizer or the other analog to digital converter (QNT), the filter output signal (S3) is quantized to the quantized intermediate signal (S4) and each k-th output multiplier (M _2, j) of the m output multipliers (M _2.1 , M _2.2 , M _2.3 , ... M 2 _{, k} , ... M _2,m ) the intermediate signal (S4) with a k-th analysis signal (MY _k ) of the m analysis signals (MY ₁ , MY _{2 ,} MY ₃ , .... MY _k , .... MY _m ) to a k-th decimation advance signal (S6 _k ) of the m decimation advance signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) and each k-th decimation filter (LPF _k/ DEZ _k ) of the m decimation filters (LPF _1/ DEZ ₁ , LPF ₂ /DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) this k-th decimation filter (LPF _k /DEZ _k ) of the m decimation filters (LPF ₁ /DEZ ₁ , LPF ₂ / DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m/ DEZ _m ) bijectively assigned kth decimation advance signal (S6 _k ) d er m decimation pre-signals (S6 ₁ , S6 ₂ , S6 ₃ ,... S6 _k ,... S6 _m ) to one of the m decimation _filters (LPF _{1/ DEZ 1} , LPF _2/ DEZ ₂ , LPF ₃ /DEZ ₃ ,... LPF _k /DEZ _k ,... LPF _m /DEZ _m ) bijectively assigned kth output signal (out _k ) of the m output signals (out ₁ , out ₂ , out ₃ ,... out _k ,... out _m ) filters. device after claim 6 with a digital-to-analog converter (DAC) and with a feedback signal (S5), wherein the summation and difference formation device (Σ) calculates the values of the n summand signals (S0 ₁ , S0 ₂ , S0 ₃ ,... S0 _j , ... S0 _n ) after subtracting the value of the feedback signal (S5) and thus forming the difference signal (S2) and with the digital-to-analog converter (DAC), possibly in cooperation with a delay device, producing the quantized intermediate signal (S4) delayed to the feedback signal (S5). device after claim 6 and/or 7, wherein an analysis signal (MY _k ) has the same center frequency (ω _mm,j ) as a modulation signal (MX _j ) and wherein this analysis signal (MY _k ) has a non-zero frequency as compared to this modulation signal (MX _j ). Has phase shift, so that the analysis signal (MY _k ) the modulation signal (MX _j ) lags behind in time. Device according to one or more of Claims 6 until 8th , wherein the filtering of each k-th decimation pre-signal (S6 _k ) in the k-th decimation filter (LPF _k/ DEZ _k ) with a k-th filter function F _k[ S6k(t)] results in a k-th digitized output signal (out _k ) takes place in such a way that the filtering respectively has the property $${\text{f}}_{\text{k}}\left[{\mathrm{\lambda }}_{\text{j}}\times {\text{MX}}_{\text{j}}\left(\text{t}-{\mathrm{\tau }}_{\text{j}}\right)\times {\text{MY}}_{\text{k}}\left(\text{t}\right)\right]=0\text{f}\ddot{\text{and}}\text{rk}\ne \text{j}$$

and $${\text{f}}_{\text{k}}\left[{\mathrm{\lambda }}_{\text{j}}\times {\text{MX}}_{\text{j}}\left(\text{t}-{\mathrm{\tau }}_{\text{j}}\right)\times {\text{MY}}_{\text{k}}\left(\text{t}\right)\right]={\mathrm{\beta }}_{\text{j}}\text{f}\ddot{\text{and}}\text{rk}=\text{j}$$

with τ _j as a temporal phase shift, λ _j as a complex factor and β _j as a constant complex value. Method according to one or more of the Claims 6 until 9 , where for a modulation signal (MX _j (t)) and an associated analysis signal (MY _j (t)) the equation MX _j (t-λ _j ) = η MY _k (t) with η as a complex value and with λ _j as temporal phase shift applies.

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