DE102021004707A1 - solar cell contact arrangement - Google Patents

Abstract

Solar cell contact arrangement, comprising a semiconductor body with a top side, a bottom side, the semiconductor body having a plurality of solar cell stacks and a carrier substrate on the bottom side, and each solar cell stack at least two III-V partial cells arranged on the carrier substrate and at least one from the top side to the bottom side the semiconductor body has a through contact with a continuous side wall that reaches far, wherein the through contact has a first edge region on the upper side and a second edge region on the underside, and the first edge region has a first section and a second metallic section, and the second edge region has a first section and a second section, wherein the respective second sections completely enclose the respective first sections, and an insulating layer, wherein the insulating layer at the first edge area on the first section, the side wall and formed on the first section and the second section in the second edge region is an electrically conductive layer which is at least partially arranged on the insulating layer.

Description

The invention relates to a solar cell contact arrangement.

In order to reduce shading on the front of a solar cell, it is possible to arrange both the positive and the negative external contact area on the back. In the case of so-called Metal Wrap Through (MWT) solar cells, the front side of the solar cell is contacted, for example, through a through contact opening from the rear side.

Various methods are known for producing a hole or a through-contact opening through a solar cell. The metallization running through the through opening is insulated from the layers of the solar cell stack by means of an insulating layer.

For example, from the US 9,680,035 B1 a solar cell contact arrangement with a solar cell stack comprising a plurality of III-V partial cells on a GaAs substrate with a front side contacted on the back is known. In this case, a hole extending from the top of the solar cell through the sub-cells into a substrate layer that has not yet been thinned is produced by means of a wet-chemical etching process. Passivation and metallization of the front side and the hole is performed before thinning the substrate layer.

Against this background, the object of the invention is to develop the prior art.

The object is achieved by a device having the features of patent claim 1. Advantageous configurations of the invention are the subject matter of dependent claims.

According to the subject matter of the invention, a solar cell contact arrangement is provided.

The solar cell contact arrangement comprises a semiconductor body with a top and a bottom.

The semiconductor body comprises at least one solar cell stack on the top and a carrier substrate on the bottom.

Each solar cell stack comprises at least two III-V sub-cells arranged on the carrier substrate and at least one via contact extending from the top to the bottom of the semiconductor body.

The via contact has a continuous side wall with a first edge area formed on the upper side and a second edge area formed on the underside.

The first edge area has a first section and a second metal section and the second edge area has a first section and a second section.

Furthermore, an insulating layer is formed on the first portion at the first edge region, on the side wall and on the first portion and the second portion at the second edge region.

The insulating layer has a thickness between 5 μm and 200 μm.

An electrically conductive layer is also formed at the first edge region on the first section and the second section, at the side wall and at the second edge region on the first section, the electrically conductive layer being at least partially arranged on the insulating layer.

The electrically conductive layer is designed as a heterogeneous layer with gas inclusions and has a thickness of between 5 μm and 200 μm.

It should be noted that the gas inclusions comprise at least one volume percent and at most forty volume percent of the total volume of the electrically conductive layer, or the electrically conductive layer comprises gas inclusions between two and ten volume percent.

On the upper side, the electrically conductive layer is formed at least partially beyond the first section in the first edge region in order to contact a metal structure on the front.

On the underside, the electrically conductive layer is formed in the second edge region within the first section and not on the second section. In other words, the electrically conductive layer lies completely on the insulating layer in the second edge region.

The electrically conductive layer has organic components. In one development, the electrical layer goes through an annealing process of at least 200° C. and a duration of at least 5 minutes.

The semiconductor body is preferably in the form of a semiconductor wafer. In one development, the semiconductor body includes a plurality of solar cell stacks. Precisely two solar cell stacks are preferably formed on the semiconductor wafer.

In the case of the second edge region, an electrically conductive layer is preferably formed exclusively on the first section.

The electrically conductive layer preferably at least partially or completely covers the first section in the second edge area.

In the case of the first edge region, the insulation layer is preferably formed exclusively on the first section.

It goes without saying that the electrically conductive layer is arranged on the insulating layer if the insulating layer is formed.

There is preferably a material connection between the insulation layer and the electrical layer.

It should be noted that the insulating layer completely covers the sidewall, i.e. the surface of the via formed perpendicularly to the surface.

The insulation layer preferably covers the first section in the first edge area and the first section and the second section in the second edge area in each case at least partially or completely.

It should be noted that the term “insulation layer” also means in particular a dielectric layer system that includes the insulation layer. Furthermore, the term edge area designates an area on the upper side and on the underside arranged directly on the through-opening.

It should be noted that light is irradiated onto the upper side of the semiconductor body. In order to shade as little as possible from the top, the top is electrically connected by means of a metallic finger structure.

The band gap of the III-V sub-cells preferably decreases from sub-cell to sub-cell from the upper side in the direction of the carrier substrate.

In general, the sub-cells of the respective solar cell stack have an n-on-p arrangement. It goes without saying that a tunnel diode is formed between two sub-cells in order to connect the individual sub-cells in series from an electrical point of view. In particular, the top sub-cell comprises an InGaP compound and has a band gap greater than 1.7 eV.

It goes without saying that a generally finger-shaped upper-side metallization is arranged on the upper side in order to electrically connect the front side. The top-side metallization is also referred to below as a metal structure.

It goes without saying that with each solar cell stack, the top side is electrically connected from the rear side by means of one or more through-openings.

Before the through-opening is formed, the semiconductor body, which is formed, for example, as a semiconductor disk and preferably has a diameter of 100 mm or 150 mm, is preferably thinned to the desired final thickness. For this purpose, the carrier substrate is removed from the back.

Furthermore, it should be noted that the semiconductor body embodied as a semiconductor wafer in a development has a plurality of solar cell stacks that have not been isolated, with the carrier substrate forming the underside of the semiconductor body. It goes without saying that the solar cell stack also has 3 or 4 or 5 or a maximum of 6 sub-cells.

In one development, exactly one of the several sub-cells is designed as a Ge sub-cell.

One advantage of the solar cell contact arrangement is that a front side of the solar cell stack formed on the top side is connected from the bottom side by means of the via contact. In other words, the solar cell stack is electrically connected from the rear only. There is no need to form metal surfaces, i.e. pads, on the front side. The receiving area on the front increases and the efficiency of the arrangement increases.

The formation of the via, i.e. the formation of an electrical connection of the front from the rear, simplifies the electrical connection of the solar cell stack. Another advantage is that both contacts, i.e. the n-contact and the p-contact, can be connected on the back with a single soldering process step, for example. This allows the yield and reliability to be increased.

It is noted that the solar cell contact arrangement is preferably formed using one or multiple application of a printing process. The top side and the rear side are preferably coated with the insulating layer by means of a first printing process and the front side and the rear side with the electrical layer by means of a second printing process.

In this case, the first printing method and the second printing method each comprise one or more process steps.

For example, only one side of the semiconductor body and the through-opening is printed in each case in a first process step and then the other side of the semiconductor body and the through-opening or excluding the through-opening are printed in each case in a second process step.

Alternatively, the first printing method and/or the second printing method comprises only a single printing step in each case in which both sides of the semiconductor body are printed.

In one development, in the first process step and/or the second process step, when the respective single printing step is carried out, one side of the semiconductor body is printed using a material guided through the through-opening.

Since the respective layers can be applied in a structured manner using the printing process, photolithographic process steps are no longer necessary. In other words, both the insulating layer and the electrically conductive layer can be applied in a structured manner, reliably and cost-effectively.

Another advantage of the printing process is that the above-mentioned layers can be reliably applied without further ado, even if there are large differences in the topography. Expensive and time-consuming masking steps are avoided. Reliable protection of the insulation layer in the area of the through opening can also be provided. In particular, the time and technical effort and the material consumption are low compared to the prior art using lacquer masks. Reliability and yield can be increased as a result.

The through-opening and the areas on the upper side and on the underside adjoining the through-opening are preferably covered exclusively by means of the printing process. The method can be used to produce highly efficient and reliable multi-junction solar cells in a simple and cost-effective manner, the front of which is electrically connected to the rear.

In one development, the electrically conductive layer is formed on the underside of the carrier substrate in a first contact area. This allows the top side of the semiconductor wafer, ie the front side of the solar cell stack, to be electrically connected to the back.

In another development, a second contact area is formed on the underside of the carrier substrate. The underside of the electrically conductive carrier substrate can be electrically connected by means of the second contact area. The first contact area is preferably in the form of an n-contact and the second contact area is in the form of a p-contact. It goes without saying that the two contact areas on the underside are spaced apart from one another in order to ensure electrical insulation.

In another development, both contact areas are of planar design and each have a size of at least 1.0 mm ² . In one embodiment, both contact areas have at least partially the same height. In other words, the surfaces of the two contact areas are equidistant from the underside of the carrier substrate. One advantage is that the two contact areas can be connected to a base at the same time, for example by means of a so-called reflow soldering step.

In one embodiment, the first contact area, i.e. the electrically conductive layer, has a material connection with the underlying insulating layer. In particular, the electrical layer has a complete material connection with the insulation layer in the first contact area.

In another embodiment, the diameter of the through-opening in the carrier substrate is, in a first approximation, the same or exactly the same from the top side in the direction of the bottom side, or simulates a conical shape.

In one development, after the formation of the conductive layer, the through-opening is partially or completely closed, or the through-opening still has a through hole.

In one embodiment, the first edge area on the upper side has a different, in particular smaller, diameter than the second edge area on the underside.

In another embodiment, the first edge area and the second edge area are each formed as an edge area running completely around the through-opening. The respective edge region parallel to the semiconductor body preferably has a diameter of at least 10 μm and at most 3.0 mm. Alternatively, the respective edge region parallel to the semiconductor body per a diameter of at least 100 µm and at most 1.0 mm.

In another development, the through opening of the semiconductor body has a total height of at most 500 μm and at least 30 μm or at most 200 μm and at least 50 μm.

In one embodiment, the through-opening has an oval circumference, in particular a round circumference, in cross-section. Before the application of the first printing method, i.e. without forming the insulating layer, the through-opening preferably has a diameter of between 25 µm and 1 mm. Alternatively, the diameter of the through opening is in a range between 50 μm and 300 μm.

In another development, the carrier substrate is designed to be electrically conductive. The carrier substrate preferably comprises germanium or GaAs or silicon or consists of one of the aforementioned materials. Alternatively, the carrier substrate includes a metal foil or includes an electrically conductive plastic.

In one embodiment, the through-opening is preferably of oval design. In the present case, the term "oval" also includes round, in particular circular, egg-shaped and elliptical shapes.

In another embodiment, the through-opening is designed as a quadrangular or square shape with rounded corners.

In a further development, a first heating step is carried out after the first printing process and before the second printing process is carried out. In another development, a second heating step is carried out after the second printing process. The insulation layer and the conductive layer are each conditioned by means of the heating steps. The baking steps are preferably carried out in a temperature range between 100.degree. C. and 450.degree.

In a development, a paste is used to form the insulation layer. The paste preferably comprises organic components.

In another development, a paste containing metal particles is used to form the conductive layer.

In one embodiment, the first printing method and/or the second printing method is carried out exclusively from the front or exclusively from the back. Alternatively, the first printing process and/or the second printing process is carried out both from the front and from the back.

In another embodiment, the through opening also has a through hole after the insulation layer has been formed. Alternatively, the passage opening is opened in a central area by means of a laser.

Preferably, the conductive layer on the first edge area and in the through opening and on the second edge area consists of the same material. In an alternative embodiment, different compositions are used to form the conductive layer on the upper side and on the lower side.

If the through-opening is completely closed by means of the conductive layer, in one development the conductive layer protrudes beyond the top and/or on the bottom. Alternatively, the conductive layer on the underside on the insulation layer forms what is, to a first approximation, a planar surface with the conductive layer in the center of the through-opening.

In a development, the printing process is carried out using an inkjet process or a screen printing process or using a dispensing process. Alternatively, the printing process is carried out using a stencil printing process. In another development, at least two of the different printing methods are combined.

In a development, the diameter of the through-opening before the application of the printing process in the carrier substrate is approximately or exactly the same from the top side to the bottom side.

Alternatively, the diameter of the through-opening becomes smaller from the upper side towards the lower side, with the taper preferably being formed in steps. In a development, the passage opening has an hourglass-shaped view in a cross section. Here, the cross-section tapers down to about half of the total thickness.

In another development, the taper in the through-opening includes exactly one step that runs all the way around or exactly two steps that run all the way around.

The semiconductor body or the carrier substrate preferably has a size of 100 mm or 150 mm or larger.

If the carrier substrate includes or consists of germanium, the Ge carrier substrate forms the underside of the semiconductor bodies. A first sub-cell is preferably formed as a Ge sub-cell in the Ge carrier substrate on the side facing away from the underside, the Ge sub-cell having the smallest band gap of the sub-cells of the solar cell stack.

When Ge is used as the carrier substrate, a first step is formed at the interface between the Ge sub-cell and the overlying III-V sub-cells. A second stage is preferably formed between the Ge sub-cell and the Ge substrate.

Preferably, the through hole also tapers inside the Ge substrate. The step-shaped or conical design of the through-opening has the advantage that the thickness of the layers can be formed sufficiently on the side surfaces, particularly with a preferably conformal deposition of the insulation layer and/or other layers to be applied as part of a metallization.

In one development, a further step is formed on the upper side of the semiconductor bodies at the interface between the metal structure and the upper side of the uppermost III-V sub-cell.

In one embodiment, the solar cell stack includes a Ge sub-cell. As a result, the solar cell stack comprises at least 3 sub-cells.

In another embodiment, part of the insulating layer is formed on top of a metal surface. This ensures that the metal structure, i.e. the front of the solar cell stack, is connected to the top.

In other words, since the conductive layer on the upper side overlaps the insulating layer and forms a material connection with a part of the metal structure and on the lower side only covers the part of the second edge area that is directly adjacent to the through-opening, this creates a contact area on the lower side for a electrical connection of the metal structure MV formed.

In a development, the respective second sections completely enclose the respective first sections.

In one embodiment, the proportion of organic components in the electrical layer is between 0.1 and 5% by volume or between 0.2 and 2% by volume. It goes without saying that the electrical layer is applied to the surface by means of the printing process using a metal-organic paste.

In another development, the thickness of the part of the electrical layer directly at the edge of the first edge area towards the through-opening is at least half the thickness of the part of the electrical layer resting on the second edge area.

In a further development, the through-opening is completely filled after the electrical layer has been formed.

In another embodiment, the insulating layer includes organic components. The proportion of the organic components is preferably in a range between 0.1% and 5% by volume.

In a development, the insulating layer has a thickness of between 5 μm and 200 μm or between 5 μm and 250 μm and/or the electrically conductive layer has a thickness of between 5 μm and 500 μm. In another development, the thickness of the insulating layer is between 10 μm and 100 μm and/or the thickness of the electrically conductive layer is between 10 μm and 200 μm.

In one embodiment, the electrically conductive layer has a metal volume fraction of less than 99% and more than 50%.

In another embodiment, the electrical conductivity is between 30% and 90% of the metal conductivity of a metal layer formed homogeneously with the same material composition in a first approximation.

• 1 eine Querschnittsansicht einer metallisierten Durchgangsöffnung in einer Ausführungsform,
• 2 eine Querschnittsansicht einer metallisierten Durchgangsöffnung in einer weiteren Ausführungsform,
• 3 eine Querschnittsansicht einer metallisierten Durchgangsöffnung in einer anderen Ausführungsform,
• 4a eine Draufsicht auf die Oberseite der metallisierten Durchgangsöffnung entsprechend der Ausführungsform, dargestellt in Zusammenhang mit der Abbildung der 3,
• 4b eine Draufsicht auf die Unterseite der metallisierten Durchgangsöffnung entsprechend der Ausführungsform, dargestellt in Zusammenhang mit der Abbildung der 3,
• 5 eine Querschnittsansicht einer metallisierten Durchgangsöffnung mit einem ersten Kontaktbereich und einem zweiten Kontaktbereich.
• 6 eine Draufsicht auf eine Halbleiterkörper mit zwei Solarzellenstapel.

The invention is explained in more detail below with reference to the drawings. Similar parts are labeled with identical designations. The illustrated embodiments are highly schematic, ie the distances and the lateral and vertical extent are not to scale and, unless otherwise stated, do not have any derivable geometric relationships to one another. In it show the

• 1 a cross-sectional view of a metallized through hole in one embodiment,
• 2 a cross-sectional view of a metallized through opening in a further embodiment,
• 3 a cross-sectional view of a metallized through hole in another embodiment,
• 4a 12 is a top plan view of the metallized through hole according to the embodiment shown in conjunction with FIG 3 ,
• 4b 12 is a bottom plan view of the metallized through hole according to the embodiment shown in conjunction with FIG 3 ,
• 5 a cross-sectional view of a metallized through hole with a first contact area and a second contact area.
• 6 a top view of a semiconductor body with two solar cell stacks.

The illustrations of 1 shows a cross-sectional view of a metallized through-opening 22 of a semiconductor body 10.

A semiconductor body 10 is provided with an upper side 10.1, an underside 10.2 and a through-opening 22 extending from the upper side 10.1 to the underside 10.2 with a continuous side wall 22.1.

The semiconductor body 10 comprises a plurality of solar cell stacks 12 that have not yet been separated; only one solar cell stack 12 is shown here, each with a layer sequence comprising a carrier substrate 14 forming the underside 10.2, a first III-V partial cell 18 and a second III-V forming the upper side 10.1 -Part cell 20.

A metal structure MV is formed on the upper side 10.1. The metal structure MV is designed almost exclusively as a finger-shaped structure and has a continuous metal surface formed completely around the through-opening 22, particularly in the first edge region 11.1 of the through-opening 22.

A rear-side metallization MR covering the whole area is formed on the underside 10.2 in order to connect the conductive carrier substrate 14. It goes without saying that the respective solar cell stack 12 is electrically connected to the two metallizations MV and MR.

The through-opening 22 has a first edge area 11.1 on the upper side 10.1 and a second edge area 11.2 on the underside 10.2. The first edge region 11.1 is formed directly on the metal structure MV and the second edge region 11.2 is formed directly on the rear-side metallization MR.

The first edge area 11.1 has a first section 12.1 and a second metal section 12.2. The second edge region 11.2 has a first section 13.1 and a second section 13.2. Subsequently, the first section 12.1 of the first edge region 11.1 and the second section 12.2. of the first edge area 11.1 also referred to as the first part or as the second part of the first edge area.

Correspondingly, the first section 13.1 and the second section 13.2 of the second edge area 11.2 are also referred to as the first part or as the second part of the second edge area 11.2.

A part of the first edge region 11.1 formed directly around the through-opening 22. and the entire second edge region 11.2 and the side wall 22.1 of the through-opening 22 are coated with an insulation layer 24, with the insulation layer 24 being formed using a first printing method. It goes without saying that the side wall 22.1 in the through opening 22 is completely covered by the insulating layer 24.

A conductive layer 32 is applied to the entire area of the first edge region 11.1 and completely to the entire surface of the side wall 22.1 and to a part of the second edge region 11.2 directly adjoining the through-opening 22 by means of a second printing process. In the present case, the through-opening 22 is still open even after the conductive layer 32 has been formed.

Because the conductive layer 32 on the upper side 10.1 overlaps the insulating layer 24 and forms a material connection with a part of the metal structure MV and on the lower side 10.2, however, only covers that part of the second edge region 11.2 that is directly adjacent to the through-opening 22 10.2 formed a contact area for a connection of the metal structure MV.

In the illustration of 2 another embodiment is shown. In the following, only the differences to the illustration of the 1 explained.

In the illustrated embodiment, the conductive layer 32 meets at the center of the substrate 14 and forms an hourglass-shaped profile.

In the illustration of 3 another embodiment is shown. In the following, only the differences to the illustration of the 1 explained.

In the illustrated embodiment, the through hole 22 is completely covered by the leitfä Higen layer 32 is filled and forms an elevation protruding from the top 10.1 and from the bottom 10.2.

In the illustration of 4a FIG. 14 is a top plan view of the plated through hole 22 according to the embodiment shown in conjunction with FIG 3 , pictured.

The first edge area 11.1, as part of the metal structure MV, encloses the through-opening 22 completely. The part of the first edge region 11.1 covered with the insulation layer 24 is drawn in with dashed lines. It can be seen that the conductive layer 22 completely covers the insulating layer 24 on the upper side 10.1.

In the illustration of 4b FIG. 14 is a bottom plan view of the plated through hole 22 according to the embodiment shown in conjunction with FIG 3 , pictured.

The second edge region 11.2, as part of the rear-side metallization MR, encloses the through-opening 22 completely. The part of the second edge region 11.2 covered with the insulating layer 24 is now larger than the part covered with the conductive layer 22. In other words, the conductive layer 22 only partially covers the insulating layer 24 on the underside 10.2.

In the illustration of 5 Another cross-sectional view of a metallized through hole is shown. In the following, only the differences to the illustration of the 1 and the illustration of 4b explained.

On the underside 10.2, the first section 13.1 of the second edge area 11.2 is widened at least on the right-hand side of the through-opening 22 in order to form a first contact area K1. On the second section 13.2 of the second edge region 11.2, the underside 10.2 is only covered with the insulating layer 24.

On the underside 10.2, adjoining the second section 24, a second contact region K2 is formed as part of the rear-side metallization MR.

In a part of the second contact area K2, the insulation layer 24 is also formed on the underside 10.2 to adjust the height of the second contact area K2. In other words, the rear-side metallization MR is formed in a materially bonded manner on the insulation layer 24 in the second contact region K2.

As a result, the two surfaces of the first contact area K1 and the second contact area K2 can be adjusted in such a way that both contact areas K1 and K2 can be soldered at the same time.

In the illustration of 6 a plan view of a semiconductor body 10 with two solar cell stacks is shown. In the present case, the semiconductor body 10 has precisely two solar cell stacks 12 . It goes without saying that in specific embodiments that are not illustrated, more than two solar cell stacks 12 are also formed on the semiconductor body 10 .

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US 9680035 B1 [0004]

Claims (17)

Solar cell contact arrangement comprising - a semiconductor body (10) with an upper side (10.1) and an underside (10.2), the semiconductor body (10) having at least one solar cell stack (12) and comprising a carrier substrate (14) on the underside, - each solar cell stack (12) has at least two III-V partial cells (18, 20) arranged on the carrier substrate (14) and at least one through contact (22 ) having a continuous side wall (22.1), wherein the through contact (22) has a first edge area (11.1) on the top side (10.1) and a second edge area (11.2) on the underside (10.2), and the first edge area (11.1) has a first section (12.1) and a second metal section (12.2), and the second edge region (11.2) has a first section (13.1) and a second section (13.2), wherein - an insulating layer (24) with a thickness of 5 µm to 200 µm, wherein the insulating layer (24) in the first edge area (11.1) on the first section (12.1), the side wall (22.1) and in the second edge area (11.2) is formed on the first section (13.1) and the second section (13.2), - An electrically conductive layer (32), wherein the electrically conductive layer (32) is designed as a heterogeneous layer with inclusions of gas, and the electrically conductive layer has a thickness between 5 µm and 200 µm, and the electrically conductive layer in the first edge region (11.1) on the first section (12.1) and at least partially on the second section (12.2), on the side wall (22.1) and in the second edge region (11.2), the electrically conductive layer is formed within the first section (13.1), and the electrically conductive layer (32) is arranged on the insulating layer (24). Solar cell contact arrangement after claim 1 , characterized in that the electrically conductive layer (32) on the underside of the carrier substrate (14) forms a first contact region (K1). Solar cell contact arrangement after claim 1 or claim 2 , characterized in that a second contact area (K2) is formed on the underside of the carrier substrate (14) and the carrier substrate (14) is electrically connected to the underside (10.2) by means of the second contact area (K2). Solar cell contact arrangement according to one of claims 2 or 3 , characterized in that the solar cell stack (12) is electrically connected by means of the first contact area (K1) and by means of the second contact area (K2). Solar cell contact arrangement according to one of claims 2 or 3 , characterized in that the two contact areas (K1, K2) are planar and each have a size of at least 1.0 mm ² . Solar cell contact arrangement according to one of claims 2 until 5 , characterized in that both contact areas (K1, K2) at least partially have the same height. Solar cell contact arrangement according to one of the preceding claims, characterized in that after the formation of the conductive layer (32) the through opening is partially or completely closed or the through opening still has a through hole. Solar cell contact arrangement according to one of the preceding claims, characterized in that the first edge area (11.1) has a smaller diameter than the second edge area (11.2). Solar cell contact arrangement according to one of the preceding claims, characterized in that the first edge area (11.1) and the second edge area (11.2) are each formed as an edge area running completely around the through-opening (22) and the respective edge area (11.1, 11.2) parallel to the semiconductor body (10) has a diameter of at least 10 µm and at most 3.0 mm. Solar cell contact arrangement according to one of the preceding claims, characterized in that before the insulation layer (24) and the conductive layer (32) are formed, the through-opening (22) has a diameter of between 25 µm and 1 mm. Solar cell contact arrangement according to one of the preceding claims, characterized in that the respective second sections (12.2, 13.2) completely enclose the respective first sections (12.1, 13.1). Solar cell contact arrangement according to one of the preceding claims, characterized in that the proportion of organic components in the electrical layer (32) between 0.1 and 5% by volume or between 0.2 and 2% by volume. Solar cell contact arrangement according to one of the preceding claims, characterized in that the thickness of the part of the electrical layer directly at the edge of the first edge area (11.1) towards the through-opening (22) is at least half the thickness of the part of the part lying on the second edge area (11.2). electrical layer (32) is. Solar cell contact arrangement according to one of the preceding claims, characterized in that the passage opening is completely filled after the formation of the electrical layer. Solar cell contact arrangement according to one of the preceding claims, characterized in that the insulating layer (24) comprises organic components in a range between 0.1 and 5 percent by volume. Solar cell contact arrangement according to one of the preceding claims, characterized in that the insulating layer (24) has a thickness of between 5 µm and 250 µm and/or the electrically conductive layer (32) has a thickness of between 5 µm and 500 µm. Solar cell contact arrangement according to one of the preceding claims, characterized in that and has a metal volume fraction of less than 99% and more than 50%, and a maximum electrical conductivity between 30% and 90% of the metal conductivity of a homogeneous with a first approximation of the same material Composition formed metal layer.

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