DE102020135101A1 - DISPLAY DEVICE AND THE SAME MULTI-DISPLAY DEVICE - Google Patents

Abstract

A display device (10) and a multi-display device comprising the same are disclosed. The display device (10) has a first substrate (100) which has a plurality of pixel areas (PA) which are provided in a display area (AA), a second substrate (200) which is connected to the first substrate (100) is coupled, and a wiring portion (400) arranged on an outer surface (OS) of the first substrate (100) and an outer surface (OS) of the second substrate (200), wherein the first substrate (100) is a Dam structure (105) arranged along an edge of the display area (AA), a light emitting device layer (103) comprising a common electrode (CE) and a light emitting device (ED) resting on the dam structure (105) and of the plurality of pixel regions (PA) is arranged, and a laser patterning portion (LPP) which is arranged close to the dam structure (105), and wherein the light emitting device (ED) and the common electrode (CE) by means of the laser -Structurer section (LPP) are isolated.

Description

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority from Korean Patent Application No. 10-2019-0 180 116 , filed on December 31, 2019.

BACKGROUND

Field of invention

The present disclosure relates to a display device and a multi-display device comprising the same.

Discussion of related technology

Recently, with the advance of multimedia, the importance of display devices is increasing. Therefore, display devices such as liquid crystal display (LCD) devices, organic light emitting displays, and light emitting diode displays are being commercialized.

Display devices have good properties such as thinness, lightness and low power consumption, and thus are widely used as a display screen for televisions (TVs), notebook computers and monitors, and portable electronic devices such as electronic notebooks, e-books, portable multimedia Players (PMPs), navigation devices, ultra-mobile personal computers (PCs), cell phones, smartphones, smart watches, tablet personal computers (PCs), watch phones, and mobile communication terminals have been used.

Display devices may have a display panel that has a plurality of pixels, a thin film transistor (TFT) connected to a data line and a gate line, a data drive circuit for supplying a data voltage to the data line and a gate drive circuit for supplying a scanning signal the gate line having. The display panel may have a display area having the plurality of pixels for displaying an image and a border area surrounding the display area.

A related art display device may need a bezel (or mechanism) for covering a border area located at a border (or an edge portion) of a display panel, and due to this, a width of the bezel may increase.

Recently, multi-display devices have been commercialized in which a large screen is implemented by arranging a plurality of display devices as a grid type.

In a related art multi-display device, however, a boundary portion such as a seam is formed between adjacent display devices due to a border area or a bezel of each of a plurality of display devices. The boundary portion gives an impression of interruption (or discontinuity) of an image when an image is displayed on an entire screen of the multi-display device, and therefore the involvement of a viewer viewing the image is reduced.

[Reference to prior art]

[Patent specification]

Korean Patent Registration Number 10-1 441 956 (Title of Invention: Multi-Panel Display Device, Int.CI .: G02F 1/1335, G02F 1/13357)

OVERVIEW

Accordingly, the present disclosure is directed to providing a display device and a multi-display device including the same that substantially obviates one or more problems due to limitations and disadvantages in the related art.

One aspect of the present disclosure is directed to providing a display device in which a bezel is not provided.

Another aspect of the present disclosure is directed to providing a multi-display device for displaying an image without an impression of discontinuity.

Additional advantages and features of the disclosure will be made known in the following description and will in part be apparent to those of ordinary skill in the art from studying the following or may be learned through application of the disclosure. The objectives and other advantages of the disclosure can be realized and achieved by means of the structure particularly emphasized in the written description and the claims resulting therefrom, as well as the attached drawings.

To achieve these and other advantages, and in accordance with the aim of the disclosure as embodied and described in detail herein, a display device according to claim 1 and a display device according to claim 13 are provided. Further embodiments are described in the dependent claims. A display device according to some embodiments includes a first substrate having a plurality of pixel areas provided in a display area, a second substrate coupled to the first substrate, and a wiring portion disposed on an outer surface of the first substrate and a outer surface of the second substrate is arranged on, wherein the first substrate has a dam structure, which is arranged along an edge of the display area, a light emitting device layer having a common electrode and a light emitting device, which on the dam structure and in the plurality of pixel regions and has a laser patterning portion disposed close to the dam structure, and the light emitting device and the common electrode are isolated by means of the laser patterning portion.

A display device according to some embodiments of the present disclosure comprises a first substrate having a plurality of pixel areas provided in a display area, a passivation layer disposed on the display area, a dam structure disposed on the passivation layer along an edge of the Display area, a light emitting device layer comprising a common electrode and a light emitting device disposed on the dam structure and in the plurality of pixel areas, at least one cut line disposed close to the dam structure, and a second substrate, connected to a back surface of the first substrate, wherein the at least one cut line is formed by patterning the light emitting device and the common electrode to be concave.

A multi-display device according to some embodiments of the present disclosure includes a plurality of display modules arranged in at least one direction of a first direction and a second direction crossing the first direction, each of the plurality of display modules having a first substrate having a plurality of pixel areas provided in a display area, a second substrate coupled to the first substrate, and a wiring portion disposed on an outer surface of the first substrate and an outer surface of the second substrate wherein the first substrate comprises a dam structure disposed along an edge of the display area, a light emitting device layer comprising a common electrode and a light emitting device disposed on the dam structure and in the plurality of pixel areas, and a laser Structuring tion portion which is arranged close to the dam structure, and the light emitting device and the common electrode are isolated by means of the laser patterning portion.

A multi-display device according to some embodiments of the present disclosure includes a plurality of display modules arranged in at least one direction of a first direction and a second direction crossing the first direction, each of the plurality of display modules having a first substrate having a plurality of pixel areas provided in a display area, a passivation layer disposed on the display area, a dam structure disposed on the passivation layer along an edge of the display area, a light emitting device layer a common electrode and a light emitting device disposed on the dam structure and in the plurality of pixel areas, at least one cut line disposed close to the dam structure, and a second substrate connected to a back surface of the first substrate wherein the at least one cut line is formed by patterning the light emitting device and the common electrode to be concave.

According to some embodiments of the present disclosure, a display device that does not have a bezel and a multi-display device that includes the display device may be provided.

According to some embodiments of the present disclosure, the display device may have a barrier structure area which is arranged on an edge portion of a display area in such a way that it isolates a light-emitting device, whereby a display device and a multi-display device comprising the display device for preventing the light-emitting device from being exposed via the Penetration of water in a lateral direction is deteriorated, and can be provided to improve the reliability of the light emitting device.

According to some embodiments of the present disclosure, a multi-display device for displaying an image without an impression of discontinuity can be provided.

It is noted that both the foregoing general description and the following detailed description of the present disclosure are exemplary and explanatory and are intended to provide further clarifications of the disclosure as claimed.

Figure list

• 1A und 1 B sind ein Schaubild, das eine Anzeigevorrichtung der vorliegenden Offenbarung darstellt;
• 2A bis 2D sind eine vergrößerte Ansicht eines in 1 dargestellten Bereichs „B1“;
• 3A und 3B sind Schaubilder, die einen Umrandungsbereich einer Anzeigevorrichtung gemäß einem Vergleichsbeispiel und eine Luft-Einfassung einer Anzeigevorrichtung gemäß der vorliegenden Offenbarung darstellen;
• 4 ist eine perspektivische Ansicht, die eine Anzeigevorrichtung gemäß einer Ausführungsform der vorliegenden Offenbarung darstellt.
• 5 ist ein Schaubild, das eine Rückseitenoberfläche einer Anzeigevorrichtung gemäß einer Ausführungsform der vorliegenden Offenbarung darstellt;
• 6 ist eine vergrößerte Ansicht eines in 4 dargestellten Bereichs „B2“;
• 7 ist ein Schaubild, das einen Gate-Ansteuerungsschaltkreis, der in einem in 4 dargestellten Anzeigebereich angeordnet ist, darstellt;
• 8 ist ein Ersatzschaltbild, das ein in 4 und 6 dargestelltes Pixel darstellt;
• 9 ist ein Schaubild, das ein in 5 dargestelltes zweites Substrat darstellt;
• 10 ist eine vergrößerte Ansicht eines in 9 dargestellten Bereichs „B3“;
• 11 ist ein Ersatzschaltbild, das eine in 7 dargestellte i-te Stufen-Schaltkreiseinheit darstellt;
• 12 ist ein Ersatzschaltbild, das einen Knotensteuerschaltkreis, einen ersten Inverterschaltkreis, einen zweiten Inverterschaltkreis und einen ersten Ermittlungssteuerschaltkreis, die jeweils in 11 dargestellt sind, darstellt;
• 13 ist ein Ersatzschaltbild, das einen Knotenrückstellschaltkreis, einen Ausgabepufferschaltkreis und einen zweiten Ermittlungssteuerschaltkreis, die jeweils in 11 dargestellt sind, darstellt;
• 14 ist ein Schaubild zum Beschreiben eines Gate-Ansteuerungsschaltkreises gemäß einer weiteren Ausführungsform der vorliegenden Offenbarung, die in 4 dargestellt ist;
• 15 ist eine Querschnittansicht entlang einer in 4 dargestellten Linie I-I';
• 16 ist eine vergrößerte Ansicht eines in 15 dargestellten Bereichs „B4“;
• 17 ist eine Querschnittansicht entlang einer in 4 dargestellten Linie II-II';
• 18 ist ein Schaubild, das ein in 5 dargestelltes zweites Substrat darstellt;
• 19 ist eine Querschnittansicht entlang einer in 18 dargestellten Linie III-III';
• 20 ist eine Querschnittansicht entlang einer in 6 dargestellten Linie IV-IV';
• 21 ist eine weitere Querschnittansicht entlang einer in 6 dargestellten Linie IV-IV';
• 22 ist eine weitere Querschnittansicht entlang einer in 4 dargestellten Linie II-II';
• 23 ist eine vergrößerte Ansicht eines in 22 dargestellten Bereichs „B5“;
• 24 ist eine weitere Querschnittansicht entlang einer in 4 dargestellten Linie II-II';
• 25 ist eine vergrößerte Ansicht eines in 24 dargestellten Bereichs „B6“;
• 26 ist eine weitere Querschnittansicht entlang einer in 4 dargestellten Linie II-II';
• 27 ist eine vergrößerte Ansicht eines in 26 dargestellten Bereichs „B7“;
• 28 ist eine weitere Querschnittansicht entlang einer in 4 dargestellten Linie II-II';
• 29 ist eine vergrößerte Ansicht eines in 28 dargestellten Bereichs „B8“;
• 30 ist eine Mikroskop-Photographie, die eine Querschnittsoberfläche einer in 29 dargestellten unteren Grabenkonstruktion zeigt;
• 31 ist eine weitere Querschnittansicht entlang einer in 4 dargestellten Linie II-II';
• 32 ist eine vergrößerte Ansicht eines in 31 dargestellten Bereichs „B9“;
• 33A bis 33E sind Schaubilder, die ein Verfahren zum Herstellen einer lichtemittierenden Vorrichtung, einer gemeinsamen Elektrode und einer Verkapselungsschicht, die jeweils in 31 darstellt sind, darstellt;
• 34 ist eine Mikroskop-Photographie der 33B;
• 35 ist ein Schaubild, das eine Rückseitenoberfläche eines in 4 dargestellten zweiten Substrats darstellt;
• 36 ist ein Schaubild, das eine Multi-Anzeigevorrichtung gemäß einer Ausführungsform der vorliegenden Offenbarung darstellt;
• 37 ist ein Schaubild, das einen Kachelungsprozess einer in 36 dargestellten Anzeigevorrichtung darstellt;
• 38 ist eine Querschnittansicht entlang einer in 36 dargestellten Linie V-V';
• 39A und 39B sind Schaubilder, die Bilder darstellen, die jeweils mittels einer Multi-Anzeigevorrichtung gemäß einem Vergleichsbeispiel und einer Multi-Anzeigevorrichtung gemäß der vorliegenden Offenbarung angezeigt werden.

The accompanying drawings, which are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principle of the disclosure. In the drawings:

• 1A and 1 B. FIG. 13 is a diagram illustrating a display device of the present disclosure;
• 2A until 2D are an enlarged view of an in 1 shown area "B1";
• 3A and 3B 12 are diagrams illustrating a border area of a display device according to a comparative example and an air surround of a display device according to the present disclosure;
• 4th FIG. 3 is a perspective view illustrating a display device according to an embodiment of the present disclosure.
• 5 FIG. 12 is a diagram illustrating a back surface of a display device according to an embodiment of the present disclosure;
• 6th FIG. 10 is an enlarged view of a FIG 4th area “B2” shown;
• 7th Fig. 13 is a diagram showing a gate drive circuit included in an in 4th shown display area is arranged;
• 8th is an equivalent circuit diagram showing an in 4th and 6th represents displayed pixel;
• 9 is a graph showing an in 5 illustrated second substrate;
• 10 FIG. 10 is an enlarged view of a FIG 9 shown area "B3";
• 11 is an equivalent circuit diagram that contains an in 7th Fig. 3 shows illustrated i-th stage circuit unit;
• 12th FIG. 13 is an equivalent circuit diagram showing a node control circuit, a first inverter circuit, a second inverter circuit, and a first detection control circuit, respectively, shown in FIG 11 are shown represents;
• 13th FIG. 13 is an equivalent circuit diagram including a node reset circuit, an output buffer circuit, and a second detection control circuit, each shown in FIG 11 are shown represents;
• 14th FIG. 13 is a diagram for describing a gate drive circuit according to another embodiment of the present disclosure shown in FIG 4th is shown;
• 15th FIG. 13 is a cross-sectional view taken along a line in FIG 4th shown line I-I ';
• 16 FIG. 10 is an enlarged view of a FIG 15th shown area "B4";
• 17th FIG. 13 is a cross-sectional view taken along a line in FIG 4th illustrated line II-II ';
• 18th is a graph showing an in 5 illustrated second substrate;
• 19th FIG. 13 is a cross-sectional view taken along a line in FIG 18th illustrated line III-III ';
• 20th FIG. 13 is a cross-sectional view taken along a line in FIG 6th illustrated line IV-IV ';
• 21 FIG. 13 is another cross-sectional view taken along a line in FIG 6th illustrated line IV-IV ';
• 22nd FIG. 13 is another cross-sectional view taken along a line in FIG 4th illustrated line II-II ';
• 23 FIG. 10 is an enlarged view of a FIG 22nd shown area "B5";
• 24 FIG. 13 is another cross-sectional view along a line in FIG 4th illustrated line II-II ';
• 25th FIG. 10 is an enlarged view of a FIG 24 shown area "B6";
• 26th FIG. 13 is another cross-sectional view along a line in FIG 4th illustrated line II-II ';
• 27 FIG. 10 is an enlarged view of a FIG 26th shown area "B7";
• 28 FIG. 13 is another cross-sectional view taken along a line in FIG 4th illustrated line II-II ';
• 29 FIG. 10 is an enlarged view of a FIG 28 shown area "B8";
• 30th Fig. 10 is a microscope photograph showing a cross-sectional surface of an in 29 shows the lower trench structure illustrated;
• 31 FIG. 13 is another cross-sectional view taken along a line in FIG 4th illustrated line II-II ';
• 32 FIG. 10 is an enlarged view of a FIG 31 shown area "B9";
• 33A until 33E are diagrams showing a method of manufacturing a light emitting device, a common electrode and an encapsulation layer, each in 31 represents, represents;
• 34 is a microscope photograph of the 33B ;
• 35 is a diagram showing a back surface of an in 4th illustrated second substrate;
• 36 FIG. 13 is a diagram illustrating a multi-display device according to an embodiment of the present disclosure;
• 37 is a diagram illustrating a tiling process of an in 36 represents the display device shown;
• 38 FIG. 13 is a cross-sectional view taken along a line in FIG 36 line V-V 'shown;
• 39A and 39B 14 are diagrams showing images respectively displayed by a multi-display device according to a comparative example and a multi-display device according to the present disclosure.

DETAILED DESCRIPTION OF THE DISCLOSURE

Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used to identify the same or similar parts in all drawings.

Advantages and features of the present disclosure and its implementation methods are made known by means of the following embodiments, which are described with reference to the accompanying drawings. The present disclosure, however, may be embodied in various forms and should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is only defined by the scope of the claims.

A shape, a size, a ratio, an angle, and a number disclosed in the drawings for describing embodiments of the present disclosure are merely an example, and thus the present disclosure is not limited to these illustrated details. The same reference numbers refer to the same elements throughout. In the following description, the detailed description will be omitted if it is found that the detailed description of the relevant known function or arrangement unnecessarily obscures the important aspect of the present disclosure. In a case where “have”, “have” and “contain” are used in the present application, another part may be added, except when “only ∼” is used. The designation in a singular form can include plural forms, unless the contrary is specified.

When designing an element, the element is designed in such a way that it has a defect area, even if there is no explicit description for it.

When describing a spatial relationship, for example when a spatial relationship between two parts is described as “on”, “over”, “under” and “close to”, one or more further parts can be arranged between two parts except when “exactly” or “directly” is used.

When describing a temporal relationship, for example when the temporal sequence is described as "after ~", "below -", "next ∼" and "before ∼", a case that is not continuous may be included, except when " exactly ”or“ directly ”is used.

It should be noted that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be referred to as a second element and similarly a second element could be referred to as a first element without departing from the scope of the present disclosure.

In describing the elements of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Such terms are only used to distinguish the corresponding elements from other elements, and the gist of the corresponding elements, an order thereof, or a sequence thereof are not limited by the terms. It should be noted that when an element or layer is described as being "on" or "connected to" another element or layer, it may be directly or indirectly connected to the other element or layer, or be inserted Element or an inserted layer can. It should also be noted that when an element is arranged on or under another element, it can denote a case in which the elements are arranged in such a way that they directly contact one another, but can also denote that the elements are arranged, without touching each other directly.

The phrase "at least one" should be understood to include any and all combinations of one or more of the associated listed items. For example, the meaning of “at least one of a first element, a second element and a third element” denotes the combinations of all named elements of two or more of the first element, the second element and the third element, as well as the first element, the second element or the third element.

The term “surround” as used herein includes at least partially surrounding as well as completely surrounding one or more of the attached elements. Similarly, as used herein, the term “covering” includes at least partial covering as well as complete covering of one or more of the ancillary elements. For example, if an encapsulation layer surrounds a dam structure, this can be designed in such a way that the encapsulation layer at least partially surrounds the dam structure. In some embodiments, however, the encapsulation layer can also completely surround the dam structure. The meaning in which the term “surround” is used herein can be further specified based on the accompanying drawings. In the present disclosure, the terms “surrounds”, “surrounds at least partially”, “surrounds completely” or the like are used. Consistent with the definition of “surround” as set forth above, when in one embodiment only the term “surround” is used, it may mean either at least partially surrounded or completely surrounded by one or more of the associated elements. The same applies to the term “cover”.

Features of various embodiments of the present disclosure can be partially or completely connected to one another or combined with one another and can be operated and technically controlled with one another in various ways, as is sufficiently understood by the person skilled in the art. The embodiments of the present disclosure may be carried out independently, or may be carried out together in an interdependent relationship.

In the following, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In adding reference characters to elements of each of the drawings, although the same elements are depicted in other drawings, the same reference characters may indicate similar elements. Also, for convenience of description, a scale of each of the elements shown in the accompanying drawings differs from a true scale and is thus not limited to a scale shown in the drawings.

1A FIG. 13 is a plan view illustrating a display device according to the present disclosure, and FIG 1 B. Figure 13 is a side view illustrating the display device according to the present disclosure. 2A until 2D are enlarged views of an in 1A area "B1" shown.

Referring to 1A and 1 B. For example, the display device according to the present disclosure can include a first substrate 100 have a display area AA and a plurality of pixels P that are in a first interval D1 in the display area AA of the first substrate 100 are arranged, having.

The first substrate 100 can be a first surface 100a , a second surface 100b and have an outer surface OS. The first surface 100a of the first substrate 100 may be defined as a front surface, a top surface, or a top facing a front surface (or a front direction) of the display device. The second surface 100b of the first substrate 100 may be defined as a back surface, a back surface, a bottom surface, or an underside facing a back surface (or a back direction) of the display device. The outer Surface OS of the first substrate 100 may be a side surface, a side surface, or a side wall extending along an outer perimeter between the first surface 100a and the second surface 100b extending opposite the side surface (or the side direction) of the display device and exposed to the ambient air. In some cases, when multiple display devices are connected to one another, the outer surface OS (or the outermost side surface OS) of a display device positioned in the periphery of the connected multiple display devices may be adjacent to ambient air. For example, if the first substrate 100 has a hexahedral structure, the outer surface OS of the first substrate 100 Have side surfaces of the hexahedral structure.

The outer surface OS of the first substrate 100 can be formed parallel to a thickness direction Z of the display device. For example, the outer surface OS of the first substrate 100 a first outer surface that is parallel to a first direction X, a second outer surface that is parallel to the first outer surface, a third outer surface that is parallel to a second direction Y that intersects (or crosses) with the first Direction X, is arranged and which is interposed between one end of the first outer surface and one end of the second outer surface, and a fourth outer surface that is parallel to the third outer surface and between the other end of the first outer surface and the other end of the second outer surface is inserted. The first direction X can be a first longitudinal direction (for example, a widthwise orientation) of the first substrate 100 or the display device, and the second direction Y may be a second length direction (for example, a length direction) of the first substrate 100 or the display device.

The display area AA of the first substrate 100 may be an area that displays an image and may be referred to as a display area or an active area. A size of the display area AA may be the same or substantially the same as that of the first substrate 100 (or the display device). For example, a size of the display area AA can be equal to a total size of the first surface 100a of the first substrate 100 be. Therefore, the display area AA can be on the entire front surface of the first substrate 100 implemented (or arranged), and thus the first substrate 100 does not have an opaque non-display area running along an edge portion of the first surface 100a is provided so that it surrounds the entire display area AA. Accordingly, an entire front surface of the display device can implement the display area AA.

One end (or an outermost portion) AAa of the display area AA can be the outer surface OS of the first substrate 100 overlap or may be substantially aligned with it. For example, a side surface AAa of the display area AA can be substantially coplanar with the outer surface OS of the first substrate 100 be. In other words, the side surface of the display area AA and the outer surface OS of the first substrate 100 be aligned at substantially the same position. The side surface AAa of the display area AA cannot be surrounded by a separate mechanism and can only be surrounded by air. As a further example, the side surface of the display area AA can be the outer surface OS of the first substrate 100 overlap or may be substantially aligned with them. That is, all of the side surfaces of the display area AA can be provided in a structure that directly contacts air without being surrounded by a separate mechanism.

With respect to a thickness direction Z of the first substrate 100 one end AAa of the display area AA and a vertical extension line VL extending vertically from the outer surface OS of the first substrate 100 extend, overlap each other, or may be aligned in substantially the same plane. For example, a first end (or a top end) of the display area AA can be a first outer surface (or a top sidewall) of the first substrate 100 a second end (or a lower end) of the display area AA may be a second outer surface (or a lower sidewall) of the first substrate 100 a third end (or a left end) of the display area AA may be a third outer surface (or a left side wall) of the first substrate 100 and a fourth end (or a right end) of the display area AA may be a fourth outer surface (or a right side wall) of the first substrate 100 be. Therefore, the outer surface OS of the first substrate 100 corresponding to the end AAa of the display area AA may be surrounded by air, and thus the display device according to the present disclosure may be an air-enclosing structure or a non-enclosing structure in which the end AAa of the display area AA (or the side surface of the display area AA ) is surrounded by air instead of an opaque non-display area.

The display area (or the display section) AA according to an embodiment may have a plurality of pixel areas PA.

The plurality of pixel areas PA according to an embodiment can be in the first interval D1 in the display area AA of the first substrate 100 set up (or arranged). Two pixel areas PA, which are in the first direction X and the second direction Y of the first substrate 100 are adjacent to each other can have the same first interval D1 without a defect area of a manufacturing process. The first interval D1 may be a distance (or a pixel pitch) between two adjacent pixel areas PA. For example, the first interval D1 a shortest distance (or length) between central sections of two adjacent ones Be pixel areas PA. Optionally, the pixel spacing can be a size between one end and the other end of a pixel area PA parallel to the first direction X. Likewise, as a further example, the pixel spacing can be referred to as a size between one end and the other end of a pixel area PA parallel to the second direction Y.

Each of the plurality of pixel areas PA may have a first length L1 parallel to the first direction X and a second length L2 have parallel to the second direction Y. Both the first length L1 as well as the second length L2 can be equal to the first interval D1 be. For example, the first length L1 may be referred to as a first width, a broadside length or a broadside width. The second length L2 can be referred to as a second width, a long side length, or a long side width. The first length L1 or the second length L2 of the pixel area PA can be referred to as a pixel pitch.

A second interval D2 between each of outermost pixel areas PAo of the plurality of pixel areas PA and the outer surface OS of the first substrate 100 can be half of the first interval D1 or less, so that the entire front surface of the first substrate 100 (or the entire front surface of the display device) is referred to as a display area AA. For example, the second interval D2 a shortest distance (or shortest length) between a central portion of the outermost pixel region PAo and the outer surface OS of the first substrate 100 be.

If the second interval D2 is greater than one half of the first interval D1 , can be the first substrate 100 one around an area between an end of the outermost pixel area PAo (or the end AAa of the display area AA) and the outer surface OS of the first substrate 100 larger in size than that of the display area AA, and thus an area between the end of the outermost pixel area PAo and the outer surface OS of the first substrate 100 as a non-display area surrounding the entire display area AA. Therefore, the first substrate 100 necessarily have a border area based on a non-display area surrounding the entire display area AA. On the other hand, if the second interval D2 half or less of the first interval D1 the end of the outermost pixel area PAo (or the end AAa of the display area AA) is the outer surface OS of the first substrate 100 overlap or may be in a space outside the outer surface OS of the first substrate 100 may be arranged, and thus the display area AA can be on the entire front surface of the first substrate 100 implemented (or arranged).

The display area (or display section) AA according to an embodiment may include the outermost pixel area PAo and an internal pixel area (or an inner pixel area PAi).

The outermost pixel area PAo may be along an edge portion (or a peripheral portion) of the first substrate 100 be arranged from the plurality of pixel areas PA. For example, the outermost pixel area PAo can be referred to as a first pixel area PA1.

The internal pixel area PAi can be a different pixel area than the outermost pixel area PAo out of the plurality of pixel areas PA or can be surrounded by the outermost pixel area PAo. The internal pixel area PAi can be referred to as a second pixel area PA2.

Each of the plurality of pixels P may be in a corresponding one of the plurality of pixel areas PA on the first surface 100a of the first substrate 100 are defined, be arranged. For example, the display area AA can be a pixel matrix that has the plurality of pixels P that are on the first substrate 100 are arranged, having. The pixels P of the pixel matrix can directly adjoin one another in the first direction X and the second direction Y. For example, the pixels P of the pixel matrix in the first direction X and the second direction Y can be arranged directly adjacent to one another without a separating space (or a gap). As a further example, a plurality of outermost pixels Po of the pixel matrix may coincide in such a way that they correspond to one another on the outer surface of the first substrate 100 overlap or can be aligned on the same plane. For example, each pixel P of the pixel matrix can be in this way on the first substrate 100 be arranged so that there is a pixel pitch D1 in the first direction X and the second direction Y, and an interval D2 between a central portion of each of the outermost pixels Po and the outer surface OS of the first substrate 100 can be half or less of the pixel pitch D1 be.

The display area (or display section) AA according to an embodiment may have an outermost pixel Po and an internal pixel (or an inner pixel) Pi.

The outermost pixel Po may be on the edge portion (or a peripheral portion) of the first substrate 100 be arranged below the plurality of pixel areas PA. For example, this can outermost pixel Po as a first pixel P1 arranged in the outermost pixel area PAo.

The internal pixel Pi may be a different pixel from the outermost pixel Po out of the plurality of pixels P or may be arranged such that it is surrounded by the outermost pixel Po. For example, the internal pixel Pi can be used as a second pixel P2 are designated. The internal pixel Pi (or the second pixel P2 ) may be made to have a configuration or structure different from the outermost pixel Po (or the first pixel P1 ).

The second interval D2 between each of the outermost pixel Po of the plurality of pixels P and the outer surface OS of the first substrate 100 can be half or less of the first interval D1 so that the entire front surface of the first substrate 100 (or the entire front surface of the display device) is designated as a display area AA. The first interval D1 may be a shortest distance (or shortest length) between central portions of two neighboring pixels P. The second interval D2 may be a shortest distance (or shortest length) between a central portion of the outermost pixel Po and the outer surface OS of the first substrate 100 be.

Each of the plurality of pixels P according to an embodiment may, as in FIG 2A shown, have a central portion Pc having a plurality of emission regions PA, and an edge portion (or a peripheral portion) Pe surrounding the entire central portion Pc.

A center of the central portion Pc may overlap a central portion of the pixel P. The central portion Pc may be referred to as an opening area or a light emitting portion of the pixel P.

The central section Pc according to an embodiment can have a first emission area EA1 to fourth emission area EA4, which are arranged with respect to the central section of the pixel P. For example, the first emission area EA1 to fourth emission area EA4 can be arranged directly adjacent to one another in the first direction X and the second direction Y. For example, the first emission area EA1 to fourth emission area EA4 can directly contact each other in the first direction X and the second direction Y without a separating space (or a gap).

The first emission area EA1 to fourth emission area EA4 can each have a square shape and can be arranged in a 2 × 2 shape or a square shape. According to another embodiment, the first emission area EA1 to fourth emission area EA4 can each have a rectangular shape, which has a short side parallel to the first direction X and a long side parallel to the second direction Y, and can for example be in a 1x4 shape or be arranged in a 1 x4 strip shape.

The first emission region EA1 can be implemented such that it emits light of a first color, the second emission region EA2 can be implemented such that it emits light of a second color, the third emission region EA3 can be implemented such that it emits light of a third color , and the fourth emission region EA4 may be implemented to emit light of a fourth color. For example, all of the first color through the fourth color can be different. For example, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another example, some of the first color through fourth color may be the same. For example, the first color can be red, the second color can be a first green, the third color can be a second green, and the fourth color can be blue.

According to a further embodiment, as in 2 B shown, the central section Pc a first emission area EA1 to third emission area EA3, which are arranged with respect to the central section of the pixel P, have. In this case, the first emission area EA1 to third emission area EA3 may each have a rectangular shape having a short side parallel to the first direction X and a long side parallel to the second direction Y, and may, for example, be in a 1 × 3 shape or be arranged in a 1 × 3 strip shape. For example, the first color can be red, the second color can be blue, and the third color can be green.

The edge portion Pe may be arranged in the pixel region PA so as to surround the entire central portion Pc, and thus may define the central portion Pc of the pixel region PA or the pixel P. The edge portion Pe may have a size larger than the central portion Pc. The edge portion Pe may be referred to as a non-opening portion, a non-emission portion, or a pixel separating portion of the pixel P. As shown in FIG.

Referring again to 2A According to a further embodiment, each of a plurality of pixels P can have a first subpixel SP1 to a fourth subpixel SP4.

The first subpixel SP1 can be arranged in a first subpixel area of the pixel area PA, the second subpixel SP2 can be arranged in a second subpixel area of the pixel area PA, the third subpixel SP3 can be arranged in a third subpixel area of the pixel area PA, and the fourth subpixel SP4 can be arranged in a fourth sub-pixel area of the pixel area PA. For example, with respect to the central section of the pixel P, the first subpixel SP1 can be a left upper area of the pixel area PA, the second subpixel SP2 can be a right upper area of the pixel area PA, the third subpixel SP3 can be a left lower area of the Be pixel area PA, and the fourth sub-pixel SP4 can be a right lower area of the pixel area PA.

The first subpixel SP1 to fourth subpixel SP4 can each have a plurality of emission areas EA1 to EA4 and a plurality of circuit areas CA1 to CA4.

The emission regions EA1 to EA4 may be arranged on the central portion Pc of the pixel P or may be arranged close to the central portion of the pixel P. FIG.

Each of the circuit areas CA1 to CA4 may be arranged close to a corresponding one of the emission areas EA1 to EA4. Each of the circuit areas CA1 to CA4 may include a signal line, a power line, and a circuit that allows a corresponding sub-pixel to emit light.

The emission areas EA1 to EA4 of the first subpixel SP1 to fourth subpixels SP4 according to one embodiment can have the same size in a corresponding pixel P or pixel area PA. For example, the emission regions EA1 to EA4 of the first subpixel SP1 to fourth subpixels SP4 can have a uniform square structure or a non-uniform stripe structure. For example, the emission regions EA1 to EA4 of the first subpixel SP1 to fourth subpixels SP4 can be designed in such a way that they have the same size around (or close to) the central section of the pixel P.

According to a further embodiment, as in 2C shown, each of the emission areas EA1 to EA4 of each of the first subpixel SP1 to fourth subpixel SP4 in a corresponding pixel P or pixel area PA have different sizes. For example, the emission regions EA1 to EA4 of the first subpixel SP1 to the fourth subpixel SP4 can have a non-uniform square structure or a non-uniform strip structure. For example, the emission regions EA1 to EA4 of the first subpixel SP1 to fourth subpixels SP4 can be designed in such a way that they have different sizes around (or close to) the central section of the pixel P.

A size of each of the emission areas EA1 to EA4 of each of the first sub-pixel SP1 to fourth sub-pixel SP4 having a non-uniform square structure (or a non-uniform stripe structure) may be set based on a resolution, an emission yield, or an image quality being. For example, if the emission areas EA1 to EA4 have a non-uniform square structure (or a non-uniform stripe structure), in the emission areas EA1 to EA4 of the first subpixel SP1 to fourth subpixels SP4, the emission area EA4 of a green subpixel SP4 can have a smallest size , and the emission area EA3 of a white sub-pixel SP3 can have a largest size.

In the first subpixel SP1 to fourth subpixel SP4 according to another embodiment, each of the emission regions EA1 to EA4 may be arranged at a distance from one another in the first direction X and the second direction Y, but are not limited to this and may be immediately adjacent to one another.

Alternatively, as in 2D shown in order to increase an aperture ratio of the subpixels SP1 to SP4 in accordance with sizes of the emission regions EA1 to EA4 or the pixel pitch D1 Since a resolution of the pixel P is larger, the emission areas EA1 to EA4 of the first sub-pixel SP1 to fourth sub-pixel SP4 extend to the circuit areas CA1 to CA4 so as to overlap some or all of the circuit areas CA1 to CA4. For example, each of the emission regions EA1 to EA4 of the first subpixel SP1 to fourth subpixels SP4 can be on the first substrate in this way 100 be designed to overlap a corresponding circuit area of the circuit areas CA1 to CA4. In this case, the emission areas EA1 to EA4 may have a size equal to or larger than that of the circuit areas C1 to CA4.

Again referring to 1A until 2D The display device according to the present disclosure may further include a pad area 110 having a plurality of pads arranged in the display area AA and are selectively connected to the plurality of pixels P. For example, the pad area 110 be a first pad area or a front pad area.

The pad area 110 may be in the outermost pixels Po on a first edge portion of the first surface 100a of the first substrate 100 are arranged parallel to the first direction X, be included. This means that the outermost pixels Po, which are on the first edge portion of the first substrate 100 are arranged, may have at least one of the plurality of pads. Therefore, the plurality of pads may be arranged or contained within the display area AA, and thus a non-display area (or a border area) based on the pad area 110 may or may not be formed on the first substrate 100 be. Therefore, the outermost pixel Po (or the first pixel P1 ) the pad area 110 and can thus be embodied in such a way that it has a configuration or a structure that differs from the internal pixel Pi (or the second pixel P2 ) that has no pad area 110 has, differs.

For example, if the pad area 110 is not provided inside the outermost pixels Po and between the outermost pixels Po and the outer surface OS of the first substrate 100 is arranged, the first substrate 100 a non-display area (or a non-display portion) corresponding to an area in which the pad area 110 is provided, and due to the non-display area, the second interval D2 between the outermost pixels Po and the outer surface OS of the first substrate 100 be greater than half of the first interval D1 , the entire first substrate 100 may not be embodied as the display area AA, and a separate bezel (or structure) to cover the non-display area may be required. On the other hand, the pad area 110 according to the present disclosure between the emission regions EA1 to EA4 of the outermost pixels Po and the outer surface OS of the first substrate 100 and may be included within the outermost pixels Po, and thus a non-display area (or a border area) based on the pad area 110 may not be formed between the outermost pixels Po and the outer surface OS of the first substrate 100 lie.

Therefore, the display device according to the present disclosure can have an air-fringing structure in which an entire first substrate 100 that is the pad area 110 is embodied as the display area AA, and thus all of the outer surfaces (or outer surfaces of the display panel) are OS of the first substrate 100 aligned with one end of the display area AA, surrounded by air.

3A and 3B 12 are diagrams illustrating a border area of a display device according to a comparative example and an air surround of a display device according to the present disclosure.

Referring to 3A In the display device according to the comparative example, it can be seen that the display device has a border area (or a non-display area) BA surrounding an entire display area AA representing an image, and thus a black border area BA which is provided by means of the Display area AA surrounds the image shown. In a multi-display device in which a plurality of display devices according to the comparative example are arranged as a grid type, an impression of interruption (or discontinuity) of an image occurs in a boundary portion between adjacent display devices due to the border area BA of each of the display devices .

As in 3B In the display device according to the present disclosure, it can be seen that the display device does not have a border area (or a non-display area) surrounding an entire display area AA representing an image and has an air border structure in which the display area AA is surrounded by air, and thus there is no border surrounding the image displayed by means of the display area AA. For example, the outer surface of the first substrate 100 be exposed on the outside of the display device or can be surrounded by air, and the display area AA, which is designed such that it is from the first substrate 100 is superimposed, can be arranged such that the lateral surface (or the end) AA a of the display area AA substantially the outer surface OS of the first substrate 100 is equivalent to. As a further example, the side surface (or the end) AAa of the display area AA and the outer surface OS of the first substrate 100 be arranged substantially in correspondence with one another and aligned on the same plane, be directly exposed on the outside of the display device and be directly surrounded by air. In a multi-display device in which a plurality of display devices according to the present disclosure are arranged as a grid type, since no border area is provided in each of the display devices, an impression of discontinuity (or interruption) of an image occurs in a boundary portion between adjacent display devices.

4th Fig. 13 is a perspective view showing a display device 10 according to an embodiment of the present disclosure, and 5 Fig. 13 is a diagram showing a back surface of the display device 10 according to an embodiment of the present disclosure.

Referring to 4th and 5 can the display device 10 according to an embodiment of the present disclosure, a first substrate 100 , a second substrate 200 , a coupling element 300 and a wiring section 400 exhibit.

The first substrate 100 may be referred to as a display substrate, a pixel array substrate, a top substrate, a front substrate, or a base substrate. The first substrate 100 may comprise a glass material or a plastic material. The first substrate 100 may be a glass substrate, or it may be a thin glass substrate or a plastic substrate that is bendable or flexible. The first substrate 100 According to one embodiment, it can be a glass substrate or coated glass. For example, the tempered glass may include one of sapphire glass and gorilla glass or a glass stacked therefrom.

The display device 10 According to one embodiment, a plurality of pixel drive lines and a plurality of pixels P may be formed on the first substrate 100 are arranged, have.

The pixel drive lines can be on a first surface 100a of the first substrate 100 may be provided and a signal required for driving (emitting light) each of the plurality of pixels P can be transmitted. For example, the pixel drive line can be a data line DL , a gate line GL , a pixel drive power line (or a first power line) PL and a pixel shared power line (or a second power line) CPL exhibit. In addition, the pixel drive line can also be a reference current line (or a detection line) RL , based on a control (or an operation) of a pixel circuit arranged in a circuit area of the pixel P.

Each of the pixel drive lines according to an embodiment can be electrically connected to a first pad area 110 on a first edge portion of the first surface 100a of the first substrate 100 is arranged to be connected. The first pad area 110 may be in a plurality of outermost pixels Po located on the first edge portion of the first substrate 100 are arranged parallel to a first direction X, be included. Here, the first edge section of the first surface 100a of the first substrate 100 a first outer surface (or a side surface) OS1a of an outer surface OS of the first substrate 100 exhibit.

The first pad area 110 may have a plurality of first pads that are parallel to one another in the first direction X on a passivation layer 101d (please refer 16 ) on the first edge portion of the first surface 100a of the first substrate 100 is exposed, are arranged.

The plurality of first pads according to an embodiment may be divided (or classified) into a plurality of first data pads, a plurality of first pixel drive current pads, and a plurality of first pixel common current pads. Therefore, the first pad area 110 a first data pad area having the plurality of first data pads connected to a plurality of data lines DL a first pixel drive current pad area including the plurality of first pixel drive current pads connected to the plurality of pixel drive current lines PL, and a first pixel common current pad area including the plurality of first pixel common power pads connected to the plurality of pixel common power lines CPL. Optionally, the first pad area 110 furthermore have a first reference current pad region which has a plurality of first reference current pads which are connected to a plurality of reference current lines RVL.

The plurality of pixels P may each be in a plurality of pixel areas PA which are arranged at a first interval (or a first distance) D1 in the first direction X and a second direction Y. Each of the plurality of pixels P may be a self-light-emitting device (or a self-light-emitting element) that emits light on the basis of a top emission type based on a signal supplied through a corresponding pixel drive line adjacent thereto the light on a section above the first surface 100a of the first substrate 100 emits, and a pixel circuit which is connected to pixel drive lines adjacent thereto in such a way that the self-light-emitting device can emit light. For example, the pixel circuit can have a drive thin-film transistor (TFT) which, at the self-light-emitting device, generates a data stream that is transmitted to one through the data line DL supplied data signal, provides.

A distance between an outermost pixel of the plurality of pixels P and the outer surface OS of the first substrate 100 can be half or less of the first interval D1 be. A second interval D2 between a central portion of the outermost pixel and the outer surface OS of the first substrate 100 can be half or less of the first interval D1 and thus an entire front surface of the first substrate can be 100 (or an entire front surface of the display device) can be implemented as the display area AA. Accordingly, the display device 10 according to the present disclosure, have an air border structure in which the display area AA is surrounded by air.

The first substrate 100 can furthermore have a first inclined edge which is located in a corner section between the first substrate 100a and the outer surface OS is provided. The first bevel can damage the corner portion of the first substrate 100 caused by physical impact exerted from the outside, and can minimize disruption of the wiring section 400 by means of the corner portion of the first substrate 100 is caused, prevent. For example, the first inclined edge can have a 45 ° angle, but is not limited to this. The first bevel edge can be implemented by means of a beveling process using a cutting wheel or a polishing wheel. Accordingly, each of outer surfaces of the first pads of the first pad area can be 110 arranged to contact the first bevel, an inclined surface inclined at an angle corresponding to an angle of the first bevel by removing or polishing a corresponding portion thereof together with the corner portion of the first substrate 100 is inclined by the beveling process. For example, if the first beveled edge is at an angle of 45 ° between the outer surface OS and the first surface 100a of the first substrate 100 is formed, outer surfaces of the first pads can be formed at an angle of 45 °.

The first substrate 100 may further include a gate drive circuit 150 , which is arranged in the display area AA.

The gate drive circuit 150 can be arranged in the display area AA such that it corresponds to the pixels P which are on the first substrate 100 are arranged to supply a sampling signal (or a gate signal). The gate drive circuit 150 pixels P, which are arranged in a horizontal line parallel to the first direction X, can simultaneously carry the scanning signal. For example, the gate drive circuit 150 To pixels P, which are arranged in a horizontal line, supply at least one scanning signal through at least one gate line GL.

The gate drive circuit 150 According to one embodiment, having a shift register that has a plurality of stage circuit units 1501 until 150m (where m is an integer of 2 or more). This means that the display device according to the present disclosure can have a shift register which is arranged in the display area AA of the first substrate in such a way that it supplies the scanning signal to the pixel P.

Each of the plurality of stage circuit units 1501 until 150m can have a plurality of branch circuits 1511 until 151n (where n is an integer of 2 or greater) in each horizontal line of the first substrate 100 are arranged at a distance from each other in the first direction X. The majority of branch circuits 1511 until 151n may have at least one TFT (or a branch TFT) and may be arranged between two adjacent pixels P (or pixel areas PA) in a horizontal line along the first X direction. For example, the branch circuits 1511 until 151n be arranged individually between two adjacent pixels P (or pixel areas PA) within a horizontal line along the first direction X. Each of the plurality of stage circuit units 1501 until 150m may be in response to a gate control signal passed through the first pad area 110 is supplied, generate the scanning signal in a predetermined order and can supply the scanning signal to the gate line GL. For example, the gate control signal can have a start signal, a plurality of shift clocks, at least one gate drive current and at least one gate common current.

The first substrate 100 may further comprise a plurality of gate control line groups GCL, which are arranged at a distance from each other or individually between the plurality of pixels P, and to the gate drive circuit 150 are connected. Each of the gate control line groups GCL can be selectively connected to the plurality of branch circuits 1511 until 151 n, each in the plurality of stage circuit units 1501 until 150m are arranged to be connected. For example, the plurality of gate control line groups GCL can be distributed between the plurality of pixels P.

The gate control line group GCL according to an embodiment may have a start signal line, a plurality of shift clock lines, comprise at least one gate drive power line and at least one gate common power line. The plurality of shift clock lines according to an embodiment may be divided (or classified) into a plurality of scan clock lines and a plurality of carrier clock lines. Here, the plurality of carrier clock lines can be omitted.

The first pad area 110 may further include a first gate pad region having a plurality of first gate pads connected to the gate control line group GCL.

A plurality of first gate pads according to an embodiment can be in a first start signal pad connected to the start signal line, a plurality of first shift clock pads each connected to the plurality of shift clock lines, at least one first gate drive current pad connected to at least one Gate drive power line is connected, and at least one first gate common power pad connected to at least one gate common power line can be divided (classified). Therefore, the first gate pad area may include a first start signal pad, a plurality of first shift clock pads, at least one first gate drive current pad, and at least one first gate common current pad. The plurality of first shift clock pads according to an embodiment may include a plurality of first scan clock pads each connected to the plurality of scan clock lines and a plurality of first carrier clock line pads each connected to the plurality of carrier clock lines. Here, the plurality of first carrier clock pads can be omitted.

The second substrate 200 can be referred to as a wiring substrate, an interconnection substrate, a lower substrate, a back substrate, or interconnection glass. The second substrate 200 may comprise a glass material or a plastic material. The second substrate 200 can be a glass material or can be a thin glass substrate or plastic substrate that is bendable or flexible. The second substrate 200 According to one embodiment, the same material as that of the first substrate can be used 100 exhibit. For example, a size of the second substrate 200 be the same or substantially the same as that of the first substrate 100 .

The second substrate 200 can using the coupling element 300 with a second surface 100b of the first substrate 100 be paired (or connected). The second substrate 200 may have a front surface that of the second surface 100b of the first substrate 100 opposite or with the coupling element 300 is coupled, a back surface (or a back surface) 200b facing the front surface and an outer surface OS between the front surface and the back surface. The second substrate 200 can transmit a signal to the pixel drive lines and can increase the rigidity of the first substrate 100 raise.

The display device 10 According to one embodiment, a second pad area can also be used 210 that is on the second substrate 200 is arranged have.

The second pad area 210 may at a first edge portion of a back surface 200b of the second substrate 200 be arranged, the first pad area 110 that is on the first substrate 100 is arranged, overlaps. The first edge portion of the back surface 200b of the second substrate 200 may be a first outer surface (or a surface) OS1b of the outer surface OS of the second substrate 200 exhibit.

The second pad area 210 may have a plurality of second pads which are arranged at a certain distance in the first direction X such that they are each the pads of the first pad area 110 overlap.

The plurality of second pads according to an embodiment may be divided (or classified) into a plurality of second data pads, a plurality of second pixel drive current pads, and a plurality of second pixel common current pads. Therefore, the second pad area 210 a second data pad area including the plurality of second data pads, a second gate pad area including the plurality of second gate pads, a second pixel drive current pad area including the plurality of second pixel drive current pads, and a second pixel -Common power pad area having the plurality of second pixel common power pads. Optionally, the second pad area 210 furthermore have a second reference current pad region which has a plurality of second reference current pads.

A plurality of second gate pads according to an embodiment can be in a second start signal pad, a plurality of second shift clock pads, at least one second gate drive current pad and at least one second gate common current pad be subdivided (classified). Therefore, the second gate pad area may include a second start signal pad, a plurality of second shift clock pads, at least one second gate drive current pad, and at least one second gate common current pad. The plurality of second shift clock pads according to an embodiment may be divided (classified) into a plurality of second scan clock pads and a plurality of second carrier clock pads. The plurality of second carrier clock pads can be omitted here.

The display device 10 According to one embodiment, a third pad area (or an input pad area) 230 and a connecting line section can furthermore be provided 250 that are on the second substrate 200 are arranged, have.

The third pad area 230 can on the back surface 200b of the second substrate 200 be arranged. For example, the third pad area 230 in a central portion adjacent to a first edge portion from the back surface 200b of the second substrate 200 be arranged. The third pad area 230 according to one embodiment, a plurality of third pads (or input pads) which are arranged separated from one another at a certain distance.

The connecting line section 250 can be between the second pad area 210 and the third pad area 230 on the back surface 200b of the second substrate 200 be arranged. For example, the connecting line section 250 a plurality of connecting lines which individually (or in each case) the second pads of the second pad area 210 with the third pads of the third pad area 230 connect, exhibit.

The second substrate 200 may further include a second bevel formed in a corner portion between the rear surface 200b and the outer surface OS is provided. The second bevel can damage the corner portion of the second substrate 200 that is caused by a physical impact exerted from the outside, and can minimize one by means of the corner portion of the second substrate 200 caused interruption of the wiring section 400 prevent. For example, the second inclined edge can have a 45 ° angle, but is not limited to this.

The coupling element 300 can between the first substrate 100 and the second substrate 200 be arranged. The first substrate 100 and the second substrate 200 can by means of the coupling element 300 be mutually bonded to each other. For example, the second surface 100b of the first substrate 100 with a surface of the coupling element 300 be coupled, and the front surface of the second substrate 200 can with the other surface of the coupling element 300 be coupled. Accordingly, the first substrate 100 and the second substrate 200 that by means of the coupling element 300 are reciprocally bonded (or coupled) together, may be referred to as a display panel.

The wiring section 400 can be arranged such that it has the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200 surrounds. The wiring section 400 According to an embodiment, a plurality of wiring lines may be formed on each of the first outer surface (or a surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or a surface) OS1b of the outer surface OS of the second substrate 200 are arranged, have. Each of the plurality of wiring lines may be formed to be each of the first outer surface OS1a of the first substrate 100a and the first outer surface OS1b of the second substrate 200 surrounds. For example, the plurality of wiring lines can each (or individually) be connected to the pixel drive lines that are on the first substrate 100 are arranged, and can be connected directly to the pixel drive lines. As another example, the plurality of wiring lines may each (or individually) pass through the pad of the first pad area 110 that is on the first substrate 100 is connected to the pixel drive lines, and in this case, a resistance of each of the pixel drive lines and / or the voltage drop (or IR drop) of a signal applied to the pixel drive lines due to an increase in size based on a Pad be reduced.

The plurality of wiring lines according to an embodiment may be classified into a plurality of data wiring lines, a plurality of gate wiring lines, a plurality of pixel drive power wiring lines, and a plurality of pixel common power wiring lines.

According to a further embodiment, the wiring section 400 a data wiring section, a gate wiring section, a pixel driving power wiring section, and a pixel common power wiring section.

The data wiring section (or a first wiring section) may be the first data pad area of the first pad area 110 electric with a second data pad area of the second pad area 210 associate. The data wiring section according to an embodiment may have a plurality of data wiring lines 410 exhibit. The plurality of data wiring lines (or a first wiring line) 410 may include the plurality of first data pads in the first pad area 110 are arranged, with the plurality of second data pads in the second pad area 210 are arranged, individually (or each) connect.

The gate wiring section (or a second wiring section) may be the first gate pad area of the first pad area 110 electrically to the second gate pad area of the second pad area 210 associate. The gate wiring section according to an embodiment may include a plurality of gate wiring lines 430 exhibit. The plurality of gate wiring lines (or a second wiring line) 430 may include the plurality of first gate pads located in the first pad area 110 are arranged with the plurality of second gate pads in the second pad area 210 are arranged, individually (or each) connect.

The plurality of gate wiring lines 430 according to an embodiment may be classified into a start signal wiring line, a plurality of shift clock wiring lines, at least one gate drive current wiring line, and at least one gate common current wiring line. Therefore, the gate wiring section may include a start signal wiring line, a plurality of shift clock wiring lines, at least one gate drive power wiring line, and at least one gate common power wiring line. The plurality of shift clock wiring lines according to an embodiment may be divided (classified) into a plurality of sampling clock wiring lines and a plurality of carrier clock wiring lines. Here, the plurality of carrier clock wiring lines can be omitted.

The start signal wiring line may have a first start signal pad located in the first pad area 110 is arranged, electrically with a second start signal pad, which is in the second pad area 210 is arranged to connect.

The plurality of shift clock wiring lines may include the plurality of first shift clock pads located in the first pad area 110 are arranged, with the plurality of second shift clock pads in the second pad area 210 are arranged, individually (or each) connect.

The plurality of scan clock wiring lines of the plurality of shift clock wiring lines according to an embodiment may include the plurality of first scan clock pads located in the first pad area 110 are arranged with the plurality of second sampling clock pads located in the second pad area 210 are arranged, individually (or each) connect.

The plurality of carrier clock wiring lines from the plurality of shift clock wiring lines according to an embodiment may include the plurality of first carrier clock pads located in the first pad area 110 are arranged, with the plurality of second carrier clock pads in the second pad area 210 are arranged, individually (or each) connect.

The at least one gate drive current wiring line may include the at least one first gate drive current pad located in the first pad region 110 is arranged electrically to the at least one second gate drive current pad that is in the second pad region 210 is arranged to connect.

The at least one gate common power wiring line may be the at least one first gate common power pad located in the first pad region 110 is arranged electrically with the at least one second gate common current pad that is in the second pad area 210 is arranged to connect.

The pixel drive current wiring section (or a third wiring section) may be the first pixel drive current pad area of the first pad area 110 electrically to the second pixel drive current pad area of the second pad area 210 associate. The pixel drive current wiring section according to an embodiment may include a plurality of pixel drive current wiring lines 450 exhibit. The plurality of pixel drive current wiring lines (or a third wiring line) 450 may include the plurality of first pixel drive current pads located in the first pad area 110 are arranged with the plurality of second pixel drive current pads located in the second pad area 210 are arranged, individually (or each) connect.

The pixel-common power wiring section (or a fourth wiring section) may be the first pixel-common power pad area of the first pad area 110 electrically to the second pixel common power pad area of the second pad area 210 associate. The pixel common power wiring section according to an embodiment may be a plurality of pixel-common-electricity wiring lines 470 exhibit. The plurality of pixel common power wiring lines (or a fourth wiring line) 420 may include the plurality of first pixel common power pads located in the first pad area 110 are arranged with the plurality of second pixel-common-current pads located in the second pad area 210 are arranged, individually (or each) connect.

The wiring section 400 according to an embodiment may further comprise a reference current wiring section.

The reference current wiring section (or a fifth wiring section) may be the first reference current pad area of the first pad area 110 electrically to the second reference current pad area of the second pad area 210 associate. The reference current wiring section according to an embodiment may have a plurality of reference current wiring lines 490 exhibit. The plurality of reference current wiring lines (or a fifth wiring line) 490 the plurality of first reference current pads located in the first pad area 110 are arranged, with the plurality of second reference current pads in the second pad area 210 are arranged, individually (or each) connect.

The display device 10 According to an embodiment of the present disclosure, a drive circuit unit may furthermore 500 exhibit.

The drive circuit unit 500 can be the pixels P that are on the first substrate 100 are arranged, based on digital video data and a timing synchronization signal supplied from a display drive system, drive (or emit light) so that the display area AA can display an image corresponding to image data. The drive circuit unit 500 can with the third pad area 230 that is on the back surface 200b of the second substrate 200 is arranged, connected and can be used to drive (or emit light) the on the first substrate 100 arranged pixel P a data signal, a gate control signal and a drive current to the third pad area 230 output. For example, the control circuit unit 500 have a size smaller than that of the second substrate 200 and can by means of the second substrate 200 be covered and can thus be on the outer surface of the second substrate 200 or the outer surface of the first substrate 100 not be exposed.

The drive circuit unit 500 according to one embodiment, a flexible circuit film 510 , a driver integrated circuit (IC) 530 , a printed circuit board (PCB) 550 and a timing controller 570 exhibit.

The flexible circuit film 510 can with the third pad area 230 that is on the back surface 200b of the second substrate 200 is arranged to be connected. The flexible circuit film 510 According to one embodiment, it can be an adhesive tape carrier unit (TCP) or a chip-on-film (COF). For example, an edge portion (or an outer bonding portion) of the flexible circuit film can be used 510 by a film attaching process using an anisotropic conductive film on the third pad area 230 that is on the second substrate 200 is arranged to be attached. The other edge portion (or an input bonding portion) of the flexible circuit film 510 can be through a film attaching process using an anisotropic conductive film to the PCB 550 be attached.

The control IC 530 can on the flexible circuit film 510 to be appropriate. The control IC 530 can be subpixel data and a data control signal from the timing controller 570 are provided, received and convert the subpixel data on the basis of the data control signal into an analog data signal for supplying the analog data signal to a corresponding data line DL. For example, the control IC 530 be a data drive IC or a source drive IC.

The control IC 530 According to one embodiment, using a plurality of reference gamma voltages obtained from the PCB 550 are provided, generate a plurality of gray level voltages and select a gray level voltage corresponding to the subpixel data from the plurality of gray level voltages for outputting a data signal. The data signal can be provided through an output bonding portion of the flexible circuit film 510 , the third pad area 230 , the connecting line section 250 , the second pad area 210 , the wiring section 400 and the first pad area 110 a corresponding data line DL are supplied.

Furthermore, the control IC 530 generate and output a pixel drive current and a pixel common current necessary for driving (or emitting light) the pixels P using reference gamma voltages. For example, the control IC 530 as the pixel drive current and the pixel common current, a predetermined reference gamma voltage or a predetermined gray level voltage of the plurality of reference gamma voltages or one Select and output a plurality of grayscale voltages.

In addition, the control IC 530 on the basis of the driving (or operation) of a pixel circuit which is arranged in the circuit region of the pixel P, additionally generate and output a reference current. For example, the control IC 530 select and output a predetermined reference gamma voltage or a predetermined gray level voltage from the plurality of reference gamma voltages or the plurality of gray level voltages as a reference voltage.

The pixel drive current, the pixel common current and the reference current can have different voltage levels. The pixel drive current, the pixel common current and the reference current can be supplied through an output bonding portion of the flexible circuit film 510 , the third pad area 230 , the connecting line section 250 , the second pad area 210 , the wiring section 400 and the first pad area 110 a respective pixel drive power line PL , a corresponding pixel common power line CPL and a corresponding reference power line RL are fed.

The control IC 530 can set a property value of a driving TFT disposed in the pixel P by the plurality of reference current lines RL that are on the first substrate 100 are arranged, determine, generate determination raw data corresponding to a determination value and the determination raw data on the timing control 570 provide.

The PCB 550 can with the other edge portion of the flexible circuit film 510 be connected. The PCB 550 can provide a signal and current between elements of the drive circuit unit 500 transfer.

The timing control 570 can be on the PCB 550 may be attached and the digital video data and the timing synchronization signal provided by the display driver system through a user terminal located on the PCB 550 is arranged, received. Alternatively, the timing control 570 not on the PCB 550 and can be implemented in the display driver system or on a separate control panel that is placed between the PCB 550 and the display drive system is switched.

The timing control 570 can align the digital video data on the basis of the timing synchronization signal to generate pixel data matched to a pixel arrangement structure arranged in the display area AA, and can align the generated pixel data on the drive IC 530 provide.

According to one embodiment, if the pixel P is a white sub-pixel SP has the timing control 570 extract white pixel data based on the extracted white pixel data in each of the red input data, the green input data and the blue input data for calculating red pixel data, green pixel data and blue pixel data reflect offset data and the calculated red pixel data, green pixel data, blue pixel data and white pixel data corresponding to the pixel arrangement structure for supplying aligned pixel data to the drive IC 530 align. For example, the timing control 570 red input data, green input data and blue input data in four-color (e.g. red, green, blue and white) data based on a data conversion method described in Korean patent application number 10-2013-0 060 476 or 10-2013-0 030 598 is revealed to convert.

The timing control 570 can generate each of the data control signal and the gate control signal based on the timing synchronization signal, and generate a drive timing of the drive IC based on the data control signal 530 and control a drive timing of the gate drive circuit based on the gate control signal 150 steer. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or a dot clock).

The data control signal according to an embodiment may include a source start pulse, a source shift clock and a source output signal. The data control signal can be sent through the input bonding portion of the flexible circuit film 510 and the flexible circuit film 510 the control IC 530 are fed.

The gate control signal according to an embodiment may have a start signal (or a gate start pulse), a plurality of shift clocks, a forward control signal and a reverse control signal. In this case, the plurality of shift clocks may be a plurality of sampling clocks in which phases thereof are sequentially shifted and have a plurality of carrier clocks in which phases thereof are sequentially shifted. In addition, according to an embodiment, the gate control signal may further include an external detection line selection signal, an external detection reset signal, and an external detection control signal for determining a characteristic value of the driving TFT arranged in the pixel P. The gate control signal can be provided through the input bonding portion of the flexible circuit film 510 , the flexible circuit film 510 , the output bonding portion of the flexible circuit film 510 , the third pad area 230 , the connecting line section 250 , the second pad area 210 , the wiring section 400 and the first pad area 110 the gate drive circuit 150 are fed.

The timing control 570 can be any of the drive IC 530 and the gate drive circuit 150 based on an external detection mode during a predetermined external detection period, compensation data for compensating for a change in property of the driving TFT of each pixel P on the basis of the raw detection data received from the driving IC 530 are provided, generate and modulate pixel data based on the generated compensation data. For example, the timing control 570 each from the drive IC 530 and the gate drive circuit 150 based on the external detection mode for each external detection period corresponding to an idle period (or a vertical idle period) of the vertical synchronization signal. For example, the external detection mode can be in a process of turning on the power supply to the display device, a process of turning off the power supply to the display device, a process of turning off the power supply to the display device after it has been driven for a long period of time, or a blank period of a frame that is real-time or periodically is set to be carried out.

The timing control 570 According to one embodiment, the raw determination data from each pixel P that is generated by the control IC 530 are provided, store in a memory circuit based on the external discovery mode. Likewise, in a display mode, the timing control 570 Correct pixel data to be supplied to each pixel based on the raw detection data stored in the memory circuit and can be sent to the drive IC 530 provide corrected pixel data. Here, raw determination data from each pixel can have sequential change information about each of a control TFT and a self-light-emitting device which are arranged in a corresponding subpixel. Therefore, in the external discovery mode, the timing control can 570 a property value (for example, a threshold voltage or mobility) of a drive TFT, which is arranged in each subpixel, and can correct based thereon pixel data to be supplied to each subpixel, thereby reducing the deterioration in the image quality, which by means of a property value deviation caused by driving TFTs of a plurality of subpixels SP can be minimized or prevented. The external detection mode of a display device may be a technology known to those skilled in the art, and thus its detailed description is omitted. For example, the display device according to the present disclosure can set a characteristic value of the driving TFT arranged in each sub-pixel P based on a determination mode disclosed in Korean Patent Publication No. 10-2016-0 093 179, 10-2017-0 054 654 or 10-2018-0 002 099 is disclosed.

The drive circuit unit 500 According to one embodiment, a power supply circuit unit can furthermore be used 590 exhibit.

The power supply circuit unit 590 can be on the PCB 550 and can generate various source voltages required for displaying an image on the pixels P using an input voltage supplied from the outside to provide the generated source voltage to a corresponding circuit. For example, the power supply circuit unit 590 a logic source voltage that is used to drive each of the timing controls 570 and the drive IC 530 it is necessary to have the plurality of reference gamma voltages that are present on the control IC 530 are provided, and at least one gate drive current and at least one gate common current which are used to drive the gate drive circuit 150 are necessary, generate and output. The gate drive current and the gate common current can have different voltage levels.

Each of the plurality of reference gamma voltages can be applied across the input bonding portion of the flexible circuit film 510 and the flexible circuit film 510 the control IC 530 are fed. Each of the at least one gate drive current and the at least one gate common current can be via the input Bonding portion of the flexible circuit film 510 , the flexible circuit film 510 , the output bonding portion of the flexible circuit film 510 , the third pad area 230 , the connecting line section 250 , the second pad area 210 , the wiring section 400 and the first pad area 110 the gate drive circuit 150 are fed.

6th FIG. 13 is an enlarged view of an area B2 "shown in FIG 4th and is a diagram for describing pixels arranged on a first substrate.

Referring to 4th until 6th can be a first substrate 100 according to the present disclosure, a plurality of data lines DLo and DLe, a plurality of gate lines GLo and GLe, a plurality of pixel drive power lines PL, a plurality of pixel common power lines CPL, a plurality of pixels P, a common one Electrode CE, a plurality of common current connection sections CPCP, a gate control line group GCL, a gate drive circuit 150 and a first pad area 110 exhibit.

The plurality of data lines DLo and DLe may extend long in a second direction Y and may be in a display area AA of the first substrate 100 be arranged in a first direction X at a predetermined distance away from each other. For example, in the plurality of data lines DLo and DLe, an odd-numbered data line DLo may be at a first edge portion of each of a plurality of pixel areas PA formed on the first substrate 100 arranged in the second direction Y, and an even data line DLe may be arranged at a second edge portion of each of the plurality of pixel areas PA that are on the first substrate 100 are arranged in the second direction Y, be arranged. Here, with respect to the first direction X, the first edge portion of each of the plurality of pixel areas PA may be a left edge portion of a corresponding pixel area PA and the second edge portion of each of the plurality of pixel areas PA may be a right edge portion of a corresponding pixel area PA.

The plurality of gate lines GLo and GLe may extend long in the first direction X and may be in the display area AA of the first substrate 100 in the second direction Y at a predetermined distance apart from each other. For example, in the plurality of gate lines GLo and GLe, an odd gate line GLo may be at a third edge portion of each of the plurality of pixel regions PA formed on the first substrate 100 arranged in the first direction X, and an even gate line GLe may be arranged on a fourth edge portion of each of the plurality of pixel areas PA that are on the first substrate 100 are arranged in the first direction X, be arranged. Here, with respect to the second direction Y, the third edge portion of each of the plurality of pixel areas may PA an upper edge portion of a corresponding pixel area PA and the fourth edge portion of each of the plurality of pixel areas PA may be a lower edge portion of a corresponding pixel area PA be.

The plurality of pixel drive power lines PL may extend long in the second direction Y and may be in the display area AA of the first substrate 100 be arranged in the first direction X at a predetermined distance away from each other. For example, in the plurality of pixel drive power lines PL , an odd pixel drive power line PL at a first edge portion of an odd pixel area PA with respect to the first direction X, and an even-numbered pixel drive current line PL may at a second edge portion of an even pixel region PA be arranged in relation to the first direction X.

Two adjacent pixel drive power lines PL of the plurality of pixel drive power lines PL may be connected to a plurality of power distribution lines PSL arranged in each of the pixel regions PA arranged in the second direction Y. For example, the plurality of pixel drive power lines PL by means of the plurality of power distribution lines PSL be electrically connected to one another and can thus have a conductor structure or a mesh structure. The plurality of pixel drive power lines PL may have a ladder structure or a mesh structure, and thus the voltage drop (IR drop) of the pixel drive current caused by a line resistance of each of the plurality of pixel drive power lines PL can be prevented and or minimized. Accordingly, the display device 10 in accordance with the present disclosure, the deterioration in image quality which can be prevented or minimized by means of a deviation in the pixel drive current supplied to each of the pixels P.

Each of the plurality of power distribution lines PSL can from an adjacent pixel drive power line PL branch off parallel to the first direction X and can each pixel area in a central area PA be arranged.

The plurality of pixel common power lines CPL may extend long in the second direction Y and may be in the display area AA of the first substrate 100 be arranged in the first direction X at a predetermined distance away from each other. For example, each of the plurality of pixel common power lines CPL at a first edge portion of an even pixel area PA be arranged in relation to the first direction X.

A plurality of pixels P may be in the plurality of pixel areas, respectively PA which are defined to be in the display area AA of the first substrate 100 have the same size, be arranged.

Each of the plurality of pixels P may have at least three sub-pixels. For example, as in 2 As illustrated, each of the plurality of pixels P is a first sub-pixel SP1 to fourth subpixel SP4 exhibit.

Referring to 2 and 6th can be any of the first sub-pixel SP1 to fourth subpixel SP4 a pixel circuit Pc and a light emitting device ED exhibit.

The pixel circuit Pc According to one embodiment, in a circuit area CA of the pixel area PA be arranged and can be arranged with gate lines adjacent thereto GLo and GLe , to adjacent data lines DLo and DLe and the pixel drive power line PL be connected. For example, a pixel circuit Pc that is in a first subpixel SP1 is arranged, with an odd-numbered data line DLo and an odd gate line GLo be connected, a pixel circuit Pc that is in a second subpixel SP2 is arranged, can with an even-numbered data line DLe and an odd gate line GLo be connected, a pixel circuit Pc that is in a third subpixel SP3 is arranged, can with an odd-numbered data line DLo and an even gate line GLe be connected, and a pixel circuit Pc that is in a fourth subpixel SP4 is arranged, can with an even-numbered data line DLe and an even-numbered gate line GLe be connected.

The pixel circuit Pc from each of the first sub-pixel SP1 to fourth subpixel SP4 may be a data signal generated in response to a strobe signal emitted from respective gate lines GLo and GLe is supplied by appropriate data lines DLo and DLe is supplied, and can sample a current drawn from the pixel drive power line PL to the light emitting device ED flows, based on a sampled data signal. For example, the pixel circuit Pc sample a data signal using at least two TFTs and at least one capacitor and can sample a current flowing into the light emitting device ED flows, based on a sampled data signal.

The pixel circuit Pc from each of the first sub-pixel SP1 to fourth subpixel SP4 may be implemented as a pixel drive power chip through a semiconductor manufacturing process, in a circuit area CA of a corresponding pixel area PA arranged and with gate lines adjacent thereto GLo and GLe , to adjacent data lines DLo and DLe and the pixel drive power line PL be connected. For example, the pixel driving chip may be a minimum unit microchip or a chipset, and may be a semiconductor unit device which has two or more transistors and one or more capacitors and is fine in size. Such a pixel drive chip can transmit a data signal in response to a scanning signal from corresponding gate lines GLo and GLe is supplied by appropriate data lines DLo and DLe is supplied, and may be a current drawn from the pixel drive power line PL to the light emitting device ED flows, based on a sampled data signal.

The light emitting device ED can be in an emission range EA of the pixel area PA arranged with the pixel circuit Pc electrically connected and with the common electrode CE be electrically connected. The light emitting device ED can with a current drawn by the pixel circuit Pc to the common electrode CE flowing, emitting light. For example, the light emitting device ED emit light based on a top emission type and can emit the light onto a portion above a first surface of a first substrate 100 radiate, but is not limited to this.

The light emitting device ED according to one embodiment may have a self-light-emitting device. For example, the light emitting device ED an organic light emitting device or an inorganic light emitting device. The inorganic light emitting device may include a semiconductor light emitting diode, a micro light emitting diode, or a quantum dot light emitting diode. For example, if the light emitting device ED the inorganic light emitting device is the light emitting device ED have a scale of 1 µm to 100 µm, but is not limited to this.

The light emitting device ED according to one embodiment, light may emit red light, green light, blue light, and white light. For example, the light emitting device ED from each of the first sub-pixel SP1 to fourth subpixel SP4 be designed such that it emits white light, but is not limited to this.

Again referring to 4th until 6th can use the common electrode CE in a display area AA of the first substrate 100 be arranged and can be with the light emitting device ED of each of the plurality of pixels P can be connected. For example, the common electrode CE in an area that is different from a first pad area 110 arranged in the first substrate from the display area AA of the first substrate 100 be arranged.

The common electrode CE According to one embodiment, a light-transmissive conductive material can comprise the light emitted by the light-emitting device ED emitted from each of the plurality of pixels P is allowed to pass. For example, the transparent conductive material can be indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

Each of the plurality of common power connection portions CPCP may be disposed between two adjacent pixels P of the plurality of pixels P each overlapping the plurality of pixel common power lines CPL, and may electrically connect the common electrode CE with a corresponding one Pixel-common-power lines CPL connect the plurality of pixel-common-power lines CPL. With respect to the second direction Y, each of the plurality of common power connection sections CPCP according to an embodiment can be electrically connected to a corresponding pixel common power line CPL of the plurality of pixel common power lines CPL at a section between the Plurality of pixels P or at a boundary portion between the plurality of pixels P and may be electrically connected to a portion of the common electrode CE and thus the common electrode CE may be electrically connected to a corresponding pixel common power line CPL of the plurality of Connect Pixel Common Power Lines CPL.

Each of the plurality of common power connection portions CPCP may be disposed between two adjacent pixels P of the plurality of pixels P to be the common electrode CE electrically with a corresponding pixel-common-power-line CPL of the plurality of pixel common power lines CPL connects, and can thus measure the voltage drop (IR drop) of the pixel-common current, which is generated by means of a surface resistance of the common electrode CE caused, prevent or minimize. Accordingly, the display device 10 according to the present disclosure, the deterioration in image quality which prevent or minimize by means of a deviation in the pixel drive current supplied to each of the pixels P arranged in the display area AA.

The gate control line group GCL can have a gate drive circuit 150 and a plurality of gate control lines in the display area AA of the first substrate 100 exhibit.

The gate control line group GCL in accordance with one embodiment, a start signal line may include a plurality of shift clock lines, at least one gate drive current line, and at least one gate common current line. The lines of the gate control line group GCL may extend long in the second direction Y and may be in the display area AA of the first substrate 100 be arranged in the first direction X at a predetermined distance from one another. For example, each of the lines of the gate control line group GCL can be arranged between one or more pixels P in the first direction X.

The gate drive circuit 150 can be in the display area AA of the first substrate 100 be arranged. Therefore, as the gate drive circuit 150 in the display area AA of the first substrate 100 is arranged, a second interval D2 between a central portion of an outermost pixel area PAo and each of the outer surfaces OS of the first substrate 100 half or less of a first interval (or pixel pitch) D1 between adjacent pixel areas PA be. For example, if the gate drive circuit 150 not in the display area AA of the first substrate 100 is arranged and between the outermost pixel area PAo and the outer surface OS of the first substrate 100 is due to a size (or a width) determined by the gate drive circuit 150 is occupied, the second interval is not half or less of the first interval D1. Accordingly, in one embodiment of the present disclosure, the gate drive circuit 150 within the display area AA of the first substrate 100 is arranged, the second interval D2 can be designed such that it is half or less of the first interval D1.

Referring to 6th and 7th can be a gate drive circuit 150 according to a Embodiment with a shift register which has a plurality of stage circuit units 1501 until 150m has to be executed.

Each of the plurality of stage circuit units 1501 until 150m can be in each horizontal line of a first surface 100a of the first substrate 100 be arranged at a distance from one another in the first direction X and can be connected to one another in a dependent manner in the second direction Y. Each of the plurality of stage circuit units 1501 until 150m may be in response to a gate control signal passed through the first pad area 110 and the gate control line group GCL is supplied, generates a scanning signal in a predetermined order, and can supply the scanning signal to a corresponding gate line GL.

Each of the plurality of stage circuit units 1501 until 150m according to one embodiment, a plurality of branch circuits 1511 until 151n and a branch network 153 exhibit.

The majority of branch circuits 1511 until 151n can through the branch network 153 be selectively connected to the lines of the gate control line group GCL and can through the branch network 153 be electrically connected to each other. Each of the plurality of branch circuits 1511 until 151n may be based on a gate control signal transmitted through a corresponding line of the gate control line group GCL and the branch network 153 and a signal passing between branch networks 153 is transmitted, generate the scanning signal, and can transmit the scanning signal to a corresponding gate line GL respectively.

Each of the plurality of branch circuits 1511 until 151n may be at least one of a plurality of TFTs, the one of the stage circuit units 1501 until 150m set up, exhibit. Each of the plurality of branch circuits 1511 until 151n may be in a circuit area between two adjacent pixels P or in a circuit area between two pixels P in each horizontal line of the first substrate 100 may be arranged, but not limited to, in a circuit area between one or more pixels P on the basis of the number of TFTs that each of the stage circuit units 1501 until 150m set up, and the number of pixels P arranged in a horizontal line.

The branch network 153 can be in each horizontal line of the first substrate 100 may be arranged and the plurality of branch circuits 1511 until 151 n electrically connect. The branch network 151 according to one embodiment can have a plurality of control nodes and a network line.

The plurality of control nodes can be in each horizontal row of the first substrate 100 and may be arranged in a horizontal line selectively with the plurality of branch circuits 1511 until 151n be connected. For example, the plurality of control nodes in an upper edge region (or a lower edge region) can be composed of pixel regions which are in each horizontal line of the first substrate 100 are arranged, be arranged.

The network line can be connected to the lines of the gate control line group GCL disposed in the first substrate can be selectively connected and can be connected to the plurality of branch circuits 1511 until 151n be selectively connected. For example, the network line can supply the gate control signal, which is fed through the lines of the gate control line group GCL, to corresponding branch circuits 1511 until 151n and can transmit a signal between the plurality of branch circuits 1511 until 151n transfer.

Again referring to 4th until 6th can be the first pad area 110 at a first edge portion from the first surface of the first substrate 100 be arranged parallel to the first direction X. The first pad area 110 may be on a third edge portion of each of outermost pixel areas PAo that are on the first edge portion of the first substrate 100 are arranged, be arranged. With respect to the second direction Y, one end of the first pad area 110 one end of each of the outermost pixel areas PAo overlap or be flush with it. Therefore, the first pad area 110 in each of the outermost pixel regions PAo that are on a first edge portion of the first substrate 100 arranged, included (or arranged), and thus a non-display area (or a border area) based on the first pad area 110 on the first substrate 100 not be formed or not be present.

The first pad area 110 may have a plurality of first pads parallel to each other in the first direction X on the first edge portion of the first substrate 100 are arranged, have. The plurality of first pads can be converted into a plurality of first data pads DP1 , a plurality of first gate pads GP1 , a plurality of first pixel drive power pads PPP1 and a plurality of first pixel common power pads CPP1 be subdivided (or classified).

The first pad area 110 According to one embodiment, a first data pad area, a first gate pad area, a first pixel Have drive current pad area and a first pixel-common current pad area.

The first data pad area can have a plurality of first data pads DP1. Each of the plurality of first data pads DP1 can be connected to one end of each of a plurality of data lines DLo and DLe , which are arranged on the first substrate, individually (or each) connected.

The first data pad area may have a data wiring section formed in a wiring section 400 is arranged to be connected. Each of the plurality of first data pads DP1 disposed in the first data pad area may be connected to one end of each of a plurality of data wiring lines 410 that are in the wiring section 400 are arranged, individually (or each) connected. Therefore, any of the plurality of data lines DLo and DLe that are on the first substrate 100 are arranged by a corresponding first data pad area DP1 the plurality of first data pads DP1 electrically with a corresponding data wiring line 410 of the plurality of data wiring lines 410 be connected.

The first gate pad region can have a plurality of first gate pads GP1. Each of the plurality of first gate pads GP1 may be connected to one end of a corresponding gate control line from the plurality of gate control lines which are in the gate control line group GCL which are on the first substrate 100 is arranged, is included, individually (or each) connected.

The first gate pad region may be provided with a gate wiring portion included in the wiring portion 400 is arranged to be connected. Each of the plurality of first gate pads GP1 disposed in the first gate pad region may be connected to one end of each of a plurality of gate wiring lines 430 a plurality of wiring lines formed in the wiring section 400 are arranged, individually (or each) connected. Therefore, any line that is in the gate control line group GCL that are on the first substrate 100 is arranged, is contained by a corresponding first gate pad GP1 a plurality of first gate pads GP1 electrically to a corresponding gate wiring line 430 of the plurality of gate wiring lines 430 be connected.

The majority of first gate pads GP1 according to an embodiment may be divided (or classified) into a first start signal pad, a plurality of first shift clock pads, at least one first gate drive current pad and at least one first gate common current pad.

The first start signal pad may be electrically connected to a start signal wiring line provided in a gate wiring line portion of the wiring portion 400 is arranged to be connected. Therefore, the start signal line that is on the first substrate 100 is arranged to be electrically connected to the start signal wiring line through the first start signal pad.

Each of the plurality of first shift clock pads may be connected to a corresponding shift clock wiring line of the plurality of shift clock wiring lines provided in the gate wiring portion of the wiring portion 400 are arranged to be electrically connected. Therefore, any of the plurality of shift clock lines formed on the first substrate 100 are arranged, be electrically connected by a corresponding first shift clock pad of a plurality of first shift clock pads to a corresponding shift clock pad of the plurality of shift clock pads.

The at least one first gate drive current path may connect to the at least one gate drive current wiring line provided in the gate wiring section of the wiring section 400 is arranged to be electrically connected. Therefore, the at least one first gate drive current line formed on the first substrate 100 is arranged through which at least one first gate drive current path can be electrically connected to the at least one gate drive current wiring line.

The at least one first gate common power pad may connect to the at least one gate common power wiring line provided in the gate wiring section of the wiring section 400 is arranged to be electrically connected. Therefore, the at least one first gate common current line that is on the first substrate 100 is arranged by the at least one first gate common power pad being electrically connected to the at least one gate common power wiring line.

The first pixel drive current pad may have a plurality of first pixel drive current pads PPP1. Each of the plurality of first pixel drive power pads PPP1 may be connected to one end of a corresponding one of the pixel drive power lines PL of the plurality of pixel drive power lines PL that are on the first substrate 100 are arranged, individually (or each) connected.

The first pixel drive current pad area may be connected to the pixel drive current wiring section included in the wiring section 400 is arranged to be connected. Each of the plurality of first pixel drive current pads PPP1 arranged in the first pixel drive current pad area may be connected to one end of a corresponding one of the pixel drive current wiring lines 450 of the plurality of pixel drive current wiring lines 450 that are in the wiring section 400 are arranged, individually (or each) connected. Therefore, each of the plurality of pixel drive power lines PL that are on the first substrate 100 are arranged by a corresponding one of the first pixel drive current pads PPP1 of the plurality of first pixel drive current pads PPP1 having one end of a corresponding one of the pixel drive current wiring lines 450 the plurality of pixel drive current wiring lines 450 individually (or each) connected.

The first pixel common power pad may have a plurality of first pixel common power pads CPP1. Each of the plurality of first pixel common power pads CPP1 may be connected to one end of a corresponding pixel common power line CPL of the plurality of pixel common power lines CPL that are on the first substrate 100 are arranged, individually (or each) connected.

The first pixel-common-power pad area may be connected to the pixel-common-power wiring section included in the wiring section 400 is arranged to be connected. Each of the plurality of first pixel common power pads CPP1 arranged in the first pixel common power pad area may be connected to one end of a corresponding pixel common power wiring line 470 of the plurality of pixel common power wiring lines 470 that are in the wiring section 400 are arranged, individually (or each) connected. Therefore, each of the plurality of pixel common power lines CPL residing on the first substrate 100 are arranged by a corresponding first pixel common power pad CPP1 of the plurality of first pixel common power pads CPP1 having one end of a corresponding pixel common power wiring line 470 of the plurality of pixel common power wiring lines 470 individually (or each) connected.

The first pad area 110 According to one embodiment, a plurality of pad groups PG that, in the order of a first pixel drive current pad PPP1, two first data pads DP1 , a first gate pad GP1 , a first pixel shared stream pad CPP1, two first data pads DP1 and a first pixel drive current path PPP1 are arranged along the first direction X. Any of the plurality of pad groups PG may be connected to two adjacent pixels P arranged along the first direction X. For example, the plurality of pad groups PG a first pad group PG1 that have a first pixel drive current pad PPP1, two first data pads DP1 and a first gate pad GP1 that are continuously in an odd-numbered pixel area PA are arranged along the first direction X, and a second pad group PG2 who have favourited a first pixel shared stream pad CPP1, two first data pads DP1 and a first pixel drive current path PPP1 which is continuous in an even pixel area PA are arranged along the first direction X, having.

The first substrate 100 Further, in accordance with the present disclosure, a plurality of secondary power lines may be used SPL and a plurality of secondary power connection sections SPCP.

Each of the plurality of secondary power lines SPL may extend long in the second direction Y and may be adjacent to a corresponding pixel common power line CPL of the plurality of pixel common power lines CPL be arranged. Each of the plurality of secondary power lines SPL can be electrically connected to an adjacent pixel-common-power-line CPL can be connected without being electrically connected to the first pixel common power pad CPP1, and you can through the adjacent pixel common power line CPL a common pixel stream can be supplied. For this purpose, the first substrate 100 further a plurality of conduit connection structures in accordance with the present disclosure LCP having a pixel-common-power line CPL and a secondary power line SPL that are adjacent to each other, electrically connect.

Each of the plurality of line connection structures LCP can on the first substrate 100 be arranged such that the line connection structure LCP and a pixel common power line CPL and a secondary power line SPL that are adjacent to each other intersect each other, and may be a pixel common power line CPL and electrically connecting a secondary power line SPL adjacent to each other using a line skipping structure. For example, one side of each of the plurality of Line connection structures LCP through a first line contact hole formed in an insulating layer on the secondary power line SPL, electrically connected to a portion of the secondary power line SPL, and the other side of each of the plurality of line connection structures LCP can be through a second line contact hole formed in a insulating layer on the pixel-common-current-line CPL is formed with a portion of the pixel common power line CPL be connected.

Each of the plurality of secondary power connection sections SPCP may connect between the plurality of pixels P, each of which is the plurality of secondary power lines SPL overlap, be arranged and the common electrode CE electrically to each of the plurality of secondary power lines SPL associate. With respect to the second direction Y, each of the plurality of secondary power connection sections may SPCP according to an embodiment in a section between the plurality of pixels P or a boundary section between the plurality of pixels P electrically with a corresponding secondary power line SPL the plurality of secondary power lines SPL and may be electrically connected to a portion of the common electrode and thus may be the common electrode CE electrically to each of the plurality of secondary power lines SPL associate. Therefore, the common electrode CE through each of the plurality of secondary power connection sections SPCP in addition to each of the plurality of secondary power lines SPL be connected. Accordingly, the display device 10 according to the present disclosure, prevent or minimize the deterioration in image quality caused by a deviation in the pixel common current supplied to each of the pixels P arranged in the display area AA. Likewise, in the display device 10 in accordance with the present disclosure, although a first pixel shared power pad CPP1 , which is connected to each of the plurality of secondary power lines SPL, is not additionally arranged (or formed) in each of the plurality of pixel areas PA the pixel common current can be supplied to the common electrode CE.

The display device 10 Furthermore, in accordance with the present disclosure, a plurality of reference power lines RL exhibit.

The plurality of reference power lines RL may extend long in the second direction Y and may be in the display area AA of the first substrate 100 be arranged in the first direction X at a predetermined distance away from each other. Each of the plurality of reference power lines RL can be in a central area of each of the pixel areas PA arranged in the second direction Y can be arranged. For example, each of the plurality of reference power lines RL between an odd-numbered data line DLo and an even data line DLe in each pixel area PA be arranged.

Each of the plurality of reference power lines RL can be in the first direction X in each pixel area PA of two neighboring subpixels (( SP1 , SP2 ) ( SP3 , SP4 )) to be shared. To this end, each of the plurality of reference power lines RL a reference branch RDL exhibit.

The reference branch RDL can be in the first direction X in each pixel area PA to the two neighboring subpixels (( SP1 , SP2 ) ( SP3 , SP4 )) branch off (or protrude) and can be electrically connected to the two neighboring subpixels (( SP1 , SP2 ) ( SP3 , SP4 )) be connected.

The first pad area 110 in accordance with the present disclosure may further comprise a first reference current pad area.

The first reference current pad area can have a plurality of first reference current pads RPP1. Each of the plurality of first reference current pads RPP1 may be connected to one end of a corresponding reference current line RL of the plurality of reference power lines RL individually (or each) connected. For example, each of the plurality of first reference current pads RPP1 can be between two first data pads DP1 in each of a plurality of outermost pixel areas PAo are arranged, be arranged, but is not limited to this.

The first reference current pad area may be connected to the reference current wiring section included in the wiring section 400 is arranged to be connected. Each of the plurality of first reference current pads RPP1 arranged in the first reference current pad area may be connected to one end of a corresponding reference current wiring line 490 of the plurality of reference current wiring lines 490 that are in the wiring section 490 are arranged, individually (or each) connected. Therefore, each of the plurality of reference power lines RL that are on the first substrate 100 are arranged by a corresponding first reference current pad RPP1 of the plurality of first reference current pads RPP1 electrically with a corresponding reference current wiring line 490 of the plurality of reference current wiring lines 490 be connected.

Optionally, the plurality of reference power lines RL , the reference branch RDL , the plurality of first reference current pads RPP1 and the plurality of reference current wiring lines 490 based on a circuit design of the pixel circuit Pc can be omitted.

8th is an equivalent circuit diagram showing an in 4th and 6th illustrated pixel, and is a diagram for describing a pixel circuit of a sub-pixel. When describing the 8th are elements that are equal to the elements of the 4th until 7th are or correspond to them are denoted by the same reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 8th According to the present disclosure, a pixel P can be a first sub-pixel SP1 to fourth subpixel SP4 each having a pixel circuit Pc , a pixel electrode PE and a light emitting device ED.

The pixel circuit Pc that is in each of the first subpixel SP1 to fourth subpixel SP4 the pixel P is arranged may be arranged in a circuit area and may be connected to adjacent gate lines GLo and GLe , neighboring data lines DLo and DLe , a reference power line RL and a pixel drive power line PL be connected. The pixel circuit Pc can be attached to the light emitting device ED provide a data stream which is a differential voltage between a data signal which is supplied through the adjacent data lines DLo and DLe, and a reference voltage which is produced by the reference current line RL is supplied in response to a scan signal passed through the adjacent gate lines GLo and GLe is supplied, corresponds to, whereby the light emitting device ED can emit light.

The pixel circuit Pc According to one embodiment, it can have a first switching TFT Tsw1, a second switching TFT Tsw2, a storage capacitor Cst and a control TFT Tdr. In the following description, a thin film transistor can be referred to as a TFT.

At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be an N-type TFT or a P-type TFT. At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be an amorphous silicon (a-Si) TFT, a poly-Si TFT, an oxide TFT, or an organic TFT being. For example, in the pixel circuit PC, some of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be a TFT that is a semiconductor layer (or an active layer) that is a low-temperature polysilicon (LTPS ) having an excellent response characteristic, and the other of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr may be a TFT containing a semiconductor layer (or an active layer) containing an oxide which is good in its off-current characteristic. The first switching TFT Tsw1, the second switching TFT Tsw2 and the drive TFT Tdr can have different sizes (or channel sizes). For example, the driving TFT Tdr may have a size larger than that of each of the first switching TFT Tsw1 and the second switching TFT Tsw2, and the second switching TFT Tsw2 may have a size larger than that of the first switching TFT Tsw1.

The first switching TFT Tsw1 may have a gate electrode connected to the adjacent gate lines GLo and GLe is connected, a first source / drain electrode which is connected to the adjacent data lines DLo and DLe and a second source / drain electrode connected to a first node (or a gate electrode of the drive TFT Tdr) n1. The first switching TFT Tsw1 can be switched on by means of a sampling signal which is supplied through corresponding gate lines GLo and GLe, and a data signal which is supplied through corresponding data lines DLo and DLe can be sent to the first node n1 (ie the gate Electrode n1 of the control TFT Tdr) transferred.

According to one embodiment, the gate electrode of the first switching TFT Tsw1, which is in the pixel circuit Pc of each of the first sub-pixel SP1 and the second sub-pixel SP2 is arranged with an odd gate line GLo be connected, and the gate electrode of the first switching TFT Tsw1 included in the pixel circuit Pc from each of the third sub-pixel SP3 and the fourth subpixel SP4 may be arranged with an even gate line GLe be connected. The first source / drain electrode of the first switching TFT Tsw1, which is in the pixel circuit Pc from each of the first sub-pixel SP1 and the third subpixel SP3 is arranged, can with an odd-numbered data line DLo be connected, and the first source / drain electrode of the first switching TFT Tsw1, which is in the pixel circuit Pc from each of the second sub-pixel SP2 and the fourth subpixel SP4 is arranged, can with an even-numbered data line DLe be connected.

The second switching TFT Tsw2 may have a gate electrode connected to the adjacent gate lines GLo and GLe connected, a first Source / drain electrode connected to an adjacent reference power line RL and a second source / drain electrode connected to a second node (or a source electrode of the drive TFT Tdr) n2. The second switching TFT Tsw2 can by means of a scanning signal which is transmitted through corresponding gate lines GLo and GLe is supplied, can be switched on and a reference voltage, which is generated by a corresponding reference branch line RDL and a reference power line RL is supplied to the source electrode n2 of the drive TFT Tdr.

According to one embodiment, the gate electrode of the second switching TFT Tsw2, which is in the pixel circuit Pc from each of the first sub-pixel SP1 and the second subpixel SP2 is arranged with an odd gate line GLo be connected, and the gate electrode of the second switching TFT Tsw2, which is in the pixel circuit Pc from each of the third sub-pixel SP3 and the fourth subpixel SP4 may be arranged with an even gate line GLe be connected. The first source / drain electrode of the second switching TFT Tsw2, which is in the pixel circuit Pc from each of the first sub-pixel SP1 to fourth subpixel SP4 is arranged, can by a corresponding reference branch line RDL together with an adjacent reference power line RL be connected.

The scanning signal supplied through the gate electrode of the first switching TFT Tsw1 and the scanning signal supplied to the gate electrode of the second switching TFT Tsw2 may be the same signal. For example, the gate electrode of the first switching TFT Tsw1 and the gate electrode of the second switching TFT Tsw2 can have the same gate lines GLo and GLe be connected. Therefore, the first switching TFT Tsw1 and the second switching TFT Tsw2, which are in the pixel circuit Pc from each of the first sub-pixel SP1 and the second subpixel SP2 are arranged by means of a sampling signal transmitted through the odd-numbered gate line GLo can be switched on or off at the same time. Similarly, the first switching TFT Tsw1 and the second switching TFT Tsw2 included in the pixel circuit Pc of each of the third sub-pixel SP3 and the fourth sub-pixel SP4 are arranged by means of a scanning signal transmitted through the even gate line GLe can be switched on or off at the same time.

Optionally, the scanning signal supplied to the gate electrode of the first switching TFT Tsw1 and the scanning signal supplied to the gate electrode of the second switching TFT Tsw2 may be different signals. For example, the gate electrode of the first switching TFT Tsw1 and the gate electrode of the second switching TFT Tsw2 can have different gate lines GLo and GLe be connected.

Each from the odd gate line GLo and the even gate line GLe according to an embodiment may include a first gate line and a second gate line.

The first gate line of the odd gate line GLo can be connected to the gate electrode of the first switching TFT Tsw1, which is in the pixel circuit Pc of each of the first sub-pixel SP1 and the second sub-pixel SP2 is arranged, be connected, and the second gate line of the odd-numbered gate line GLo can be connected to the gate electrode of the second switching TFT Tsw2, which is in the pixel circuit Pc of each of the first sub-pixel SP1 and the second sub-pixel SP2 is arranged to be connected.

The first gate line of the even gate line GLe can be connected to the gate electrode of the first switching TFT Tsw1, which is in the pixel circuit Pc from each of the third sub-pixel SP3 and the fourth subpixel SP4 is arranged, and the second gate line of the even gate line GLe can be connected to the gate electrode of the second switching TFT Tsw2 included in the pixel circuit PC of each of the third subpixels SP3 and the fourth subpixel SP4 is arranged to be connected.

Therefore, the first switching TFT Tsw1 and the second switching TFT Tsw2, which are in the pixel circuit Pc from each of the first sub-pixel SP1 and the second subpixel SP2 are arranged by means of the same scanning signal that is transmitted through the first gate line and the second gate line of the odd-numbered gate line GLo is supplied, switched on or off, or can be switched on or off by means of various scanning signals which are transmitted through the first gate line and the second gate line of the odd gate line GLo can be supplied, switched on or switched off individually. Similarly, the first switching TFT Tsw1 and the second switching TFT Tsw2 included in the pixel circuit Pc from each of the third sub-pixel SP3 and the fourth subpixel SP4 are arranged by means of the same scanning signal that is transmitted through the first gate line and the second gate line of the even-numbered gate line GLe is supplied, can be switched on or off simultaneously, or can be switched on or off individually by means of various scanning signals which are supplied to the even-numbered gate line GLe through the first gate line and the second gate line. For example, in each of the first subpixel SP1 to fourth subpixel SP4 , the first switching TFT Tsw1 based on a first sampling signal generated by a first Gate line is supplied, can be turned on, and the second switching TFT Tsw2 can be turned on based on a second scanning signal supplied through a second gate line.

The second switching TFT Tsw2 that is in the pixel circuit Pc from each of the first sub-pixel SP1 to fourth subpixel SP4 is arranged, can through the reference power line RL during a data loading period (or portion) of the pixel P based on an external detection mode by the reference power line RL transmit a reference voltage to the source electrode n2 of the drive TFT Tdr, and during a detection period (or portion) of the pixel P can transmit a current flowing in the source electrode n2 of the drive TFT Tdr to the reference power line RL In this case, the drive circuit unit for generating compensation data for compensating for a characteristic variation of the drive TFT Tdr can detect the current supplied to the reference power line RL, and can modulate pixel data based on the generated compensation data. For example, the property variation of the control TFT Tdr can have a shift in a threshold voltage and / or a mobility.

The storage capacitor Cst may be provided in an overlap area between the gate electrode n1 and the source electrode n2 of the drive TFT Tdr. The storage capacitor Cst may have a first capacitor electrode connected to the gate electrode of the drive TFT Tdr, a second capacitor electrode connected to the source electrode of the drive TFT Tdr, and a dielectric layer formed in an overlap area between the first capacitor electrode and the second capacitor electrode is formed. The storage capacitor Cst can be charged with a differential voltage between the gate electrode n1 and the source electrode n2 of the drive TFT Tdr, and then can turn the drive TFT Tdr on or off based on a charged voltage.

The drive TFT Tdr may have a gate electrode (or a gate node) n1 connected to the second source / drain electrode of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst, a source electrode (or a source node) which is commonly connected to the second source / drain electrode of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst and a pixel electrode PE, and a drain electrode (or a drain node) which is connected to an adjacent pixel drive power line PL.

The drain electrode of the drive TFT Tdr, which is in the pixel circuit Pc from each of the first sub-pixel SP1 to fourth subpixel SP4 may be arranged through a power distribution line PSL with an adjacent pixel drive power line PL be connected. The power distribution line PSL may be parallel to the first direction X from the adjacent pixel drive power line PL adjacent thereto and may be arranged in a central area of the pixel P. The drive TFT Tdr can be turned on based on a voltage of the storage capacitor Cst and can control the amount of current drawn by the pixel drive power line PL to the light emitting device ED flows, control.

The driving TFTs Tdr, each in the pixel circuits Pc of the first subpixel SP1 to fourth subpixels SP4 can be arranged on the basis of the emission efficiency of a corresponding light emitting device ED have different sizes (or duct sizes). For example, the driving TFT Tdr of the first sub-pixel (or a red sub-pixel) SP1 may have a size larger than that of the driving TFT Tdr of each of the second sub-pixel SP2 to fourth subpixel SP4 , the control TFT Tdr of the fourth subpixel (or a green subpixel) SP4 may have a size larger than that of the driving TFT Tdr of each of the second sub-pixel SP2 and the third subpixel SP3 , and the control TFT Tdr of the second subpixel (or a blue subpixel) SP2 may have a size larger than that of the driving TFT Tdr of the third subpixel (or a white subpixel) SP3 .

Optionally, in each of the first subpixel SP1 to fourth subpixel SP4 , the pixel circuit Pc , which comprises the first switching TFT Tsw1, the second switching TFT Tsw2, the storage capacitor Cst and the driving TFT Tdr, as a pixel driving chip included in a circuit area CA of a corresponding pixel area PA is arranged, executed and with gate lines adjacent thereto GLo and GLe , to adjacent data lines DLo and DLe and the pixel drive power line PL be connected. Such a pixel drive chip can receive a data signal from corresponding data lines DLo and DLe in response to a scan signal from respective gate lines GLo and GLe is supplied, is supplied, can be sampled and the pixel electrode PE supply a data stream corresponding to a sampled data signal.

The pixel electrode PE may be in an emission region of each of the first subpixels SP1 to fourth subpixel SP4 be arranged and can be connected to the drain electrode of a drive TFT Tdr which is arranged in a corresponding pixel circuit PC.

Based on a resolution of the display device 10 can the pixel electrode PE be arranged in a corresponding subpixel area in such a way that they have the pixel circuit Pc does not overlap or that they overlap a portion of the pixel circuit PC or the entire pixel circuit Pc overlaps. For example, as in one of the 2A until 2C shown, the pixel electrode PE be arranged in a subpixel area in such a way that they form a portion of the circuit area CA or the entire circuit area CA overlaps.

The pixel electrode PE according to one embodiment it can be arranged in a subpixel area in such a way that it has the pixel circuit Pc not overlapped. For example, the pixel electrode PE be arranged close to a central portion of the pixel P in the sub-pixel area.

According to a further embodiment, the pixel electrode PE be arranged in the sub-pixel area in such a way that they form a portion of the pixel circuit Pc overlaps. For example, the pixel electrode PE be arranged close to the central portion of the pixel P in the subpixel area such that it is a portion of the pixel circuit Pc overlaps.

According to a further embodiment, the pixel electrode PE be arranged in the sub-pixel area in such a way that they cover the entire pixel circuit Pc overlaps. For example, the pixel electrode PE be arranged in the entire sub-pixel area so as to cover the entire pixel circuit Pc overlaps.

The light emitting device ED can on the pixel electrode PE and can be electrically connected to the pixel electrode PE be connected. The light-emitting device can likewise ED be electrically connected to the common electrode. That means the light emitting device ED between the pixel electrode PE and the common electrode. The light emitting device ED can with a data stream from a corresponding pixel circuit Pc is supplied, emit light. The light emitting device ED can with a data stream from a corresponding pixel circuit Pc is supplied, emit light and can the light on a portion above a first surface of the first substrate 100 radiate. The light emitting device ED According to one embodiment, it can have a self-light-emitting device described above.

Optionally, in the pixel circuit Pc According to an embodiment, the second switching TFT Tsw2 based on a driving manner (or operation) of the pixel P can be omitted, and in this case that on the first substrate 100 arranged reference current line RL can also be omitted.

9 is a graph showing an in 5 represents the illustrated second substrate, and 10 FIG. 10 is an enlarged view of a FIG 9 area "B3" shown. When describing 9 and 10 are repetitive descriptions of elements that are the same as elements of the 4th until 8th or correspond to them, are omitted or are briefly indicated below.

Referring to 5 , 6th , 9 and 10 can be a second substrate 200 according to the present disclosure, a second pad area 210 exhibit.

The second pad area 210 may be at a first edge portion from the second surface 200b of the second substrate 200 be arranged parallel to the first direction X such that it has the first pad area 110 that is on the first substrate 100 is arranged, overlaps. The second pad area 210 may have a plurality of second pads parallel to each other on the first edge portion of the second substrate 200 are arranged in the first direction X, have. The plurality of second pads can be converted into a plurality of second data pads DP2 , a plurality of second gate pads GP2, a plurality of second pixel drive current pads PPP2, and a plurality of second pixel common current pads CPP2 can be divided (or classified).

The second pad area 210 according to an embodiment may have a second data pad area, a second gate pad area, a second pixel drive current pad area and a second pixel common current pad area.

The second data pad area can pass through the wiring section 400 electrically to the first data pad area of the first pad area 110 be connected.

The second data pad area according to an embodiment can have a plurality of second data pads DP2 exhibit. Each of the plurality of second data pads DP2 can be arranged such that a corresponding first data pad DP1 the plurality of first data pads DP1 that are in the first pad area 110 of the first substrate 100 are arranged, individually (or each) overlapped. Each of the plurality of second Data pads DP2 according to one embodiment, by a corresponding data wiring line 410 of the plurality of data wiring lines 410 of the plurality of wiring lines formed in the wiring section 400 are arranged, with a corresponding first data pad DP1 the plurality of first data pads DP1 individually (or each) connected. Accordingly, each of the plurality of second data pads DP2 through a corresponding data wiring line 410 and a corresponding first data pad DP1 electrically with corresponding data lines DLo and DLe be electrically connected.

The second gate pad area can pass through the wiring section 400 with the first gate pad area of the first pad area 110 be electrically connected.

The second gate pad region according to an embodiment can have a plurality of second gate pads GP2 exhibit. Each of the plurality of second gate pads GP2 can be arranged such that there is a corresponding first gate pad GP1 the plurality of first gate pads GP1 that are in the first pad area 110 of the first substrate 100 are arranged, individually (or each) overlapped. Each of the plurality of second gate pads GP2 according to one embodiment, to the other end of a corresponding gate wiring line 430 of the plurality of gate wiring lines 430 of the plurality of wiring lines formed in the wiring section 400 are arranged, individually (or each) connected. Accordingly, each of the plurality of second gate pads GP2 through a corresponding gate wiring line 430 and a corresponding first gate pad GP1 electrically to a corresponding gate control line, which is in a gate control line group GCL is included, be connected.

The plurality of second gate pads GP2 according to an embodiment may be divided (or classified) into a second start signal pad, a plurality of second shift clock pads, at least one second gate drive current pad, and at least one second gate common current pad.

The second start signal pad may be electrically connected to a start signal wiring line provided in a gate wiring section of the wiring section 400 is arranged to be connected. Therefore, the second start signal pad can be formed by a corresponding first start signal pad and a corresponding start signal wiring line out of the plurality of gate wiring lines 430 be electrically connected to a corresponding start signal line included in the gate control line group GCL.

Each of the plurality of second shift clock pads can be electrically connected to a corresponding shift clock wiring line of the plurality of shift clock wiring lines provided in the gate wiring portion of the wiring portion 400 are arranged to be connected. Therefore, each of the plurality of second shift clock pads can be replaced by a corresponding first shift clock pad and a corresponding shift clock wiring line among the plurality of gate wiring lines 430 be electrically connected to a corresponding shift clock line of the plurality of shift clock lines included in the gate control line group GCL.

The at least one second gate drive current path may be electrically connected to the at least one gate drive current wiring line provided in the gate wiring portion of the wiring portion 400 is arranged to be connected. Therefore, the at least one second gate drive current path can be passed through a corresponding first gate drive current path and a corresponding gate drive current wiring line out of the plurality of gate wiring lines 430 be electrically connected to the gate drive power line included in the gate control line group GCL.

The at least one second gate common power pad may be electrically connected to the at least one gate common power wiring line included in the gate wiring section of the wiring section 400 is arranged to be connected. Therefore, the at least one second gate common power pad can be defined by a corresponding first gate common power pad and a corresponding gate common power wiring line out of the plurality of gate wiring lines 430 be electrically connected to the gate common power line included in the gate control line group GCL.

The second pixel drive current pad area can pass through the wiring section 400 electrically to the first pixel drive current pad area of the first pad area 110 be connected.

The second pixel drive current pad area according to an embodiment may have a plurality of second pixel drive current pads PPP2. Each of the plurality of second pixel drive current pads PPP2 may be arranged to be a corresponding one of the plurality of first pixel drive current pads PPP1 of first pixel drive current pads PPP1 that are in the first pad area 110 of the first substrate 100 are arranged, individually (or each) overlapped. Each of the plurality of second pixel drive current pads PPP2 according to an embodiment can be connected through a corresponding pixel drive current wiring line 450 the plurality of pixel drive current wiring lines 450 of the plurality of wiring lines formed in the wiring section 400 are included, can be connected to a corresponding first pixel drive current pad PPP1 of the plurality of first pixel drive current pads PPP1 individually (or each). Accordingly, each of the plurality of second pixel drive current pads PPP2 can be connected through a corresponding pixel drive current wiring line 450 and a corresponding first pixel drive current pad PPP1 may be electrically connected to a corresponding pixel drive current line PL.

The second pixel common power pad area can pass through the wiring section 400 electrically to the first pixel common power pad area of the first pad area 110 be connected.

The second pixel common power pad area according to an embodiment may include a plurality of second pixel common power pads CPP2 exhibit. Each of the plurality of second pixel common power pads CPP2 can be arranged such that there is a corresponding first pixel-common-current pad CPP1 the plurality of first pixel common power pads CPP1 that are in the first pad area 110 of the first substrate 100 are arranged, individually (or each) overlapped. Each of the plurality of second pixel common power pads CPP2 according to one embodiment, through a corresponding pixel common power wiring line 470 of the plurality of pixel common power wiring lines 470 of the plurality of wiring lines formed in the wiring section 400 are arranged, with a corresponding first pixel-common-current pad CPP1 the plurality of first pixel common power pads CPP1 individually (or each) connected. Accordingly, each of the plurality of second pixel common power pads CPP2 through a corresponding pixel common power wiring line 470 and a corresponding first pixel common power pad CPP1 may be electrically connected to a corresponding pixel common power line CPL.

The second pad area 210 according to one embodiment, a plurality of pad groups PG in the order of a second pixel drive current pad PPP2 , two second data pads DP2 , a second gate pad GP2 , a second pixel shared power pad CPP2 , two second data pads 2 and a second pixel drive current pad PPP2 are arranged along the first direction X in such a way that they correspond to the order in which the pads are arranged in the first pad area 110 are arranged, is the same (or correspond to this). For example, the plurality of pad groups PG a first pad group PG 1 who have favourited a second pixel drive current pad PPP2 , two second data pads DP2 and a second gate pad GP2 arranged continuously along the first direction X, and a second pad group PG 2 who have favourited a second pixel-shared-electricity pad CPP2 , two second data pads DP2 and a second pixel drive current pad PPP2 arranged continuously along the first direction X.

The second pad area 210 in accordance with the present disclosure may further comprise a second reference current pad area.

The second reference current pad area can pass through the wiring section 400 electrically to the first reference current pad area of the first pad area 110 be connected.

The second reference current pad area according to an embodiment can have a plurality of second reference current pads RPP2 exhibit. Each of the plurality of second reference current pads RPP2 can be arranged such that there is a corresponding first reference current path RPP1 the plurality of first reference current pads RPP1 that are in the first pad area 110 of the first substrate 100 are arranged, individually (or each) overlapped. Accordingly, each of the plurality of second reference current pads may RPP2 through an appropriate reference current wiring line 490 and a corresponding first reference current pad RPP1 be electrically connected to a corresponding reference current line RL.

The second substrate 200 In accordance with the present disclosure, a third pad area can furthermore be used 230 and a connecting line section 250 exhibit.

The third pad area 230 can on the back surface 200b of the second substrate 200 be arranged. For example, the third pad area 230 at a central portion adjacent to the first edge portion of the back surface 200b of the second substrate 200 be arranged.

The third pad area 230 According to one embodiment, a plurality of third pads (or input pads) which are arranged at a certain distance from one another along the first direction X. The plurality of third pads can be converted into a plurality of third data pads DP3 , a third pixel drive current pad PPP3 , a plurality of third gate pads GP3 and a plurality of third pixel common power pads CPP3 be subdivided (or classified).

The third pad area 230 according to an embodiment may have a third data pad area, a third pixel drive current pad area, a third gate pad area and a third pixel common current pad area.

The third pad area 230 may include a first area (or a central area) including the third data pad area and the third pixel drive current pad area, a second area (or area) including the third gate pad area, and a third area (or the other area) having the third pixel common current pad area.

The third data pad area can pass through the connecting line section 250 electrically to the second data pad area of the second pad area 210 be connected.

The third data pad area according to an embodiment can have a plurality of third data pads DP3. The plurality of third data pads DP3 can be parallel in the first direction X in a first area of the third pad area 230 be arranged at a certain distance from each other.

Each of the plurality of third data pads DP3 according to one embodiment, through the connecting line section 250 with a corresponding second data pad DP2 from the plurality of second data pads DP2 that are in the second pad area 210 are arranged, individually (or each) connected. Each of the plurality of third data pads DP3 can from the control IC 530 the drive circuit unit 500 a data signal can be supplied. According to one embodiment, the data signal can be transmitted through a corresponding third data pad DP3 from a plurality of third data pads DP3 and the connecting line section 250 each of the plurality of second data pads DP2 residing in the second pad area 210 are arranged to be fed.

The third pixel drive current pad area can pass through the connection line section 250 at a certain distance from the second pixel drive current pad area of the second pad area 210 be connected.

The third pixel drive current pad area according to an embodiment may have a plurality of third pixel drive current pads PPP3 exhibit. The plurality of third pixel drive current pads PPP3 can be parallel along the first direction X in a first area of the third pad area 230 be arranged at a certain distance from each other.

Each of the plurality of third pixel drive current pads PPP3 according to one embodiment, through the connecting line section 250 with a corresponding second pixel drive current pad PPP2 the plurality of second pixel drive current pads PPP2 that are in the second pad area 210 are arranged, individually (or each) connected. For example, each of the plurality of third pixel drive current pads PPP3 from the control IC 530 the drive circuit unit 500 a pixel drive current can be supplied. The pixel drive current according to an embodiment can be through a corresponding third pixel drive current path PPP3 the plurality of third pixel drive current pads PPP3 and the connecting line section 250 each of the plurality of second pixel drive current pads PPP2 that are in the second pad area 210 are arranged to be fed.

The plurality of third data pads DP3 and the plurality of third pixel drive current pads PPP3 can in the first area of the third pad area 230 in parallel in the same order as the arrangement order of the plurality of second data pads DP2 and the plurality of second pixel drive current pads PPP2 that are in the second pad area 210 are arranged, be arranged.

The third gate pad region can pass through the connecting line section 250 with the second gate pad area of the second pad area 210 be electrically connected.

The third gate pad area according to an embodiment may have a plurality of third gate pads GP3 exhibit. The plurality of third gate pads GP3 can be parallel along the first direction X in a second area of the third pad area 230 be arranged in parallel at a certain distance from each other.

Each of the plurality of third gate pads GP3 according to one embodiment, through the connecting line section 250 with a corresponding second gate pad GP2 from the plurality of second gate pads GP2 that are in the second pad area 210 are arranged, individually (or each) connected. For example, can each of the plurality of third gate pads GP3 from the timing control 570 the drive circuit unit 500 a gate control signal can be supplied. According to one embodiment, the gate control signal can be passed through a corresponding third gate pad GP3 of the plurality of third gate pads GP3 and the connection line section 240 each of the plurality of second gate pads GP2 located in the second pad area 210 are arranged to be fed.

The plurality of third gate pads GP3 according to an embodiment may be divided (or classified) into a third start signal pad, a plurality of third shift clock pads, at least one third gate drive current pad and at least one third gate common current pad.

The third start signal pad can be through the connecting line section 250 electrically with the second start signal pad that is in the second pad area 210 is arranged to be connected. For example, the third start signal pad from the timing control 570 the drive circuit unit 500 a start signal (or a start pulse) can be supplied. According to one embodiment, the start signal can be generated by a corresponding start signal pad from the plurality of third start signal pads and the connecting line section 250 the second start signal pad that is in the second pad area 210 is arranged to be fed.

Each of the plurality of third shift clock pads can pass through the connection line section 250 electrically to a corresponding second shift clock pad from the plurality of second shift clock pads located in the second pad area 210 are arranged to be connected. For example, each of the plurality of third shift clock pads can be controlled by the timing controller 570 the drive circuit unit 500 can be supplied to one of a plurality of gate shift clocks. Each of the plurality of gate shift clocks according to an embodiment can be passed through a corresponding third shift clock pad of the plurality of third shift clock pads and the connection line section 250 the second shift clock pad that is in the second pad area 210 is arranged to be fed.

The at least one gate drive current path can pass through the connecting line section 250 electrically to the at least one second gate drive current pad located in the second pad area 210 is arranged to be connected. For example, the at least one third gate drive current path from the drive current unit 590 the drive circuit unit 500 a gate drive current can be supplied. According to an embodiment, the gate drive current can flow through a corresponding third gate drive current pad from the plurality of third gate drive current pads and the connecting line section 250 the second gate drive current pad located in the second pad area 210 is arranged to be fed.

The at least one third gate common power pad can pass through the connecting line section 250 electrically to the at least one second gate common power pad located in the second pad area 210 is arranged to be connected. For example, the at least one third gate common power pad from the power circuit unit 590 the drive circuit unit 500 a gate common current can be supplied. The gate common current according to an embodiment can pass through a corresponding third gate common current pad of the plurality of third gate common current pads and the connecting line section 250 the second gate common power pad that is in the second pad area 210 is arranged to be fed.

The third pixel-shared-stream pad area may have at least one third pixel-shared-stream pad CPP3 exhibit. The at least one third pixel-shared-stream pad CPP3 can in a third area of the third pad area 230 be arranged.

The at least one third pixel-shared-stream pad CPP3 can through the connecting line section 250 with a corresponding second pixel-shared-stream pad CPP2 that is in the second pad area 210 is arranged, individually (or each) connected. For example, the at least one third pixel-common-current pad CPP3 from the power circuit unit 590 the drive circuit unit 500 a common pixel stream can be supplied. The pixel-shared stream according to an embodiment can be passed through a corresponding third pixel-shared stream pad CPP3 of the plurality of third pixel common power pads CPP3 and the connecting line section 250 each of the plurality of second pixel common power pads CPP2 that are in the second pad area 210 are arranged to be fed.

The third pad area 230 can further include a first dummy area which is arranged between the first area and the second area and has a plurality of dummy pads, and a second dummy area which is arranged between the first area and the third area and a plurality of dummy pads.

The third pad area 230 according to one embodiment can furthermore have a third reference current pad area.

The third reference current pad area can pass through the connecting line section 250 electrically to the second reference current pad area of the second pad area 210 be connected.

The third reference current pad area according to an embodiment can have a plurality of third reference current pads RPP3 exhibit. The plurality of third reference current pads RPP3 can be parallel along the first direction X in the first area of the third pad area 230 be arranged at a certain distance from each other.

Each of the plurality of third reference current pads RPP3 according to one embodiment, through the connecting line section 250 with a corresponding second reference current pad RPP2 from the plurality of second reference current pads RPP2 that are in the second pad area 210 are arranged, individually (or each) connected. For example, each of the plurality of third reference current pads RPP3 from the control IC 530 the drive circuit unit 500 a reference current can be supplied. The reference current according to one embodiment can be through a corresponding third reference current path RPP3 from the plurality of third reference current pads RPP3 and the connecting line section 250 each of the plurality of second reference current pads RPP2 that are in the second pad area 210 are arranged to be fed.

Each of the plurality of third pixel drive current pads PPP3 , the plurality of third data pads DP3 and the plurality of third reference current pads RPP3 in the first area of the third pad area 230 may be in the same order as the arrangement order of the plurality of second pixel drive current pads PPP2 , the plurality of second data pads DP2 and the plurality of second reference current pads RPP2 that are in the second pad area 210 are arranged, be arranged in parallel.

The connecting line section 250 can be between the second pad area 210 and the third pad area 230 be arranged. The connecting line section 250 may have a plurality of connection lines that connect the second pads of the second pad area 210 individually (or in each case) with the third pads of the third pad area 230 connect, exhibit.

The plurality of connection lines according to one embodiment can be converted into a plurality of data connection lines 251 , a plurality of gate interconnection lines 253 , a plurality of pixel drive current connection lines 255 and a pixel common power connection line 257 be subdivided (or classified). Therefore, the connecting line section 250 a plurality of data links 251 , a plurality of gate interconnection lines 253 , a plurality of pixel drive current connection lines 255 and a pixel common power connection line 257 exhibit.

According to a further embodiment, the connecting line section 250 a data connection section, a gate connection section, a pixel drive current connection section, and a pixel common current connection section.

The data connection section (or a first connection section) can be the second data pad area of the second pad area 210 electrically to the third data pad area of the third pad area 230 associate.

The data connection section according to an embodiment can have a plurality of data connection lines 251 exhibit. Each of the plurality of data connection lines (or first connection lines) 251 can be a corresponding second data pad of the plurality of second data pads DP2 that are in the second pad area 210 are arranged, with a corresponding third data pad of the plurality of third data pads DP3 that is in the third pad area 230 are arranged, individually (or each) connect. Accordingly, a data signal sent to each of the plurality of third data pads DP3 is supplied, through a corresponding data connection line 251 a corresponding second data pad DP2 and can be fed through an appropriate data wiring line 410 and a corresponding first data pad DP1 corresponding data line DLo and DLe are fed.

The gate connection section (or a second connection section) may be the second gate pad region of the second pad region 210 electrically to the third gate pad area of the third pad area 230 associate.

The gate connection section according to an embodiment may have a plurality of gate connection lines 253 exhibit. Each of the plurality of gate interconnection lines (or second interconnection lines) 253 may be a corresponding second gate pad of the plurality of second gate pads GP2 that are in the second pad area 210 are arranged, with a corresponding third gate pad of the plurality of third gate pads GP3 that is in the third pad area 230 are arranged, individually (or each) connect. Accordingly, a gate control signal applied to each of the plurality of third gate pads GP3 is supplied through a corresponding gate connection line 253 a corresponding second gate pad GP2 and can be fed through an appropriate gate wiring line 430 and a corresponding first gate pad GP1 a corresponding gate connection line included in the gate control line group GCL is included.

The plurality of gate interconnection lines 253 according to one embodiment, in a start signal connecting line 253a , a plurality of shift clock connection lines 253b , at least one gate drive power connection line 253c and at least one gate common power connection line 253d be subdivided (classified). Accordingly, the gate connection portion can be the start signal connection line 253a , the plurality of shift clock connection lines 253b that have at least one gate drive power connection line 253c and the at least one gate common power connection line 253d exhibit.

The start signal connection line 253a can be the second start signal pad that is in the second pad area 210 is arranged, electrically with the third start signal pad, which is in the third pad area 230 is arranged to connect. Accordingly, a start signal that is fed to the third start signal pad can be fed to the second start signal pad through the start signal connecting line, and can be fed through the start signal wiring line and the first start signal pad to a corresponding start signal line included in the gate control line group GCL.

Each of the plurality of shift clock connection lines 253b may be a corresponding second shift clock pad of the plurality of second shift clock pads located in the second pad area 210 are arranged electrically with a corresponding third shift clock pad of the plurality of third shift clock pads that are in the third pad area 230 are arranged, connect. Accordingly, a gate shift clock supplied to each of the plurality of third shift clock pads can be passed through a corresponding shift clock connection line 253b a corresponding second shift clock pad and can be supplied through the shift clock wiring line and the first shift clock pad to a corresponding shift clock line included in the gate control line group GCL.

The at least one gate drive power connection line 253c may include the at least one second gate drive current pad located in the second pad area 210 is arranged, electrically with the at least one third gate drive current pad, which is in the third pad area 230 is arranged to connect. Accordingly, a gate drive current supplied to the third gate drive current pad can be passed through the gate drive current connection line 253c may be supplied to the second gate drive current path and may be supplied through the gate drive current wiring line and the first gate drive current path to the gate drive current line included in the gate control line group GCL.

The at least one gate common power connection line 253d may include the at least one second gate common current pad located in the second pad area 210 is arranged, electrically with the at least one third gate common current pad, which is in the third pad area 230 is arranged to connect. Accordingly, a gate common current supplied to the third gate common current pad can be passed through the gate common current connection line 253d to the second gate common power pad and can be supplied through the gate common power wiring line and the first gate common power pad to the gate common power line included in the gate control line group GCL , respectively.

The pixel drive current connection portion (or a third connection portion) may be the second pixel drive current pad area of the second pad area 210 electrically to the third pixel drive current pad area of the third pad area 230 associate.

The pixel drive current connection section according to an embodiment may have a plurality of pixel drive current connection lines 255 exhibit. Each of the plurality of pixel drive current connection lines (or third connection lines) 255 may the plurality of second pixel drive current pads PPP2 that are in the second pad area 210 are arranged with the plurality of third pixel drive current pads PPP3 that is in the third pad area 230 are arranged, individually (or each) connect. Accordingly, a pixel drive current supplied to each of the plurality of third pixel drive current pads PPP3 is supplied through a corresponding pixel drive current connection line 255 a corresponding second pixel drive current pad PPP2 and can be fed through the pixel drive power wiring line 450 and the first pixel drive current pad PPP1 a corresponding pixel drive power line PL are fed.

The plurality of data links 251 , the plurality of gate interconnects 253 and the plurality of pixel drive current connection lines 255 can each have a first line section that connects to the second pad area 210 is connected, a second line section which is connected to the third pad area 230 is connected, and a third line section, which is connected between the first line section and the second line section, have. Each of the first pipe section and the second pipe section may have a straight-line shape, and the third pipe section may have a non-straight-line shape. For example, the third line section can have a diagonal shape which corresponds to a shortest path between the first line section and the second line section.

The pixel-common-current connecting portion (or a fourth connecting portion) may be the second pixel-common-current pad area of the second pad area 210 with the third pixel-shared power pad area of the third pad area 230 connect electrically.

The pixel-common power connection section according to an embodiment may be a pixel-common power connection line 257 exhibit. Each of the plurality of pixel common power connection lines (or fourth connection lines) 257 may include the plurality of second pixel-common-flow pads CPP2 located in the second pad area 210 are arranged with the plurality of third pixel common power pads CPP3 that is in the third pad area 230 are arranged to connect together. Correspondingly, a pixel-shared-stream flowing from each of the at least one third pixel-shared-stream pad CPP3 is supplied through the pixel common power connection line 257 the plurality of second pixel common power pads CPP2 are supplied through a corresponding one of the plurality of pixel common power wiring lines 470 and a corresponding first pixel common power pad of the plurality of first pixel common power pads CPP1 each of the plurality of pixel common power lines CPL and through each of the plurality of common current contact portions CPCP the common electrode CE are fed.

The Pixel Common Power Link 254 According to one embodiment, a first common connecting line 257a , a second common connection line 257b and a plurality of third common connection lines 257c exhibit.

The first common connection line 257a can with the at least one third pixel-shared-stream pad CPP3, which is in the third pad area 230 is arranged to be connected together. For example, the first common connecting line 257a at a corner portion of the back surface 200b of the second substrate 200 be arranged.

The first common connection line 257a can in this way between the second pad area 210 and the third pad area 230 on the back surface 200b of the second substrate 200 be arranged to have a relatively wide size (or area) so that the voltage drop of the pixel common current applied thereto is minimized. A size of the first common connection line 257a according to one embodiment it may gradually increase in a direction from one side thereof to the other side thereof. For example, a size of the first common connecting line 257a according to one embodiment in a direction from the third pad area 230 to the outer surface OS of the second substrate 200 gradually increase.

In the first common connection line 257a According to one embodiment, a side thereof that adjoins the third pad area 230 adjacent to the at least one third pixel-shared-stream pad CPP3 that is in the third pad area 32 is arranged to be connected together, and the other side thereof that is attached to the second pad area 210 adjacent, the second common connection line 257b overlap. For example, the first common connecting line 257a on the back surface 200b of the second substrate 200 together with the data connection line 251 or the gate connection line 253 be arranged.

The second common connection line 257b may on the first edge portion of the back surface 200b of the second substrate 200 be arranged such that they the first edge portion of the first substrate 100 overlapped and to the second pad area 210 adjoins. The second common connection line 257b According to one embodiment, it can be arranged parallel to the first direction X in such a way that all pads that are in the second pad area 210 are arranged opposite. For example, the second common connecting line 257b have a rod shape that is relatively wide in size (or area) to minimize the voltage drop of the Pixel-common-voltage, which is applied to the pixel-common-current connection line 257 is created.

The second common connection line 257b may be any of the plurality of pixel drive current connection lines 255 , the plurality of data connection lines 251 and the plurality of gate interconnects 253 overlap. For example, the data connection line 251 on the gate interconnect 253 be arranged, and the second common connecting line 257b can be on the pixel drive power connection line 255 be arranged. Likewise, the pixel drive current connection line 255 on the gate interconnect 253 together with the data connection line 251 be arranged.

One side of the second common connection line 257b can through a connection contact hole 257h electrically to the other side of the first common connection line 257a be connected.

Each of the plurality of third common connection lines 257c can with the second common connection line 257b be connected in common and can be connected to a corresponding second pad from the plurality of second pads. Each of the plurality of third common connection lines 257c According to one embodiment, the second common connection line can extend in one direction from the other side 257b to the plurality of second pixel common power pads CPP2 that are in the second pad area 210 disposed, extending (or protruding) and electrically connected to a corresponding second pixel common power pad of the plurality of second pixel common power pads CPP2 be connected. For example, each of the plurality of third common connection lines 257c together with the second common connection line 257b be educated. Likewise, the plurality of third common connecting lines 257c and the second common connection line 257b together with the pads of the second pad area 210 be educated.

The connecting line section 250 according to one embodiment can furthermore have a reference current connection section.

The reference current connection section (or a fifth connection section) may be the second reference current pad area of the second pad area 210 electrically to the third reference current pad area of the third pad area 230 associate.

The reference current connection section according to an embodiment may have a plurality of reference current connection lines 259 exhibit. Each of the plurality of reference current connection lines (or fifth connection lines) 259 may be a corresponding second reference current pad of the plurality of second reference current pads RPP2 located in the second pad area 210 are arranged, with a corresponding third reference current pad of the plurality of third reference current pads RPP3, which are in the third pad area 230 are arranged, individually (or each) connect. Therefore, a reference voltage supplied to each of the plurality of third reference current pads RPP3 can be supplied through a corresponding reference current connection line 259 a corresponding second reference current pad RPP2 and can be supplied through the reference current wiring line 490 and the first reference current pad RPP1 are fed to a corresponding reference current line RL.

The plurality of reference current connection lines 259 can each have a first line section connected to a corresponding second reference current path RPP2 is connected, a second line section which is connected to the third reference current path RPP3 is connected, and a third line section, which is connected between the first line section and the second line section, have. Each of the first pipe section and the second pipe section may have a straight-line shape, and the third pipe section may have a non-straight-line shape. For example, the third line section can have a diagonal shape which corresponds to a shortest path between the first line section and the second line section.

The connecting line section 250 according to an embodiment, it may further comprise a gate control signal transmission section 254 exhibit.

The gate control signal transmission section (or a sixth connection section) 254 can use the third pad area 230 and can electrically connect the third gate pad region to the gate connecting portion.

The gate control signal transmission section 254 in accordance with an embodiment may include a plurality of gate control signal transmission lines.

Each of the plurality of gate control signal transmission lines (or sixth connection lines) may be a corresponding one of the plurality of third gate pads GP3 that is in the third pad area 230 are arranged, selectively connect to a corresponding gate interconnection line of the plurality of gate interconnection lines. For example, the plurality of gate control signal transmission lines and the plurality of gate connection lines may be 253 on the back surface 200b of the second substrate 200 may be disposed on different layers, and a corresponding side of each of the plurality of gate interconnects 253 may be electrically connected to a corresponding gate control signal transmission line through a connection via. Optionally, the other side of each of the plurality of gate interconnection lines can be 253 pass through an area between two adjacent third pads and may be selectively connected to a plurality of gate control signal transmission lines so as to interfere with the third pad located in the third pad area 230 is arranged, not overlapped.

The plurality of gate control signal transmission lines according to an embodiment can be integrated into a start signal transmission line 254a , a plurality of shift clock transmission lines 254b , at least one gate drive current transmission line 254c and at least one gate common power transmission line 254d be subdivided (classified). Therefore, the gate control signal transmission section 254 the start signal transmission line 254a , the plurality of shift clock transmission lines 254b that are at least one gate drive current transmission line 254c and the at least one gate common power transmission line 254d exhibit.

The start signal transmission line 254a the third start signal pad can be electrically connected to the start signal connecting line 253a associate. The start signal transmission line 254a According to one embodiment, one line section thereof, which is electrically connected to the third start signal pad, the other line section thereof, which is electrically connected to the start signal connecting line 253a is connected, and a middle line section which is electrically connected between the one line section thereof and the other line section thereof that it is the third pad region 230 bypasses.

The one line section of the start signal transmission line 254a can be arranged parallel to the second direction Y and can be electrically connected to the third start signal pad.

The other line section of the start signal transmission line 254a can be arranged in such a way that it is attached to the third pad area 230 parallel to the first direction X and can be electrically connected to the start signal connecting line 253a be connected. For example, the other line section can be the start signal transmission line 254a electrically to the start signal connection line through a connection contact hole 253a be connected. Therefore, a start signal supplied to a third start signal pad can pass through the start signal transmission line 254a , the start signal connection line 253a , the second start signal pad, the start signal wiring line and the first start signal pad are supplied to the start signal line included in the gate control line group GCL.

The middle section of the start signal transmission line 254a may have a first middle line extending from the one line section parallel to the first direction X, and a second middle line extending from the first middle line so as to be from one end (or a left end) of the third pad region 230 is arranged remotely and is electrically connected to the other line section. For example, the middle line section can have a "⌜" shape, the third pad area 230 bypasses.

The start signal connection line 253a according to one embodiment, through the third pad area 230 pass through and can be electrically connected to the other line section of the start signal transmission line 254a be connected. For example, the start signal connecting line 253a be arranged in such a way that it passes through an area between two adjacent third pads in such a way that it connects to the third pad that is in the third pad area 230 is arranged, not overlapped. In this case, a start signal can be sent to the start signal connecting line 253a is supplied does not vary (or change) based on a signal supplied to the third pad and can be maintained at an original voltage level.

Each of the plurality of shift clock transmission lines 254b may selectively connect a corresponding third shift clock pad of the plurality of shift clock pads with a corresponding shift clock connection line of the plurality of shift clock connection lines 253b associate. For example, when the gate control signal transmission section 254 a first shift clock transmission line to fourth shift clock transmission line 254b and the line connecting portion 250 a plurality of first shift clock connection lines to fourth shift clock connection lines 253b each of the plurality of first shift clock connection lines 253b with the first shift clock transmission line 254b together be connected, each of the plurality of second shift clock connection lines 253b can with the second shift clock transmission line 254b be connected in common, each of the plurality of third shift clock connection lines 253b can with the third shift clock transmission line 254b be connected in common, and each of the plurality of fourth shift clock connection lines 253b can with the fourth shift clock transmission line 254b be connected together.

Each of the plurality of shift clock transmission lines 254b may have a shape that the start signal transmission line 254a surrounds and can thus be parallel to the start signal transmission line 254a be arranged that they the third pad area 230 bypasses. Each of the plurality of shift clock transmission lines 254b According to one embodiment, one line section thereof which is electrically connected to a corresponding third shift clock pad, the other line section thereof which is electrically connected to a corresponding shift clock connection line 253b is connected, and a middle line section which is electrically connected between one line section thereof and the other line section thereof, that it is the third pad area 230 bypasses. For example, the other line portion may be of each of the plurality of shift clock transmission lines 254b through a connection contact hole electrically to a corresponding shift clock connection line 253b be connected. Therefore, a gate shift clock supplied to each of the plurality of third shift clock pads can be passed through a corresponding shift clock transmission line 254b , a corresponding shift clock connection line 253b , a corresponding second shift clock pad, a corresponding gate shift clock wiring line, and a corresponding first shift clock pad are supplied to the shift clock line included in the gate control line group GCL.

Each of the plurality of shift clock connection lines 253b according to one embodiment, through the third pad area 230 pass through and can be electrically connected to the other line section of a corresponding shift clock transmission line 254b be connected. For example, each of the plurality of shift clock connection lines may 253b be arranged in such a way that it passes through an area between two adjacent third pads in such a way that it passes the third pad in the third pad area 230 is arranged, not overlapped. In this case, a gate shift clock that is each of the plurality of shift clock connection lines 253b is supplied does not vary (or change) based on a signal supplied to the third pad and can be maintained at an original voltage level.

The at least one gate drive power transmission line 254c At least one gate drive current path may be electrically connected to at least one gate drive current connection line 253c associate.

The at least one gate drive power transmission line 254c may have a shape that is an outermost shift clock transmission line 254b surrounds and can thus be parallel to the shift clock transmission line 254b be arranged that they the third pad area 230 bypasses. The at least one gate drive power transmission line 254c According to one embodiment, one line portion thereof electrically connected to the third gate drive current pad, the other line portion thereof electrically connected to the gate drive current connection line 253c is connected, and a middle line section which is electrically connected between one line section thereof and the other line section thereof, that it is the third pad area 230 bypasses. For example, the other line portion of the at least one gate drive current transmission line may be 254c electrically to the gate drive current connection line through a connection contact hole 253c be connected. Therefore, a gate drive current supplied to the at least one gate drive current pad can pass through the gate drive current transmission line 254c , the gate drive current connection line 253c , the second gate drive current path, the gate drive current wiring line, and the first gate drive current path are supplied to the gate drive current line included in the gate control line group GCL.

The at least one gate drive power connection line 253c according to one embodiment, through the third pad area 230 and can be electrically connected to the other line portion of the gate drive current transmission line 254c be connected. For example, the at least one gate drive current connection line may be 253c be arranged in such a way that it passes through an area between two adjacent third pads in such a way that it encounters the third pad in the third pad area 230 is arranged, not overlapped. In this case, a gate drive current flowing from the gate drive current connection line 273c is supplied based on a signal that the third Pad supplied does not vary (or change) and can be maintained at an original voltage level.

The at least one gate common power transmission line 254d the at least one gate common power pad may be electrically connected to the at least one gate common power connection line 253d associate.

The at least one gate common power transmission line 254d may have a shape that is the gate drive current transmission line 254c surrounds and may so in parallel with the gate drive current transmission line 254c be arranged that they the third pad area 230 bypasses. The at least one gate common power transmission line 254d According to one embodiment, one line portion thereof that is electrically connected to the third gate common power pad, the other line portion thereof that is electrically connected to the gate common power connection line 253d is connected, and a middle line section which is electrically connected between one line section thereof and the other line section thereof, that it is the third pad area 230 bypasses. For example, the other line section of the at least one gate common power transmission line 254d electrically to the gate common power connection line through a connection contact hole 253d be connected. Therefore, a gate common power supplied to the at least one gate common power pad can pass through the gate common power transmission line 254d who have favourited the Gate Common Power Interconnect 253d , the second gate common power pad, the gate common power wiring line, and the first gate common power pad are supplied to the gate common power line included in the gate control line group GCL .

The at least one gate common power connection line 253d according to one embodiment, through the third pad area 230 pass through and can be electrically connected to the other line portion of the gate common power transmission line 254d be connected. For example, the at least one gate common power connection line 253d be arranged in such a way that it passes through an area between two adjacent third pads in such a way that it encounters the third pad in the third pad area 230 is arranged, not overlapped. In this case, a gate common current may be that of the gate common current connecting line 253d is supplied does not vary (or change) based on a signal supplied to the third pad and can be maintained at an original voltage level.

11 is an equivalent circuit diagram that contains an in 7th i-th stage circuit unit illustrated.

Referring to 6th until 8th and 11 can be an i-th stage circuit unit 150i according to the present disclosure in response to a gate control signal received from a gate control line group GCL residing on the first substrate 100 is arranged, is supplied, output two scanning signals SSi and SSi + 1 and a carrier signal CSi.

The gate control signal according to an embodiment may include a start signal Vst, a plurality of shift clocks, which have a plurality of sampling clocks sCLK and a plurality of carrier clocks cCLK, a first gate drive current to third gate drive current GVdd1, GVdd2 and GVdd3 and a first gate -Gate common current GVss1 and a second common gate current GVss2. In this case, the gate control line group GCL a start signal line, a plurality of scan clock lines, a plurality of carrier clock lines, a first gate drive power line to a third gate drive power line, and a first gate common power line and a second gate common power line.

The gate control signal according to an embodiment may have first through j-th carrier clocks and first through j-th sampling clocks. For example, j can be, but is not limited to, 4, and can be an even number of 6, 8, or 10 or more.

If the gate control signal has the first carrier clock to fourth carrier clock, the first carrier clock can be applied to a 4k-3-th (where k is a natural number) stage circuit unit, the second carrier clock can be applied to a 4k-2-th stage circuit unit The third carrier cycle can be applied to a 4k-1-th stage circuit unit, and the fourth carrier cycle can be applied to a 4k-th stage circuit unit. When the gate control signal has the first sampling clock to the fourth sampling clock, the first sampling clock and the second sampling clock can be applied to an odd stage circuit unit, and the third sampling clock and the fourth sampling clock can be applied to an even stage circuit unit.

Furthermore, according to one embodiment, the gate control signal can furthermore have a forward control signal FWS and a reverse control signal BWS. In this case the gate control line group GCL may further include a forward drive signal line and a reverse drive signal line.

The gate control signal according to an embodiment may further comprise an external detection line selection signal Slss, an external detection reset signal Srst and an external detection control signal Scs for an external detection mode. In this case, the gate control line group GCL may further include an external detection selection signal line, an external detection reset signal line, and an external detection control signal line.

The i-th stage circuit unit 150i in accordance with the present disclosure, a branch network 153 , a node control unit NCC, a first inverter circuit IC1, a second inverter circuit IC2, a node reset circuit NRC and an output latch circuit OBC.

The branch network 153 can be designed such that it forms a circuit connection between the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC and the output latch circuit OBC and that it is selectively connected to the lines of the gate control line group GCL connected is.

The branch network 153 may be selectively connected to the lines of the gate control line group GCL. The branch network 153 According to one embodiment, it can have a first control node to third control nodes Q, QBo and QBe and a network line NL.

Each of the first control node to the third control node Q, QBo and QBe may be located in an upper edge area (or a lower edge area) of each of the pixel areas included in an i-th horizontal line of the first substrate 100 are arranged, be arranged. Each of the first control node to third control nodes Q, QBo and QBe may be arranged in parallel with a first direction X or a gate line. For example, each of the first control node to third control nodes Q, QBo and QBe can be arranged adjacent to the gate line.

The network line NL can be selectively connected to the lines of the gate control line group GCL and can be selectively connected to the first control node to third control nodes Q, QBo and QBe. Likewise, the network line NL can selectively between circuits that the stage circuit unit 150i set up, be switched.

The node control circuit NCC may be configured to control a voltage of each of the first control node to third control nodes Q, QBo and QBe.

The node control circuit NCC according to an embodiment may be connected to each of the first control node to the third control node Q, QBo and QBe through the network line NL and may be designed to be operated in response to the start signal Vst, the reset signal Vrst and the first gate Driving current GVdd1, which is supplied through the network line NL, controls the voltage of each of the first control node to third control nodes Q, QBo and QBe. For example, the start signal can be an i-2-th carrier signal CSi-2, which is output by the i-2-th stage circuit unit 150i-2. The reset signal Vrst may be an i + 2-th carrier signal CSi + 2 output from an i + 2-th stage circuit unit 150i + 2.

According to a further embodiment, the node control circuit NCC can be connected by the network line NL to each of the first control node to the third control node Q, QBo and QBe and, in response to the start signal Vst, the reset signal Vrst, the forward control signal FWS, the reverse Control signal BWS and the first gate control current GVdd1, which are fed through the network line NL, control. For example, if the forward control signal FWS has a high voltage level (or a high potential voltage level), the reverse control signal BWS can have a low voltage level (or a low potential voltage level), and if the forward control signal FWS has a low voltage level (or a low Has potential voltage level), the reverse activation signal BWS can have a high voltage level (or a high potential voltage level). For example, when the forward drive signal FWS has a high voltage level, the gate drive circuit can 150 on the basis of forward scan control, supply a scan signal up to a last gate line from a first gate line, and when the backward control signal BWS has a high voltage level, the gate control circuit 150 supply the scan signal up to the first gate line from the last gate line based on backward scan driving. Here, a high voltage level can be referred to as a first voltage level, a high potential voltage level, a gate-on voltage level or a transistor-on-voltage level, and a low voltage level can be referred to as a second voltage level, a low one Potential voltage level, a gate switch-off voltage level or a transistor-off voltage level are designated.

The first inverter circuit IC1 can control or discharge the voltage of the second control node QBo based on the voltage of the first control node Q. The first inverter circuit IC1 according to one embodiment can be connected to the second gate drive current GVdd2, the first control node Q, the second control node QBo, the first gate common current GVss1 and the second gate common current GVss2 through the network line NL. In response to the second gate drive current GVdd2 and the voltage of the first control node Q, the first inverter circuit IC1 may supply the first gate common current GVss1 to the second control node QBo to discharge the voltage of the second control node QBo.

The second inverter circuit IC2 can control or discharge the voltage of the third control node QBe based on the voltage of the first control node Q. The second inverter circuit IC2 according to one embodiment can be connected to the third gate drive current GVdd3, the first control node Q, the third control node QBe, the first gate common current GVss1 and the second gate common current GVss2 through the network line NL. In response to the third gate drive current GVdd3 and the voltage of the first control node Q, the second inverter circuit IC2 may supply the first gate common current GVss1 to the third control node QBe to discharge the voltage of the third control node QBe.

The second gate drive current GVdd2 and the third gate drive current GVdd3 may have voltage levels that are inverted (or opposite to each other) therebetween. For example, if the second gate drive current GVdd2 has a high voltage level, the third gate drive current GVdd3 can have a low voltage level, and if the second gate drive current GVdd2 has a low voltage level, the third gate drive current GVdd3 can have a high voltage level .

The second gate common current GVss2 and the first gate common current GVss1 can have the same voltage level or different voltage levels.

The node reset circuit NRC can maintain a voltage level of each of the second control node QBo and the third control node QBe while the voltage of the first control node Q is at a high voltage level.

The node reset circuit NRC according to an embodiment can reset the voltage of the second control node QBo and the voltage of the third control node QBe at the same time in response to the start signal Vst and the reset signal Vrst supplied through the network line NL. For example, the node reset circuit NRC can supply the first gate common current GVss1 to the second control node QBo and the third control node QBe in response to the start signal Vst and the reset signal Vrst, and thus can the second control node QBo and the third control node QBe at a voltage level of the first Gate common current GVss1 maintained.

According to a further embodiment, the node reset circuit NRC in response to the start signal Vst, the reset signal Vrst, the forward control signal FWS and the reverse control signal BWS, which are fed through the network line NL, the voltage of the second control node QBo and the voltage of the third Reset control node QBe at the same time. For example, in response to the start signal Vst, the reset signal Vrst, the forward drive signal FWS and the reverse drive signal BWS, the node reset circuit NRC can supply the first gate common current GVss1 to the second control node QBo and the third control node QBe, and thus can either of the second control node QBo and the third control node QBe are maintained at a voltage level of the first gate common current GVss1.

The output latch circuit OBC may be configured to respond to the voltage of each of the first control node to third control nodes Q, QBo and QBe on the basis of the carrier clock cCLK, the sampling clock sCLK, the first gate common current GVss1 and the third gate common current GVss3 supplied through the network line NL successively outputs two scanning signals having a gate-on voltage level or successively outputting two scanning signals having a gate-off voltage level.

When the voltage of the first control node Q has a high voltage level and the voltage of each of the second control node QBo and the third control node QBe has a low voltage level, the output latch circuit OBC according to one embodiment can store each of an i-th carrier signal CSi corresponding to the Carrier clock cCLK, an i-th Output sampling signal SSi corresponding to an odd-numbered sampling clock sCLKo and an i + 1-th sampling signal SSi + 1 corresponding to an even-numbered sampling clock sCLKe. For example, the i + 2-th stage circuit unit can be fed the i-th carrier signal CSi as the start signal Vst, the i-th sampling signal SSi can be fed to an odd-numbered gate line GLo (or an i-th gate line GLi), and the i + 1-th scan signal SSi + 1 can be fed to an even-numbered gate line GLe (or an i + 1-th gate line GLi + 1).

When the voltage of each of the first control node Q and the third control node QBe has a low voltage level and the voltage of the second control node QBo has a high voltage level, the output latch circuit OBC according to one embodiment can store each of the i-th sampling signal SSi and the i + 1-th sampling signal SSi + 1, each of which has a gate-off voltage level corresponding to a voltage level of the third gate common current GVss3, and can output the i-th carrier signal CSi which has a gate-off voltage level corresponding to a Having voltage level of the first common gate current GVss1, output.

When the voltage of each of the first control node Q and the second control node QBo has a low voltage level and the voltage of the third control node QBe has a high voltage level, the output latch circuit OBC can according to an embodiment each of the i-th scan signal SSi and the i + 1-th sampling signal SSi + 1, each of which has a gate-off voltage level corresponding to a voltage level of the third gate common current GVss3, and can output the i-th carrier signal CSi which has a gate-off voltage level corresponding to a Having voltage level of the first common gate current GVss1, output.

The output buffer circuit OBC according to one embodiment can be arranged in a central area of the i-th horizontal line parallel to the first direction X. For example, when the output latch circuit OBC is disposed adjacent to one end (or the other end) of a horizontal line, a voltage level of the scanning signal may decrease due to a line resistance of a horizontal line in a direction from one end of a gate line to the other end thereof, and thus, in order to prevent such a problem, the output latch circuit OBC should be arranged in the central area of the i-th horizontal line parallel to the first direction X, but is not limited to this, and may be on one side or the other of the i-th horizontal row can be arranged when a total length of the gate line is relatively short.

The first gate common current to the third gate common current GVss1, GVss2 and GVss3 can have the same voltage level or different voltage levels.

The i-th stage circuit unit 150i according to the present disclosure may further comprise a fourth control node Qm, a first determination control circuit SCC1 and a second determination control circuit SCC2.

The fourth control node Qm can be implemented in such a way that it is electrically connected between the first determination control circuit SCC1 and the second determination control circuit SCC2. The fourth control node Qm can be in the branch network 153 and can be electrically connected between the first determination control circuit SCC1 and the second determination control circuit SCC2 through the network line NL.

The first detection control circuit SCC1 may be configured to read a voltage from each of the first control node Q and the fourth control node Qm in response to the i-th carrier signal CSi, the external detection line selection signal Slss, the external detection control signal Scs, the external detection reset signal Srst and the first gate drive current GVdd1 passing through the branch network 153 are fed controls. For example, the first detection control circuit SCC1 can load the first gate drive current GVdd1 into the fourth control node Qm in response to the i-th carrier signal CSi having a high voltage level and the external detection line selection signal Slss having a high voltage level then, in response to a voltage charged in the fourth control node Qm, the external detection control signal Scs having a high voltage level supplied during a pre-period of a vertical idle period, and the first gate drive current GVdd1 the voltage of the first Control node Q. Therefore, the output latch circuit OBC can each of the i-th carrier signal CSi corresponding to the carrier clock cCLK, the i-th sampling signal SSi corresponding to the odd-numbered sampling clock sCLKo and the i + 1-th sampling signal SSi + 1 corresponding to the even-numbered sampling clock sCLKe during the vertical Output idle period based on the voltage of the first control node Q.

In addition, the first determination control circuit SCC1 can determine the voltage of the first control node Q in response to the external Discovery reset signal Srst generated by the branch network 153 is fed, discharged. For example, the first detection control circuit SCC1, in response to the external detection reset signal Srst having a high voltage level supplied during a later period of the vertical idle period, the first control node Q to reset or initialize the voltage of the first control node Q, the first gate common -Supply current GVss1.

The second detection control circuit SCC2 may be configured to change the voltage of each of the second control node QBo and the third control node QBe in response to the voltage of the fourth control node Qm and the external detection reset signal Scs passed through the branch network 153 is supplied, discharges. For example, in response to the voltage of the fourth control node Qm being at a high voltage level and the external detection control signal Scs being at a high voltage level, the second determination control circuit SCC2 may each of the second control node QBo and the third control node QBe to simultaneously discharge the second control node QBo and of the third control node QBe supply the first gate common current GVss1.

12th FIG. 13 is an equivalent circuit diagram showing the node control circuit, the first inverter circuit, the second inverter circuit and the first detection control circuit shown in FIG 11 are shown, represents.

Referring to 11 and 12th For example, a node control circuit NCC according to an embodiment may have a first node control circuit NCC1 to a fourth node control circuit NCC4.

In the forward scan drive, the first node control circuit NCC1 can load a high voltage level of a forward drive signal FWS into a first control node Q in response to a start signal Vst which has a high voltage level and the forward drive signal FWS which has a high voltage level. Also, in the backward scan driving, the first node control circuit NCC1 can electrically provide a forward driving signal line having a low voltage level in response to the start signal Vst having a high voltage level and the forward driving signal FWS having a low voltage level connect to a first control node Q for discharging a voltage charged in the first control node Q to a low voltage level.

The first node control circuit NCC1 can be a first TFT T1 to third TFT T3 exhibit.

The first TFT T1 can output the forward control signal FWS to a first connection node Nc1 in response to the start signal Vst. For example, the first TFT T1 can be turned on based on the start signal Vst having a high voltage level, and can output the forward drive signal FWS supplied through the forward drive signal line to the first connection node Nc1.

The second TFT T2 can electrically connect the first connection node Nc1 to a first control node Q in response to the start signal Vst. For example, the second TFT T2 based on the start signal Vst, which has a high voltage level, can be turned on and the forward drive signal FWS generated by the first TFT T1 and the first connection node Nc1 is supplied to the first control node Q.

The third TFT T3 may output a first gate drive current GVdd1 supplied through a first gate drive power line to the first connection node Nc1 in response to a voltage of the first control node Q. For example, the third TFT T3 based on the voltage of the first control node Q, which has a high voltage level, can be turned on and the first gate drive current GVdd1 to the first connection node Nc1 between the first TFT T1 and the second TFT T2 transmitted, thereby preventing the voltage leakage of the first control node Q. For example, the third TFT T3 a voltage difference between a gate voltage of the second TFT T2 and the voltage of the first connection node Nc1 for turning off the second TFT T2 , which has been switched off based on the start signal Vst which has a low voltage level, and can thus increase the voltage drop of the first control node Q through the switched off second TFT T2 prevent, whereby the voltage of the first control node Q is stably maintained.

In the backward scan drive, the second node control circuit NCC2 can in response to a reset signal Vrst that a has a high voltage level, and the reverse drive signal BWS, which has a high voltage level, load a high voltage level of a reverse drive signal BWS into the first control node Q. Also, in the forward scan driving, the second node control circuit NCC2 can discharge a voltage charged in the first control node Q in response to the reset signal Vrst having a high voltage level and the reverse driving signal BWS having a low voltage level is to electrically connect a reverse drive signal line having a low voltage level to the first control node Q at a low voltage level.

The second node control circuit NCC2 according to an embodiment may be a fourth TFT T4 and a fifth TFT T5 exhibit.

The fourth TFT T4 can output the reverse drive signal BWS in response to the reset signal Vrst. For example, the fourth TFT T4 based on the reset signal Vrst having a high voltage level, and can output the reverse drive signal BWS, which is supplied through a reverse drive signal line, to a second connection node Nc2.

The fifth TFT T5 can electrically connect the second connection node Nc2 to the first control node Q in response to the reset signal Vrst. For example, the fifth TFT T5 based on the reset signal Vrst, which has a high voltage level, can be turned on and the reverse drive signal BWS generated by the fourth TFT T4 and the second connection node Nc2 is supplied to the first control node Q.

The second connection node Nc2 between the fourth TFT T4 and the fifth TFT T5 can be electrically connected to the first connection node Nc1. Therefore, the second connection node Nc2 through the third TFT T3 of the first node control circuit NCC1, the first gate drive current GVdd1 supplied through the first gate drive power line can be supplied. That's why the third TFT T3 of the first node control circuit NCC1, a voltage difference between a gate voltage of the fifth TFT T5 of the second node control circuit NCC2 and the voltage of the second connection node Nc2 to turn off the fifth TFT completely T5 , which has been switched off based on the reset signal Vrst having a low voltage level, and can thus increase the voltage drop (or the current leakage) of the first control node Q through the switched-off fifth TFT T5 prevent, whereby the voltage of the first control node Q is stably maintained.

The third node control circuit NCC3 can discharge the voltage of the first control node Q in response to a voltage of a second control node QBo. For example, the third node control circuit NCC3 for discharging the voltage of the first control node Q to the first gate common current line on the basis of a high voltage level of the second control node QBo can establish a current path between the first control node Q and a first gate common current line. Form leadership.

The third node control circuit NCC3 according to an embodiment can be a sixth TFT T6 and a seventh TFT T7 exhibit.

The sixth TFT T6 may supply the first gate common current GVss1 supplied through the first gate common current line to the second connection node Nc2 in response to the voltage of the second control node QBo. For example, the sixth TFT T6 can be turned on based on a high voltage level of the second control node QBo and can electrically connect the second connection node Nc2 to the first gate common power line.

The seventh TFT T7 can electrically connect the second connection node Nc2 to the first control node Q in response to the voltage of the second control node QBo. For example, the seventh TFT T7 can be switched on based on a high voltage level of the second control node QBo and can electrically connect the second connection node Nc2 to the first control node Q.

The seventh TFT T7 can be turned off based on a low voltage level of the second control node QBo and a voltage difference between a gate voltage of the turned off seventh TFT T7 and a voltage of the second connection node Nc2 may be based on the first gate drive current GVdd1 passed through the third TFT T3 of the first node control circuit NCC1 is supplied to the second connection node Nc2, thereby increasing the seventh TFT T7 , which is turned off based on the low voltage level of the second control node QBo, can be completely turned off based on the first gate drive current GVdd1 supplied through the second connection node Nc2. Accordingly, the voltage drop (or current leakage) of the first control node Q can be prevented by the third node control circuit NCC3 as the seventh TFT T7 is completely turned off, whereby the voltage of the first control node Q is stably maintained.

The fourth node control circuit NCC4 may, in response to a voltage of a third Control node QBe, the voltage of the first control node Q discharged. For example, the fourth node control circuit NCC4 for discharging the voltage of the first control node Q to the first gate common current line on the basis of a high voltage level of the third control node QBe can establish a current path between the first control node Q and the first gate common current. Form leadership.

The fourth node control circuit NCC4 according to an embodiment can be an eighth TFT T8 and a ninth TFT T9 exhibit.

The eighth TFT T8 may supply the first gate common current GVss1 supplied through the first gate common current line to the second connection node Nc2 in response to the voltage of the third control node QBe. For example, the eighth TFT T8 can be turned on based on a high voltage level of the third control node QBe and can electrically connect the second connection node Nc2 to the first gate common power line.

The ninth TFT T9 can electrically connect the second connection node Nc2 to the first control node Q in response to the voltage of the third control node QBe. For example, the ninth TFT T9 can be switched on based on a high voltage level of the third control node QBe and can electrically connect the second connection node Nc2 to the first control node Q.

The ninth TFT T9 can be turned off based on a low voltage level of the third control node QBe, and a voltage difference between a gate voltage of the turned off ninth TFT T9 and a voltage of the second connection node Nc2 may be based on the first gate drive current GVdd1 passed through the third TFT T3 of the first node control circuit NCC1 is supplied to the second connection node Nc2, thereby increasing the ninth TFT T9 that is turned off based on the low voltage level of the third control node QBe can be completely turned off based on the first gate drive current GVdd1 that is supplied to the second connection node Nc2. Accordingly, the voltage drop (or current leakage) of the first control node Q can be prevented by the fourth node control circuit NCC4 as the ninth TFT T9 is completely turned off, whereby the voltage of the first control node Q is stably maintained.

The first inverter circuit IC1 can discharge the voltage of the second control node QBo in response to the voltage of the first control node Q and a second gate drive current GVdd2. For example, the first inverter circuit IC1 for discharging the voltage of the second control node QBo to the first gate common current line on the basis of a high voltage level of the first control node Q can establish a current path between the second control node QBo and the first gate common current. Form leadership.

The first inverter circuit IC1 according to an embodiment may be a tenth TFT T10 to thirteenth TFT T13 and a first capacitor C1 exhibit.

The tenth TFT T10 can be turned on or off based on the second gate drive current GVdd2 and, when turned on, can output the second gate drive current GVdd2 having a high voltage level to a first internal node Ni1. The tenth TFT T10 According to one embodiment, a diode can be connected between the second gate drive current GVdd2 and the first internal node Ni1.

The eleventh TFT T11 can be turned on or off based on the voltage of the first control node Q and, when turned on, can discharge a voltage of the first internal node Ni1 to a second gate common power line.

The twelfth TFT T12 can be turned on or off based on the voltage of the first internal node Ni1 and, when turned on, can supply the second gate drive current GVdd2 to the second control node QBo.

The thirteenth TFT T13 can be turned on or off based on the voltage of the first control node Q and, when turned on, can supply the voltage of the second control node QBo to the first gate common power line.

The first capacitor C1 may be between the first internal node Ni1 and a node (or the second control node QBo) between the twelfth TFT T12 and the thirteenth TFT T13 be educated. For example, the first capacitor C1 allow Ure-input charging to occur in the first internal node Ni1 based on a voltage variation of the second gate drive current GVdd2. Therefore, if a voltage level of the second gate Drive current GVdd2 varies, the voltage of the first internal node Ni1 by means of a voltage variation of the second gate drive current GVdd2 due to charging by means of Ureinput, which is achieved by coupling the first capacitor C1 and the second gate drive current GVdd2 is caused to vary further, thereby an output characteristic of the twelfth TFT T12 is further strengthened.

The second inverter circuit IC2 can discharge the voltage of the third control node QBe in response to the voltage of the first control node Q and a third gate drive current GVdd3. For example, the second inverter circuit IC2 for discharging the voltage of the third control node QBe to the first gate common current line on the basis of a high voltage level of the first control node Q can establish a current path between the third control node QBe and the first gate common current. Form leadership.

The second inverter circuit IC2 according to an embodiment may be a fourteenth TFT T14 to seventeenth TFT T17 and a second capacitor C2 exhibit.

The fourteenth TFT T14 can be turned on or off based on the third gate drive current GVdd3 and, when turned on, can supply the third gate drive current GVdd3 having a high voltage level to a second internal node Ni2. The fourteenth TFT T14 According to one embodiment, a diode can be connected between the third gate drive current GVdd3 and the second internal node Ni2.

The fifteenth TFT T15 can be turned on or off based on the voltage of the first control node Q and, when turned on, can discharge a voltage of the second internal node Ni2 to the second gate common power line.

The sixteenth TFT T16 can be turned on or off based on the voltage of the second internal node Ni2 and, when turned on, can supply the third gate drive current GVdd3 to the third control node QBe.

The seventeenth TFT T17 can be turned on or off based on the voltage of the first control node Q and, when turned on, can supply the voltage of the third control node QBe to the first gate common power line.

The second capacitor C2 may be between the second internal node Ni2 and a node (or the third control node QBe) between the sixteenth TFT T16 and the seventeenth TFT T17 be educated. For example, the second capacitor C2 allow Ure-input charging to occur in the second internal node Ni2 based on a voltage variation of the third gate drive current GVdd3. Therefore, when a voltage level of the third gate drive current GVdd3 varies, the voltage of the second internal node Ni2 can be due to charging by means of Ure-input by coupling the second capacitor C2 and the third gate drive current GVdd3 is caused to further vary a voltage variation of the third gate drive current GVdd3, thereby an output characteristic of the sixteenth TFT T16 is further strengthened.

The first detection control circuit SCC1 may be configured to generate a voltage of each of the above in response to an i-th carrier signal CSi, an external detection line selection signal Slss, an external detection control signal Scs, an external detection reset signal Srst and the first gate drive current GVdd1 first control node Q and the fourth control node Qm controls.

The first determination control circuit SCC1 according to an embodiment may have a fifth node control circuit NCC5 and a sixth node control circuit NCC6.

The fifth node control circuit NCC5 can control the voltage of each of the first control node Q and the fourth control node Qm in response to the i-th carrier signal CSi, the external detection line selection signal Slss, the external detection control signal Scs, and the first gate drive current GVdd1.

The fifth node control circuit NCC5 according to an embodiment may be a thirty-third TFT T33 to the thirty-seventh TFT T37 and a third capacitor C3 exhibit.

The thirty-third TFT T33 can output the i-th carrier signal CSi to a third connection node Nc3 in response to the external detection line selection signal Slss supplied together with the start signal Vst. For example, the thirty-third TFT T33 can be switched on based on the external detection line selection signal Slss, which has a high voltage level, and can output the i-th carrier signal CSi to the third connection node Nc3.

The thirty-fourth TFT T34 can electrically connect the third connection node Nc3 to the fourth control node Qm in response to the external detection line selection signal Slss. For example, the thirty-fourth TFT T34 based on the external detection line selection signal Slss, which has a high voltage level, are turned on, and the fourth control node Qm can receive the i-th carrier signal CSi transmitted by the thirty-third TFT T33 and fed to the third connection node Nc3. The third connection node Nc3 can be a connection line between the thirty-third TFT T33 and the thirty-fourth TFT T34 be.

The thirty-fifth TFT T35 may supply the first gate drive current GVdd1 to the third connection node Nc3 in response to the voltage of the fourth control node Qm. For example, the thirty-fifth TFT T35 can be turned on based on the voltage of the fourth control node Qm, which has a high voltage level, and can supply the first gate drive current GVdd1 to the third connection node Nc3, thereby preventing the voltage leakage of the fourth control node Qm. For example, the thirty-fifth TFT T35 a voltage difference between a gate voltage of the thirty-fourth TFT T34 and a voltage of the third connection node Nc3, and thus can increase the thirty-fourth TFT T34 , which has been turned off based on the external detection line selection signal Slss having a low voltage level, completely turn off, whereby the voltage drop (or a current leakage) of the fourth control node Qm through the turned off thirty-fourth TFT T34 thus preventing the voltage of the fourth control node Qm from being stably maintained.

The thirty-sixth TFT T36 can supply the first gate drive current GVdd1 to the thirty-seventh TFT in response to the voltage of the fourth control node Qm T37 output. For example, the thirty-sixth TFT T36 based on the voltage of the fourth control node Qm, which has a high voltage level, can be turned on and the thirty-seventh TFT T37 supply the first gate drive current GVdd1.

The thirty-seventh TFT T37 may receive the thirty-sixth TFT in response to the external detection control signal Scs T36 electrically connect to the first control node Q. For example, the thirty-seventh TFT T37 based on the external detection control signal Scs, which has a high voltage level, are turned on and can for charging a voltage level of the first gate drive current GVdd1 in the first control node Q, the first control node Q, the first gate drive current GVdd1, which is generated by the thirty-sixth TFT T36 is fed, feed.

The third capacitor C3 may be formed between the fourth control node Qm and the first gate drive power line, and may store a differential voltage between the fourth control node Qm and the first gate drive power line. For example, a first electrode of the third capacitor C3 electrically to the fourth control node Qm, which is connected to a gate electrode of the thirty-fifth TFT T35 and a gate electrode of the thirty-sixth TFT T36 connected in common, be connected, and a second electrode of the third capacitor C3 may be electrically connected to the first gate drive power line. The third capacitor C3 may correspond to turning on the thirty-third TFT, thirty-fourth TFT, and thirty-fifth TFT T33 until T35 store the i-th carrier signal CSi, and if the thirty-third TFT, the thirty-fourth TFT and the thirty-fifth TFT T33 until T35 are off, the voltage of the fourth control node Qm is maintained at a high voltage level using the stored voltage. For example, the third capacitor C3 maintain the voltage of the fourth control node Qm at a high voltage level using the stored voltage during a horizontal period.

The sixth node control circuit NCC6 can discharge the voltage of the first control node Q in response to the external detection reset signal Srst. For example, the sixth node control circuit NCC6 may supply the first gate common current GVss1 to the first control node Q in response to the external detection reset signal Srst having a high voltage level, whereby the voltage of the first control node Q is reset or initialized.

The sixth node control circuit NCC6 according to an embodiment may be a thirty-eighth TFT T38 and a thirty-ninth TFT T39 exhibit.

The thirty-eighth TFT T38 may supply the first gate common current GVss1 supplied through the first gate common current line to the second connection node Nc2 in response to the external detection reset signal Srst. For example, the thirty-eighth TFT T38 based on the external detection reset signal Srst, which has a high voltage level, can be turned on and the output first gate common current GVss1 to the second connection node Nc2.

The thirty-ninth TFT T39 can electrically connect the second connection node Nc2 to the first control node Q in response to the external detection reset signal Srst. For example, the thirty-ninth TFT T39 based on the external detection control signal Srst, which has a high voltage level, are turned on, and the first control node Q can receive the first gate common current GVss1 flowing through the thirty-eighth TFT T38 and is supplied to the second connection node Nc2.

The second connection node Nc2 between the thirty-eighth TFT T38 and the thirty-ninth TFT T39 can be electrically connected to the first connection node Nc1. Therefore, the second connection node Nc2 can receive the first gate drive current GVdd1 through the third TFT T3 of the first node control circuit NCC1. That's why the third TFT T3 of the first node control circuit NCC1, a voltage difference between a gate voltage of the thirty-ninth TFT T39 of the sixth node control circuit NCC6 and the voltage of the second connection node Nc2 to completely turn off the thirty-ninth TFT T39 that has been turned off based on the external detection reset signal Srst having a low voltage level, and thus can increase the voltage drop (or current leakage) of the first control node Q by the thirty-ninth TFT turned off T39 prevent, whereby the voltage of the first control node Q is stably maintained.

Optionally, the first determination control circuit SCC1 can be omitted. That is, the first determination control circuit SCC1 may be a circuit that is used to determine a property value of a drive TFT arranged in a subpixel of a pixel on the basis of an external detection mode of the pixel, and when the pixel is not in the external detection mode is driven, the first detection control circuit SCC1 may be an undesirable element and thus can be omitted.

13th FIG. 13 is an equivalent circuit diagram showing the node reset circuit, the output latch circuit and the second detection control circuit shown in FIG 11 are shown, represents.

Referring to 11 and 13th For example, a node reset circuit NRC according to an embodiment can maintain a voltage level of each of a second control node QBo and a third control node QBe while a voltage of a first control node Q is at a high voltage level.

The node reset circuit NRC according to one embodiment may be an eighteenth TFT T18 to the twenty-third TFT T23 exhibit.

The eighteenth TFT T18 can electrically connect a fourth connection node Nc4 to a forward drive signal line in response to a start signal Vst and a forward drive signal FWS. For example, the eighteenth TFT T18 can be switched on based on the start signal Vst, which has a high voltage level, and can feed the forward control signal FWS to the fourth connection node Nc4.

The nineteenth TFT T19 may electrically connect a second control node QBo to a first gate common power line in response to a voltage of a fourth connection node Nc4. For example, the nineteenth TFT T19 based on a voltage of the fourth connection node Nc4 and can form a current path between the second control node QBo and the first gate common control line for discharging a voltage of the second control node QBo to the first gate common current line, whereby the voltage of the second control node QBo is reset to a voltage level of a first common gate current GVss1.

The twentieth TFT T20 may electrically connect the fourth connection node Nc4 to the first gate common power line in response to the voltage of the second control node QBo. For example, the twentieth TFT T20 are switched on based on a high voltage level of the second control node QBo and can form a current path between the fourth connection node Nc4 and the first gate-common current line for discharging a voltage of the first connection node Nc4 to the first gate-common-current line, whereby the voltage of the fourth connection node Nc4 is reset to the voltage level of the first gate common current GVss1. Accordingly, when the voltage of the second control node QBo is at a high voltage level, the twentieth TFT can T20 to switch off the nineteenth TFT T19 reset the voltage of the fourth connection node Nc4 to the voltage level of the first gate common current GVss1 and can thus prevent the voltage of the second control node QBo through the nineteenth TFT T19 is discharged to the first gate common power line.

The twenty-first TFT T21 can connect the fourth connection node Nc4 to a reverse drive signal line in response to a reset signal Vrst and a reverse drive signal BWS. For example, the twenty-first TFT T21 can be switched on based on the reset signal Vrst, which has a high voltage level, and the reverse actuation signal BWS, which has a high voltage level, can be fed to the fourth connection node Nc4.

The twenty-second TFT T22 may electrically connect the third control node QBe to the first gate common power line in response to the voltage of the fourth connection node Nc4. For example, the twenty-second TFT T22 can be switched on based on the voltage of the fourth connection node Nc4 and can form a current path between the third control node QBe and the first gate common current line for discharging a voltage of the third control node QBe to the first gate common current line, whereby the voltage of the third control node QBe is reset to the voltage level of the first gate common current GVss1.

The twenty-third TFT T23 may electrically connect the fourth connection node Nc4 to the first gate common power line in response to the voltage of the third control node QBe. For example, the twenty-third TFT T23 are switched on based on a high voltage level of the third control node QBe and can form a current path between the fourth connection node Nc4 and the first gate-common current line for discharging the voltage of the fourth connection node Nc4 to the first gate-common-current line, whereby the voltage of the fourth connection node Nc4 is reset to the voltage level of the first gate common current GVss1. Accordingly, when the voltage of the third control node QBe is at a high voltage level, the twenty-second TFT can be turned off T22 reset the voltage of the fourth connection node Nc4 to the voltage level of the first gate common current GVss1 and can thus prevent the voltage of the third control node QBe from passing through the twenty-second TFT T22 is discharged to the first gate common power line.

The nineteenth TFT T19 and the twenty-second TFT T22 can be turned on or off at the same time based on the voltage of the fourth connection node Nc4.

For example, in the forward scan driving of the gate driving circuit 150 , the nineteenth TFT T19 and the twenty-second TFT T22 based on a high voltage level of the forward drive signal FWS generated by the eighteenth TFT T18 , which is turned on based on the start signal Vst having a high voltage level, is supplied to the fourth connection node Nc4, can be turned on at the same time, and based on the first gate common current GVss1 supplied to the fourth connection node Nc4 through the twentieth TFT T20 that is turned on based on a high voltage level of the second control node QBo, can be turned off at the same time, or can be turned off based on the first gate common current GVss1 that is supplied to the fourth connection node Nc4 through the twenty-third TFT T23 , which is turned on based on a high voltage level of the third control node QBe, can be turned off at the same time.

As another example, in reverse scan driving the gate drive circuit 150 the nineteenth TFT T19 and the twenty-second TFT T22 based on a high voltage level of the reverse drive signal BWS sent to the fourth connection node Nc4 through the twenty-first TFT T21 , which is turned on based on the reset signal Vrst having a high voltage level, is turned on at the same time, and can be turned on based on the first gate common current GVss1 sent to the fourth connection node Nc4 through the twenty-third TFT T23 that is turned on based on a high voltage level of the third control node QBe, can be turned off at the same time or can be turned off based on the first gate common current GVss1 that is supplied to the fourth connection node Nc4 through the twentieth TFT T20 , which is switched on based on a high voltage level of the second control node QBo, can be switched off at the same time.

The output latch circuit OBC can receive a carrier clock cCLK, an odd-numbered sampling clock sCLKo, an even-numbered sampling clock sCLKe, a first gate common current GVss1, the second gate common current GVss2 and a third gate common current GVss3 and can in Response to the voltage of each of the first control node to third control nodes Q, QBo and QBe based on the carrier clock cCLK, the sampling clock sCLK and output an i-th scan signal SSi, an i + 1-th scan signal SSi + 1 and an i-th carrier signal CSi to the third common gate current GVss3. For example, when the voltage of the first control node Q has a high voltage level, the output latch circuit OBC can the i-th carrier signal CSi corresponding to the carrier clock cCLK, the i-th sampling signal SSi corresponding to the odd-numbered sampling clock sCLKo and the i + 1-th sampling signal Output SSi + 1 according to the even-numbered sampling cycle sCLKe.

The output buffer circuit OBC according to one embodiment can have a first output buffer circuit OBC1 to a third output buffer circuit OBC3.

The first output latch circuit OBC1 can, based on the voltage of each of the first control node to third control nodes Q, QBo and QBe, the i-th sample signal SSi, which is a voltage level of the odd-numbered sampling clock sCLKo or a voltage level of the third gate common current GVss3 has to output.

The first output latch circuit OBC1 according to one embodiment may be a twenty-fourth TFT T24 to the twenty-sixth TFT T26 and a coupling capacitor Cc.

The twenty-fourth TFT T24 (or a first pull-up TFT) can transmit the odd-numbered sampling clock sCLKo to the i-th gate line GLi through a first output node No1 on the basis of the voltage of the first control node Q. For example, the twenty-fourth TFT T24 a gate electrode connected to the first control node Q, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to an odd-numbered scan clock line.

The twenty-fifth TFT T25 (or an odd first pull-down TFT) can transmit the third gate common current GVss3 through the first output node No1 to the i-th gate line GLi based on the voltage of the second control node QBo. For example, the twenty-fifth TFT T25 a gate electrode connected to the second control node QBo, a first source / drain electrode connected to the first output node No1, and a second source / Darin electrode connected to a third gate common current Line is connected, have.

The twenty-sixth TFT T26 (or a straight first pull-down TFT) can transmit the third gate common current GVss3 through the first output node No1 to the i-th gate line GLi on the basis of the voltage of the third control node QBe. For example, the twenty-sixth TFT T 26 may have a gate electrode connected to the third control node QBe, a first source / drain electrode connected to the first output node No1, and a second source / drain electrode connected to a third gate common power line is connected.

The coupling capacitor Cc can be formed between the first control node Q and the first output node No1. For example, the coupling capacitor Cc may be a parasitic capacitor between a gate electrode of the twenty-fourth TFT T24 and the first output node No1. The coupling capacitor Cc can allow charging by means of original input to take place in the first control node Q on the basis of a phase shift (or variation) of the odd-numbered sampling clock sCLKo. Accordingly, when the odd-numbered sampling clock sCLKo is shifted from a low voltage level to a high voltage level, the voltage of the first control node Q by means of a high voltage level of the odd-numbered sampling clock sCLKo on the basis of the loading by means of Ureinput, which is achieved by coupling between the coupling capacitor Cc and the odd-numbered sampling clock sCLKo, which has a high voltage level, is caused to be boosted to a higher voltage. For example, since the odd-numbered sampling clock sCLKo having a high voltage level may be the second source / drain electrode of the twenty-fourth TFT T24 is supplied, the voltage of the first control node Q, which is precharged by means of the first node control circuit NCC1 with a voltage level of the first forward drive signal FWS, can be boosted to a higher voltage, and thus the twenty-fourth TFT T24 can be completely switched on and the odd-numbered sampling clock sCLKo, which has a high voltage level, can be used as the i-th sampling signal SSi, the i-th gate line GLi through the first output node No1 and the twenty-fourth TFT which is switched on T24 can be supplied without loss of voltage.

The second output latch circuit OBC2 can, based on the voltage of each of the first control node to third control nodes Q, QBo and QBe, the i + 1-th sampling signal SSi + 1, which is a voltage level of the even-numbered sampling clock sCLKe or a voltage level of the third gate common current GVss3.

The second output latch circuit OBC2 according to one embodiment may be a twenty-seventh TFT T27 to the twenty-ninth TFT T29 exhibit.

The twenty-seventh TFT T27 (or a second pull-up TFT) can transmit the even-numbered sampling clock sCLKe to the i + 1-th gate line GLi + 1 through a second output node No2 based on the voltage of the first control node Q. For example, the twenty-seventh TFT T27 a gate electrode connected to the first control node Q, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to an even-numbered scan clock line. The twenty-seventh TFT T27 can be turned on based on the input load voltage of the first control node Q, and thus can use the even-numbered sampling clock sCLKe, which has a high voltage level supplied through an even-numbered sampling clock line, as the i + 1th sampling signal SSi + 1 through the second output node No2 is transmitted to the i + 1-th gate line GLi + 1 without a voltage loss.

The twenty-eighth TFT T28 (or an odd second pull-down TFT) can transmit the third gate common current GVss3 to the i + 1-th gate line GLi + 1 through the second output node No2 based on the voltage of the second control node QBo. For example, the twenty-eighth TFT T28 a gate electrode connected to the second control node QBo, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the third gate common current Line is connected, have.

The twenty-ninth TFT T29 (or a straight second pull-down TFT) can transmit the third gate common current GVss3 through the second output node No2 to the i + 1-th gate line GLi + 1 based on the voltage of the third control node QBe. For example, the twenty-ninth TFT T29 a gate electrode connected to the third control node QBe, a first source / drain electrode connected to the second output node No2, and a second source / drain electrode connected to the third gate common current Line is connected, have.

The third output latch circuit OBC 3 may output the i-th carrier signal CSi having a voltage level of the carrier clock cCLK or a voltage level of the first gate common current GVss1 based on the voltage of each of the first control node to the third control node Q, QBo and QBe.

The third output latch circuit OBC3 according to an embodiment may be a thirtieth TFT T30 to thirty-second TFT T32 exhibit.

The thirtieth TFT T30 (or a third pull-up TFT) can output the carrier clock cCLK as the i-th carrier signal CSi through a third output node No3 based on the voltage of the first control node Q. For example, the thirtieth TFT T30 a gate electrode connected to the first control node Q, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to a carrier clock line. The thirtieth TFT T30 can be turned on based on the original input charging voltage of the first control node Q and can, as the i-th carrier signal CSi, use the carrier clock cCLK having a high voltage level supplied through the carrier clock lines without a voltage loss through the third output node No3 output.

The thirty-first TFT T31 (or an odd third pull-down TFT) may, as the i-th carrier signal CSi, output the first gate common current GVss1 through the third output node No3 based on the voltage of the second control node QBo. For example, the thirty-first TFT T31 a gate electrode connected to the second control node QBo, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate common current Line is connected, have.

The thirty-second TFT T32 (or an even third pull-down TFT) can, as the i-th carrier signal CSi, output the first gate common current GVss1 through the third output node No3 on the basis of the voltage of the third control node QBe. For example, the thirty-second TFT T32 a gate electrode connected to the third control node QBe, a first source / drain electrode connected to the third output node No3, and a second source / drain electrode connected to the first gate common current Line is connected, have.

Alternatively, the coupling capacitor Cc can be formed between the first control node Q and the third output node No3. Furthermore, the coupling capacitor Cc in at least one of an area between the first control node Q and the first output node No1, an area between the first control node Q and the second output node No2, and an area between the first control node Q and the third output node No3.

The second determination control circuit SCC2 may be configured such that, in response to the voltage of the fourth control node Qm and the external determination control signal Scs, the voltage of each of the second control node QBo and the third control node QBe is discharged.

The second determination control circuit SCC2 according to an embodiment may have a first node discharge circuit NDC1 and a second node discharge circuit NDC2.

The first node discharge circuit NDC1 can discharge the voltage of the second control node QBo in response to the voltage of the fourth control node Qm and the external detection control signal Scs. For example, in response to the voltage of the fourth control node Qm having a high voltage level and the external detection control signal Scs having a high voltage level, the first node discharge circuit NDC1 may supply the first gate common current GVss1 to the second control node QBo, and thus can discharge the voltage of the second control node QBo to the first gate common current line or can reset the voltage of the second control node QBo to the first gate common current GVss1.

The first node discharge circuit NDC1 according to an embodiment may be a fortieth TFT T40 and a forty-first TFT T41 exhibit.

The fortieth TFT T40 may transfer the first gate common current GVss1 to the forty-first TFT in response to the voltage of the fourth control node Qm T41 transfer. For example, the fortieth TFT T40 can be turned on based on a high voltage level of the fourth control node Qm and can be between the forty-first TFT T41 and the first gate common current GVss1 form a current path.

The forty-first TFT T41 can electrically connect the second control node QBo to the fortieth TFT in response to the external detection control signal Scs T40 associate. For example, the forty-first TFT T41 based on the external detection control signal Scs having a high voltage level, and can be switched between the second control node QBo and the fortieth TFT T40 form a current path. The forty-first TFT T41 can be based on the external detection control signal Scs having a high voltage level in a state where the fortieth TFT T40 based on a high voltage level of the fourth control node Qm is turned on, and thus the voltage of the second control node QBo can be discharged to the first gate common power line or through each of the forty-first TFT T41 and the fortieth TFT T40 be reset to the first common gate current GVss1.

The second node discharge circuit NDC2 can discharge the voltage of the third control node QBe in response to the voltage of the fourth control node Qm and the external detection control signal Scs. For example, the second node discharge circuit NDC2 may supply the first gate common current GVss1 to the third control node QBe in response to the voltage of the fourth control node Qm having a high voltage level and the external detection control signal Scs having a high voltage level can thus discharge the voltage of the third control node QBe to the first gate common current line or can reset the voltage of the third control node QBe to the first gate common current GVss1.

The second node discharge circuit NDC2 according to an embodiment may be a forty-second TFT T42 and a forty-third TFT T43 exhibit.

The forty-second TFT T42 may transfer the first gate common current GVss1 to the forty-third TFT in response to the voltage of the fourth control node Qm T43 transfer. For example, the forty-second TFT T42 based on a high Voltage level of the fourth control node Qm can be switched on and a current path between the forty-third TFT T43 and form the first gate common current GVss1.

The forty-third TFT T43 can electrically connect the third control node QBe to the forty-second TFT in response to the external detection control signal Scs T42 associate. For example, the forty-third TFT T43 based on the external detection control signal Scs having a high voltage level, and can establish a current path between the third control node QBe and the forty-second TFT T42 form. The forty-third TFT T43 can be based on the external detection control signal Scs having a high voltage level in a state where the forty-second TFT T42 , based on a high voltage level of the fourth control node Qm is turned on, and thus the voltage of the third control node QBe can be discharged to the first gate common power line or through each of the forty-third TFT T43 and the forty-second TFT T42 be reset to the first common gate current GVss1.

Alternatively, the second determination control circuit SCC2 can be omitted together with the first determination control circuit SCC1. That is, each of the first determination control circuit SCC1 and the second determination control circuit SCC2 may be a circuit used for determining a property value of a drive TFT disposed in a sub-pixel of a pixel on the basis of an external determination mode of the pixel, and, when the pixel is not driven in the external detection mode, each of the first detection control circuit SCC1 and the second detection control circuit SCC2 may be an undesirable element and thus be omitted.

The first TFT T1 to the forty-third TFT T43 , in the 12th and 13th are shown, can be arranged separately (or distributed) in a horizontal line of the display area AA and can through the branch network 153 be connected to each other and thus the branch circuits 1511 until 151 n, which are arranged between the plurality of pixels P in a longitudinal alignment of the plurality of gate lines at a distance from one another and with the in 7th gate control line group GCL shown. For example, each of the stage circuit units 1501 until 150m a first branch circuit 1511 through n-th (where n is 43) branch circuits 151 n in which one of the first TFT T1 through forty-third TFT T43 arranged or provided, but not limited to, and each of the branch circuits of the plurality of branch circuits 1511 until 151n can with at least one of the first TFT T1 through forty-third TFTs T43 based on the number of pixels arranged in one horizontal line.

In addition, in the step circuit unit 150i , in the 11 until 13th is shown when the first switching TFT Tsw1 and the second switching TFT Tsw2 included in the pixel circuit PC of each of the plurality of sub-pixels SP1 to SP4 shown in FIG 8th are arranged, based on various first and second scanning signals, the i-th scanning signal SSi are used as a first scanning signal supplied through a first gate line to the odd-numbered gate line GLo, and the i + The 1st scan signal SSi + 1 can be used as the first scan signal supplied to the even gate line GLe through a first gate line. Therefore, the output latch circuit OBC of the stage circuit unit 150i , in the 11 until 13th further comprising a fourth output latch circuit and a fifth output latch circuit.

The fourth output latch circuit can be configured to output a second sampling signal to a second gate line of the odd gate line GLo, and the fifth output latch circuit can be configured to output the second sampling signal to a second gate line of the even gate line GLe be executed.

The fourth output latch circuit according to an embodiment can, based on the voltage of each of the first control node to third control nodes Q, QBo and QBe, an i-th second sample signal which is a voltage level of a second sampling odd-numbered sampling clock or a voltage level of the third gate -Common-Stroms GVss3, output. Besides the fact that the fourth output latch circuit outputs the i-th second sampling signal based on the second sampling odd sampling clock, the fourth output latch circuit may include three TFTs which are substantially the same as those of the first output latch circuit OBC1 who is in 13th is shown, and thus its detailed description is omitted.

The fifth output latch circuit according to an embodiment can, on the basis of the voltage of each of the first control node to third control nodes Q, QBo and QBe, an i + 1-th second sampling signal which is a voltage level of a second sampling even-numbered sampling clock or a voltage level of the third gate common current GVss3, output. In addition to the fifth output latch circuit outputting the i + 1-th second sampling signal based on the second sampling-even sampling clock, the fifth output latch circuit may have three TFTs that are substantially the same as those of the second output latch. Buffer circuit OBC2, which is in 13th is shown, and thus its detailed description is omitted.

In the in 11 until 13th step circuit unit shown 150i the odd sampling clock sCLKo can be referred to as a first sampling odd sampling clock, and the even sampling clock sCLKe may be referred to as a first sampling even sampling clock. For example, a first sampling-sampling clock and a second sampling-sampling clock can have the same phase or different phases. Likewise, the first sampling-sampling clock and the second sampling-sampling clock can have the same clock width or different clock widths.

14th FIG. 13 is a diagram for describing a gate drive circuit according to another embodiment of FIG 4th illustrated present disclosure, and illustrates an embodiment in which a configuration of each stage circuit unit in the gate drive circuit illustrated in FIG 6th and 7th is shown is modified. When describing the 14th become elements that are equal to the elements of the 6th and 7th or correspond to them are denoted by the same reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 14th can be a gate drive circuit 150 according to a further embodiment, a plurality of step circuit units 1501 until 150m have in each horizontal line of a first substrate 100 are arranged in a first direction X and are interconnected in a second direction Y in a dependent manner.

Each of the plurality of stage circuit units 1501 until 150m According to one embodiment, a first stage circuit part 151A and a second stage circuit part 151B exhibit.

The first step circuit part 151A can be in an area of each horizontal line on a first surface 100a a first substrate 100 be arranged in a first direction X. The first step circuit part 151A may generate a scan signal and may apply the scan signal to a corresponding gate line GL in response to a gate control signal supplied through each line of a gate control line group GCL.

The first step circuit part 151A According to one embodiment, the branch network 153 , the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC and the output latch circuit OBC shown in FIG 11 until 13th are shown. The first step circuit part 151A having such elements may have the same elements as those of the i-th stage circuit unit 150i , in the 11 until 13th is illustrated, and thus their repeated descriptions will be omitted.

The branch network 153 of the first step circuit part 151A may comprise a plurality of first control nodes to third control nodes and a network line, and the plurality of first control nodes to third control nodes may have a second stage circuit part 151B to be shared. This means that each of the first control node to the third control node with the first stage circuit part 151A and the second stage circuit part 151B can be connected together.

The first step circuit part 151A according to an embodiment, the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC and a plurality of branch circuits 1511 until 151n that have at least one of the TFTs T1 until T43 that set up the output latch circuit OBC. Each of the plurality of branch circuits 1511 until 151n can through the branch network 153 dependent on each other.

The second step circuit part 151B can be in the other area of each horizontal line of the first surface 100a of the substrate 100 be arranged. The second step circuit part 151B may generate a scan signal and may apply the scan signal to a corresponding gate line GL in response to a gate control signal supplied through each line of a gate control line group GCL. For example, the second stage circuit part 151B be electrically connected to the same gate line as the first stage circuit part 151A and can supply the same scanning signal as the first stage circuit part to the same gate line 151A . In this case, the gate drive circuit 150 a double feeding manner for simultaneously feeding a sampling signal in one area and the other area of a gate line by the first stage circuit part 151A and the second stage circuit part 151B and thus the delay of the scanning signal caused by a line resistance of each gate line can be prevented or minimized.

Optionally, the second step circuit section 151B be designed as a redundancy circuit to replace the first stage circuit part 151A if in the first step circuit part 151A a control error or a defect occurs.

The second step circuit part 151B according to an embodiment, the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC and the output latch circuit OBC shown in FIG 11 until 13th are shown. The second step circuit part 151B having such elements may have the same elements as those of the i-th stage circuit unit 150i , in the 11 until 13th is illustrated, and thus their repeated descriptions are omitted.

The second step circuit part 151B according to an embodiment, the node control circuit NCC, the first inverter circuit IC1, the second inverter circuit IC2, the node reset circuit NRC and a plurality of branch circuits 1511 until 151n that have at least one of TFTs T1 until T43 that set up the output latch circuit OBC. Each of the plurality of branch circuits 1511 until 151n can through the branch network 153 dependent on each other.

15th FIG. 13 is a cross-sectional view taken along a line I-I 'shown in FIG 4th is shown, and 16 FIG. 13 is an enlarged view of an area "B4" shown in FIG 15th is shown. 15th and 16 12 are diagrams for describing a cross-sectional structure of each of the first substrate and the second substrate of a display device according to the present disclosure. When describing the 15th and 16 become elements that are equal to the elements of the 4th or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 6th , 8th , 15th and 16 can be a display device 10 in accordance with the present disclosure, a first substrate 100 and a second substrate 200 made using a coupling element 300 are coupled (or bonded) together.

The first substrate 100 according to one embodiment, a circuit layer 101 , a planarization layer 102 , a light emitting device layer 103 , a wall 104 , a dam structure 105 and an encapsulation layer 106 exhibit.

The circuit layer 101 can on a first surface 100a of the first substrate 100 be arranged. The circuit layer 101 can be referred to as a pixel matrix layer or a TFT matrix layer.

The circuit layer 101 according to one embodiment, a buffer layer 101a and a circuit matrix layer 101b exhibit.

The buffer layer 101a can prevent materials such as hydrogen from being present in the first substrate 100 is included in a high temperature process of a manufacturing process of a TFT in the circuit matrix layer 101b diffused. The buffer layer can also 101 a Prevent external water or moisture from entering the light emitting device layer 103 penetrates. The buffer layer 101a According to one embodiment, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON) or a multilayered layer thereof can comprise, but is not limited to this. For example, the buffer layer 101a a first buffer layer BL1 comprising SiNx and on the first substrate 100 is arranged, and a second buffer layer BL2, which comprises SiOx and is arranged on the first buffer layer BL1.

The circuit matrix layer 101b can have a plurality of pixel drive lines GL , DL , PL , RL , CPL , PSL , RDL and LCP that are on the buffer layer 101a and a pixel circuit Pc , which has a control TFT Tdr in each of a plurality of pixel areas PA on the buffer layer 101a are arranged, have.

The control TFT Tdr that is in each pixel area PA is arranged, an active layer ACT , a gate insulating layer Eq , a gate electrode GE, an interlayer insulation layer 101c , a first source / drain electrode SD1 , a second source / drain electrode SD2 and a passivation layer 101d exhibit.

The active layer ACT can be in any pixel area PA on the buffer layer 101a be arranged. The active layer ACT may have a channel area that is the gate electrode GE overlaps, and a first source / drain region and a second source / drain region, which are arranged parallel to one another between adjacent channel regions, have. The active layer ACT can have conductivity in a conductivity process and can thus be used as a bridge line of a jump structure that directly connects lines in the display area AA or electrically connects lines arranged on different layers.

The gate insulating layer Eq can be in the channel region of the active layer ACT be arranged. The gate insulating layer Eq can be the active layer ACT isolate from the gate electrode GE. For example, the gate insulating layer GI SiOx, SiNx, SiON or a multilayer layer thereof, but is not limited to this.

The gate electrode GE can be on the gate insulating layer Eq be arranged. The gate electrode GE may overlap the channel region of the active layer ACT with the gate insulating layer Gl therebetween.

The gate electrode GE may have a single-layer structure or a multi-layer structure including at least one of molybdenum (Mo), titanium (Ti), Mo-Ti alloy (MoTi), and copper (Cu). The gate electrode according to an embodiment may comprise a first gate metal layer on top of the gate insulating layer Eq and a second gate metal layer disposed on the first gate metal layer. For example, the first gate metal layer can comprise Ti or MoTi. The second gate metal layer can comprise Cu. In this case, the gate electrode GE can have a two-layer structure made of Cu / MoTi or Cu / Ti.

Each of the gate lines GL , Power distribution lines PSL, line connection structures LCP and a reference branch line RDL out of the pixel drive lines GL , DL , PL , RL , CPL , PSL , RDL and LCP may have the same material as that of the gate electrode GE but is not limited to this.

The intermediate insulation layer 101c can on the first substrate 100 be arranged such that they have the gate electrode GE and the active layer ACT overlaps. The intermediate insulation layer 101c can the gate electrode GE from the source / drain electrode SD1 and the source / drain electrode SD2 electrically isolate. For example, the intermediate insulation layer 101c SiOx, SiNx, SiON or a multilayer layer thereof, but is not limited to this.

The first source / drain electrode SD1 can on the intermediate insulation layer 101c representing the first source / drain region of the active layer ACT overlapped, and can be arranged through a first source / drain contact hole, which is in the interlayer insulation 101c is arranged, electrically with the first source / drain region of the active layer ACT be connected. For example, the first source / drain electrode SD1 a source electrode of the drive TFT Tdr and the first source / drain region of the active layer ACT can be a source area.

The second source / drain electrode SD2 can on the intermediate insulation layer 101c representing the second source / drain region of the active layer ACT overlapped, and can be arranged through a second source / drain contact hole, which is in the interlayer insulation 101c is arranged, electrically with the second source / drain region of the active layer ACT be connected. For example, the second source / drain electrode SD2 a drain electrode of the drive TFT Tdr and the second source / drain region of the active layer ACT may be a drain region.

The source / drain electrode SD1 and the source / drain electrode SD2 According to an embodiment, a single-layer structure or a multilayer structure that is the same material as that of the gate electrode GE has, have.

Each of data lines DL , Pixel drive power lines PL and reference power lines RL of the plurality of pixel drive lines GL , DL , PL , RL , CPL , PSL , RDL and LCP may have the same material as that of the source / drain electrode SD1 and the source / drain electrode SD2 but is not limited to this. Likewise, each line of a gate control line group GCL can be the same material as that of the source / drain electrode SD1 and the source / drain electrode SD2 have, but is not limited to.

A passivation layer 101d can on a first surface 100a of the first substrate 100 be arranged so as to cover the pixel circuit PC having the drive TFT Tdr. The passivation layer 101d According to one embodiment, SiOx, SiNx, SiON or a multi-layer layer thereof can comprise, but is not limited to this.

Each of the first switching TFT Tsw1 and the second switching TFT Tsw2 constituting the pixel circuit PC can be constituted together with the driving TFT Tdr, and thus their detailed descriptions are omitted.

The circuit layer 101 According to one embodiment, a light-blocking layer can furthermore be used 101e have that under the active layer ACT of each of the TFTs Tdr, Tsw1 and Tsw2 that make up the pixel circuit Pc set up, is arranged.

The light-blocking layer (or a light-blocking structure) 101e may be in an island shape between the first substrate 100 and the active layer ACT be arranged. The light blocking layer 101e can by means of the buffer layer 101a be covered. The light blocking layer 101e can light passing through the first substrate 100 on the active layer ACT incident, block, thereby causing an external light-induced variation of a threshold voltage of each TFT is prevented. Optionally, the light-blocking layer 101e electrically to the first source / drain electrode SD1 of a corresponding TFT and can thus be used as a lower gate electrode of the corresponding TFTs work, and in this case, a light-induced characteristic variation of each TFT and a bias induced threshold voltage variation of each TFT minimized or prevented.

It can also use the light-blocking layer 101e as at least one of the power distribution lines PSL , the line connection structures LCP and the reference branch RDL from the pixel drive lines GL , DL , PL , RL , CPL , PSL , RDL and LCP be used.

The gate drive circuit 150 who is in 4th and 6th can be shown together with the driving TFT Tdr of the pixel circuit Pc are formed. For example, a plurality of TFTs, each of the stage circuit units 1501 until 150m of the gate drive circuit 150 can be established together with the drive TFT Tdr, and thus the plurality of branch circuits 1511 until 151n that are in each horizontal line on the first substrate 100 are arranged to be executed. The first control node to the fourth control node Q , QBo , QBe and Sqm who have favourited the branch network 153 from each of the tap circuit units 1501 until 150m can set up together with the gate line GL are formed. A network line can also NL who have favourited the branch network 153 from each of the tap circuit units 1501 until 150m establishes, together with at least one of the light-blocking layer 101e , the gate line GL and the data line DL based on a position of a connection area of each of the branch circuits 1511 until 151n to be connected are formed, but is not limited to this.

The planarization layer 102 can on the first surface 100a of the first substrate 100 may be arranged and a flat surface on the circuit layer 101 provide. The planarization layer 102 can the circuit layer 101 that control the TFT Tdr in each of the plurality of pixel areas PA is arranged, cover. The planarization layer 102 According to one embodiment, acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin can include, but is not limited to these.

The planarization layer 102 According to one embodiment, it can be formed such that it has the circuit layer 101 apart from an edge portion of the first surface 100a of the first substrate 100 covered. Therefore, the passivation layer 101d the circuit layer 101 on the edge portion of the first surface 100a of the first substrate is arranged, be exposed without means of the planarization layer 102 to be covered.

The light emitting device layer 103 can on the planarization layer 102 be arranged and can be based on a top emission type light in the direction of the first surface 100a of the first substrate 100 emit.

The light emitting device layer 103 according to one embodiment, a pixel electrode PE , a light emitting device ED and a common electrode CE exhibit.

The pixel electrode PE can be used as an anode electrode, a reflective electrode, a lower electrode, or a first electrode of the light emitting device ED are designated.

The pixel electrode PE can on the planarization layer 102 that have an emission range EA of each of the plurality of pixel areas PA overlapped, be arranged. The pixel electrode PE can be in any pixel area PA structured and arranged in an island reform and electrically connected to the first source / drain electrode SD1 of the control TFT Tdr a corresponding pixel circuit Pc be connected. One side of the pixel electrode PE may differ from the emission range EA of the pixel area PA to the first source / drain electrode SD1 of the control TFT Tdr that is in a circuit area CA is arranged, extend and can through a contact hole CH that is in the planarization layer 102 is provided electrically with the first source / drain electrode SD1 of the control TFT Tdr be connected.

The pixel electrode PE According to one embodiment, a metal material whose exit energy is low and whose reflection efficiency is good may have.

For example, the pixel electrode PE a three-layer structure comprising a first pixel electrode layer to a third pixel electrode layer. The first pixel electrode layer can be used as an adhesion layer that of the planarization layer 102 corresponds to, and can act as a secondary electrode of the light emitting device ED act and can also have indium tin oxide (ITO) or indium zinc oxide (IZO). The second pixel electrode layer can function as a reflector and can perform a function of lowering a resistance of the pixel electrode PE and can also be made of a material of aluminum (Al), silver (Ag), Mo, Ti and MoTi. The third pixel electrode layer can be used as an electrode of the light emitting device ED work and can have ITO or IZO. For example, according to an embodiment, the pixel electrode PE can be in a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

As another example, the pixel electrode PE may have a four-layer structure comprising a first pixel electrode layer to a fourth pixel electrode layer. The first pixel electrode layer can be used as the adhesion layer that of the planarization layer 102 corresponds to, and can act as the secondary electrode of the light emitting device ED and may also have a material of ITO, Mo and MoTi. The second pixel electrode layer can perform a function of lowering a resistance of the pixel electrode PE and can include Cu. The third pixel electrode layer can act as a reflector and can be made of a material of Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can be used as an electrode of the light emitting device ED work and can ITO or IZO exhibit. For example, the pixel electrode PE according to a further embodiment in a four-layer structure of ITO / Cu / MoTi / ITO.

Optionally, the line connection structures LCP from the pixel drive lines GL , DL , PL , RL , CPL , PSL , RDL and LCP may be formed from the same material together with the pixel electrode PE, but are not limited to this. Likewise, first pads of a first pad area 110 that is on the first substrate 100 may be formed from the same material together with the pixel electrode PE, but are not limited to this.

The light emitting device ED can on the pixel electrode PE may be formed and the pixel electrode PE touch directly. The light emitting device ED may be a common layer that resides together in each of a plurality of subpixels SP are formed in such a way that they are not differentiated into sub-pixel SP units. The light emitting device ED can respond to a current passing between the pixel electrode to emit white light PE and the common electrode CE flows. The light emitting device ED According to an embodiment, may comprise an organic light emitting device or an inorganic light emitting device, or may have a stacked structure or a combination structure of an organic light emitting device (or an inorganic light emitting device) and a quantum dot light emitting device.

An organic light emitting device according to an embodiment may have two or more light emitting material layers (or a light emitting portion) for emitting white light. For example, the organic light emitting device may have a first light emitting material layer and a second light emitting material layer for emitting white light based on a combination of first light and second light. Here, the first light-emitting material layer may have at least one of a blue light-emitting material, a green light-emitting material, a red light-emitting material, a yellow light-emitting material and a yellow-green light-emitting material. The second light-emitting material layer may have at least one of a blue light-emitting material, a green light-emitting material, a red light-emitting material, a yellow light-emitting material and a yellow-green light-emitting material, for emitting second light that is used to generate white Light is combined with first light.

The organic light-emitting device according to one embodiment can furthermore have one or more functional layers for improving the emission yield and / or the service life. For example, the functional layer can be arranged above and / or below a light-emitting material layer.

An inorganic light emitting device according to an embodiment may include a semiconductor light emitting diode, a micro light emitting diode, or a quantum dot light emitting diode. For example, when the light emitting device ED is the inorganic light emitting device, the light emitting device ED may have a scale of 1 µm or 100 µm, but is not limited to this.

The common electrode CE can be referred to as a cathode electrode, a light transmissive electrode, an upper electrode, or a second electrode of the light emitting device ED. The common electrode CE may be formed on the light emitting device ED and may directly contact the light emitting device ED or may electrically and directly contact the light emitting device. The common electrode CE may comprise a transparent conductive material that allows light emitted from the light emitting device ED to pass therethrough.

The common electrode CE according to an embodiment may be formed in a single-layer structure or a multi-layer structure comprising at least one of graphene and a light-transmissive conductive material having a relatively high exit energy. For example, the common electrode CE can have a metal oxide such as ITO or IZO or can comprise a combination of oxide and metal, such as, for example, ZnO: Al or SnO2: Sb.

In addition, by adjusting a refractive index of the light emitting device ED emitted light, further on the common electrode CE a capping layer for improving the emission efficiency of light can be arranged.

The wall 104 can in such a way on the planarization layer 102 be arranged to have an edge portion of the pixel electrode PE covered. The wall 104 can have an emission range EA (or an opening area) of each of the plurality of sub-pixels SP can define and pixel electrodes PE that are in neighboring subpixels SP are arranged, electrically isolate. The wall 104 can be formed such that it has a contact hole CH that is in each of the plurality of pixel areas PA is arranged, covered. The wall 104 can by means of the light emitting device ED be covered.

For example, the Wall 104 a translucent material (e.g. acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin) and in this case the wall 104 be a translucent wall.

As another example, the Wall 104 a light absorbing material or an opaque material comprising a black dye such as carbon black and may include, for example, polyimide resin, acrylic resin or benzocyclobutene (BCB), in which case the wall may 104 be a black wall that prevents or minimizes color mixing between adjacent subpixels SP.

The dam structure 105 can be on the circuit layer 101 at an edge portion of the first substrate 100 be arranged to have a closed loop shape or a closed loop line shape. For example, the dam structure 105 on a passivation layer 101d the circuit layer 101 be arranged. The dam structure 105 can spread or overflow of the encapsulation layer 106 prevent. The dam structure 105 may be within outermost pixels Po (or outermost pixel regions PAo) on an edge portion of the first substrate 100 are arranged from a plurality of pixels P (or a plurality of pixel regions PA ) must be included. In this case, a section of the dam structure 105 between the first pad area 110 that is on the first substrate 100 is arranged, and an emission area EA from each of the outermost pixels Po (or the outermost pixel area PAo) be arranged (or implemented).

The dam structure 105 according to one embodiment, together with the planarization layer 102 have the same material. The dam structure 105 can be the same height (or thickness) as that of the planarization layer 102 or may have a height that is greater than that of the planarization layer 102 . For example, a height (or thickness) of the dam structure 105 twice a height (or thickness) of the planarization layer 102 be.

According to a further embodiment, the dam structure 105 a lower dam structure that together with the planarization layer 102 formed of the same material, and an upper dam structure stacked on the lower dam structure and the same material as that of the wall 104 has, have. The lower dam structure can be the same height (or thickness) as that of the planarization layer 102 or may have a height that is greater than that of the planarization layer 102 . For example, a height (or thickness) of the lower dam structure can be twice a height (or thickness) of the planarization layer 102 be.

The light emitting device ED having an organic light emitting device can only be in an internal area (or an internal area) by means of the dam structure 105 is surrounded, be executed. That means the light emitting device ED comprising an organic light emitting device in a portion apart from a portion between an outer surface OS of the first substrate 100 and the dam structure 105 in the first surface 100a of the first substrate 100 may be arranged and between the outer surface OS of the first substrate 100 and the dam structure 105 and on an upper surface of the dam structure 105 cannot be arranged. Likewise, the common electrode CE the light emitting device layer 103 be designed such that they are the light emitting device ED and the dam structure 105 covered.

The first substrate 100 according to one embodiment, a first edge region can furthermore MA1 , a second margin area MA2 and a dam structure area DPA exhibit.

The first margin area MA1 can between an emission range EA of the outermost pixel Po and the dam structure 105 be arranged. The first edge area MA1 may be based on a shadow area (or a tail portion of the light emitting device) of the light emitting device ED involved in a process of forming the light emitting device ED inevitably occurs between one end of the Emission range EA (or of the wall 104 ) of the outermost pixel Po and the dam structure 105 have a first width. Accordingly, the dam structure 105 be designed such that they are in relation to the first direction X from the end of the emission range EA is arranged away from the first width of the first edge region MA1.

The second edge area MA2 can be between the outer surface OS of the first substrate 100 and the dam structure 105 be arranged. The second border area MA2 may be based on the reliability tolerance of the light emitting device ED compared to water, a second width between the outer surface OS of the first substrate 100 and the dam structure 105 exhibit. Accordingly, the dam structure 105 be designed such that they are in relation to the first direction X from the outer surface OS of the first substrate 100 by the second width of the second edge area MA2 is located away.

The second border area MA2 According to one embodiment, it can have a pad edge area which forms the first pad area 110 on a first edge portion of the first surface 100a of the first substrate 100 is arranged, overlaps.

The dam structure area DPA can be between the first edge area MA1 and the second edge area MA2 be arranged. The dam structure area DPA may have a third width that is a width of a lowermost soil surface (or a soil surface) of the dam structure 105 corresponds to have.

A width of each of the first edge area MA1 , the second edge area MA2 and the dam structure area DPA can be designed such that a second interval D2 with respect to the first direction X between a central portion of the outermost pixel and the outer surface OS of the first substrate 100 a half or less of a first interval (or a pixel pitch) D1 between two adjacent pixel areas PA.

For example, if one half of the first interval (or pixel spacing) D1 between the two adjacent pixel areas PA is 700 μm within a process error area, a total width of the first edge area MA1, the second edge area MA2 and the dam structure area DPA can be made to be about 670 µm based on a shadow edge based on the shadow area of the light emitting device ED and an encapsulation margin based on ensuring the reliability of the light emitting device ED towards water. In this case the second interval can D2 between an outermost outer surface VL of the first substrate 100 and a central portion of the outermost pixel that is the first pad area 110 has, be designed such that it is within a process error range 700 microns. Here, the outermost outer surface VL of the first substrate 100 an outermost outer side wall or an outer side wall of the display device (or a display panel).

The first margin area MA1 and the second edge area MA2 can be the same width or different widths. The dam structure area DPA can have a width which is relatively smaller than that of the first edge region MA1 and the second edge area MA2 . For example, in relation to the first direction X, the first edge region MA1 be designed in such a way that it is 300 μm or less in width, the second edge region MA2 may be made to have a width of 300 µm or less, and the dam structure area DPA can be designed so that it has a width of 70 µm. Likewise, a pad edge area (or a lateral wiring area) that is in the second edge area MA2 is included, be made such that it is with respect to the first direction X is a width of 100 microns or less.

The encapsulation layer 106 may be on a portion apart from an outermost edge portion of the first surface 100a of the first substrate 100 be arranged so as to have the light emitting device layer 103 covered. For example, the encapsulation layer 106 be made to have the entirety of a front surface and side surfaces of the light emitting device layer 103 surrounds.

The encapsulation layer 106 according to one embodiment, a first encapsulation layer 106a through third encapsulation layer 106c exhibit.

The first encapsulation layer 106a can be designed to prevent oxygen or water from entering the light emitting device layer 103 penetration. The first encapsulation layer 106a can on the common electrode CE be arranged so as to have the light emitting device layer 103 surrounds. Therefore, the entirety of the front surface of side surfaces of the light emitting device layer can be made 103 by means of the first encapsulation layer 106a be surrounded. For example, one end of the first encapsulation layer can 106a in the second edge area MA2 adjacent to the dam structure 105 be arranged. The first encapsulation layer 106a can have a top surface the passivation layer 101d at an outer periphery of the dam structure 105 directly touch and may be a boundary portion (or an interface) between the common electrode CE and the passivation layer 101d cover up the dam structure 105 can be a top surface of the passivation layer 101d touch them directly, which prevents or minimizes water ingress from the side.

The first encapsulation layer 106a according to one embodiment can comprise an inorganic material. For example, the first encapsulation layer 106a can be referred to as a first inorganic encapsulation layer. For example, the first encapsulation layer 106a a single-layer structure comprising one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), titanium oxide (TiOx), and aluminum oxide (AlOx), or a stacked structure thereof.

The second encapsulation layer 106b can in such a way on the first encapsulation layer 106a be designed that it has a thickness which is relatively thicker than that of the first encapsulation layer 106a . The second encapsulation layer 106b may be a thickness to sufficiently cover particles (or an undesirable material or structure) deposited on the first encapsulation layer 106a may or may not be. The second encapsulation layer 106b can become an edge portion of the first surface due to a relatively thick thickness 100a of the first substrate 100 spread out, however, the spread of the second encapsulation layer 106b by means of the dam structure 105 be blocked. For example, one end of the second encapsulation layer 106b the first encapsulation layer 106a on the dam structure 105 touch directly. Accordingly, the second encapsulation layer 106b in an internal area (or an internal area) by means of the dam structure 105 is surrounded, only on the first encapsulation layer 106a be arranged. The second encapsulation layer 106b can be referred to as a particle masking layer.

The second encapsulation layer 106b According to one embodiment, an organic material, such as silicon-oxycarbon (SiOCz) -acrylic or epoxy-based resin, for example.

The third encapsulation layer 106c can be designed such that it substantially prevents oxygen or water from entering the light emitting device layer 103 penetration. The third encapsulation layer 106c can be designed in such a way that it consists of the entirety of the second encapsulation layer 106b and the first encapsulation layer 106a by means of the second encapsulation layer 106b is not covered, surrounds. For example, one end of the third encapsulation layer can 106c between the end of the first encapsulation layer 106a and the outer surface OS of the first substrate 100 be arranged and the passivation layer 101d touch directly. The third encapsulation layer 106c can be a top surface of the passivation layer 101d directly and may contact a boundary portion (or an interface) between the first encapsulation layer 106a and the passivation layer 101 d cover, which additionally prevents or minimizes the ingress of water from the side.

The third encapsulation layer 106c according to one embodiment can comprise an inorganic material. For example, the third encapsulation layer 106c can be referred to as a second inorganic encapsulation layer. For example, the third encapsulation layer 106c a single-layer structure comprising one of SiOx, SiNx, SiONx, TiOx and AlOx, or a stacked structure thereof.

The first substrate 100 according to an embodiment, a wavelength conversion layer may furthermore be used 107 exhibit.

The wavelength conversion layer 107 can be a wavelength of light emanating from the emission region EA of each of the plurality of pixel areas PA occurs to transform. For example, the wavelength conversion layer 107 white light coming from the emission area EA incident into colored light corresponding to a corresponding pixel P.

The wavelength conversion layer 107 according to an embodiment, a plurality of wavelength conversion structures 107a and a protective layer 107b exhibit.

The plurality of wavelength converting structures 107a can on the encapsulation layer 106 that are in the emission area EA of each of the plurality of pixel areas PA is arranged, be arranged. The plurality of wavelength converting structures 107a can be divided (or classified) into a red light filter that converts white light into red light, a green light filter that converts white light into green light, and a blue light filter that converts white light into blue light. For example, the plurality of wavelength conversion structures 107a into the red light filter (or a first light filter) arranged in the first subpixel SP1, the green light filter (or a second light filter) arranged in the second subpixel SP2, and the blue light filter (or a third light filter) arranged in the fourth sub-pixel SP4 can be divided (or classified).

Each of the plurality of wavelength converting structures 107a According to one embodiment, it can be designed in such a way that it has a size that is larger than the emission area EA of each of the plurality of pixel areas PA . That means that in order to get a color mixture between neighboring subpixels SP to prevent each of the plurality of wavelength converting structures 107a the same size as that of the pixel electrode PE may have or have a size larger than the pixel electrode PE , and thus a section of the wall 104 , the one edge portion of the pixel electrode PE covered, can overlap. For example, any of the plurality of wavelength converting structures may be used 107a be arranged in such a way that they represent an entirety of the emission area EA of each of the plurality of pixel areas PA overlaps and a portion of the circuit area CA that is to the emission area EA adjoins, overlaps. In this case, in order to prevent external light from passing through an area that has the wavelength conversion structure 107a not overlapped, of each of the plurality of pixel areas PA incident, is reflected by means of the pixel drive lines, or to minimize the reflection of the external light, the wall 104 a light absorbing material or a black dye.

According to a further embodiment, each of the plurality of wavelength conversion structures 107a be made to have the same size as that of each of the plurality of pixel areas PA . That is, each of the plurality of wavelength converting structures 107a may be arranged to prevent or minimize the reflection of external light by the pixel drive lines, all of each of the plurality of pixel areas PA overlaps. For example, any of the plurality of wavelength converting structures may be used 107a be arranged in such a way that they take up an entirety of the emission area EA and the circuit area CA of each of the plurality of pixel areas PA covered. In this case the wall can 104 be a black wall or a translucent wall.

In addition, any of the plurality of wavelength converting structures may be used 107a a quantum dot which is used to additionally emit colored light corresponding to a corresponding pixel light based on white light or blue light emitted from the light emitting device layer 103 occurs, emitted again. The quantum dot can be selected from CdS, CdSe, CdZnSeS, CdTe, ZnS, ZnSe, GaAs, GaP, GaAs-P, Ga-Sb, InAs, InP, InSb, AlAs, AlP and AlSb. For example, the red light filter that is in the first subpixel SP1 is arranged, have a red quantum dot, such as CdSe or InP, which emits red light, the green light filter, which is in the second subpixel SP2 is arranged, may have a green quantum dot, such as CdZnSeS, which emits green light, and the blue light filter, which is in the fourth subpixel SP4 may have a blue quantum dot such as ZnSe that emits blue light. As described above, when each of the plurality of wavelength converting structures 107a has the quantum dot, the color rendering of a light emitting display device increases.

According to a further embodiment, the plurality of wavelength conversion structures can 100a be designed so that they each other in the circuit area CA of each of the plurality of pixel areas PA overlap. In this case, the circuit area CA of each of the plurality of pixel areas PA by means of at least two wavelength conversion structures 107a that overlap each other may be covered. For example, the circuit area CA of each of the plurality of pixel areas PA be covered by means of a two-layer stacked portion comprising the red light filter and the green light filter. As another example, the circuit area CA of each of the plurality of pixel areas PA by means of a three-layer stacked section comprising the red light filter, the green light filter and the blue light filter. The two-layer stacked portion including two light filters or the three-layer stacked portion including three light filters may be a function of a black matrix that mixes colors between adjacent sub-pixels SP prevents or prevents or minimizes the reflection of external light.

The protective layer 107b can be designed in such a way that they have the wavelength conversion structures 107a covered and on the wavelength conversion structures 107a provides a flat surface. The protective layer 107b may be arranged to have the wavelength conversion structures 107a and the encapsulation layer 106 where the wavelength conversion structures 107a are not arranged, covered. The protective layer 107b according to one embodiment can comprise an organic material. For example, the protective layer 107b Acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin include, but is not limited to these. Optionally, the protective layer 107b of Also have a getter material for adsorbing water and / or oxygen.

Alternatively, the wavelength conversion layer 107 to a wavelength conversion sheet having a sheet shape, and can be placed on the encapsulation layer 106 be arranged. In this case, the wavelength converting film (or a quantum dot film) may have the wavelength converting structures 107a sandwiched between a pair of films. For example, if the wavelength conversion layer 107 has a quantum dot that re-emits a colored set of light in a subpixel, the light-emitting device layer 103 of a subpixel can be implemented in such a way that it emits white light or blue light.

The first substrate 100 According to one embodiment, a functional layer can also be used 108 exhibit.

The functional layer 108 can on the wavelength conversion layer 107 be arranged. For example, the functional layer 108 by means of a transparent adhesive member with the wavelength conversion layer 107 be coupled. The translucent adhesive element can comprise a pressure-sensitive adhesive (PSA), an optically clear adhesive (OCR) or an optically clear resin (OCR).

The functional layer 108 According to an embodiment, to improve an outdoor visibility and a contrast ratio with respect to an image displayed by means of the display device 10 may have an anti-reflective layer (or an anti-reflective film) for preventing reflection of external light. For example, the anti-reflection layer can have a circular polarization layer (or a circular polarization film) that prevents external light from being transmitted by means of TFTs and / or the pixel control lines that are on the first substrate 100 are arranged, is reflected, is transmitted to the outside.

The functional layer 108 According to one embodiment, it can further comprise a barrier layer (or a barrier film) for primarily preventing the penetration of water or oxygen, and the barrier layer can comprise a material (for example a polymer material) that has a low water transfer rate.

The functional layer 108 according to an embodiment, may further comprise a light path control layer (or a light path control film) for controlling a path of the light output from each pixel P to the outside. The light path control layer may have a stacked structure in which a high refraction layer and a low refraction layer are alternately stacked, and, in order to minimize a color shift based on a viewing angle, can define a path of light incident from each pixel P, to change.

The first substrate 100 According to one embodiment, a side sealing element can furthermore be used 109 exhibit.

The side seal member (or an edge seal member) 109 may be between the first substrate 100 and the functional layer 108 and may be all of the side surfaces (or side surfaces) of each of the circuit layer 101 , the planarization layer 102 and the wavelength conversion layer 107 cover. That means the side sealing element 109 all of the side surfaces of each of the circuit layer 101 , the planarization layer 102 and the wavelength conversion layer 107 that is on the outside of the display device 10 between the functional layer 108 and the first substrate 100 exposed to the outside, covered. The side sealing element can likewise 109 a first bevel 100c by a chamber process at a corner portion between the first surface 100a and the outer surface OS of the first substrate 100 is formed (or arranged) cover. For example, any of the outermost surfaces of the first substrate 100 , an outer surface of the side seal member 109 and an outer surface of the functional layer 108 be arranged (or aligned) on the same vertical line VL.

The side sealing element 109 according to one embodiment may comprise a silicon-based or ultraviolet (UV) curable sealant (or resin), taking into account tackiness processing time, the side sealing member may 109 however, include the UV curable sealant. The side sealing element can likewise 109 have a color (e.g., blue, red, bluish green, or black), but is not limited to this, and may include a colored resin or a light-blocking resin for preventing side light leakage. The side sealing element 109 can using light emerging from an inner portion of the wavelength conversion layer 107 to an outer surface thereof, prevent side light leakage of light emitted from the light emitting device ED of each sub-pixel SP. In particular, the side sealing element 109 that the first pad area of the first substrate 100 overlaps, the reflection of external light, which is caused by means of the pad arranged in the first pad area, prevent or minimize.

Optionally, the side sealing element 109 furthermore have a getter material for adsorbing water and / or oxygen.

The first substrate 100 according to one embodiment may further comprise a front-side coating layer.

The front coating layer may be between the wavelength conversion layer 107 and the functional layer 108 be provided so as to be an upper surface of the wavelength conversion layer 107 covered and all side surfaces of each by the circuit layer 101 , the planarization layer 102 and the wavelength conversion layer 107 covered. That is, the front-side coating layer can be made to cover all of the side surfaces of each of the circuit layer 101 , the planarization layer 102 and the wavelength conversion layer 107 that is on the outside of the display device 10 are arranged between the functional layer 108 and the first substrate 100 and may also be configured to cover a portion of each of a top surface and a side surface of a wiring portion 400 that is connected to the first pad area of the first substrate 100 is connected, covered. The front-side coating layer according to one embodiment can be formed by an atomic layer deposition process. For example, the front-side coating layer can be made to have a thickness of several µm.

In the present embodiment, the side sealing member 109 be configured to have the front-side coating layer on the edge portion of the first surface 100a of the first substrate 100 covered or can be left out.

The second substrate 200 According to an embodiment, a metal structure layer that is connected to the wiring portion 400 is connected, and an insulation layer that insulates the metal structure layer.

The metal structure layer (or a conductive structure layer) can have a plurality of metal layers. The metal structure layer according to an embodiment can be a first metal layer 201 , a second metal layer 203 and a third metal layer 205 exhibit. The insulation layer can have a plurality of insulation layers. For example, the insulation layer can be a first insulation layer 202 , a second layer of insulation 204 and a third insulation layer 206 exhibit. The insulation layer can be referred to as a rear-side insulation layer or a structure insulation layer.

The first layer of metal 201 can on a back surface 200b a second substrate 200 be executed. The first layer of metal 201 according to one embodiment may have a first metal structure. For example, the first metal layer 201 may be referred to as a first interconnection layer or an interconnection layer.

The first metal structure according to one embodiment can have a two-layer structure (Cu / MoTi) made of Cu and MoTi. The first metal structure can be used as a connecting line of a connecting line section 250 who is in 9 can be used. For example, the first metal structure can be used as a plurality of data connection lines 251 , a plurality of pixel drive current connection lines 255 , a plurality of gate control signal transmission lines and a first common connection line 257a a pixel common power connection line 257 can be used, but is not limited to this.

The first layer of insulation 202 can on the back surface 200b of the second substrate 200 be designed such that they have the first metal layer 201 covered. The first layer of insulation 202 according to one embodiment can comprise an inorganic material. For example, the first insulation layer 202 have a material made of SiOx, SiNx, SiONx, but is not limited to this.

The second metal layer 203 can be on the first layer of insulation 202 be executed. The second metal layer 203 according to one embodiment can have a second metal structure. For example, the second metal layer 203 may be referred to as a second tie layer, a jump conduction layer, or a bridge conduction layer.

The second metal structure according to one embodiment can have a two-layer structure (Cu / MoTi) made of Cu and MoTi. The second metal structure may be a plurality of gate interconnects 253 a plurality of connecting lines of the connecting line section 250 who is in 10 is used, but is not limited to this. For example, the second metal layer 203 as one Jump line (or a bridge line) for electrically connecting the connection lines made of different metal materials on different layers in the connection line section 250 are formed.

Optionally, an interconnection line (for example a plurality of first interconnection lines) formed on the second metal layer 203 is arranged to be modified such that it is on the first metal layer 201 is arranged, and an interconnection line (for example, a plurality of second interconnection lines) formed on the first metal layer 201 is arranged, can be modified such that it is on the second metal layer 203 is arranged.

The second layer of insulation 204 can on the back surface 200b of the second substrate 200 be designed such that they have the second metal layer 203 covered. The second layer of insulation 204 according to one embodiment can comprise an inorganic material. For example, the second insulation layer 204 comprise a material made of SiOx, SiNx and SiONx.

The third layer of metal 205 can on the second insulation layer 204 be executed. The third layer of metal 205 according to one embodiment can have a third metal structure. For example, the third metal layer 205 may be referred to as a third tie layer or a pad electrode layer.

The third metal structure according to an embodiment may have a stacked structure of at least two materials of ITO (or IZO), Mo, Ti and MoTi. For example, the third metal structure can have a three-layer structure made of ITO / Mo / ITO, ITO / MoTi / ITO, IZO / Mo / ITO or IZO / MoTi / ITO. The third metal structure can be any of second pads of the second pad area 210 , third pad of the third pad area 230 and a second common trunk 257b and a plurality of third common connection lines 257c the pixel common power connection line 257 , in the 9 can be used.

The third layer of insulation 206 can on the back surface 200b of the second substrate 200 be designed such that they have the third metal layer 205 covered. The third layer of insulation 206 according to one embodiment can comprise an organic material. For example, the third insulation layer 206 an insulating material such as photo acrylic. The third layer of insulation 206 can prevent the third metal layer 205 is exposed to the outside, the third metal layer 205 cover. The third layer of insulation 206 may be referred to as an organic insulating layer, a protective layer, a back protective layer, an organic protective layer, a back clad layer or a back cover layer.

The third layer of insulation 206 may further include a pad exposure hole opening a portion of each of the second pads of the second pad area 210 and the third pads of the third pad area 230 who have favourited the third metal layer 205 have exposed.

The coupling element 300 can between the first substrate 100 and the second substrate 200 be arranged. Therefore, the first substrate 100 and the second substrate 200 by means of a coupling element 300 be mutually bonded to each other. The coupling element 300 according to one embodiment, a light-permeable adhesive element or a double-sided adhesive tape which has an OCA or an OCR can be. According to a further embodiment, the coupling element 300 have a glass fiber.

The coupling element 300 according to one embodiment, in an entire space between the first substrate 100 and the second substrate 200 be arranged. For example, the entire second surface 100b of the first substrate 100 with an entire surface of the coupling element 300 be coupled, and an entire front surface 200a of the second substrate 200 can with the entire other surface of the coupling element 300 be coupled.

The coupling element 300 According to a further embodiment, in a pattern structure between the first substrate 100 and the second substrate 200 be arranged. For example, the coupling element 300 have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include a bent portion that contains an air bubble that is formed in a process of bonding the first substrate 100 with the second substrate 200 between the first substrate 100 and the second substrate 200 occurs, discharges to the outside.

Optionally, the coupling element 300 furthermore have a heat transfer element. In this case, the coupling element 300 to prevent or minimize an increase in the temperature of the first substrate 100 Heat generated in the first substrate 100 occurs through the heat transfer element to the second substrate 200 transfer. The second substrate 200 can be used as a temperature sink device that increases the temperature of the first substrate 100 prevents or minimizes effect. For example, can the heat transfer element comprises a plurality of heat transfer particles or a heat transfer layer comprising a metal material. If the heat transfer element has a heat transfer layer that has a metal layer, the heat transfer layer can be electrically grounded or floating and thus can act as a noise-blocking layer that prevents frequency noise or static electricity from being generated in a drive circuit that is on the rear surface 200b of the second substrate 200 occurs in the pixels, the pixel drive lines and the gate drive circuit 150 that are on the first substrate 100 are arranged, flows.

17th FIG. 11 is a cross-sectional view taken along a line II-II 'shown in FIG 4th and is a diagram for describing a cross-sectional structure of a first pad area, a second pad area, and a wiring portion of a display device according to the present disclosure. When describing the 17th become elements that are equal to the elements of the 4th or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 5 and 15th until 17th , can in a display device 10 according to the present disclosure, a first pad area 110 a plurality of first pads 111 on a first edge portion of a first surface 100a a first substrate 100 are arranged, have. The majority of first pads 111 may be divided (or classified) into a plurality of first data pads, a plurality of first pixel drive current pads, and a plurality of first pixel common current pads. Likewise, the plurality of first pads 111 further divided (or classified) into a plurality of first reference current pads.

Each of the plurality of first pads 111 can through a first pad contact hole that is in a planarization layer 102 is arranged to be electrically connected to a corresponding one of a plurality of pixel drive lines. For example, the first data pad can be through the first pad contact hole that is in the planarization layer 102 is arranged to be electrically connected to one end of a data line DL.

In the display device 10 in accordance with the present disclosure, a second pad area 210 a plurality of second pads 211 have, which at a first edge portion of the first pad area 110 overlapped, a back surface 200b a second substrate 200 are arranged. The plurality of second pads 211 may be divided (or classified) into a plurality of second data pads, a plurality of second pixel drive current pads, and a plurality of second pixel common current pads. Likewise, the plurality of second pads 211 further divided (or classified) into a plurality of second reference current pads.

Each of the plurality of second pads 211 can through a second pad contact hole made in each of the first insulation layer 202 and the second insulation layer 204 is arranged, with a connecting line of a connecting line section 250 that is a first metal layer 201 or a second metal layer 203 that are on the back surface 200b of the second substrate 200 are arranged, has to be electrically connected. For example, the second data pad can pass through the second pad contact hole that is in each of the first insulation layer 202 and the second insulation layer 204 is arranged, electrically with one end of a data connection line 251 be connected.

The wiring section 400 can be arranged to have an outer surface OS of the first substrate 100 and an outer surface OS of the second substrate 200 surrounds. For example, the wiring section 400 on each of a first outer surface (or a surface) OS1a the outer surface OS of the first substrate 100 and a first outer surface (or a surface) OS1b the outer surface OS of the second substrate 200 be arranged.

The wiring section 400 according to an embodiment, a plurality of wiring lines 401 on each of the first outer surface (or any surface) OS1a the outer surface OS of the first substrate 100 and the first outer surface (or a surface) OS1b the outer surface OS of the second substrate 200 are arranged, have. The plurality of wiring lines 401 may be divided (classified) into a plurality of data wiring lines, a plurality of gate wiring lines, a plurality of pixel drive power wiring lines, and a plurality of pixel common power wiring lines. Likewise, the plurality of wiring lines 401 further divided (or classified) into a plurality of reference current wiring lines.

Each of the plurality of wiring lines 401 may be formed to have any of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200 surrounds. For example, any of the plurality of Wiring lines 401 be formed by a printing process using a conductive paste. For example, each of the plurality of wiring lines 401 formed by a printing process using an Ag paste, but is not limited to this.

In each of the plurality of wiring lines 401 an end portion thereof may have a first bevel 100c and the first pad 111 of the first pad area 110 on a first edge portion of the first substrate 100 is arranged, surrounded, the other end portion thereof may have a second bevel 200c and the second pad 211 of the second pad area 210 on a first edge portion of the second substrate 200 and a central portion thereof between the one end portion and the other end portion may be any of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200 surround. For example, in a data wiring line 410 , an end portion thereof can be designed such that it has the first bevel 100c and a first data pad of the first pad area 110 on the first edge portion of the first substrate 100 is arranged, surrounds, the other end portion thereof may be designed such that it the second bevel 200c and a second data pad of the second pad area 210 on a first edge portion of the second substrate 200 is arranged, and a middle portion thereof between the one end portion and the other end portion may be configured to encompass each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200 surrounds.

Optionally, if the coupling element 300 the heat transfer element has one end 301 of the coupling element 300 , which is closest to the first outer surface OS1a of the first substrate 100 is arranged such at a distance from the first outer surface OS1a of the first substrate 100 and / or the first outer surface OS1b of the second substrate 200 be arranged so that it is not electrically connected to each of the plurality of wiring lines 401 is connected, and thus may not be electrically connected to or may be electrically isolated from each of the plurality of wiring lines 401 . In this case, a portion of each of the plurality of wiring lines 401 an area between the first substrate 100 and the second substrate 200 penetrate, and thus a separation distance between the coupling element 300 having the heat transfer element and the first outer surface OS1a of the first substrate 100 based on a passage length (or passage distance) of a central portion of the wiring line 401 representing the area between the first substrate 100 and the second substrate 200 penetrates, can be adjusted.

The wiring section 400 In accordance with an embodiment of the present disclosure, an edge coat layer may further be used 403 exhibit.

The edge coat layer 403 may be configured to have the plurality of wiring lines 401 covered. The edge coat layer 403 according to one embodiment, it can be configured to include all of the first edge portion and the first outer surface OS1a of the first substrate 100 and the first edge portion and the first outer surface OS1b of the second substrate 200 , in addition to the plurality of wiring lines 401 , covered. The edge coat layer 403 can the corrosion of each of the plurality of wiring lines 401 having a metal material or an electrical short circuit between the plurality of wiring lines 401 prevent. Likewise, the edge coat layer 403 the reflection of external light by the plurality of wiring lines 401 and the first pads 111 of the first pad area 110 caused, prevent or minimize. The edge coat layer 403 according to one embodiment, a light blocking material comprising a black ink can comprise.

A top surface of the edge coat layer 403 who have made the first bevel 100c of the first substrate 100 covered, can by means of the side sealing element 109 be covered.

An outer surface of the edge coat layer 403 may be an outermost outer surface of the first substrate 100 and thus any of the outermost outer surface of the first substrate 100 , an outer surface of the side seal member 109 and an outer surface of the functional layer 108 be arranged on the same vertical line VL.

18th is a diagram showing a second substrate used in 5 is represented, represents, and 19th FIG. 13 is a cross-sectional view taken along a line III-III 'shown in FIG 18th is shown. 18th and 19th illustrate an embodiment which is designed in such a way that it contains the second insulation layer, which is shown in FIG 15th until 17th is shown modified. When describing the 18th and 19th become elements that are equal to the elements of the 15th until 17th or correspond to them, denoted by the same reference numerals, and their repeated Descriptions are omitted or briefly described below.

Referring to 18th and 19th can be a second substrate 200 according to a further embodiment of the present disclosure, a first area A1 and a second area A2 exhibit.

The first area A1 and the second area A2 may be in a rear-side insulating layer (or a structural insulating layer) that is provided on a rear-side surface of the second substrate 200 arranged, arranged or implemented. That means that in order to have a bending phenomenon occurring in an outer portion of the second substrate 200 occurs, to prevent or minimize the back side insulation layer the first area A1 and the second area A2 , in which the insulation layer has different thicknesses. For example, the layer in the second area A2 a thick one D22 have that is thinner than a thickness D11 of the first area A1 . The backside insulating layer according to an embodiment can have an insulating structure region, and in this case, in the structural insulating layer, a non-insulating structure region can have a first thickness D11 and the layer in the isolation structure region may have a second thickness D22 that is thinner than that of the first thickness D11 , exhibit. For example, the insulation structure region can only be one of the first insulation layer 202 and the second insulation layer 204 have, and can thus be the thickness D22 that is thinner than the thickness D11 of the non-insulating structure region, which is a stacked structure of all of the first insulating insulating layer 202 and the second insulation layer 204 having.

The first region (or a metal structure layer) A1 can be in a region that forms the second pad region 210 , the third pad area 230 and the connecting line section 250 has, from the back surface 200b of the second substrate 200 be arranged. The first area A1 According to one embodiment, a first insulation layer 202 that are on the back surface 200b of the second substrate 200 is arranged, and a second insulation layer 204 that is on the first layer of insulation 202 is arranged have. The first area A1 can by means of the third insulation layer 206 , which has an organic layer, be covered. The first area A1 may be a multilayer inorganic layer structure based on a stacked structure of the first insulating layer 202 and the second insulation layer 204 comprising an inorganic material.

The second area A2 can be in an area outside the first area A1 from the back surface 200b of the second substrate 200 be arranged. For example, the second area A2 in a sub-area of an area between the third pad area 230 and a second outer surface (or the other surface or a second longitudinal side), which runs parallel to a first outer surface (or a surface or a first longitudinal side), of the second substrate 200 be arranged, and in this case the first area A1 in the other area of the area between the second outer surface of the second substrate 200 and the third pad area 230 be arranged.

The second area A2 according to one embodiment, by means of the first insulation layer 202 that are on the back surface 200b of the second substrate 200 is arranged to have a single inorganic layer. For example, the second insulation layer 204 be designed in such a way that it covers the entire first insulation layer 202 that are on the back surface 200b of the second substrate 200 is arranged, covered, and the second insulation layer 204 that is in the second area A2 is arranged, can be removed by means of a structuring process, whereby the second insulation layer 204 in the second area A2 cannot be arranged. Therefore, the second area A2 by means of the first area A1 be surrounded. The first layer of insulation 202 that is in the second area A2 is arranged, the third insulation layer 206 , which has an organic layer, directly touch or can by means of the third insulation layer 206 be covered.

Because the second area A2 by means of the first insulation layer 202 comprising an inorganic material having a single inorganic layer structure may have a layer in the second region A2 the fat D22 have which is relatively thinner than the thickness D11 of the first area A1 , which is a multilayer inorganic layer structure based on the first insulating layer 202 and the second insulation layer 204 having. Accordingly, the second area A2 bending an outer portion of the second substrate 200 prevent or minimize in a process of bonding (or laminating) the first substrate to the second substrate using a coupling element.

Because a metal structure in an area other than an area between the outer surface OS1b of the second substrate 200 and the third pad area 230 is not arranged, and the second substrate 200 by means of the first insulation layer 202 and the second insulation layer 204 has a multilayered inorganic layer structure, bending the second substrate can 200 due to a voltage difference between the second substrate 200 and an inorganic layer appear. For example, there may be a bending phenomenon in an outer portion of the second substrate 200 due to compressive stress occurring by means of a stacked inorganic layer that is on the back surface 200b of the second substrate 200 is arranged, and the bending of the second substrate 200 may cause a bonding defect caused by misalignment between the first substrate and the second substrate in the process of bonding (or laminating) the first substrate to the second substrate using the coupling member.

On the other hand, the second substrate 200 the second area according to the present disclosure A2 have, by means of the first insulation layer 202 comprises a single inorganic layer, and can thus reduce a stress on the second substrate caused by an inorganic layer, a portion of the second insulation layer 204 sever (or isolate), thereby preventing or minimizing bending of the outer portion of the second substrate 200 a compressive load applied to the second substrate 200 acts, is distributed.

The second area A2 according to one embodiment can have a first structure region parallel to a first direction X and a plurality of second structure regions which protrude parallel to a second direction Y from one side of the first structure region.

According to a further embodiment, the second area A2 be arranged or designed such that it has a ladder shape, a mesh shape or an island shape.

Optionally, the second area A2 by means of the second insulation layer 204 that are the back surface 200b of the second substrate 200 touched directly, have a single inorganic layer. For example, the first insulation layer 202 be formed so that they take all of the back surface 200b of the second substrate 200 covered, and the first insulation layer 202 that is in the second area A2 is arranged, can be removed by means of a structuring process, whereby the first insulation layer 202 in the second area A2 cannot be arranged. The second insulation layer can likewise 204 on the first layer of insulation 202 in the first area A1 and can be formed on the back surface 200b of the second substrate 200 who have favourited the second area A2 overlaps, be formed and thus the rear surface 200b of the second substrate 200 in the second area A2 touch directly. Accordingly, the second area A2 a single inorganic layer based on the second insulating layer 204 thereby preventing or minimizing bending of the outer portion of the second substrate 200 a compressive load applied to the second substrate 200 acts, is distributed.

The second area A2 may be referred to as a stepped area, a single layer inorganic layer area, a stress relieving area, a bending restriction area, or an isolation structure area.

According to a further embodiment, the second substrate 200 the first area A1 , which has a multilayered inorganic layer structure, and the second region A2 having a single-layer inorganic layer structure, and thus bending the outer portion of the second substrate 200 prevented or minimized. Therefore, in a display device, the second substrate 200 according to another embodiment of the present disclosure, bending the outer portion of the second substrate 200 prevented or minimized in the process of bonding (or laminating) the first substrate to the second substrate using the coupling member, thereby minimizing or preventing a bonding defect caused by misalignment between the first substrate and the second substrate.

20th FIG. 13 is a cross-sectional view taken along a line IV-IV 'shown in FIG 6th and is a diagram for describing a common power contact portion and a secondary power contact portion shown in FIG 6th are shown. When describing the 20th become elements that are equal to the elements of the 6th or correspond to them are denoted by the same reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 6th , 15th , 16 and 20th , can be a common current contact section CPCP according to an embodiment of the present disclosure between a plurality of pixels P, each having a plurality of pixel-common-current lines CPL overlap, be arranged and may have a common electrode CE electrically to each of the plurality of pixel common power lines CPL associate.

Each of the plurality of pixel common power lines CPL can be a first pixel common power lines CPLa , a second pixel-shared power line CPLb and a contact line CPLc exhibit.

The first Pixel-Common-Stream-Line CPLa may extend long in a second direction Y and so may be in a display area AA of the first substrate 100 be arranged that it has a predetermined distance in a first direction X. The first Pixel-Common-Stream-Line CPLa according to one embodiment can be used together with a light-blocking layer 101e made of the same material on a first surface 100a of the first substrate 100 be educated.

The second pixel-shared power line CPLb can be on a gate insulating layer Eq who have favourited the first Pixel-Common-Stream-Line CPLa overlapped, be formed. The second pixel-shared power line CPLb according to one embodiment can be formed from the same material together with a gate line.

The contact line CPLc can be on an intermediate layer of insulation 101c who have favourited the first Pixel-Common-Stream-Line CPLa and the second pixel common power line CPLb overlapped, be formed. The contact line CPLc can through a contact hole made in the interlayer insulation 101c is formed electrically with the second pixel common power line CPLb be connected and can be through a contact hole in the interlayer insulation 101c and a buffer layer 101a is formed electrically with the first pixel common power line CPLa be connected. The contact line CPLc can be formed from the same material together with a data line.

Each of the plurality of pixel common power lines CPL can be the first Pixel-Common-Stream-Line CPLa and the second pixel common power line CPLb going through the contact line CPLc are electrically connected to one another, whereby an overall line resistance is reduced.

The common power contact section (or a common power contact pad) CPCP may be electrically connected between the plurality of pixels P with a corresponding pixel common power line CPL and may be electrically connected to the common electrode on a side-contact basis CE be connected.

The common current contact section CPCP according to one embodiment, a first contact metal layer M1 to third contact metal layer M3 exhibit. For example, the common power contact portion CPCP together with a pixel electrode PE , which has a three-layer structure, be formed.

The first contact metal layer M1 can be on a planarization layer 102 who have favourited the Pixel-Common-Stream-Line CPL overlaps, may be arranged and may be electrically connected to the pixel common power line through a contact hole CPL be connected. The first contact metal layer M1 can be an adhesive force between the current common contact portion CPCP and the planarization layer 102 strengthen. The first contact metal layer M1 can reduce an overall resistance of the common current contact portion CPCP be formed such that it is relatively thicker than the third contact metal layer M3 . The first contact metal layer M1 according to one embodiment IZO or ITO exhibit. For example, the first contact metal layer M1 have the same material as that of the lowermost layer of the pixel electrode PE , which has a three-layer structure. The first contact metal layer M1 may increase an etching speed of a lower portion of a side surface of the second contact metal layer M2 adjacent to the planarization layer 102 versus an etching speed of an upper portion of the side surface of the second contact metal layer M2 adjacent to the third contact metal layer M3 in an electrode patterning process performed on the common current contact portion CPCP act as a sacrificial layer.

The second contact metal layer M2 can be on the first contact metal layer M1 and may be electrically connected to the common electrode CE on a side-contact basis. The second contact metal layer M2 may comprise a light reflective metal material having a resistance that is relatively less than that of the third contact metal layer M3 . The second contact metal layer M2 For reducing an overall resistance of the common current contact portion CPCP, may be formed to be relatively thicker than the third contact metal layer M3 . The second contact metal layer M2 may comprise a metal material that has an etching rate that is slower than that of the first contact metal layer M1 . The second contact metal layer M2 According to one embodiment, a material composed of Al, Ag, Mo, Ti and MoTi can comprise. For example, the second contact metal layer M2 have the same material as that of a middle layer of the pixel electrode PE, which has a three-layer structure.

The third contact metal layer M3 can be on the second contact metal layer M2 be arranged and the corrosion of the first contact metal layer M1 and the second contact metal layer M2 prevent. The third contact metal layer M3 can comprise a material (or a substance), which is stronger in terms of corrosion resistance than any of the first contact metal layer M1 and the second contact metal layer M2 . An oxidation rate of the third contact metal layer M3 can be less than that of the first contact metal layer M1 . The third contact metal layer M3 according to one embodiment can comprise IZO or ITO. For example, the third contact metal layer M3 have the same material as that of an uppermost layer of the pixel electrode PE, which has a three-layer structure.

The common current contact section CPCP can in such a way on the planarization layer 102 may be formed to have the same three-layer structure as that of the pixel electrode PE and then be patterned based on an electrode patterning process (or an etching process) by batch etching.

In the electrode patterning process according to an embodiment, an etching speed of the first contact metal layer can be M1 be higher than that of the second contact metal layer M2 .

For example, in the electrode patterning process, the common current contact portion CPCP may sequentially up to the first contact metal layer M1 from the third contact metal layer M3 to be etched. In this case, there can be an etching speed of the first contact metal layer M1 is higher than that of the second contact metal layer M2 , from a point of time when an upper surface thereof is exposed to an etching source, the first contact metal layer M1 are etched faster than the second contact metal layer M2 , and thus, there may be a side surface of the first contact metal layer M1 in front of a lateral surface of the second contact metal layer M2 is etched, a lower portion of the side surface of the second contact metal layer M2 can be etched faster than an upper portion of the side surface thereof. Therefore, the side surface of the first contact metal layer M1 have an inclined shape or a tapered shape, and the side surface of the second contact metal layer M2 may have an inclined shape or an inversely tapered shape. Accordingly, the common current contact portion CPCP a side contact section SCP formed concave on the side surface of each of the first contact metal layer M1 and the second contact metal layer M2 exhibit.

A tapered shape of the first contact metal layer M1 according to one embodiment, may be defined as a shape in which an included angle (or an internal angle) between a top surface and the side surface thereof is larger than an included angle (or an internal angle) between a bottom surface and the side surface thereof . An inversely tapered shape of the second contact metal layer M2 according to one embodiment, may be defined as a shape in which an included angle (or an internal angle) between a top surface and the side surface thereof is less than an included angle (or an internal angle) between a bottom surface and the side surface thereof . For example, the included angle between the top surface and the side surface of the first contact metal layer M1 be an obtuse angle, and the included angle between the bottom surface and the side surface of the first contact metal layer M1 can be an acute angle. The included angle between the top surface and the side surface of the second contact metal layer M2 can be an acute angle, and the included angle between the bottom surface and the side surface of the second contact metal layer M2 can be an obtuse angle.

The side contact section SCP According to one embodiment, to a certain distance away from a vertical line extending in a thickness direction Z of the first substrate 100 extends inward from an outermost side surface of the third contact metal layer M3 and thus cannot be to the outside of a side surface of the third contact metal layer M3 with respect to the first direction X and can protrude by means of the third contact metal layer M3 be covered. For example, the side contact portion SCP can have a gutter structure or can have a “(” -shaped cross-sectional structure or a “〈” -shaped cross-sectional structure.

The side contact section SCP of the common power contact section CPCP may be formed to be concave, or may have a gutter structure, and thus may be electrically connected to the common electrode CE be connected without the light emitting device ED that are on the common-power contact section CPCP is provided to be electrically contacted. For example, in a case where the light emitting device ED formed by a deposition process, a deposition material of the light emitting device ED And thus may have linearity in a portion of each of a top surface and the side surface of the third contact metal layer M3 and a portion of a lower portion of the side surface of the first contact metal layer M1 but may not be formed on the side contact portion SCP , by means of the third contact metal layer M3 is covered, be educated. Accordingly, the side contact portion SCP may be the common current contact portion CPCP not by means of the light emitting device ED be covered and can be exposed on the outside of a side surface. Likewise, the side contact portion SCP can be the light emitting device ED isolate (or cut or sever).

The common electrode CE can on an upper surface of the light emitting device ED and can be formed by piercing a concave side surface of the common current contact portion CPCP at the side contact portion SCP be formed and thus can be electrically connected to the light emitting device ED and can be electrically connected to the side contact portion SCP of the common power contact section CPCP be connected. For example, the common electrode CE can be formed by a deposition process such as a sputtering process for performing a step coverage which is relatively excellent, and in this case, a sputtering electrode material can be formed on the light emitting device ED and can be deposited on all of the side surfaces of the common current contact portion CPCP having the side contact portion SCP by penetrating into a concave side surface of each of the first contact metal layer M1 and second contact metal layer M2 to be deposited. Accordingly, the common electrode CE through the side contact section SCP of the common power contact section CPCP electrically with the Pixel-Common-Power-Line CPL be connected even without a process of forming a separate contact hole or a separate contact structure.

The display device according to an embodiment of the present disclosure may further include a secondary power contact portion SPCP.

The secondary power contact section SPCP according to an embodiment of the present disclosure may be arranged between a plurality of pixels P each overlapping a plurality of secondary power lines SPL, and may be the common electrode CE electrically to each of the plurality of secondary power lines SPL associate.

Each of the plurality of secondary power lines SPL can be a first secondary power line SPLa , a second secondary power line SPLb and a secondary contact line SPLc exhibit.

The first secondary power line SPLa may extend long in the second direction Y and may be in the display area AA of the first substrate 100 parallel to the first pixel common power line CPLa be arranged. According to an embodiment, the first secondary power line SPLa can be used together with the first pixel common power line CPLa made of the same material on the first surface 100a of the first substrate 100 and can be formed by a plurality of line connection structures LCP electrically to the first pixel common power line CPLa be connected.

The second secondary power line SPLb may be on the gate insulating layer Gl, which is the first secondary power line SPLa overlapped, be formed. The second secondary power line SPLb according to one embodiment, together with the second pixel common power line CPLb be made of the same material.

The secondary contact line SPLc can on the intermediate insulation layer 101c who have favourited the first secondary power line Spa and the second secondary power line SPLb overlapped, be formed. The secondary contact line SPLc can through a contact hole made in the interlayer insulation 101c is arranged electrically to the second secondary power line SPLb be connected and can be through a contact hole in the interlayer insulation 101c and the buffer layer 101a is arranged electrically to the first secondary power line SPLa be connected. The secondary contact line SPLc according to one embodiment, together with the contact line CPLc be made of the same material.

As each of the plurality of secondary power lines SPL the first secondary power line SPLa and the second secondary power line SPLb having that through the secondary contact line SPLc are electrically connected to one another, an overall line resistance can be reduced.

The secondary power contact section (or a secondary power contact pad) SPCP may be electrically connected between the plurality of pixels P with a corresponding secondary power line SPL and can be electrically connected to the common electrode CE on the basis of the side contact manner.

The secondary power contact section SPCP According to one embodiment, the first contact metal layer can M1 to third contact metal layer M3 exhibit. For example, the secondary power contact section SPCP be formed together with the common power contact portion CPCP. Besides being the first Contact metal layer M1 electrically to the secondary power line SPL is connected, the secondary power contact portion SPCP together with the common current contact section CPCP containing the first contact metal layer described above M1 to third contact metal layer M3 and may be formed on the basis of the side-contact manner electrically with the common electrode CE and thus repeated description thereof will be omitted.

21 FIG. 13 is another cross-sectional view taken along a line IV-IV 'shown in FIG 6th and illustrates an embodiment useful for modifying the common power contact portion and the secondary power contact portion shown in FIG 20th are shown, is executed. When describing the 21 become elements that are equal to the elements of the 20th or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 6th , 15th , 16 and 21 can be a common power contact section CPCP according to one embodiment, a first contact metal layer M1 to fourth contact metal layer M4 exhibit. For example, the common power contact portion CPCP together with a pixel electrode PE having a four-layer structure.

The first contact metal layer M1 can be on a planarization layer 102 who have favourited the Pixel-Common-Stream-Line CPL overlaps, may be arranged and may be electrically connected to the pixel common power line through a contact hole CPL be connected. The first contact metal layer M1 can be an adhesive force between the current common contact portion CPCP and the planarization layer 102 strengthen. An oxidation rate of the first contact metal layer M1 may be lower than that of each of the second contact metal layer M2 and the third contact metal layer M3 . The first contact metal layer M1 according to one embodiment it can comprise ITO or MoTi. For example, the first contact metal layer M1 have the same material as that of a first layer (or a lowermost layer) of the pixel electrode PE having the four-layer structure.

The second contact metal layer M2 can be on the first contact metal layer M1 and may be electrically connected to a common electrode CE on the basis of the side contact manner. The second contact metal layer M2 may comprise a metal material that has a resistance that is relatively less than that of the third contact metal layer M3 . The second contact metal layer M2 For reducing an overall resistance of the common current contact portion CPCP, may be formed to be relatively thicker than each of the first contact metal layer M1 and the fourth contact metal layer M4 . The second contact metal layer M2 may comprise a metal material that has an etching speed higher than that of the third contact metal layer M3 . The second contact metal layer M2 According to one embodiment, it can comprise copper (Cu). For example, the second contact metal layer M2 have the same material as that of a second layer of the pixel electrode PE, which has the four-layer structure. The second contact metal layer M2 can further increase an etching speed of an underside of the third contact metal layer M3 adjacent to the planarization layer 102 versus an etching speed of an upper side of the third contact metal layer M3 adjacent to the fourth contact metal layer M4 in an electrode patterning process performed on the common current contact portion CPCP act as a sacrificial layer.

The third contact metal layer M3 can be on the second contact metal layer M2 and may be electrically connected to the common electrode CE on the basis of the side contact manner. The third contact metal layer M3 can act as a reflective electrode comprising a light reflective metal material. The third contact metal layer M3 may comprise a metal material having a resistance that is relatively less than that of each of the first contact metal layer M1 and the fourth contact metal layer M4 . The third contact metal layer M3 may include a metal material that has an etching speed higher than that of the fourth contact metal layer M4 and is lower than that of the second contact metal layer M2 . The third contact metal layer M3 can reduce an overall resistance of the common current contact portion CPCP be formed to be relatively thicker than each of the first contact metal layer M1 and the fourth contact metal layer M4 . The third contact metal layer M3 According to one embodiment, a material composed of Al, Ag, Mo, Ti and MoTi can comprise. For example, the third contact metal layer M3 have the same material as that of a third layer of the pixel electrode PE, which has the four-layer structure.

The fourth contact metal layer M4 can on the third contact metal layer M3 be arranged and the corrosion of the first contact metal layer M1 to third contact metal layer M3 prevent. The fourth contact metal layer M4 may comprise a material (or substance) stronger than any in terms of corrosion resistance from the second contact metal layer M2 and the third contact metal layer M3 . An oxidation rate of the fourth contact metal layer M4 may be lower than that of each of the second contact metal layer M2 and the third contact metal layer M3 . The fourth contact metal layer M4 according to one embodiment can comprise IZO or ITO. For example, the fourth contact metal layer M4 have the same material as that of a fourth layer of the pixel electrode PE which has the four-layer structure.

The common current contact section CPCP can in such a way on the planarization layer 102 may be formed to have the same four-layer structure as that of the pixel electrode PE, and then be patterned based on an electrode patterning process (or an etching process) by batch etching.

In the electrode patterning process according to an embodiment, an etching speed of the third contact metal layer can be M3 be higher than that of the fourth contact metal layer M4 , and an etching speed of the second contact metal layer M2 can be higher than that of the third contact metal layer M3 .

For example, in the electrode patterning process, the common current contact portion CPCP may sequentially up to the first contact metal layer M1 from the fourth contact metal layer M4 to be etched.

As an etching speed of the third contact metal layer M3 is higher than that of the fourth contact metal layer M4 , can be the third contact metal layer M3 from a point of time when an upper surface thereof is exposed to an etching source, can be etched faster than the fourth contact metal layer M4 , and thus, there can be a side surface of the third contact metal layer M3 in front of a lateral surface of the fourth contact metal layer M4 is etched, a side surface of the third contact metal layer M3 are etched faster than a side surface of the fourth contact metal layer M4 .

As an etching speed of the second contact metal layer M2 is higher than that of the third contact metal layer M3 , can be the second contact metal layer M2 from a point of time when an upper surface thereof is exposed to an etching source, can be etched faster than the third contact metal layer M3 , and thus an upper portion of a side surface of the second contact metal layer becomes M2 in front of the side surface of the third contact metal layer M3 etched, a lower portion of the side surface of the third contact metal layer M3 can be etched faster than an upper portion of the side surface thereof, and an upper portion of the side surface of the second contact metal layer M2 can be etched faster than a lower portion of the side surface thereof. Therefore, the side surface of the second contact metal layer M2 have an inclined shape or a tapered shape, and the side surface of the third contact metal layer M3 may have an inclined shape or an inversely tapered shape. Accordingly, the common current contact portion CPCP a side contact section SCP formed concave on the side surface of each of the second contact metal layer M2 and the third contact metal layer M3 exhibit.

A tapered shape of the second contact metal layer M2 according to one embodiment, may be defined as a shape in which an included angle (or an internal angle) between a top surface and the side surface thereof is larger than an included angle (or an internal angle) between a bottom surface and the side surface thereof . An inversely tapered shape of the third contact metal layer M3 according to one embodiment may be defined as a shape in which an included angle (or an internal angle) between a top surface and the side surface thereof is less than an included angle (or an internal angle) between a bottom surface and the side surface thereof . For example, the included angle between the top surface and the side surface of the second contact metal layer M2 be an obtuse angle, and the included angle between the bottom surface and the side surface of the second contact metal layer M2 can be an acute angle. The included angle between the top surface and the side surface of the third contact metal layer M3 can be an acute angle, and the included angle between the bottom surface and the side surface of the third contact metal layer M3 can be an obtuse angle.

The side contact section SCP According to one embodiment, to a certain distance away from a vertical line extending in a thickness direction Z of the first substrate 100 extends inward from an outermost side surface of the fourth contact metal layer M4 and thus cannot be to the outside of a side surface of the fourth contact metal layer M4 with respect to a first direction X and can protrude by means of the fourth contact metal layer M4 be covered. For example, the side contact portion SCP have a gutter structure or may have a "(" shaped cross-sectional structure or have a "〈" shaped cross-sectional structure.

The side contact section SCP of the common power contact section CPCP may be formed to be concave, or may have a gutter structure, and thus may be electrically connected to the common electrode CE be connected without being connected to the light emitting device ED that are on the common-power contact section CPCP is provided to be electrically connected. For example, in a case where the light emitting device ED formed by a deposition process, a deposition material of the light emitting device ED And thus may have linearity in a portion of each of a top surface and the side surface of the fourth contact metal layer M4 , a portion of the side surface of the first contact metal layer M1 and a portion of a lower portion of the side surface of the second contact metal layer M2 but may not be formed on the side contact portion SCP , by means of the fourth contact metal layer M4 is covered, be formed. Accordingly, the side contact portion SCP of the common power contact section CPCP not by means of the light emitting device ED be covered and can be exposed on the outside of a side surface. Likewise, the side contact section SCP the light emitting device ED isolate.

The common electrode CE can on an upper surface of the light emitting device ED and can be formed by piercing a concave side surface of the common current contact portion CPCP at the side contact portion SCP be formed and thus can be electrically connected to the light emitting device ED and can be electrically connected to the side contact portion SCP of the common power contact section CPCP be connected. For example, the common electrode CE can be formed by a deposition process such as a sputtering process for performing a step coverage which is relatively excellent, and in this case, a sputtering electrode material can be formed on the light emitting device ED and can be deposited on all of the side surfaces of the common current contact portion CPCP , which is the side contact section SCP by penetrating into a concave side surface of each of the second contact metal layer M2 and third contact metal layer M3 to be deposited. Accordingly, the common electrode CE through the side contact section SCP of the common power contact section CPCP electrically with the Pixel-Common-Power-Line CPL be connected even without a process of forming a separate contact hole or a separate contact structure.

The secondary power contact section SPCP According to one embodiment, the first contact metal layer can M1 to fourth contact metal layer M4 exhibit. For example, the secondary power contact section SPCP together with the common current contact section CPCP be educated. Apart from the fact that the first contact metal layer M1 is electrically connected to a secondary power line SPL, the secondary power contact portion SPCP together with the common current contact section CPCP containing the first contact metal layer described above M1 to fourth contact metal layer M4 and may be electrically connected to the common electrode CE on the basis of the side contact manner, and thus repeated description thereof will be omitted.

22nd FIG. 11 is another cross-sectional view taken along a line II-II 'shown in FIG 4th is shown, and 23 FIG. 13 is an enlarged view of an area "B5" shown in FIG 22nd is shown. 22nd and 23 illustrate an embodiment useful for modifying a dam structure in the display device shown in FIG 1 until 21 is shown, is executed. When describing the 22nd and 23 become elements that are equal to the elements of the 4th or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 22nd and 23 can, in a display device 10 according to the present disclosure, a dam structure 105 a first dam structure 105a and a second dam structure 105b exhibit.

The first dam structure 105a may be at an edge portion of a first substrate 100 such on a circuit layer 101 be arranged to have a closed loop shape or a closed loop line shape. For example, the first dam structure 105a such on a passivation layer 101d the circuit layer 101 be set up so that it is arranged adjacent to an emission region EA of an outermost pixel Po. The first dam structure 105a can spread or overflow of an encapsulation layer 106 prevent. The first dam structure 105a can be referred to as an internal dam structure, internal dam, blocking wall, or partition wall.

The first dam structure 105a According to one embodiment, it can be arranged such that it is adjacent to a shadow area (or a tail portion of the light emitting device) of the light emitting device ED in a first edge area MA1 that is on the first substrate 100 is defined, is arranged. Therefore, one end (or a tail portion) of the light emitting device ED that are in the first margin area MA1 is arranged, an inner surface of the first dam structure 105a touch or may be from the inner surface of the first dam structure 105a in a direction towards the emission area EA be arranged remotely.

A dam structure area DPA who made the first dam structure 105a overlaps, can in the direction of the first edge area MA1 can be enlarged, and a water infiltration path can be due to the first dam structure 105a be extended, creating the first edge area MA1 based on the shadow area of the light emitting device ED , can be reduced. Therefore, a second interval can D2 between a central portion of an outermost pixel Po and an outer surface OS of the first substrate 100 as the first margin area MA1 decreases, be reduced. Accordingly, in the display device 10 according to the present disclosure, the second interval D2 between the central portion of the outermost pixel Po and the outer surface OS of the first substrate 100 be smaller than the second interval D2 the display device showing the dam structure 105 , in the 15th until 17th is shown, has.

The first dam structure 105a according to one embodiment, together with the planarization layer 102 be made of the same material. For example, a height (or a thickness) of the first dam structure 105a be the same as that of the planarization layer 102 .

The second dam structure 105b can be on the circuit layer 101 at the edge portion of the first substrate 100 be arranged to have a closed loop shape or a closed loop line shape. For example, the second dam structure 105b such on the passivation layer 101d the circuit layer 101 be executed that they are the first dam structure 105a surrounds. For example, a height (or a thickness) of the second dam structure 105b be larger than that of the first dam structure 105a . The second dam structure 105b can lengthen a side water penetration path, thereby improving the reliability of the light emitting device ED against water penetration. The second dam structure 105b can be referred to as an external dam structure or an external dam.

The second dam structure 105b according to one embodiment, a lower dam structure LD and an upper dam structure UD exhibit.

The lower dam structure LD can in such a way on the passivation layer 101d adjacent to an outer surface of the first dam structure 105a be made to have a closed loop shape (or a closed loop line shape) that the first dam structure 105a surrounds. The lower dam structure LD according to one embodiment, together with the planarization layer 102 be made of the same material. For example, a height (or a thickness) of the lower dam structure LD equal to that of the planarization layer 102 be.

The upper dam structure UD can be on the lower dam structure LD be made to have a closed loop shape (or a closed loop line shape) that the first dam structure 105a surrounds. The upper dam structure UD according to one embodiment, together with a wall 104 be made of the same material. For example, a height (or a thickness) of the upper dam structure DU may be equal to that of the wall 104 be.

In some embodiments, the light emitting device can ED a light emitting device layer 103 only in an internal area (or an internal area) by means of the first dam structure 105a is surrounded, be executed. That means the light emitting device ED having an organic light emitting layer at a portion different from a portion between the first dam structure 105a and the outer surface OS of the first substrate 100 , in a first surface 100a of the first substrate 100 be arranged and can be between the first dam structure 105a and the outer surface OS of the first substrate 100 and on a top surface of the first dam structure 105a not be arranged.

The common electrode CE of the light emitting device 103 can be designed to be the light emitting device ED and the dam structure 105 covered. One end of the common electrode CE can the passivation layer 101d adjacent to an outer surface of the second dam structure 105b touch directly. Likewise, the common electrode CE the passivation layer 101d , between the first dam structure 105a and the second dam structure 105b , touch it directly. Therefore, the common electrode CE the passivation layer 101b on an outer portion of the second dam structure 105b and between the first dam structure 105a and the second dam structure 105b touch directly, whereby an effect of preventing water from entering from the side is increased.

A first encapsulation layer 106a an encapsulation layer 106 can be designed in such a way that they use the common electrode CE covered. For example, the first encapsulation layer 106a based on a surface shape of the common electrode CE be designed in a form conforming to the surface, and can thus be the common electrode CE surround. One end of the first encapsulation layer 106a can the passivation layer 101d directly touch and can one end of the common electrode CE surround. The first encapsulation layer 106a can be a top surface of the passivation layer 101 d at an outer periphery of the dam structure 105 directly touch and may be a boundary portion (or an interface) between the common electrode CE and the passivation layer 101d cover, which prevents or minimizes the ingress of water from the side.

A second layer of encapsulation 106b the encapsulation layer 106 can be designed in such a way that it is the first cabling layer 106a that is an inner surface of the first dam structure 105a covered, covered. The second encapsulation layer 106b may have a relatively thick thickness and thus may become an edge portion of the first surface 100a of the first substrate 100 spread, however, the spread of the second encapsulation layer 106b by means of the first dam structure 105a be blocked. For example, one end of the second encapsulation layer 106b the first encapsulation layer 106a on the first dam structure 105a touch directly. Accordingly, in some embodiments, the second encapsulation layer can 106b in an internal area (or an internal area) by means of the first dam structure 105a is surrounded, only on the first encapsulation layer 106a be arranged.

A third layer of encapsulation 106c the encapsulation layer 106 can be designed to include all of the first encapsulation layer 106a which is arranged in such a way that it forms the dam structure 105 overlapped, and the second encapsulation layer 106b overlaps. One end of the third encapsulation layer 106c can the passivation layer 101d touch directly and can one end of the first encapsulation layer 106a surround. The third encapsulation layer 106c can be the top surface of the passivation layer 101d at an outer periphery of the dam structure 105 directly and may contact a boundary portion (or an interface) between the first encapsulation layer 106a and the passivation layer 101d cover, whereby a lateral penetration of water is additionally prevented or minimized.

24 FIG. 11 is another cross-sectional view taken along a line II-II 'shown in FIG 4th is shown, and 25th FIG. 13 is an enlarged view of an area "B6" shown in FIG 24 is shown. 24 and 25th illustrate an embodiment in which a laser scribing portion is further in the vicinity of a dam structure in the display device shown in FIG 1 until 21 is shown, is provided. When describing the 24 and the 25th become elements that are equal to the elements of the 4th or correspond to them are denoted by the same reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 24 and 25th can be a display device 10 according to the present disclosure, a laser structuring portion LPP that is close to a dam structure 105 a first substrate 100 is arranged have.

The laser structuring section LPP can be designed to prevent the penetration of water or other foreign, external materials in a lateral direction of the first substrate 100 for preventing the deterioration in a light emitting device ED caused by lateral intrusion of materials including both water and others. The laser patterning section LPP may be the light emitting device ED of a light emitting device layer 103 at a periphery of the dam structure 105 isolate (or disconnect). Accordingly, the laser patterning portion LPP can be defined as a non-arrangement area or an isolation area in which the light emitting device ED and a common electrode CE are not arranged. Likewise, the laser structuring portion LPP can be made by simultaneously removing the light emitting device ED and the common electrode CE that are close to the dam structure 105 is arranged, are formed, and can thus be defined as at least one cutting line GOL. The at least one cut line may be formed by patterning the light emitting device ED and the common electrode CE to be concave.

The light emitting device ED the light emitting device layer 103 can with a wall 104 and a pixel electrode PE that at an emission area EA from each of the plurality of sub-pixels SP is exposed, be arranged and can also be on a passivation layer 101d on an edge portion of the first surface 100a of the first substrate 100 is exposed, be arranged. Therefore, a side surface of the light emitting device ED can be exposed on the outside, and due to this, the light emitting device ED may be deteriorated or may be due to the penetration of water through the side surface of the first substrate 100 be reduced in their reliability. In order to solve such a problem, the laser patterning portion LPP the light emitting device ED the light emitting device layer 103 that are close to the dam structure 105 is arranged, isolate (or cut off), whereby a lateral ingress of water is prevented.

The laser structuring section LPP (or an incision line GOL) can be designed such that it is at a periphery of the dam structure 105 the light emitting device ED from the common electrode CE and that it has a top surface of the passivation layer 101 d exposed. The laser structuring section LPP (or an incision line GOL) can at least partially by means of the encapsulation layer 106 be covered. In some embodiments, the encapsulation layer 106 a top surface of a circuit layer 101 at the laser scribing section LPP touch directly, and can therefore touch a side surface LIS (or an isolation surface or a laser isolation surface) of each of the light emitting device ED and the common electrode CE which are isolated by means of a laser structuring process. In some embodiments, the laser structuring process may be the light emitting device ED and the common electrode CE that are adjacent to the dam structure 105 are formed to both physically isolate and electrically isolate. For example, the encapsulation layer 106 everything from the isolation surface LIS from each of the light emitting device ED and the common electrode CE , a boundary portion (or an interface) between the light emitting device ED and the common electrode CE and a boundary portion (or an interface) between the passivation layer 101d and the light emitting device ED on the laser structuring section LPP Cover at least partially or completely, whereby a lateral penetration of water is fundamentally (or completely) prevented.

The laser structuring section LPP According to one embodiment, an inner structuring section IPP that of the dam structure 105 is arranged inwardly.

The inner structuring section (or a first laser structuring section) IPP can be adjacent to the inner section of the dam structure 105 be arranged and can by means of the dam structure 105 be surrounded. That means the inner structuring section IPP between the dam structure 105 and an emission area EA of an outermost pixel region PAo may be arranged to have a closed loop shape (or a closed loop line shape) obtained by means of the dam structure 105 is surrounded, has. For example, the inner structuring section IPP can be along an edge section of the first substrate 100 be arranged in a closed loop shape (or a closed loop line shape) and can thus by means of the dam structure 105 , which has a closed loop shape, be surrounded. The internal patterning portion IPP may be any of the common electrode CE and the light emitting device ED of the light emitting device layer 103 attached to the passivation layer 101d is provided, isolate (or separate), thereby preventing lateral ingress of water.

The inner structuring section IPP according to an embodiment may be a region that is formed by means of simultaneous removal of the common electrode CE and the light emitting device ED the light emitting device layer 103 that are on a periphery inward of the dam structure 105 is arranged, is formed by a laser structuring process. For example, in the laser structuring process, a portion of each of the light emitting device can be used ED and the common electrode CE in the first edge area MA1 on the first substrate 100 is arranged so as to be adjacent an inner portion of the dam structure 105 are arranged to be removed at the same time. Accordingly, the internal patterning portion IPP can be defined as a non-arrangement area or an isolation area in which the light emitting device ED and a common electrode CE are not arranged. Likewise, the inner structuring portion IPP can be made by simultaneously removing the light-emitting device ED and the common electrode CE, which are at a periphery of the dam structure 105 are arranged inwardly, and can thus be defined as at least one cutting line (or an inner cutting line).

The inner structuring section IPP can by means of the encapsulation layer 106 be covered. For example, the encapsulation layer 106 may be disposed on the inner patterning portion IPP, and thus may be a side surface (or an insulation surface or a laser insulation surface) of each of the common electrode CE and the light emitting device ED which are isolated by means of the laser structuring process. Accordingly can the encapsulation layer 106 all from the side surface of each of the light emitting device ED and the common electrode CE , a boundary portion (or an interface) between the light emitting device ED and the common electrode CE and a boundary portion (or an interface) between the passivation layer 101d and the light emitting device ED completely cover IPP on the inner structuring section, as a result of which lateral penetration of water is fundamentally (or completely) prevented.

The inner structuring section IPP according to one embodiment can be made by means of the first encapsulation layer 106a the encapsulation layer 106 be covered. The first encapsulation layer 106a can be a top surface of a circuit layer through the internal structuring section IPP 101 touch directly. For example, the first encapsulation layer 106a through the inner structuring section IPP, an upper surface of the passivation layer 101d directly and thus may contact a side surface (or an isolation surface or a laser isolation surface) of each of the common electrode CE and the light emitting device ED that are exposed at the inner structuring portion IPP surrounded. Accordingly, the first encapsulation layer 106a all of the isolation surface of each of the light emitting device ED and the common electrode CE , a boundary portion (or an interface) between the light emitting device ED and the common electrode CE and a boundary portion (or an interface) between the passivation layer 101d and the light emitting device ED completely cover IPP on the inner structuring section, as a result of which lateral penetration of water is fundamentally (or completely) prevented.

In the inner structuring section IPP can be a portion of a first edge region MA1 based on a shadow area of the light emitting device ED , by means of an encapsulation edge area which is based on ensuring the reliability of the light emitting device ED based, can be replaced, and thus an encapsulation edge can be based on ensuring the reliability of the light emitting device ED increase, thereby increasing the reliability of the light emitting device ED is increased. The inner structuring section can also IPP by removing the common electrode at the same time CE and the light emitting device ED that are in the first margin area MA1 adjacent to the dam structure 105 are arranged, and thus can be formed based on the shadow area of the light emitting device ED at a distance from the emission area EA of the ultimate pixel Po around the first margin area MA1 be located remotely, creating a dam structure area DPA showing the dam structure 105 overlaps, can be designed such that it is in the first edge region MA1 is included. In this case a second interval can be used D2 between an outer surface OS of the first substrate 100 and a central portion of the outermost pixel, which is designed to be half or less of a first interval (or a first distance) D1 between two adjacent pixel regions PA, can be further reduced.

The laser structuring section LPP According to one embodiment, an outer structuring section can furthermore be used OPP that of the dam structure 105 is arranged outward, have.

The outer structuring section (or a second laser structuring section) OPP can be in an outer area of the dam structure 105 can be arranged and the dam structure 105 surround. That means the outer structuring section OPP between the outer surface OS of the first substrate 100 and the dam structure 105 may be arranged to have a closed loop shape (or a closed loop line shape) representing the dam structure 105 surrounds, has. For example, the outer structuring section OPP in a closed loop shape (or a closed loop line shape) along an edge portion of the first substrate 100 can be arranged and the dam structure 105 which has a closed loop shape (or a closed loop line shape).

The outer structuring section OPP According to an embodiment, a region can be formed by simultaneously forming the common electrode CE and the light emitting device ED the light emitting device layer 103 that are on a periphery of the dam structure 105 are arranged outwards, is formed by a laser structuring process. Therefore, the outer structuring portion OPP as a non-arrangement area or an edge removal area in which the light emitting device ED and the common electrode CE are not arranged, be defined. The outer structuring section can also OPP by removing the light emitting device at the same time ED and the common electrode CE that are on a periphery of the dam structure 105 are arranged outwardly, and can thus be defined as at least one second cutting line (or outer cutting line).

The outer structuring section OPP can by means of the encapsulation layer 106 be covered. For example, the encapsulation layer 106 on the outer structuring section OPP and thus may be a side surface (or an isolation surface or a laser isolation surface) of each of the common electrode CE and the light emitting device ED which are isolated by means of the laser structuring process. Accordingly, the encapsulation layer 106 on the outer structuring section OPP all of the isolation surface of each of the light emitting device ED and the common electrode CE , a boundary portion (or an interface) between the light emitting device ED and the common electrode CE and a boundary portion (or an interface) between the passivation layer 101d and completely cover the light-emitting device ED, whereby a lateral penetration of water is fundamentally (or completely) prevented.

The outer structuring section OPP according to one embodiment, by means of the first encapsulation layer 106a the encapsulation layer 106 be covered. The first encapsulation layer 106a can through the outer structuring section OPP a top surface of the circuit layer 101 touch directly. For example, the first encapsulation layer 106a through the outer structuring section OPP a top surface of a passivation layer 101 d directly touch and thus can touch a side surface of each of the common electrode CE and the light emitting device ED attached to the outer structuring section OPP are exposed, and a boundary portion (or an interface) between the passivation layer 101d and the light emitting device ED cover. The outer structuring section OPP can improve the reliability of the light emitting device ED further increase or can add a second edge area MA2 relying on ensuring the reliability of the light emitting device ED based, decrease. In this case a second interval can be used D2 between the outer surface OS of the first substrate 100 and a central portion of an outermost pixel configured to be half or less of a first interval (or a first distance) D1 between two adjacent pixel regions PA can be further reduced.

As the display device 10 according to the present embodiment, the laser structuring portion LPP can have a total width of the first edge region MA1 and the second edge area MA2 on an edge portion of the first surface 100a of the first substrate 100 are arranged to decrease to 700 µm or less, and in this case, the display device can 10 realize a resolution higher than that of a display device not having a laser structuring portion LPP having.

For example, if one half of a first interval (or pixel pitch) D1 between two adjacent pixel areas PA is within a process error range of 350 µm, based on a shadow edge based on a shadow area of the light emitting device ED and an encapsulation rim that is focused on ensuring the reliability of the light emitting device ED based on water, a total width (or a shortest distance between an outer surface of the first substrate and an end of an emission region EA of the outermost pixel) of the first edge area MA1 , the second margin area MA2 and a dam structure area DPA be designed to be 320 µm or less. In this case a second interval can be used D2 between an outermost outer surface VL of the first substrate 100 and a central portion of an outermost pixel comprising a first pad area 110 has, be designed such that it is 350 microns within the process error range. Here, the outermost outer surface VL of the first substrate 100 an outermost outer surface of an edge coat layer 403 that have a wiring section 400 covered, be.

The first margin area MA1 and the second edge area MA2 can be the same width or different widths. For example, in relation to a first direction X, the first edge region can be designed in such a way that it has a width of 200 μm or less, and the second edge region MA2 may be made to have a width of 120 µm or less. Likewise, a pad edge area (or a lateral wiring area) that is contained in the second edge area MA2 can be designed in such a way that it has a width of 100 μm or less in relation to the first direction X.

An encapsulation layer 106 on an edge portion of the first surface 100a of the first substrate 100 is arranged, can by means of a pad opening process of opening (or exposing) first pads 111 of the first pad area 110 removed. In this case, there may be a common electrode CE on the first surface 100a of the first substrate, which is the first pad area 110 overlaps, using the outer structuring portion OPP not arranged, the first pad region 110 using only a dry etching process, without a wet etching process, can be exposed, and thus a manufacturing process of the first substrate 100 be simplified.

The display device 10 According to the present embodiment, a dummy dam structure may further be used 105m who have favourited the dam structure 105 covered, have.

The dummy dam structure 105m can be designed in such a way that it conforms to the dam structure 105 between the inner structuring section IPP and the outer structuring section OPP.

The dummy dam structure 105m According to one embodiment, a first island structure EDa, which the dam structure 105 surrounds, and a second island structure CEa surrounding the first island structure EDa.

The first island structure EDa can be in the dam structure area DPA on the passivation layer 101d who have favourited the dam structure 105 overlapped, arranged and may have side surfaces and a top surface of the dam structure 105 surround. The first island structure EDa according to an embodiment can be formed from the same material together with the light emitting device ED. For example, the first island structure EDa can be on the passivation layer in this way 101d be formed in the dam structure area DPA that they have side surfaces and the top surface of the dam structure 105 surrounds, and then may be a light emitting device material layer (or a light emitting device structure) isolated in an island shape from the light emitting device ED using the inner patterning portion IPP and the outer patterning portion OPP. In other words, the first island structure EDa may be a light emitting device material layer having an island shape that remains to be the dam structure 105 surrounds without being removed by means of a laser patterning process of forming the inner patterning portion IPP and the outer patterning portion OPP. The first island structure EDa can be a height of the dam structure 105 enlarge and can thus be a function of the dam structure 105 causing the spreading or overflowing of the encapsulation layer 106 blocked, strengthen.

The second island structure CEa can be the first island structure EDa surround. The second island structure CEa according to one embodiment, together with the common electrode CE be made of the same material. For example, the second island structure CEa as a common electrode material layer (or a common electrode structure) formed to be the same shape as that of a light emitting device ED who have favourited the first island structure EDa having, and then using the inner structuring portion IPP and the outer structuring portion OPP in an island shape from the common electrode CE is isolated. In other words, the second island structure CEa be a common electrode material layer having an island shape remaining to be the dam structure 105 surrounds without using the laser patterning process of forming the inner patterning portion IPP and the outer patterning portion OPP to be removed. The second island structure CEa can be a height of the dam structure 105 enlarge and can thus be a function of the dam structure 105 causing the spreading or overflowing of the encapsulation layer 106 blocked, strengthen.

The first island structure EDa and the second island structure CEa can through the laser patterning process of forming the inner patterning portion IPP and the outer patterning portion OPP are formed at the same time so that they have the same shape.

In addition, the second island structure CEa be designed such that they are electrically connected to at least one of a plurality of first pixel-common-current pads that are in the first pad area 110 are arranged, connected. For example, the second island structure CEa from one side parallel to the first pad area 110 protruding to at least one of the plurality of first pixel common power pads or may have at least one protruding structure and may be electrically connected to at least one of the plurality of first pixel common power pads through the at least one protruding structure. Optionally, the second island structure CEa be designed in such a way that it is supported by a grounding strip and a dummy pad that is in the first pad area 110 is arranged, is electrically connected to a ground source of a drive circuit unit. The second island structure CEa may have the same material as that of the common electrode CE and thus can act as an antistatic circuit that blocks static electricity flowing from the outside into a pixel P, or can act as an electrostatic discharge (ESD) path that discharges electrostatic electricity to the control circuit unit.

In the display device according to the present embodiment, the dam structure may 105 a first dam structure 105a and a second dam structure 105b , in the 22nd and 23 are shown. In this case, a laser scribing section (or cut line) LPP that is close to the first dam structure can be used 105a and the second dam structure 105b is arranged have. For example, the Laser scribing section LPP from the first dam structure 105a inward and from the second dam structure 105b be arranged outwards. For example, the laser structuring section LPP can be the inner structuring section IPP, which is formed by the first dam structure 105a inwardly, and the outer structuring portion OPP that of the second dam structure 105b is arranged outward, have.

26th FIG. 11 is another cross-sectional view taken along a line II-II 'shown in FIG 4th is shown, and 27 FIG. 13 is an enlarged view of an area “B7” shown in FIG 26th is shown. 26th and 27 illustrate an embodiment in which a trench structure portion is further close to a dam structure in the display device shown in FIG 1 until 21 is shown, is provided. When describing the 26th and the 27 become elements that are equal to the elements of the 1 until 21 or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 26th and 27 can be a display device 10 according to the present disclosure, a trench structure portion TPP that is close to a dam structure 105 a first substrate 100 is arranged have.

The trench structure section TPP can be designed in such a way that it prevents the penetration of water in a lateral direction of the first substrate 100 for preventing the deterioration in a light emitting device ED caused by lateral invasion of water. For example, the trench structure section TPP can be the light-emitting device ED of a light-emitting device layer 103 at a periphery of the dam structure 105 isolate (or disconnect). Accordingly, the trench structure portion TPP can be defined as an isolation region or a dividing line of the light emitting device ED.

The light emitting device ED of the light emitting device layer 103 can on a wall 104 and a pixel electrode PE exposed at an emission region EA of each of the plurality of sub-pixels SP, and may also be provided on a passivation layer 101d on an edge portion of a first surface 100a of the first substrate 100 is exposed, be arranged. Therefore, the light emitting device ED can become damaged due to the penetration of water through the side surface of the first substrate 100 may be deteriorated or may be limited in their reliability. In order to solve such a problem, the trench structure portion TPP can be configured to include the light-emitting device ED of the light-emitting device layer 103 that are close to the dam structure 105 is disposed, insulated (or cut off), thereby minimizing a decrease in the reliability of the light emitting device ED caused by lateral intrusion of water.

The trench structure section (or an isolation structure section) TPP can be so close to the dam structure 105 be designed to have an isolation structure (or a separation structure or a cut-off structure) for isolating (or separating) the light-emitting device ED that are close to the dam structure 105 or for isolating (or separating) all of the light emitting device ED and the common electrode CE having. The isolation structure may include at least one of a gutter structure (or a cliff structure), a spike structure (or a protrusion spike structure), and an undercut structure. Therefore, the common electrode CE and the light emitting device ED that are close to the dam structure 105 are arranged, are isolated (or separated) by means of an isolation structure of the trench structure portion TPP in the middle of performing a deposition process, without a separate process. The trench structure section TPP can be made by means of an encapsulation layer 106 be covered. The encapsulation layer 106 can be a top surface of a circuit layer 101 in the trench structure portion TPP directly and thus may contact a side surface (or an isolation surface) of each of the isolated light emitting device ED and the common electrode CE. For example, the first encapsulation layer 106a the encapsulation layer 106 into one by means of the isolation structure of the trench structure section TPP Formed isolation space be filled and can the trench structure section TPP seal or completely surround and thus the side surface (or the isolation surface) of each of the isolated light emitting device ED and the common electrode CE completely surrounded, whereby a lateral penetration of water is fundamentally (or completely) prevented.

The trench structure section TPP can be attached to a passivation layer 101d that are close to the dam structure 105 is arranged to be executed. For example, the trench structure section TPP can have an insulation structure that is created by structuring the passivation layer 101d that are close to the dam structure 105 is arranged, is executed.

The passivation layer 101d According to the present embodiment, for implementing the trench structure portion TPP may have a three-layer structure.

The passivation layer 101d According to one embodiment, a lower layer may have LL, a middle layer ML and an upper layer UL.

The lower layer (or a lower passivation layer) LL can be so on the first surface 100a of the first substrate 100 be arranged so that it covers a pixel circuit having a drive TFT. The lower layer LL according to an embodiment can have a first thickness DLL exhibit.

The middle layer (or a middle passivation layer) ML can be on the lower layer LL be arranged. The middle layer ML According to one embodiment, DML can have a second thickness that is different from the first thickness DLL . For example, the middle layer ML can have the second thickness DML, which is relatively thinner than the first thickness DLL the lower layer LL.

The top layer (or a top passivation layer) UL can be on the middle layer ML be arranged. The top layer UL According to one embodiment, DUL can have a third thickness that is different from the second thickness DML . For example, the top layer UL a third thickness DUL have which is relatively thicker than the second thickness DML the middle layer ML and is equal to or is shifting from the first thickness DLL the lower layer LL.

Each from the lower layer LL , the middle layer ML and the upper layer UL may include, but is not limited to, SiOx, SiNx, SiON or a multilayer layer thereof.

For example, the lower layer LL , the middle layer ML and the top layer UL be designed in such a way that they have different unsaturated binding sites, so that the trench structure section TPP is implemented. The lower layer LL , the middle layer ML and the top layer UL can have various unsaturated bond sites of silicon (Si). For example, unsaturated binding sites can be found in the middle layer ML be fewer than unsaturated binding sites from each of the lower layer LL and the top layer UL , and an unsaturated binding site of the lower layer LL can be less than that of the upper layer UL .

As another example, consider the lower layer LL , the middle layer ML and the top layer UL be designed in such a way that they have different densities, so that the trench structure section TPP is implemented. The lower layer LL , the middle layer ML and the top layer UL can have different densities of Si. For example, a Si density of the middle layer ML be higher than a Si density of each of the lower layer LL and the top layer UL , and a Si density of the upper layer UL may be lower than a Si density of the lower layer LL . Therefore, the top layer can UL be a porous layer, and the middle layer ML can be a dense layer.

The lower layer LL , the middle layer ML and the top layer UL the passivation layer 101d may have different unsaturated bond sites (or densities) and can thus be used in a wet etching process of forming the trench structure portion TPP have different etching speeds. For example, with respect to the same wet etching time, an etching speed of the upper layer may be UL the fastest, a middle layer etch speed ML can be the slowest, and an etching speed of the lower layer LL can be slower than that of the upper layer UL and can be faster than that of the middle tier ML .

The trench structure section TPP According to an embodiment, an inner trench structure section TPPa that of the dam structure 105 in a first edge area MA1 is arranged inwardly.

The inner trench structure section (or a first trench structure section) TPPa may be arranged to adjoin an interior portion of the dam structure 105 adjoins, and can be arranged such that it by means of the dam structure 105 is surrounded. This means that the inner trench structure section TPPa such between the dam structure 105 and an emission area EA an outermost pixel area PAo can be designed to have a closed loop shape (or a closed loop line shape) by means of the dam structure 105 is surrounded, has. For example, the inner trench structure portion TPPa may be in a closed loop shape (or a closed loop line shape) along an edge portion of the first substrate 100 be designed and can thus be designed in such a way that by means of the dam structure 105 having a closed loop shape (or a closed loop line shape) is surrounded. The inner trench structure section TPPa can be carried out on the passivation layer by means of a wet etching process 101 d a circuit layer 101 that in the first Edge area MA1 is arranged on the passivation layer 101 d can be implemented and thus the light emitting device ED the light emitting device layer 103 isolate (or disconnect) or can the common electrode CE and the light emitting device ED the light emitting device layer 103 isolate (or disconnect).

One width W1 of the inner trench structure portion TPPa according to an embodiment may be wider than a width of the dam structure 105 . For example, the width W1 of the inner trench structure portion TPPa are, however, not limited to 20 μm to 60 μm, and may be based on a width of the first edge region MA1 changed or can be based on an overall width of the first margin area MA1 and a second edge area MA2 be changed.

The inner trench structure section TPPa According to one embodiment, at least two first trench structures TP1 and at least one first trench structure TS1 exhibit.

The at least two first trench structures TP1 can on the passivation layer 101d the circuit layer 101 adjacent to the inner section of the dam structure 105 be executed. For example, the at least two first trench structures TP1 can be made using the wet etching process on the passivation layer 101d the circuit layer 101 is carried out on the passivation layer 101d formed or arranged.

Each of the at least two first trench structures TP1 According to one embodiment, a first hole structure TPa, a second hole structure TPb and a groove structure TPc.

The first hole structure TPa can be on the upper layer UL of the passivation layer 101d be executed. The first hole structure TPa according to one embodiment can be formed by a wet etching process in such a way that it passes through the upper layer UL of the passivation layer 101d leads through. For example, a cross-sectional surface of the first hole structure TPa along a first direction X may have a ladder shape or an inverted ladder shape in which an upper side thereof is wider than a lower side thereof.

The second hole structure TPb can be attached to the middle layer ML of the passivation layer 101b be designed such that they are in a thickness direction Z of the first substrate 100 with the first hole structure TPa communicates. The second hole structure TPb According to one embodiment, it can be formed by a wet etching process in such a way that it passes through the middle layer ML of the passivation layer 101d passes through. For example, a cross-sectional surface of the second hole structure TPb have a tetragonal shape or a rectangular shape along the first direction X.

A size of the second hole structure TPb can be smaller than a bottom surface of the first hole structure TPa . For example, in relation to the first direction X, a width of the second hole structure TPb be narrower than that of a bottom surface of the first hole structure TPa .

The furrow structure TPc can be so on the lower layer LL the passivation layer 101d be designed that they are in a thickness direction Z of the first substrate 100 with the second hole structure TPb communicates. The furrow structure TPc can be applied to an intermediate insulation layer by means of a wet etching process 101c that they are formed by the lower layer LL the passivation layer 101d passes through. For example, a cross-sectional surface of the furrow structure TPc along the first direction X have a ladder shape or an inverted ladder shape in which an upper side thereof is wider than a lower side thereof.

An upper surface of the furrow structure TPc may have a size wider than that of the second hole structure TPb , and a central portion of the upper surface of the furrow structure TPc can at a central portion of the second hole structure TPb be arranged. Therefore, the second hole structure TPb with respect to each of the first hole structure TPa and the furrow structure TPc to a central portion of the first trench structure TP1 protrude and can thus be a protrusion tip (or an insulation tip) that is located at an inner middle height of the first trench structure TP1 is arranged, implement. The first trench structure can accordingly TP1 the light emitting device ED the light emitting device layer 103 through the protrusion tip based on the second hole structure TPb isolate (or detach), or may all, from the light emitting device ED the light emitting device layer 103 and the common electrode CE isolate (or disconnect).

The at least one first trench structure (or a first trench structure) TS1 can on the passivation layer 101d the circuit layer 101 between at least two first trench structures TP1 is arranged to be executed. This means that the at least one first trench structure TS1 by means of two first trench structures TP1 on the passivation layer 101d can be formed.

The at least one first trench structure TS1 According to one embodiment, a lower trench structure TSa , a medium-sized trench construction TSb and an upper trench structure TSc exhibit.

The lower trench structure TSa can be at the bottom layer LL the passivation layer 101d be executed. The lower trench structure TSa can by means of the furrow structure TPc the first trench structure TP1 be implemented. For example, the lower trench structure TSa by means of the lower layer LL the passivation layer 101b that remains without going through a wet etching process of forming the furrow structure TPc the first trench structure TP1 on the lower layer LL the passivation layer 101d that are in the first margin area MA1 arranged to be removed, formed or arranged.

A side surface of the lower trench structure TSa according to an embodiment can be embodied in an inclined structure or a beveled structure. For example, a cross-sectional surface of the lower trench structure TSa along the first direction X may have a ladder shape in which an upper side thereof is narrower than a lower side thereof.

The middle trench construction TSb can be at the middle layer ML the passivation layer 101d be executed. The middle trench construction TSb can by means of the second hole structure TPb the first trench structure TP1 be implemented. For example, the middle trench construction TSb by means of the middle layer ML the passivation layer 101d that remains without going through a wet etching process of forming the second hole structure TPb the first trench structure TP1 on the middle layer ML the passivation layer 101d that are in the first margin area MA1 arranged to be removed, formed or arranged.

The middle trench construction TSb according to one embodiment may have a plate shape. The middle trench construction TSb may have a width that is wider than that of the lower trench structure TSa and can thus cover a ground surface of the lower trench structure TSa. The middle trench construction TSb can become an inner portion of the first trench structure TP1 protrude parallel to the first direction X and can thus have a protrusion tip (or an insulation tip) which is located at an internal central height of the first trench structure TP1 is arranged, implement. For example, in relation to the first direction X, the middle trench construction TSb have a width which is relatively wider than that of the lower trench structure TSa and can thus from a lateral surface of the lower trench structure TSa to the inner portion of the first trench structure TP1 protrude. The overhang of the central trench structure TSb can, with the lower trench construction TSa in between, with respect to a thickness direction Z of the first substrate 100 , removed from the intermediate insulation layer 101c be arranged. The overhang of the central trench structure TSb can be designed to be the light emitting device ED the light emitting device layer 103 isolated (or severed).

A side surface of the lower trench structure TSa can in relation to the middle trench construction TSb have an undercut structure (or an undercut area). For example, a boundary area between the lower trench structure TSa and the middle trench construction TSb or an upper side surface of the lower trench structure TSa in relation to the middle trench construction TSb be undercut. The middle trench construction TSb can in relation to the lateral surface of the lower trench structure TSa based on an undercut structure of the lower trench structure TSa in the direction of a central section of the first trench structure TP1 protrude and thus can form a bottom surface of the lower trench structure TSa cover. Accordingly, the middle trench construction TSb in relation to the lower trench structure TSa have a gutter structure or in relation to the lower trench structure TSa have an undercut area.

The side surface of the lower trench structure TSa can by means of the middle trench structure TSb be covered and can thus be defined as an undercut area with respect to the central trench structure TSb. An undercut area (or undercut structure) between the side surface of the lower trench structure TSa and a back surface of the central trench structure TSb is arranged, can be designed such that it is the light-emitting device ED the light emitting device layer 103 and the common electrode CE isolated (or severed).

The upper trench structure TSc can be attached to the top layer UL the passivation layer 101d be executed. The upper trench structure TSc can by means of the first hole structure TPa the first trench structure TP1 be implemented. For example, the lower trench structure TSc by means of the upper layer UL the passivation layer 101d that in a wet etching process of forming the first hole structure TPa the first trench structure TP1 on the top layer UL the passivation layer 101d that in the first Edge area MA1 arranged to be removed, formed or arranged.

A side surface of the upper trench structure TSc according to an embodiment can be implemented in an inclined structure or a beveled structure. For example, a cross-sectional surface of the upper trench structure TSc along the first direction X have a ladder shape in which an upper side thereof is narrower than a lower side thereof.

The inner trench structure section TPPa According to one embodiment, at least one first wall construction can furthermore be used BS1 exhibit.

The at least one first wall construction BS1 can on the at least one first trench structure TS1 be executed. The at least one first wall construction BS1 can on the upper trench structure TSc of the at least one first trench structure TS1 be formed or arranged. The at least one first wall construction BS1 can be used together with the wall 104 be made of the same material. Likewise, the at least one first wall construction BS1 be designed so that they are the same height (or thickness) as that of the rampart 104 having.

In the at least one first trench structure TS1 can be a lateral surface of the upper trench structure TSc an undercut structure in relation to the first wall construction BS1 exhibit. For example, a boundary section between the first wall construction BS1 and the upper trench structure TSc or an upper side surface of the upper trench structure TSc in relation to the first wall construction BS1 be undercut. The first wall construction BS1 can in relation to the lateral surface of the upper trench structure TSc based on an undercut structure of the upper trench structure TSc towards the middle section of the first trench structure TP1 protrude and thus can form a bottom surface of the upper trench structure TSc cover. Accordingly, the first wall construction BS1 in relation to the upper trench structure TSc have a gutter structure. For example, the first wall construction BS1 be defined as a first gutter structure.

In the at least one first trench structure TS1 can be the lateral surface of the upper trench structure TSc by means of the first wall construction BS1 be covered and can thus be used as an undercut area in relation to the first wall construction BS1 be defined. An undercut area (or undercut structure) between the side surface of the upper trench structure TSc and a back surface of the first wall structure BS1 is arranged, can be designed such that it is the light-emitting device ED the light emitting device layer 103 and the common electrode CE isolated (or severed).

The inner trench structure section TPPa According to one embodiment, a plurality of first trench structures can TS1 exhibit.

In each of the plurality of first trench structures TS1 can, for isolating (or separating) the light emitting device ED the light emitting device layer 103 and the common electrode CE , a width (or an interval) W2 between adjacent central trench structures TSb may be greater than an entire thickness of the light emitting device ED the light emitting device layer 103 and the common electrode CE . This means that if the width (or the interval) W2 between adjacent central trench structures TSb is smaller than the entire thickness of the light emitting device ED and the common electrode CE , common electrodes CE at the overhang peaks of the adjacent central trench structure TSb are arranged, can be electrically connected to one another and, because of this, the common electrode CE by means of the middle trench construction TSb or the first trench structure TP1 cannot be isolated (or segregated). On the other hand, if the width (or interval) W2 between adjacent central trench structures TSb is greater than the entire thickness of the light emitting device ED and the common electrode CE , the common electrode CE at the tip of the protrusion of each of the adjacent central trench structures TSb is arranged, by means of the middle trench structure TSb or the first trench structure TP1 isolated (or separated).

In each of the plurality of first trench structures TS1 can be a height of the lower trench structure TSa be greater than the entire thickness of the light emitting device ED and the common electrode CE . That is, when the height of the lower trench structure TSa is less than the entire thickness of the light emitting device ED and the common electrode CE , the common electrode CE at the tip of the protrusion of each of the adjacent central trench structures TSb is arranged electrically with the common electrode CE resting on a ground surface of the first trench structure TP1 is arranged, can be connected, and thus the common electrode CE by means of the middle trench construction TSb or the first trench structure TP1 cannot be isolated (or segregated). On the other hand, if the height of the lower Trench construction TSa is greater than the entire thickness of the light emitting device ED and the common electrode CE , the common electrode CE at the tip of the protrusion of each of the adjacent central trench structures TSb is arranged, and the common electrode CE that are on the ground surface of the first trench structure TP1 is arranged, by means of the middle trench structure TSb or the first trench structure TP1 isolated (or separated).

In addition, in each of the plurality of first trench structures TS1, such as the lower trench structure TSa, is for isolating (or separating) the light emitting device ED and the common electrode CE , a height of the upper trench structure TSc larger than an entire thickness of the light emitting device ED and the common electrode CE .

The inner trench structure section TPPa may be a protrusion tip that attaches to the at least one first trench structure TS1 is implemented, and can thus the light emitting device ED the light emitting device layer 103 isolate (or disconnect). The inner trench structure section can likewise TPPa a gutter structure or an undercut area (or an undercut structure) attached to the at least one first trench structure TS1 is implemented, and can thus the light emitting device ED the light emitting device layer 103 and the common electrode CE isolate (or disconnect). The inner trench structure section can likewise TPPa furthermore a gutter structure attached to the first wall construction BS1 is implemented, and can thus the light emitting device ED the light emitting device layer 103 and the common electrode CE isolate (or disconnect).

The trench structure section TPP According to one embodiment, an outer trench structure section can furthermore be used TPPb exhibit that of the dam structure 105 in the second edge area MA2 is arranged outwards.

The outer trench structure section (or a second trench structure section) TPPb may be arranged to adjoin an outer portion of the dam structure 105 adjoins, and may be arranged so that it has the dam structure 105 surrounds. This means that the outer trench structure section TPPb such between the dam structure 105 and an outer surface OS of the first substrate 100 may be designed to have a closed loop shape (or a closed loop line shape) representing the dam structure 105 surrounds, has. For example, the outer trench structure section TPPb along an edge portion of the first substrate 100 be designed in a closed loop shape (or a closed loop line shape) and can thus be designed in such a way that it has the dam structure 105 that has a closed loop shape (or a closed loop line shape) surrounds. The outer trench structure section TPPb can be done by means of a wet etching process on the passivation layer 101d the circuit layer 101 that are in the second margin area MA2 is arranged, can be implemented and thus the light emitting device ED the light emitting device layer 103 isolate (or disconnect) or can the common electrode CE and the light emitting device ED the light emitting device layer 103 isolate (or disconnect).

The outer trench structure section TPP according to one embodiment, at least two second trench structures TP2 and at least one second trench structure TS2 exhibit.

Apart from the fact that the at least two second trench structures TP2 adjacent to the outer portion of the dam structure 105 are arranged, the at least two second trench structures TP2 a first hole structure TPa , a second hole structure TPb and a furrow structure TPc which are designed such that they are essentially identical to the at least two first trench structures TP1 of the inner trench structure section TPPa and thus their repeated descriptions are omitted.

Apart from the fact that the at least one second trench construction TS2 by means of the at least two second trench structures TP2 is implemented, the at least one second trench structure TS2 a lower trench construction TSa , a medium-sized trench construction TSb and an upper trench structure TSc which are implemented such that they are substantially identical to the at least one first trench construction TS1 of the inner trench structure section TPPa and hence their repeated description is omitted. The at least one second trench structure TS2 may have a protrusion point that sticks to the middle trench structure TSb is implemented, an undercut area (or an undercut structure) between a side surface of the lower trench structure TSa and a back surface of the central trench structure TSb is implemented, and a gutter structure of the middle trench construction TSb exhibit.

The outer trench structure section TPPb According to one embodiment, at least one second wall construction can furthermore be used BS2 exhibit.

Apart from the fact that the at least one second wall construction BS2 on the at least one second trench structure TS2 is implemented, the at least one second wall construction BS2 be implemented in such a way that they are essentially identical to the at least one first wall construction BS1 of the inner trench structure section TPPa is, and thus its repeated description is omitted. The at least one second wall construction BS2 may be a gutter structure based on the second trench structure TS2 is implemented. For example, the second wall construction BS2 be defined as a second gutter structure.

The outer trench structure section TPPb may have a protrusion tip implemented on the at least one second trench structure TS2, and thus the light emitting device ED the light emitting device layer 103 isolate (or disconnect). The outer trench structure section can likewise TPPb a gutter structure or an undercut area (or an undercut structure) attached to the at least one second trench structure TS2 is implemented, and can thus the light emitting device ED the light emitting device layer 103 and the common electrode CE isolate (or disconnect). The outer trench structure section can likewise TPPb also a gutter structure attached to the second wall construction BS2 is implemented, and can thus the light emitting device ED the light emitting device layer 103 and the common electrode CE additionally isolate (or separate).

The trench structure section TPP according to the present embodiment, by means of a structuring process that is carried out on the wall 104 carried out, carried out.

The trench structure section TPP According to one embodiment, by means of a wet etching process using a mask structure that is formed on a wall material that forms the passivation layer 101d covered in each of the at least one first trench structure TS1 of the inner trench structure section TPPa and the at least one second trench structure TS2 of the outer trench structure section TPPb are to be implemented.

Each of the at least one first wall construction BS1 of the inner trench structure section TPPa and the at least one second wall construction BS2 of the outer trench structure section TPPb can be implemented using a wall material that is removed using a wet etch process.

Each of the at least one first trench structure TS1 of the inner trench structure section can likewise TPPa and the at least one second trench structure TS2 of the outer trench structure section TPPb by means of the passivation layer 101 d, which is selectively removed using a wet etch process.

The lower layer LL , the middle layer ML and the top layer UL the passivation layer 101d may have different unsaturated bond sites (or densities) and thus may have different etch speeds with respect to the same wet etch duration. When a wet etching process on the passivation layer 101d can be carried out the top layer UL are structured on the basis of a fastest etching speed in such a way that they are related to the wall construction BS1 and the wall construction BS2 having an undercut structure, the lower layer LL may have a faster etching speed than that of the middle layer ML and can thus be structured in such a way that it relates to the middle layer ML has an undercut structure, and the middle layer ML may have an etch rate slower than that of any of the top layers UL and the lower layer LL and thus can be based on the undercut structure of the lower layer LL protrude.

For example, if a wet etching process can be applied to the passivation layer 101d and the wall material that is on the first edge area MA1 and the second edge area MA2 of the first substrate 100 is stacked, is carried out, the wall structures BS1 and BS2 by means of the wall material that is not etched, and the trench structures TS1 and TS2 who have favourited the lower trench structure TSa , the middle trench construction TSb and the upper trench structure TSc may have by means of the lower layer LL , the middle layer ML and the top layer UL the passivation layer 101 d that are not etched can be implemented. In this case, an undercut structure (or an undercut area) based on different etching speeds in each of the upper trench structure TSc and the lower trench structure TSa of the trench structures TS1 and TS2 can be implemented, and a protrusion spike can be attached to the center trench structure TSb of the trench structures TS1 and TS2 implemented.

Optionally, in the trench structure section TPP according to an embodiment, each of the inner trench structure portion TPPa and the outer trench structure portion TPPb further a dummy pixel electrode structure that between the trench structures TS1 and TS2 and the wall constructions BS1 and BS2 is arranged have. The dummy pixel electrode structure can be used together with the pixel electrode PE that are in the emission area EA of the pixel P can be formed from the same material. That is, the dummy pixel electrode structure cannot be removed in a process of patterning a pixel electrode material and in an island shape on the passivation layer 101d in which the trench structures TS1 and TS2 to be implemented, can remain and thus between the trench structures TS1 and TS2 and the wall constructions BS1 and BS2 can be arranged.

In addition, in the trench structure section TPP according to an embodiment, each of the inner trench structure portion TPPa and the outer trench structure portion TPPb furthermore an island-shaped planarization layer 102 between the trench structures TS1 and TS2 and the wall constructions BS1 and BS2 is arranged or between the dummy pixel electrode structure and the trench structures TS1 and TS2 is arranged have. The planarization layer 102 can be along with the dam structure 105 Be formed from the same material and can be the same height (or thickness) as that of the dam structure 105 may have or may be the same height (or thickness) as that of the planarization layer 102 overlapping the emission area EA of the pixel P.

In the display device 10 According to the present disclosure, the light emitting device can ED the light emitting device layer 103 that are on the trench structure section TPP is formed (or deposited), once or several times by means of the trench structure section TPP isolated (or separated). For example, the trench structure section TPP at least one light emitting device isolation portion on which the light emitting device ED is isolated (or separated).

According to one embodiment, a deposition material EDm of the light emitting device ED Have linearity and thus can only be on a top surface and a side surface of each of the wall structures BS1 and BS2 , which are arranged in the trench structure portion TPP, an upper surface of the protruding tip of the middle trench structure TSb, which by means of the wall structures BS1 and BS2 is not covered, and a soil surface of each of the trench structures TP1 and TP2 and can thus be deposited on a side surface of each of the lower trench structure TSa , the middle trench construction TSb and the upper trench structure TSc , which by means of the wall constructions BS1 and BS2 are covered, are not deposited. Therefore, the light emitting device can ED that are on the trench structure section TPP is formed (or deposited) between the wall structures BS1 and BS2 and the upper trench structure TSc isolated (or separated) and can also be between the lower trench structure TSa and the middle trench structure TSb isolated (or separated). Accordingly, the light emitting device ED that are in the first margin area MA1 and the second edge area MA2 is arranged by means of the trench structure section TPP are automatically isolated (or separated) in a deposition process. Accordingly, in the display device 10 according to the present embodiment, the light emitting device ED be isolated (or separated) by means of only a deposition process performed on the light emitting device, even without a separate structuring process of isolating (or separating) the light emitting device ED that are in the first margin area MA1 and the second edge area MA2 is arranged.

In the display device 10 according to the present embodiment, the common electrode CE the light emitting device layer 103 that are on the trench structure section TPP is formed (or deposited) by means of the trench structure portion TPP be isolated (or separated) once or several times. For example, the trench structure section TPP at least one common electrode isolation portion in which the common electrode CE is isolated (or separated).

According to one embodiment, a common electrode material CEm of the light emitting device ED on only the top surface and the side surface of each of the wall structures BS1 and BS2 , a portion of an undercut area of the upper trench structure TSc , the top surface and the side surface of the protrusion tip of the central trench structure TSb and the soil surface of each of the trench structures TP1 and TP2 can be deposited, and thus the light emitting device ED attached to the trench structure section TPP has been arranged to cover. In this case, the common electrode material CEm on the side surface of each of the lower trench structure TSa and the upper trench structure TSc , which by means of the wall constructions BS1 and BS2 are covered, are not deposited. Therefore, the common electrode CE such as the light emitting device ED , or the common- Electrode material CEm formed (or deposited) on the trench structure portion TPP between the wall structures BS1 and BS2 and the upper trench structure TSc isolated (or segregated) and may also be between the lower trench structure TSa and the middle trench construction TSb isolated (or separated). Accordingly, the common electrode CE that are in the first margin area MA1 and the second edge area MA2 is arranged, in a deposition process by means of the trench structure portion TPP automatically isolated (or disconnected). Accordingly, in the display device 10 According to the present embodiment, the common electrode CE can be isolated (or separated) by only a deposition process performed on the common electrode CE, even without a separate patterning process of isolating (or separating) the common electrode CE that are in the first margin area MA1 and the second edge area MA2 is arranged. Likewise, the common electrode, which is arranged in the first edge region MA1 and the second edge region MA2, can surround an insulation surface of the light-emitting device ED in the trench structure section TPP and can thus prevent lateral penetration of water through a boundary section between the intermediate insulation layer 101c and prevent the light emitting device ED, thereby preventing a reduction in the reliability of the light emitting device ED caused by the lateral intrusion of water.

In the display device 10 According to the present embodiment, a first encapsulation layer 106a an encapsulation layer 106 that are in the first edge region MA1 and the second edge region MA2 of the first substrate 100 is arranged, be designed such that they the inner trench structure portion TPPa and the outer trench structure portion TPPb of the trench structure portion TPP and the dam structure 105 surrounds. For example, the first encapsulation layer 106a cover the trench structure section TPP and thus cannot be isolated (or separated) by means of the trench structure section TPP. For example, the first encapsulation layer 106a be filled into the trench structures TP1 and TP2 of the trench structure section TPP and can also be designed in such a way that it surrounds the trench structures TS1 and TS2 and the wall structures BS1 and BS2.

In the first edge area MA1 of the first substrate 100 can be a second encapsulation layer 106b the encapsulation layer 106 be designed such that they are the first encapsulation layer 106a that include the inner trench structure portion TPPa of the trench structure portion TPP and an inner surface of the dam structure 105 covered, covered.

In the first edge area MA1 and the second edge area MA2 of the first substrate 100 can be a third encapsulation layer 106c the encapsulation layer 106 be designed such that they are the first encapsulation layer 106a that include the inner trench structure portion TPPa of the trench structure portion TPP and an outer surface of the dam structure 105 covered, and the second encapsulation layer 106b covered. The inner trench structure section TPPa can be arranged in such a way that it has the first encapsulation layer to the third encapsulation layer 106a , 106b and 106c overlaps. The outer trench structure section TPPb can be arranged in such a way that it has the first encapsulation layer 106a and the second encapsulation layer 106b overlaps.

As the display device 10 according to the present embodiment has the trench structure portion TPP, a total width of the first edge region MA1 and the second edge region MA2, which at an edge portion of the first surface 100a of the first substrate 100 are arranged to decrease to 350 µm or less, and in this case, the display device can 10 realize a resolution that is higher than that of a display device that does not have a trench structure portion TPP.

For example, if a half of a first interval (or a pixel pitch) D1 between two adjacent pixel areas PA within the process error area is 350 µm, an entire width (or a shortest distance between an outer surface of the first substrate and an end of an emission area EA of an outermost one Pixels) of the first edge area MA1 and the second edge area MA2, based on a shadow edge based on a shadow area of the light emitting device ED, and an encapsulation edge based on ensuring the reliability of the light emitting device ED against water, can be embodied in such a way that they 320 µm or less. In this case a second interval can be used D2 between an outermost outer surface VL of the first substrate 100 and a central portion of an outermost pixel comprising a first pad area 110 has, be designed such that it is 350 microns within the process error range. Here, the outermost outer surface VL of the first substrate 100 an outermost outer surface of an edge coat layer 403 that have a wiring section 400 covered, be.

The first edge area MA1 and the second edge area MA2 can have the same width or have different widths. For example, with respect to the first direction X, the first edge region MA1 can be designed such that it has a width of 200 μm or less, and the second edge region MA2 can be designed such that it has a width of 120 μm or less . Likewise, a pad edge area (or a lateral wiring area) contained in the second edge area MA2 can be designed such that it has a width of 100 μm or less with respect to the first direction X.

Optionally, the trench structure portion TPP according to the present embodiment can include the common power contact portion and the secondary power contact portion shown in FIG 20th or 21 are shown, implement. That is, the trench structure portion TPP according to the present embodiment is located on each of a contact line CPLc and a secondary contact line SPLc shown in FIG 20th or 21 can be arranged and thus each of a pixel common power line CPL and a secondary power line SPL can electrically connect to the common electrode CE. For example, the trench structures TP1 and TP2 of the trench structure section TPP can be embodied in such a way that each of the contact line CPLc and the secondary contact line SPLc, which are shown in FIG 20th or 21 is exposed, and the common electrode CE can be electrically connected to each of the contact line CPLc and the secondary contact line SPLc exposed by the trench structures TP1 and TP2 in a deposition process. This means that, in a deposition process that is carried out on the common electrode CE, the common electrode material CEm that is deposited on the trench structure section TPP can be isolated (or separated) by means of the trench structures TS1 and TS2, however an upper surface of each of the contact line CPLc and the secondary contact line SPLc through the trench structures TP1 and TP2, which are arranged at both edge portions of the trench structure portion TPP, and thus the common electrode CE through the trench structures TP1 and TP2, which are deposited disposed on both edge portions of the trench structure portion TPP can be electrically connected to each of the contact line CPLc and the secondary contact line SPLc. Accordingly, each of the common power contact portion and the secondary power contact portion shown in FIG 20th or 21 can be changed to the trench structure section TPP.

28 FIG. 11 is another cross-sectional view taken along a line II-II 'shown in FIG 4th is shown, and 29 FIG. 13 is an enlarged view of an area "B8" shown in FIG 28 is shown. 28 and 29 illustrate an embodiment in which a trench structure portion is further arranged close to a dam structure, in the display device shown in FIG 1 until 21 When describing the 28 and the 29 become elements that are equal to the elements of the 1 until 21 or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 28 and 29 can be a display device 10 according to the present disclosure have a trench structure portion TPP that is close to a dam structure 105 a first substrate 100 is arranged.

The trench structure section TPP can be designed in such a way that it prevents the penetration of water through a lateral surface of the first substrate 100 prevents, for preventing deterioration caused by lateral invasion of water in a light emitting device ED of a light emitting device layer 103 . For example, the trench structure section TPP can be at a periphery of the dam structure 105 isolate (or disconnect) the light emitting device ED. Accordingly, the trench structure portion TPP can be defined as an isolation region or a separation line of the light emitting device ED.

The light emitting device ED of the light emitting device layer 103 can on a wall 104 and a pixel electrode PE exposed at an emission region EA of each of a plurality of sub-pixels SP, and may be further provided on a passivation layer 101d on an edge portion of a first surface 100a of the first substrate 100 is exposed, be arranged. Therefore, the light emitting device ED can become damaged due to the penetration of water through the side surface of the first substrate 100 may be deteriorated or their reliability may be reduced. In order to solve such a problem, the trench structure portion TPP may be the light emitting device ED of the light emitting device layer 103 that are close to the dam structure 105 is arranged, isolate (or cut off), thereby preventing or minimizing a reduction in the reliability of the light-emitting device ED caused by the lateral ingress of water.

The trench structure section (or an isolation structure section) TPP can be so close to the dam structure 105 be executed that he a Isolation structure (or a partition structure or a cut-off structure) for isolating (or partitioning) the light emitting device ED that is close to the dam structure 105 or implemented to isolate (or separate) all of the light emitting device ED and the common electrode CE. The isolation structure according to an embodiment may include at least one of a gutter structure (or a cliff structure) and an undercut structure. Therefore, the common electrode CE and the light emitting device ED located close to the dam structure 105 is arranged, can be isolated (or separated) by means of an isolation structure of the trench structure portion TPP in the middle of performing a deposition process, without a separate process. The trench structure section TPP can be made by means of an encapsulation layer 106 be covered. The encapsulation layer 106 can be a top surface of a circuit layer in the trench structure section TPP 101 directly and thus may surround a side surface (or an insulation surface) of each of the isolated light emitting device ED and the common electrode CE. For example, the encapsulation layer 106 be filled in an isolation space formed by the isolation structure of the trench structure portion TPP and can seal or completely surround the trench structure portion TPP and thus can completely surround the side surface (or the insulation surface) of each of the isolated light emitting device ED and the common electrode or cover, whereby a lateral penetration of water is fundamentally (or completely) prevented.

The trench structure portion TPP can be along an edge portion of the first surface 100a of the first substrate 100 be implemented in a trench structure layer. The trench structure layer can be on a passivation layer 101d on the edge portion of the first surface 100a of the first substrate 100 is arranged, be arranged. The trench structure section TPP can have an insulation structure that is created by structuring the trench structure layer that is close to the dam structure 105 is arranged to be implemented. For example, the trench structure portion TPP may have a lower structure (or an undercut structure) having an undercut structure and an upper structure (or a gutter structure) disposed on the lower structure and having a gutter structure with respect to the lower structure.

The display device 10 according to the present embodiment can furthermore have a trench structure layer for implementing the trench structure section TPP. The trench structure layer may have a first dummy material layer (or a lower material layer) and a second dummy material layer (or an upper material layer). The first dummy material layer can be used together with a planarization layer 102 that is under the light emitting device layer 103 is arranged to be formed from the same material. The second dummy material layer may comprise a material that is different from that of the first dummy material layer. The second dummy material layer can have a lower etching speed than the first dummy material layer in an etching process. For example, based on a material, the first dummy material layer can be a dummy organic material layer DOL comprising an organic material, and the second dummy material layer can be a dummy inorganic material layer DIL comprising an inorganic material.

The trench structure layer according to one embodiment can furthermore have a dummy organic material layer DOL and a dummy inorganic material layer DIL. The dummy organic material layer DOL and the dummy inorganic material layer DIL can be in a first edge region MA1 and a second edge region MA2 (or the trench structure section TPP), which are at an edge section of the first surface 100a of the first substrate 100 are defined, be arranged. For example, the dummy organic material layer DOL can be defined as a first dummy material layer or a lower material layer, and the dummy inorganic material layer DIL can be defined as a second dummy material layer or an upper material layer.

The dummy organic material layer DOL can be in the first edge region MA1 and the second edge region MA2, which are at the edge portion of the first surface 100a of the first substrate 100 are defined, and can be carried out together with the planarization layer 102 that is under the light emitting device layer 103 is arranged to be formed such that it is a circuit layer 101 covered. For example, the dummy organic material layer DOL can be embodied as a section which remains in an island shape in the first edge region MA1 and the second edge region MA2 without being involved in a structuring process of forming a contact hole for electrically connecting the pixel electrode PE to a drive TFT in the planarization layer 102 that is everything from the circuit layer 101 that are on the first substrate 100 is arranged to be covered to be removed.

The dummy inorganic material layer DIL can be applied to the dummy organic Material layer DOL be designed that it has a relatively thin thickness. The dummy inorganic material layer DIL according to one embodiment can comprise SiOx, SiNx or SiON. For example, the dummy inorganic material layer can DIL on the planarization layer 102 having a contact hole can be formed or arranged after the patterning process of forming the contact hole for electrically connecting the pixel electrode PE to the drive TFT. Likewise, a section other than the dummy inorganic material layer DIL arranged in the first edge region MA1 and the second edge region MA2 can be removed by means of the structuring process, and, in the structuring process, the dummy material layer arranged in the first edge region MA1 and the second edge region MA2 can be removed. Inorganic material layer DIL for implementing the trench structure section TPP can be partially removed.

The trench structure portion TPP according to an embodiment may include an inner trench structure portion TPPa that is formed by the dam structure 105 is arranged inwardly in the first edge region MA1.

The inner trench structure portion (or a first trench structure portion) TPPa may be arranged such that it is adjacent to an inner portion of the dam structure 105 is arranged, and can be arranged such that it is by means of the dam structure 105 is surrounded. This means that the inner trench structure section TPPa is thus between the dam structure 105 and an emission area EA of an outermost pixel area PAo may be configured to have a closed loop shape (or a closed loop shape) created by means of the dam structure 105 is surrounded, has. For example, the inner trench structure portion TPPa along an edge portion of the first substrate 100 be designed in a closed loop shape (or a closed loop shape) and can thus be designed in such a way that by means of the dam structure 105 having a closed loop shape (or a closed loop shape) is surrounded. The inner trench structure portion TPPa can be the light emitting device ED of the light emitting device layer 103 isolate (or cut off) and all of the common electrode CE and the light emitting device ED of the light emitting device layer 103 at a section inward of the dam structure 105 isolate (or disconnect).

One width W1 of the inner trench structure portion TPPa according to an embodiment may be wider than a width of the dam structure 105 . For example, the width W1 of the inner trench structure portion TPPa can be 20 μm to 60 μm, but is not limited thereto, and may be changed based on a width of the first edge region MA1 or may be changed based on a total width of the first edge region MA1 and a second edge region MA2.

The inner trench structure section TPPa according to one embodiment can have at least two first trench structures TP1 and at least one first trench structure TS1.

The at least two first trench structures TP1 can adjoin an inner section of the dam structure on the dummy inorganic material layer DIL and the dummy organic material layer DOL 105 be executed. For example, the at least two first trench structures TP1 can be implemented by means of a dry etching process that is carried out on the dummy inorganic material layer DIL and the dummy organic material layer DOL.

Each of the at least two first trench structures TP1 according to an embodiment can have a hole structure TPa and a groove structure TPg.

The hole structure TPh can be implemented on the dummy inorganic material layer DIL. The hole structure TPh according to one embodiment can be formed by a structuring process that is carried out on the dummy inorganic material layer DIL in such a way that it passes through the dummy inorganic material layer DIL. For example, a cross-sectional surface of the hole structure TPh along the first direction X can have a tetragonal shape or a right-angled shape.

A width (or a size) W2 of the hole structure TPh may be larger than an entire thickness of the light emitting device ED of the light emitting device layer 103 and the common electrode CE for isolating (or separating) the light emitting device ED of the light emitting device layer 103 and the common electrode CE. That means that if the width W2 of the hole structure TPh is less than the total thickness of the light emitting device ED and the common electrode CE, the common electrode CE arranged on a top surface and a side surface of the hole structure TPh can be electrically connected to each other, and due to this, the common electrode CE cannot be insulated (or separated) by means of the hole structure TPh. On the other hand, if the width W2 of the hole structure TPh is greater than the total thickness of the light emitting device ED and the common electrode CE, the common electrode CE, which is on each of the Upper surface and the side surface of the hole structure TPh is arranged, be isolated (or separated) by means of the hole structure TPh.

The furrow structure TPg can be in a thickness direction Z of the first substrate 100 be implemented on the dummy organic material layer DOL in such a way that it communicates with the hole structure TPh. The furrow structure TPg can be formed by a dry etching process, which is carried out at least twice, in such a way that it passes through the dummy organic material layer DOL.

The groove structure TPg according to an embodiment can have an upper section that communicates directly with the dummy inorganic material layer DIL, and a lower section that communicates with the passivation layer 101 d directly exposed, and have a central portion between the upper portion and the lower portion. The central portion of the groove structure TPg may have a width that is wider or narrower than the upper portion and the lower portion. Therefore, a cross-sectional surface of the groove structure TPg along the first direction X may have a structure in which the central portion protrudes or is recessed with respect to the upper portion and the lower portion. For example, the cross-sectional surface of the groove structure TPg along the first direction X can have a cross-sectional structure that has a “)” shape, a “〉” shape, a “(” shape or a “〈” shape.

An upper portion of the groove structure TPg may have a size wider than that of the hole structure TPh, and a central portion of the upper portion of the groove structure TPg may be arranged at a central portion of the hole structure TPh. Therefore, the hole structure TPh can protrude toward a central portion of the first trench structure TP1 with respect to the groove structure TPg, and thus can implement a protruding tip (or an isolation tip) arranged at a highest height of the first trench structure TP1. Accordingly, the first trench structure TP1 can be the light-emitting device ED of the light-emitting device layer 103 by the protruding tip based on the hole structure TPh, or may isolate (or separate) all of the light emitting device ED of the light emitting device layer 103 and isolate (or cut off) the common electrode CE.

The at least one first trench structure (or a first trench structure) TS1 can be implemented on the dummy organic material layer DOL, which is arranged between at least two first trench structures TP1. This means that the at least one first trench structure TS1 can be formed or arranged on the dummy organic material layer DOL by means of two first trench structures TP1.

The at least one first trench structure TS1 according to one embodiment can have a lower trench structure TSa and an upper trench structure TSb.

The lower trench structure TSa can be implemented on the dummy organic material layer DOL. The lower trench structure TSa can be implemented by means of the groove structure TPg of the first trench structure TP1. For example, the lower trench structure TSa can be implemented or arranged by means of the dummy organic material layer DOL, which remains without forming the groove structure TPg of the first trench structure TP1 on the dummy organic material layer DOL in an at least two-fold dry etching process is arranged in the first edge area MA1 to be removed.

The lower trench structure TSa according to an embodiment can have an upper surface that directly contacts the dummy inorganic material layer DIL, a bottom surface that the passivation layer 101 d directly touched, and have a central portion between the top surface and the bottom surface.

In the lower trench structure TSa, an upper surface between the upper surface and the central portion may be made in a sloped structure or a tapered structure. For example, the top of the lower trench structure TSa along the first direction X may have a cross-sectional structure that has a conductor structure in which an upper side thereof is narrower than a lower side thereof.

In the lower trench structure TSa, an underside between the bottom surface and the central portion may be made in a sloped structure or a sloped structure. For example, the lower side of the lower trench structure TSa along the first direction X may have a cross-sectional structure that has a ladder shape in which an upper side thereof is wider than a lower side thereof.

The central portion of the lower trench structure TSa may have a width (or size) wider or narrower than that of each of the upper surface and the bottom surface thereof.

The upper trench structure TSb can be implemented on the dummy inorganic material layer DIL. The upper trench structure TSb can be implemented by means of the hole structure TPh of the first trench structure TP1. For example, the upper trench structure TSb can be formed or arranged by means of the dummy inorganic material layer DIL, which remains without being subjected to a structuring process that is carried out on the dummy inorganic material layer DIL, which is arranged in the first edge region MA1, or a drying process. Etching process of forming the hole structure TPh of the first trench structure TP1 to be removed on the dummy inorganic material layer DIL arranged in the first edge region MA1.

The upper trench structure TSb according to an embodiment may have a plate shape. The upper trench structure TSb can have a width that is wider than that of the lower trench structure TSa and can thus cover a bottom surface of the lower trench structure TSa. The upper trench structure TSb can protrude parallel to the first direction X to an inner portion of the first trench structure TP1 and thus a protrusion tip (or an insulation tip) arranged at a highest height of the first trench structure TP1 can be implemented. For example, with respect to the first direction X, the upper trench structure TSb can have a width which is relatively wider than that of the lower trench structure TSa and can thus protrude towards the inner section of the first trench structure TP1. The protrusion tip of the upper trench structure TSb can be the reference to a thickness direction Z of the first substrate 100 at a distance from the passivation layer 101 d, with the lower trench structure TSa in between. The protruding tip of the upper trench structure TSb can be designed in such a way that it forms the light emitting device ED of the light emitting device layer 103 isolated (or severed).

The upper trench structure TSb according to one embodiment can be formed by means of a structuring process that is carried out on the dummy inorganic material layer DIL that is on the planarization layer 102 which is formed after a patterning process of forming a contact hole, which electrically connects the pixel electrode PE to a drive TFT, in the planarization layer 102 implemented. For example, the upper trench structure TSb can be implemented by means of a dry etching process that is carried out on the dummy inorganic material layer DIL.

A side surface of the lower trench structure TSa can, as in 30th shown, have an undercut structure UCS with respect to the upper trench structure TSb. For example, a boundary portion between the lower trench structure TSa and the upper trench structure TSb or an upper side surface of the lower trench structure TSa can be undercut with respect to the upper trench structure TSb. The upper trench structure TSb can protrude with respect to the lateral surface of the lower trench structure TSa on the basis of an undercut structure UCS of the lower trench structure TSa in the direction of a central portion of the first trench structure TP1 and can thus cover the side surface of the lower trench structure TSa. Accordingly, the upper trench structure TSb may have a protruding tip Ttip that protrudes with respect to the lateral surface of the lower trench structure TSa, or may have a gutter structure with respect to the lower trench structure TSa. In 30th For example, a white layer WL may be an overcoat layer experimentally layered to identify a cross-sectional structure of the first trench structure TS1, and thus may not correspond to an element of the display device according to the present disclosure.

The lateral surface of the lower trench structure TSa can be covered by means of the upper trench structure TSb and can thus be defined as an undercut area in relation to the upper trench structure TSb. An undercut area (or an undercut structure) disposed between the side surface of the lower trench structure TSa and a back surface of the upper trench structure TSb may be implemented to include the light emitting device ED of the light emitting device layer 103 and isolates (or disconnects) the common electrode CE.

The lower trench structure TSa according to an embodiment can be made by means of a dry etching process, which is carried out after a dam structuring process of forming a lower dam structure of the dam structure 105 implemented. For example, the lower trench structure TSa can be implemented on the dummy organic material layer DOL by means of a primary dry etching process that uses a photomask disposed on the upper trench structure TSb as a mask, and can be implemented using a secondary dry etching process performed after the primary dry etching process can be implemented to have an undercut area (or an undercut structure).

The inner trench structure section TPPa may have a protruding tip which is implemented on the at least one first trench structure TS1, and thus may represent the light-emitting device ED of the light-emitting device. layer 103 isolate (or disconnect). Likewise, the inner trench structure portion TPPa may have a gutter structure or an undercut area (or an undercut structure) implemented on the at least one first trench structure TS1, and thus may comprise the light emitting device ED of the light emitting device layer 103 and isolate (or cut off) the common electrode CE.

The trench structure section TPP according to an embodiment may further comprise an outer trench structure section TPPb, which is formed by the dam structure 105 is arranged outwardly in the second edge region MA2.

The outer trench structure section (or a second trench structure section) TPPb may be arranged such that it is adjacent to an outer section of the dam structure 105 is arranged, and can be arranged such that it has the dam structure 105 surrounds. This means that the outer trench structure section TPPb is thus between the dam structure 105 and an outer surface OS of the first substrate 100 It can be implemented to have a closed loop shape (or a closed loop shape) representing the dam structure 105 surrounds, has. For example, the outer trench structure portion TPPb may be in a closed loop shape (or a closed loop shape) along an edge portion of the first substrate 100 be implemented and thus can be implemented in such a way that it has the dam structure 105 which has a closed loop shape (or a closed loop shape) surrounds. The outer trench structure portion TPPb may, on an outer portion of the dam structure 105 , the light emitting device ED of the light emitting device layer 103 may isolate (or cut off) or the common electrode CE and the light emitting device ED of the light emitting device layer 103 isolate (or disconnect).

The outer trench structure section TPPb according to one embodiment can have at least two second trench structures TP2 and at least one second trench structure TS2.

Apart from the fact that the at least two second trench structures TP2 are adjacent to the outer section of the dam structure 105 are arranged, the at least two second trench structures TP2 may have a hole structure TPh and a groove structure TPg implemented such that they are substantially identical to the at least two first trench structures TP1 of the inner trench structure portion TPPa, and thus their repeated descriptions are omitted .

Apart from the fact that the at least one second trench structure TS2 is implemented by means of the at least two second trench structures TP2, the at least one second trench structure TS2 can have a lower trench structure TSa and an upper trench structure TSb, which are implemented in such a way that they are essentially identical to that are at least a first trench structure TS1 of the inner trench structure portion TPPa, and thus their repeated description is omitted. The at least one second trench structure TS2 may have a protruding tip implemented on the upper trench structure TSb, an undercut area (or an undercut structure) implemented between a side surface of the lower trench structure TSa and a rear surface of the upper trench structure TSb, and a gutter structure of the Have upper trench structure TSb.

The outer trench structure portion TPPb may have a protruding tip which is implemented on the at least one second trench structure TS2 and may thus constitute the light-emitting device ED of the light-emitting device layer 103 isolate (or disconnect). Likewise, the outer trench structure portion TPPb may have a gutter structure or an undercut area (or an undercut structure) implemented on the at least one second trench structure TS2, and thus the light emitting device ED of the light emitting device layer 103 and isolate (or cut off) the common electrode CE.

In the display device 10 According to one embodiment, the dam structure 105 on the dummy inorganic material layer DIL, which is arranged between the inner trench structure portion TPPa and the outer trench structure portion TPPb of the trench structure portion TPP. The dam structure 105 According to one embodiment, a lower dam structure comprising the same material as that of the planarization layer can be used 102 , and an upper dam structure made of the same material as the embankment 104 and stacked on the lower dam structure. The lower dam structure may be arranged on the dummy inorganic material layer DIL between the inner trench structure portion TPPa and the outer trench structure portion TPPb to be the same height (or thickness) as that of the planarization layer 102 or has a height that is greater than that of the planarization layer 102 .

Optionally, in the trench structure portion TPP according to an embodiment, each of the inner trench structure portion TPPa and the outer trench structure section TPPb furthermore have a dummy pixel electrode structure which is arranged on the upper trench structure TSb of the trench structures TS1 and TS2. The dummy pixel electrode structure can be formed together with the pixel electrode PE arranged in the emission region EA of the pixel P. This means that the dummy pixel electrode structure is not removed in a process of patterning a pixel electrode material and can additionally be formed or arranged on the dummy inorganic material layer DIL.

In the display device 10 According to the present embodiment, the light emitting device ED may be the light emitting device layer 103 , which is formed (or deposited) on the trench structure portion TPP, can be isolated (or separated) once or several times by means of the trench structure portion TPP. For example, the trench structure portion TPP can have at least one light-emitting device isolation portion in which the light-emitting device ED is isolated (or separated).

According to one embodiment, a deposition material EDm of the light-emitting device ED can have linearity and can thus be deposited on only an upper surface of the upper trench structure TSb of the trench structures TS1 and TS2 and bottom surfaces of the trench structures TP1 and TP2 that are not covered by the upper trench structure TSb and cannot be deposited on a side surface of the lower trench structure TSa that is covered by a gutter structure of the upper trench structure TSb. Therefore, the light emitting device ED formed (or deposited) on the trench structure portion TPP can be isolated (or separated) by means of a protruding tip disposed on the upper trench structure TSb of the trench structures TS1 and TS2, or an undercut structure of the lower trench structure TSa . Accordingly, the light-emitting device ED, which is arranged in the first edge region MA1 and the second edge region MA2, can be automatically isolated (or separated) in a deposition process by means of the trench structure section TPP. Accordingly, in the display device 10 According to the present embodiment, the light emitting device ED can be isolated (or separated) by means of only a deposition process performed on the light emitting device, even without a separate patterning process of isolating (or separating) the light emitting device ED located in the first edge region MA1 and the second edge area MA2 is arranged.

In the display device 10 according to the present embodiment, the common electrode CE may be the light emitting device layer 103 , which is formed (or deposited) on the trench structure portion TPP, can be isolated (or separated) once or several times by means of the trench structure portion TPP. For example, the trench structure section TPP can have at least one common electrode insulation section in which the common electrode CE is insulated (or separated).

According to one embodiment, a common electrode material CEm of the common electrode CE cannot be deposited on the undercut region which is arranged in the lower trench structure TSa of the trench structure section TPP. Therefore, like the light emitting device ED, the common electrode CE or the common electrode material CEm formed (or deposited) on the trench structure portion TPP can be isolated (or separated). Accordingly, the common electrode CE, which is arranged in the first edge region MA1 and the second edge region MA2, can be automatically isolated (or separated) in a deposition process by means of the trench structure section TPP. Accordingly, in the display device 10 According to the present embodiment, the common electrode CE can be isolated (or separated) by means of only one deposition process performed on the common electrode CE, even without a separate structuring process of isolating (or separating) the common electrode CE performed in the first Edge area MA1 and the second edge area MA2 is arranged. Likewise, the common electrode CE, which is arranged in the first edge region MA1 and the second edge region MA2, can surround an insulation surface of the light-emitting device ED in the trench structure section TPP and can thus prevent lateral penetration of water through the insulation surface of the light-emitting device ED, whereby a reduction in the reliability of the light emitting device ED caused by the lateral intrusion of water is prevented.

In the display device 10 According to the present embodiment, in the first edge region MA1 and the second edge region MA2 of the first substrate 100 , a first encapsulation layer 106a the encapsulation layer 160 be designed such that they the inner trench structure portion TPPa and the outer trench structure portion TPPb of the trench structure portion TPP and the dam structure 105 surrounds. For example, the first encapsulation layer 106a the Cover trench structure section TPP and thus cannot be isolated (or separated) by means of trench structure section TPP. For example, the first encapsulation layer 106a be filled into the trench structures TP1 and TP2 of the trench structure section TPP and can also be designed in such a way that it surrounds the trench structures TS1 and TS2.

In the first edge area MA1 of the first substrate 100 can be a second encapsulation layer 106b the encapsulation layer 106 be designed such that they are the first encapsulation layer 106a covering the inner trench structure portion TPPa of the trench structure portion TPP and an inner surface of the dam structure 105 covered. The second encapsulation layer 106b can become an edge portion of the first surface due to a relatively thick thickness 100a of the first substrate 100 spread, however, the spread of the second encapsulation layer 106b by means of the dam structure 105 be blocked. For example, one end of the second encapsulation layer 106b the first encapsulation layer 106a on the dam structure 105 touch directly. Accordingly, the second encapsulation layer 106b on only the first encapsulation layer 106a in an internal area (or an internal area) by means of the dam structure 105 is surrounded, be arranged.

In the first edge area MA1 and the second edge area MA2 of the first substrate 100 can be a third encapsulation layer 106c the encapsulation layer 106 be designed such that they are the first encapsulation layer 106a that include the inner trench structure portion TPPa of the trench structure portion TPP and an outer surface of the dam structure 105 covered, and the second encapsulation layer 106b covered.

As the display device 10 according to the present embodiment has a trench structure section TPP, a total width of the first edge region MA1 and the second edge region MA2, which is at an edge section of the first surface 100a of the first substrate 100 are arranged to decrease to 350 µm or less, and in this case, the display device may 10 realize a resolution that is higher than that of a display device that does not have a trench structure portion TPP.

For example, if a half of a first interval (or a pixel pitch) D1 between two adjacent pixel areas PA within the process error area is 350 µm, a total width (or a shortest distance between an outer surface of the first substrate and an end of an emission area EA of an outermost pixel ) the first edge area MA1 and the second edge area MA2 can be implemented to be 320 µm or less based on a shadow edge based on a shadow area of the light emitting device ED and an encapsulation edge based on ensuring the reliability of the light emitting device ED against water. In this case a second interval can be used D2 between an outermost outer surface VL of the first substrate 100 and a central portion of an outermost pixel comprising a first pad area 110 has to be implemented in such a way that it is 350 μm within the process error range. Here, the outermost outer surface VL of the first substrate 100 an outermost outer surface of an edge coat layer 403 that have a wiring section 400 covered, be.

The first edge area MA1 and the second edge area MA2 can have the same width or different widths. For example, with respect to the first direction X, the first edge region MA1 can be designed such that it has a width of 200 μm or less, and the second edge region MA2 can be designed such that it has a width of 120 μm or less . Likewise, a pad edge area (or a lateral wiring area) that is contained in the second edge area MA2 can be designed such that it has a width of 100 μm or less with respect to the first direction X.

31 FIG. 11 is another cross-sectional view taken along a line II-II 'shown in FIG 4th is shown, and 32 FIG. 13 is an enlarged view of an area “B9” shown in FIG 30th is shown. 31 and 32 illustrate an embodiment that consists of removing (or omitting) a dam structure and modifying a structure of an encapsulation layer in the display device shown in FIG 1 until 21 is shown, is set up. When describing the 31 and the 32 For example, elements other than a light emitting device, a common electrode, and an encapsulation layer are substantially the same as the elements of FIG 1 until 21 , and thus like reference numerals refer to like elements and their repeated descriptions are omitted or briefly described below.

Referring to 4th , 31 and 32 can, in a display device 10 according to the present disclosure, a light emitting device ED of a light emitting device layer 103 on a wall 104 and a pixel electrode PE exposed at an emission region EA of each of a plurality of pixels SP, and may also be disposed in a first edge region MA1 of a first surface 100a a first substrate 100 be arranged. An end section (or a first extension section) EP1 of the light-emitting device ED can have a passivation layer 101d , which is arranged in the first edge area MA1, directly touch. An extreme end of the light emitting device ED may be arranged to be adjacent to a boundary portion between the first edge area MA1 and the second edge area MA2. For example, the end portion EP1 of the light emitting device ED may be within a range of 120 μm to 320 μm at a distance from an outer surface OS of the first substrate 100 be arranged.

The common electrode CE of the light emitting device layer 103 can directly touch the light emitting device ED and can surround the light emitting device ED. For example, the common electrode CE can be embodied in a conformal shape based on a surface shape of the light emitting device ED. An end section (or a second extension section) EP2 of the common electrode CE can be arranged in the first edge region MA1 in such a way that it forms the passivation layer 101d , which is arranged in the first edge region MA1, directly touches, and thus can surround the end portion EP1 of the light emitting device ED. An extreme end of the light emitting device ED can be directly surrounded by means of the common electrode CE and thus cannot be exposed on the outside. Accordingly, the end portion EP2 of the common electrode CE may be a boundary portion (or an interface) between the end portion EP1 of the light emitting device ED and the passivation layer 101d cover, which prevents or minimizes the ingress of water from the side.

A first encapsulation layer 106a an encapsulation layer 106 can be made such that it touches the common electrode CE directly and surrounds the common electrode CE. For example, the first encapsulation layer 106a based on a surface shape of the common electrode CE in a conformal shape. An end section (or a third extension section) EP3 of the first encapsulation layer 106a can be arranged in the first edge region MA1 in such a way that it forms the passivation layer 101d , which is arranged in the first edge region MA1, directly touches, and can thus surround the end portion EP2 of the common electrode CE. Accordingly, the end section EP3 of the first encapsulation layer 106a a boundary portion (or an interface) between the end portion EP2 of the common electrode CE and the passivation layer 101d cover, which prevents or minimizes the ingress of water from the side.

A second layer of encapsulation 106b the encapsulation layer 106 can be designed such that it has the first encapsulation layer 106a touched directly and the encapsulation layer 106a surrounds. An end portion EP4 of the second encapsulation layer 106b can be arranged in the first edge region MA1 in such a way that it forms the passivation layer 101d , which is arranged in the first edge region MA1, directly touches and can thus the end section EP3 of the first encapsulation layer 106a surround. Accordingly, the end section EP4 of the second encapsulation layer 106b a boundary portion (or an interface) between the end portion EP3 of the first encapsulation layer 106a and the passivation layer 101d cover, whereby a lateral penetration of water is additionally prevented or minimized.

The end section EP4 of the second encapsulation layer 106b according to one embodiment, dissimilar to the end section EP3 of the first encapsulation layer 106a , not be sharp-edged and can have a thickness which is relatively thicker than that of the first encapsulation layer 106a . A lower portion of an outer surface of the second encapsulation layer 106b that of the outer surface OS of the first substrate 100 opposite or to the outer surface OS of the first substrate 100 adjoins, can be designed such that it is in a thickness direction Z of the first substrate 100 vertical to the passivation layer 101d is. For example, the lower portion of the outer surface of the second encapsulation layer 106b that is the passivation layer 101d directly touches an outermost vertical sidewall OSV perpendicular to an upper surface of the passivation layer 101d exhibit.

The outermost vertical side wall OVS of the second encapsulation layer 106b may be located at a distance of 10 µm to 20 µm from the end portion EP1 of the light emitting device ED. That means an interval D3 between the outermost vertical side wall OVS of the second encapsulation layer 106b and the end portion EP1 of the light emitting device ED can be 10 µm to 20 µm.

The third encapsulation layer 106c the encapsulation layer 106 can be designed in such a way that it has the second encapsulation layer 106b touched directly and the second encapsulation layer 106b surrounds. An end portion EP5 of the third encapsulation layer 106c can be arranged in the first edge region MA1 in such a way that it forms the passivation layer 101d , which is arranged in the first edge area MA1, directly touches, and can thus the end section EP4 of the second encapsulation layer 106b surround. Accordingly, the end section EP5 of the third encapsulation layer 106c a boundary portion (or an interface) between the end portion EP4 of the second encapsulation layer 106b and the passivation layer 101d cover, whereby a lateral penetration of water is additionally prevented or minimized.

The encapsulation layer 106 can by means of a protective layer 107b a wavelength conversion layer 107 be surrounded.

The protective layer 107b can be designed in such a way that it contains the third encapsulation layer 106c touched directly and the third encapsulation layer 106c surrounds. For example, an edge portion of the protective layer 107b be arranged in the second edge region MA2 adjacent to the first edge region MA1 in such a way that it has the passivation layer 101d , which is arranged in the second edge region MA1, directly touches and can thus the end section EP5 of the third encapsulation layer 106c surround.

In the display device 10 According to the present embodiment, an end portion EP1 of the light emitting device ED can be formed by means of a triple sealing structure formed on the common electrode CE, the first encapsulation layer 106a and the second encapsulation layer 106b is based, surrounded or sealed, and thus the reduction in reliability of the light emitting device ED caused by lateral intrusion of water can be prevented, and a width of the first edge portion MA1 can be substantially reduced, thereby reducing a second interval D2 between a central portion of an outermost pixel region PAo and each of outer surfaces OS of the first substrate may be made to be half or less of a first interval D1 can be between adjacent pixel areas PA. The first interval can be D1 may be referred to as a pixel pitch or a reference pixel pitch.

33A until 33E are diagrams showing a method of manufacturing a light emitting device, a common electrode, and an encapsulation layer, each shown in FIG 31 are shown, represent, and 34 is a microscope photograph of the 33B . In 34 For example, a white layer WL may be a coating layer which is applied experimentally to identify a cross-sectional structure of a mask structure and a deposition material and thus does not correspond to an element of the display device according to the present disclosure.

Referring to 33A until 33E and 34 In the following, a method for manufacturing a light emitting device, a common electrode, and an encapsulation layer according to the present disclosure will be described.

As in 33A and 34 shown, a first mask structure MP1 on a first surface 100a a first substrate 100 may be formed (or arranged), and a second mask structure MP2, which has a gutter structure with respect to the first mask structure MP1, may be formed (or arranged) on the first mask structure MP1. For example, the first mask structure MP1 and the second mask structure MP2 can be implemented by means of a process of sequentially forming (or applying) a first mask structure material and a second mask structure material on the first surface 100a of the first substrate 100 , a process of performing an exposure of the second mask structure material, a process of sequentially patterning (or removing) the second mask pattern material and the first mask pattern material, and a process of burning in a patterned first mask pattern material and a patterned second mask pattern material.

The second mask pattern material according to an embodiment may comprise a photosensitive resin. For example, the second mask structure material can have a positive photo resin or a negative photo resin.

The first mask structure material and the second mask structure material according to an embodiment can comprise a material that is not deformed by means of the exposure process. For example, the first mask structure material can comprise polydimethylglutarimide (PMGI) or polymethyl methacrylate (PMMA). The first mask pattern material can be referred to as an etch conductive layer, a sacrificial layer, a peel-off resistive layer, or a non-photosensitive layer.

A development rate of the first mask structure material on a developer can be higher than a development rate of the second mask structure material on the developer. For example, the second mask structure material can have an exposure portion that is exposed by means of the exposure process and a non-exposure portion, and the second mesh structure can be embodied as the non-exposure portion of the second mask structure material. In this case, a patterning portion of the first mask pattern material that the The exposure portion of the second mask structure material is overlapped by the developer because the exposure portion of the second mask structure material is removed by the developer, and a patterning portion of the first mask structure material that is exposed by the developer can be removed faster than the exposure portion of the second mask structure material. Accordingly, the first mask structure material can have a developer speed which is comparatively higher than that of the second mask structure material, and thus the first mask structure material can have an undercut structure with respect to the second mask structure material.

A lateral surface of the first mask structure MP1 according to one embodiment can have an undercut area (or a beveled structure) UCA with respect to the second mesh structure MP2. For example, a boundary section between the first mask structure MP1 and the second mask structure MP2 or an upper lateral surface of the first mask structure MP1 can be undercut with respect to the second mask structure MP2. The second mask structure MP2 can protrude due to the undercut area UCA of the first mask structure MP1 in relation to the lateral surface of the first mask structure MP1 and can thus cover the lateral surface of the first mask structure MP1. Accordingly, the second mask structure MP2 can have a gutter structure in relation to the first mask structure MP1.

The first mask structure MP1 can include everything from the second edge region MA2, which is on the first surface 100a of the first substrate 100 is defined, cover and can cover a portion of the first edge area MA1 adjacent to the second edge area MA2. For example, an inner surface of the first mask structure MP1 can be arranged in the first edge region MA1 adjacent to a boundary section between the first edge region MA1 and the second edge region MA2. An inner surface of the second mask structure MP2 can be arranged in the first edge region MA1 in such a way that it is arranged at a distance from the inner surface of the first mask structure MP1. This means that the inner surface of the first mask structure MP1 can be arranged between the inner surface of the second mask structure MP2 and the boundary section between the first edge region MA1 and the second edge region MA2.

As in 33B and 34 illustrated, the light emitting device ED and the common electrode CE of the light emitting device layer 103 and the first encapsulation layer 106a the encapsulation layer 106 one after the other on the first edge area MA1, the second mask structure MP2 and the first surface 100a of the first substrate 100 formed (or deposited).

The light emitting device ED can be attached to a wall 104 and a pixel electrode PE exposed at an emission region EA of each of a plurality of pixels SP, and may also be disposed on the second mask pattern MP2 and in the first edge region MA1 on the first surface 100a of the first substrate 100 to be ordered. In this case, an end section (or a first extension section) EP1 of the light-emitting device ED can penetrate into a partial area of the undercut area UCA of the first mask structure MP1 and can form a passivation layer 101d , which is exposed at the undercut area UCA of the first mask structure MP1, directly touch.

In a deposition process performed on the light emitting device ED, a position of an end portion EP1 of the light emitting device ED should be based on a shadow area of the light emitting device ED based on a distance between a deposition mask of the light emitting device ED and the first substrate 100 inevitably occurs. However, the shadow area of the light emitting device ED according to the present embodiment may overlap the second mask pattern MP2, and can be controlled or adjusted based on a protruding length of the second mask pattern MP2. Accordingly, in the display device according to the present embodiment, since the shadow area of the light emitting device ED is not reflected in the deposition process performed on the light emitting device ED, a width of the first edge area MA1 based on the shadow area of the light emitting device ED can be significant be reduced.

The common electrode CE can be formed so as to cover the light emitting device ED. In particular, an end section (or a second extension section) EP2 of the common electrode CE can penetrate into the undercut area UCA of the first mask structure MP1 and can form the passivation layer 101d , which is exposed at the undercut area UCA of the first mask structure MP1, directly touch, and thus can surround the end portion EP1 of the light emitting device ED.

The first encapsulation layer 106a can be formed so as to cover the common electrode CE. In particular, a End section EP3 of the first encapsulation layer 106a penetrate into the undercut area UCA of the first mask structure MP1 and the passivation layer can 101d , which is exposed at the undercut area UCA of the first mask structure MP1, directly touch and can thus surround the end portion EP2 of the common electrode CE.

As in 33C shown, a second encapsulation layer 106b who have favourited the first encapsulation layer 106a surrounds, on the first surface 100a of the first substrate 100 formed (or applied).

An end portion EP4 of the second encapsulation layer 106b can penetrate into the undercut area UCA of the first mask structure MP1 and can the passivation layer 101d , which is arranged in the first edge region MA1, directly touch and can thus the end section EP3 of the first encapsulation layer 106a surround. The end section EP4 of the second encapsulation layer can likewise 106b an inner surface of the first mask structure MP1 directly and can thus contact an outermost vertical side wall OVS perpendicular to an upper surface of the passivation layer 101d exhibit.

The outermost vertical side wall OVS of the second encapsulation layer 106b may be distant from the end portion EP1 of the light emitting device ED by a range of 10 µm to 20 µm. That means an interval D3 between the outermost vertical side wall OVS of the second encapsulation layer 106b and the end portion EP1 of the light emitting device ED can be 10 µm to 20 µm.

As in 33D shown, all of the first mask structure MP1 and the second mask structure MP2, which are on the first surface 100a of the first substrate 100 are arranged, removed by a peeling process.

Optionally, in order to decrease a time period for performing the peeling process on the first mask structure MP1 and the second mask structure MP2, a heated solvent can be used, and further, an ultrasonic cleaning process can be applied thereto.

As in 33E shown, a third encapsulation layer 106c , the second encapsulation layer 106b the encapsulation layer 106 surrounds, on the first surface 100a of the first substrate 100 formed (or applied).

The third encapsulation layer 106c may be formed to have a top surface, a side surface, and an end portion EP4 of the second encapsulation layer 106b surrounds. The third encapsulation layer can likewise 106c that are on a pad area 110 on the first surface 100a of the first substrate 100 is formed, can be removed by means of a structuring process or a pad opening process.

35 FIG. 13 is a diagram showing a back surface of a second substrate shown in FIG 4th and illustrates an embodiment in which a panel support member is further provided on the second substrate of the display device shown in FIG 1 until 32 is shown, is provided. When describing the 35 become elements that are equal to the elements of the 1 until 32 or correspond to them are denoted by like reference numerals, and their repeated descriptions are omitted or briefly described below.

Referring to 4th and 35 can be a display device 10 in accordance with an embodiment of the present disclosure furthermore a panel support element 600 that is on a back surface 200b a second substrate 200 is arranged have.

The panel support 600 may be used to support a back surface of a display panel having a first substrate 100 and a second substrate 200 that by means of a coupling element 300 are bonded (or coupled) together. The panel support 600 can be referred to as a back cover, a back cover, or a back panel.

The panel support 600 According to one embodiment, a support plate 610 and a plurality of fasteners 630 exhibit.

The support plate 610 can be used to support a rear surface of the display panel with the rear surface 200b of the second substrate 200 be connected. The support plate 610 may be arranged to have a portion other than a second pad area 210 and a third pad area 230 , the back surface 200b of the second substrate 100 covered and can be a printed circuit board (PCB) 550 a drive circuit unit 500 prop up. For example, the support plate 610 by means of a panel coupling element, such as double-sided tape, to the back surface 200b of the second substrate 200 be coupled.

The support plate 610 may comprise a metal material. For example, the support plate 610 but not limited to a material of Al, an Al alloy, a Mg alloy, an Fe-Ni alloy and stainless steel or an alloy thereof, or a joint structure.

‟ oder eine „

‟-Form aufweisen. In diesem Falle kann der dritte Padbereich 230 des zweiten Substrats 200 in einer Rückseitenrichtung des zweiten Substrats 200 mittels des konkaven Abschnitt 611 der Stützplatte 610 freigelegt sein. Ebenso kann der andere Kantenabschnitt einer flexiblen Schaltkreisschicht 510, die auf dem dritten Padbereich 230 des zweiten Substrats 200 angebracht ist, einen gestuften Abschnitt zwischen dem konkaven Abschnitt 611 der Stützplatte 610 und dem zweiten Substrat 200 überdecken und kann mit der PCB 550, die mittels der Stützplatte 610 abgestützt ist, elektrisch verbunden sein.The support plate 610 according to one embodiment, a concave portion 611 having a portion removed from one side thereof to expose the third pad area 230 exhibit. For example, when viewed from above to below, the support plate 610 one "

" or one "

‟Shape. In this case, the third pad area 230 of the second substrate 200 in a back direction of the second substrate 200 by means of the concave section 611 the support plate 610 be exposed. Likewise, the other edge portion can be a flexible circuit layer 510 that is on the third pad area 230 of the second substrate 200 is attached, a stepped portion between the concave portion 611 the support plate 610 and the second substrate 200 overlap and can with the PCB 550 that by means of the support plate 610 is supported, be electrically connected.

‟-Form aufweisen. In diesem Falle kann der dritte Padbereich 230 des zweiten Substrats 200 in der Rückseitenrichtung des zweiten Substrats mittels des Öffnungsloches der Stützplatte 610 freigelegt sein. Ebenso kann der andere Kantenabschnitt einer flexiblen Schaltkreisschicht 510, die an dem dritten Padbereich 230 des zweiten Substrats 200 befestigt ist, durch das Öffnungsloch der Stützplatte 610 hindurchführen und kann elektrisch mit der PCB 550, die mittels der Stützplatte 610 abgestützt ist, verbunden sein.According to a further embodiment, the support plate 610 an opening hole for exposing the third pad area 230 exhibit. For example, the support plate 610 a tetragonal opening hole having a tetragonal shape having a portion apart from the second pad area 210 , the back surface 200b of the second substrate 200 covers, have and has a size which is comparatively larger than that of the third pad area 230 . For example, when viewed from above to below, the support plate 610 one "

‟Shape. In this case, the third pad area 230 of the second substrate 200 in the rear side direction of the second substrate by means of the opening hole of the support plate 610 be exposed. Likewise, the other edge portion can be a flexible circuit layer 510 on the third pad area 230 of the second substrate 200 is attached through the opening hole of the support plate 610 pass through and can be electrically connected to the PCB 550 that by means of the support plate 610 is supported, be connected.

The plurality of fasteners 630 can on a back surface of the support plate 610 be arranged. For example, the plurality of fastening elements 630 be arranged to face each of edge portions of the support plate 610 touch and can move a certain length from the back surface of the support plate 610 protrude.

Each of the plurality of fasteners 630 According to one embodiment, a fastening groove 631 which is made to be concave from a front surface thereof.

Each of the plurality of fasteners 630 can by means of a fixing element such as a screw or a bolt on the back surface of the support plate 610 be fixed. For example, the fixing element can pass through the fastening groove 631 of the fastener 630 pass through and can on the back surface of the support plate 610 be attached and can thus be a rear side portion of the fastening element 630 on the back surface of the support plate 610 fix.

Each of the plurality of fasteners 630 According to one embodiment, it can comprise a material that can be magnetized by means of a magnet. According to a further embodiment, each of the plurality of fastening elements 630 with a magnetic block in between with the back surface of the support plate 610 be coupled. For example, the magnetic block can be a neodymium magnet.

The plurality of fasteners 630 may each be attached to a plurality of attachment pins arranged in a rear frame unit that supports the display device. For example, the fastening element 630 be coupled to the mounting pin disposed in the rear frame unit based on a magnetic force. Therefore, the display device 10 may be mounted on the rear frame assembly in accordance with the present disclosure. A plurality of display devices can also be used 10 mounted on the rear frame unit can be continuously tiled in at least one of a first direction X and a second direction Y, and thus a multi-display device or an infinitely expandable display device can be implemented. Here, the back frame unit can be referred to as a back structure, a display support unit, a tile unit, a tile structure, a box unit, a module box unit, or a box structure. Likewise, the multi-display device can be referred to as a multi-panel display device, a multi-screen display device, or a tile display device.

In addition, the display device 10 further comprise a circuit cover in accordance with an embodiment of the present disclosure. The circuit cover can be connected to a rear surface of the panel support member 600 be coupled in such a way that they are the control circuit unit 500 attached to the back surface of the panel support member 600 is exposed, covered and can thus the control circuit unit 500 protect against external influences and can protect the control circuit unit 500 Protect from static electricity. The circuit cover according to an embodiment may comprise a metal material that has a shape for covering the circuit unit 500 attached to the back surface of the panel support member 600 is exposed. For example, the circuit cover can be referred to as a cover shield.

36 FIG. 13 is a diagram illustrating a multi-display device according to an embodiment of the present disclosure; 37 FIG. 13 is a diagram showing a tiling process of a display device shown in FIG 36 is represented, represents, and 38 FIG. 13 is a cross-sectional view taken along a line V-V 'shown in FIG 36 is shown.

Referring to 36 until 38 According to an embodiment of the present disclosure, the multi-display device may have a plurality of display modules 10-1 until 10-4 and a plurality of rear frame units 30-1 until 30-4 exhibit.

The majority of display modules 10-1 until 10-4 may be arranged in an NxM form (where N is a positive integer of 2 or more and M is a positive integer of 2 or more) and thus can each display an individual image or can display an image divided. Each of the plurality of display modules 10-1 until 10-4 can the display device 10 in accordance with the present disclosure contained in 1 until 35 and thus repeated description thereof will be omitted.

The plurality of back frame units 30-1 until 30-4 can each with the plurality of display modules 10-1 until 10-4 be coupled and can each have a corresponding display module of the plurality of display modules 10-1 until 10-4 prop up. The plurality of back frame units 30-1 until 30-4 may be tiled in a first direction X and a second direction Y on the basis of a lateral coupling manner.

Each of the plurality of back frame units 30-1 until 30-4 according to one embodiment, a back frame 31 , a plurality of mounting pins 33 , a plurality of first connecting devices 35 and a plurality of second connection devices 37 exhibit.

The back frame 31 can on a rear surface of each of the display modules 10-1 until 10-4 be arranged. The back frame 31 According to one embodiment, it may have a plate shape that is a size corresponding to the display modules 10-1 until 10-4 having. Likewise, the back frame 31 a through hole 31a that enables a cable connecting a drive system (or main control panel) of a multi-display device to a PCB of each of the display modules 10-1 until 10-4 connects, can lead through. The through hole 31a can be a circular shape or a polygonal shape defined by a central portion of the back frame 31 passes through, have.

Each of the plurality of mounting pins 33 can on a front surface of the back frame 31 be arranged. For example, the plurality of fastening pins 31 each adjacent to corner sections of the rear frame 31 and can be arranged from the front surface of the rear frame 31 protrude a certain length towards the front. That means that each of the plurality of mounting pins 33 on the front surface of the back frame 31 can be fixed to each of the plurality of fasteners 630 overlaps that in the panel support member 600 that is in the display device 10 from each of the display modules 10-1 until 10-4 is included, are arranged.

Each of the plurality of mounting pins 33 can by means of a fixing element such as a screw or a bolt on the front surface of the rear frame 31 be fixed. For example, the fixing element can be through the rear frame 31 pass through and can on a rear side section of the fastening pin 33 be attached and can thus the rear portion of the fastening pin 33 on the front surface of the back frame 31 fix.

A portion of each of the plurality of mounting pins 33 may be of a size that allows each mounting pin 33 into the fastening groove 631 a corresponding fastening element 630 can be executed. For example, the one portion of each of the plurality of attachment pins can be 33 have a first diameter that allows each mounting pin 33 into the fastening groove 631 a corresponding fastening element 630 can be introduced. Likewise, the other portion of each of the plurality of attachment pins can be 33 have a second diameter that is larger than the first diameter by the front portion of the fastener 630 to contact.

Each of the plurality of mounting pins 33 according to one embodiment may comprise a metal material. Therefore, any of the plurality of attachment pins 33 by means of a magnetic force of the corresponding fastening element 630 into the fastening groove of a corresponding fastening element 630 the plurality of fasteners 630 are introduced and can thus be attached to the corresponding fastening element 630 be attached.

Optionally, any of the plurality of attachment pins 33 according to one embodiment, with a magnetic block therebetween, with the front surface of the rear frame 31 be coupled. The magnetic block can be a neodymium magnet. In this case, the magnetic block can be any of the plurality of attachment pins 33 be designed such that it is based on a magnetic force of the fastening element 630 has an attraction.

The plurality of first connection devices 35 may be at certain intervals at first rear edge portions and second rear edge portions, which are parallel to the first direction (or a horizontal direction or a widthwise orientation) X, of the rear surface of the rear frame 31 be arranged. Each of the plurality of first connection devices 35 can be designed such that it is connected to a first connecting device of a rear frame, which is arranged at an upper portion, and that, with respect to the second direction (or a vertical direction or a longitudinal direction) Y with a first connecting device of a rear frame , which is arranged at a lower portion, is connected.

Each of the plurality of first connection devices 35 according to one embodiment, a first connecting body 35a and a first connector 35b exhibit.

The first connecting body 35a may be on each of a first rear edge portion and a second rear edge portion of the rear frame 31 be arranged.

The first connector 35b can on an outer surface of the first connection body 35a exposed in the second direction Y can be arranged. The first connector 35b can be a protrusion pin or a pin hole. According to one embodiment, a first connecting element 35b a first connection device 35 attached to a first rear edge portion of the rear frame 31 is arranged to be a pin hole, and a first connecting element 35b a first connection device 35 attached to a second rear edge portion of the rear frame 31 is arranged, can be a protrusion spin.

The first connector 35b having a protruding pin can be moved in the second direction Y to move the back frame in the second direction Y based on a rotation thereof based on a handle of a worker. Therefore, the rotation of the first connecting element 35b , which has the protruding pin, for aligning an adjacent back frame 31 in the second direction Y can be used.

Each of the plurality of first connection devices 35 according to one embodiment can furthermore have a first fine adjustment element, which is located in the first connecting body 35a is arranged, the first connecting element having a pin hole 35b having.

The first fine adjustment element can be in the first connecting body 35a be arranged and can be made such that it is inserted into the pin hole protruding pin in the first direction X or a third direction (or a forward and backward direction or a thickness direction) Z parallel to a thickness direction of the display device 10 emotional. The first fine adjustment element according to an embodiment may have a first fine adjustment bolt and a second fine adjustment bolt which are in the first connection body 35a are arranged, have. For example, the first fine adjustment bolt and the second fine adjustment bolt can each be a bolt without a head.

The first fine adjustment bolt can be on the other surface of the first connecting body 35a , which is opposite to the first direction X, and can move the protruding pin inserted into the pin hole in the first direction X. Rotation of the first trim bolt can be used to align an adjacent back frame 31 can be used in the first direction X.

The second fine adjustment bolt can be on a rear surface of the first connecting body 35a be arranged and can move the protruding pin introduced into the pin hole in the third direction Z. Rotation of the second trim bolt can be used to align an adjacent back frame 31 in the third direction Z can be used.

The plurality of second connection devices 37 can be spaced at a third rear edge portion and a fourth rear edge portion, which are arranged parallel to the second direction Y, on the rear surface of the rear frame 31 be arranged. Each of the plurality of second connection devices 37 can be designed in such a way that it is connected to a second connecting device of a rear side frame which is arranged on a left section and that, with respect to the first direction X, is connected to a second connecting device of a rear side frame which is arranged on a right section is connected.

Each of the plurality of second connection devices 37 According to one embodiment, a second connecting body 37a and a second connector 37b exhibit.

The second connecting body 37a may be at each of a third rear edge portion and a fourth rear edge portion of the rear frame 31 be arranged.

The second connecting element 37b can on an outer surface of the second connection body 37a exposed in the first direction X can be arranged. The second connecting element 37b can be a protrusion pin or a pin hole. According to one embodiment, a second connecting element 37b a second connecting device 37 attached to a third rear edge portion of the rear frame 31 is arranged to be a pin hole, and a second connecting element 37b a second connecting device 37 attached to a fourth rear edge portion of the rear frame 31 is arranged, can be a protrusion spin.

The second connecting element 37b , which has a protruding pin, can be used to move the rear frame 31 can be moved in the first direction X based on a rotation thereof based on a manipulation of the worker in the first direction X. Therefore, the rotation of the second connecting element 37b , which has the protruding pin, can be used to create an adjacent back frame 31 align in the first direction X.

Each of the plurality of second connection devices 37 according to one embodiment can furthermore have a second fine adjustment element, which is located in the second connecting body 37a , the second connecting element having a pin hole 37b has, is arranged.

The second fine adjustment element can be in the second connecting body 37a be arranged and can be implemented to move the protruding pin introduced into the pin hole in the second direction Y or the third direction Z. The second fine adjustment element according to an embodiment may have a third fine adjustment bolt and a fourth fine adjustment bolt incorporated in the second connecting body 37a are arranged. For example, the third fine adjustment bolt and the fourth fine adjustment bolt can each be a headless bolt.

The third fine adjustment bolt can be on the other surface of the second connecting body 37a opposite to the second direction Y, and can move the protruding pin inserted into the pin hole in the second direction Y. One rotation of the third fine adjustment bolt can be used to adjust an adjacent rear frame 31 align in the second direction Y.

The fourth fine adjustment bolt can be on a rear surface of the second connecting body 37a be arranged and can move the protruding pin introduced into the pin hole in the third direction Z. One rotation of the fourth fine adjustment bolt can be used to adjust an adjacent rear frame 31 align in the third Z direction.

Each of the plurality of back frame units 30-1 to 30-4 may support a corresponding one of the plurality of display modules 10-1 to 10-4 and may be tiled in a 2x2 shape in the first direction X and the second direction Y, and the plurality of display modules 10-1 to 10-4 can implement a large screen display device based on the tiling.

Each of the plurality of display modules 10-1 to 10-4 may not have a border area (or a non-display area) surrounding all of a display area AA, and may have an air border structure in which the display area AA is surrounded by air, exhibit. That is, in each of the plurality of display modules 10-1 to 10-4, all of a first surface of a first substrate 100 can be designed as the display area AA. Therefore, an image displayed by means of a multi-display device in which the plurality of display modules 10-1 to 10-4 are tiled in a 2 × 2 shape can be continuously displayed without any feeling of interruption (or discontinuity ) at a boundary portion between the plurality of display modules 10-1 to 10-4, and thus the inclusion of a viewer who is informed by means of the Multi-display device viewed image displayed, be amplified.

According to the present embodiment, in each of the plurality of display modules 10-1 to 10-4, a second interval D2 may be between a central portion CP of an outermost pixel Po and an outermost outer surface VL of the first substrate 100 be designed such that it is half or less of a first interval D1 between adjacent pixels. Accordingly, in two adjacent display modules connected (or touching each other) on side surfaces thereof in the first direction X and the second direction Y on the basis of a lateral coupling manner, an interval “D2 + D2” between adjacent outermost pixels Po may be equal to be or less than the first interval D1 between two adjacent pixels.

Referring to 38 may, in a first display module 10-1 and a third display module 10-3 connected to (or contact each other) on side surfaces thereof in the second direction Y, the interval “D2 + D2” between a central portion CP of an outermost pixel Po of the first display module 10-1 and a central portion CP of an outermost pixel Po of the third display module 10-3 can be equal to or smaller than the first interval D1 between two adjacent pixels included in each of the first display module 10-1 and the third Display module 10-3 are arranged.

Therefore, the interval “D2 + D2” between central portions CP of outermost pixels Po of two adjacent display modules connected (or contacting) with each other on side surfaces thereof in the first X and second Y directions may be equal to or smaller be as the first interval D1 between two adjacent pixels arranged in each of the display modules 10-1 to 10-4, and thus there cannot be a seam or boundary portion between two adjacent display modules, whereby between the display modules 10-1 to 10- 4 cannot be a dark area caused by a boundary portion.

As a result, in a case where the display area AA of each of the plurality of display modules 10-1 to 10-4 is a screen and displays an image, a multi-display device according to the present disclosure can display an image that cannot is interrupted and is continuous at a boundary portion between the plurality of display modules 10-1 to 10-4.

In 36 and 37 It is shown that the plurality of display modules 10-1 to 10-4 are tiled in a 2x2 shape, but the present disclosure is not limited thereto, and the plurality of display modules 10-1 to 10-4 may be tiled in a xx1 shape , a 1 xy shape or an xxy shape. Here, x can be a natural number that is 2 or more, and Y can be a natural number that is 2 or more.

39A and 39B 14 are diagrams showing images respectively displayed by a multi-display device according to a comparative example and a multi-display device according to the present disclosure. One in 39B The dotted line shown represents a boundary section between display modules and is irrelevant for an image that is displayed by means of a multi-display device.

Referring to 39A the multi-display device according to the comparative example can be implemented by tiling a plurality of display modules 1-1 to 1-4 having a border area (or a non-display area) BA completely surrounding a display area AA, and thus it can be seen that an image displayed by the multi-display device according to the comparative example is interrupted and at a boundary portion between the plurality of display modules 1-1 to 1-4 due to the border area BA of each of the plurality of display modules 1-1 to 1 -4 is displayed. Therefore, in the multi-display device according to the comparative example, due to the border area BA of each of the plurality of display modules 1-1 to 1-4 in a boundary portion between the plurality of display modules 1-1 to 1-4, an impression of interruption ( or discontinuity) of an image, and due to this, the involvement of a viewer viewing an image may decrease.

Referring to 39B The multi-display device according to the present disclosure can be configured by tiling a plurality of display modules 10-1 until 10-4 having an air edging structure in an entire first surface of a first substrate 100 a display area AA and surrounded by air can be implemented, and thus it can be seen that an image displayed by the display device according to the present disclosure is at a boundary portion between the plurality of display modules 10-1 until 10-4 is continuous with no impression of interruption (or discontinuity) in the displayed image. Therefore, the multi-display device according to the present disclosure can display an image displayed at a boundary portion between the plurality of display modules 10-1 until 10-4 is continuous without any impression of interruption (or discontinuity) in the image.

As a result, even in a case where the plurality of display modules 10-1 until 10-4 connected to each other in a lattice shape on side surfaces thereof, the multi-display device according to the present disclosure display an image on the boundary portion between the plurality of display modules 10-1 until 10-4 is continuous with no impression of interruption (or discontinuity) in the image, thereby enhancing the involvement of a viewer viewing an image.

A display device and a multi-display device including the same according to the present disclosure will be described below.

A display device according to some embodiments of the present disclosure may include a first substrate including a plurality of pixel areas provided in a display area, a second substrate coupled to the first substrate, and a wiring portion attached to an outer surface of the first substrate and an outer surface of the second substrate, the first substrate having a dam structure disposed along an edge of the display area, a light emitting device layer having a common electrode, and a light emitting device disposed on the dam structure and in of the plurality of pixel regions, and may have a laser patterning portion disposed close to the dam structure, and each of the light emitting device and the common electrode can be isolated by the laser patterning portion.

According to some embodiments of the present disclosure, the laser structuring portion may have an inner structuring portion disposed inward of the dam structure.

According to some embodiments of the present disclosure, the first substrate may further include an encapsulation layer disposed on the common electrode and the laser patterning portion, and the encapsulation layer may have a laser isolation surface of each of the light emitting device and the common electrode on the surrounding inner structuring section.

According to some embodiments of the present disclosure, the laser structuring portion may have an inner structuring portion disposed inward from the dam structure and an outer structuring portion disposed outward from the dam structure.

According to some embodiments of the present disclosure, the first substrate may further include an encapsulation layer disposed on the common electrode and the laser patterning portion, and the encapsulation layer may have a laser isolation surface of each of the light emitting device and the common electrode on each surrounded by the inner structuring portion and the outer structuring portion.

According to some embodiments of the present disclosure, the first substrate may further include a passivation layer disposed on the display area and an encapsulation layer disposed on the common electrode and the laser patterning portion, the dam structure may have a top surface of the passivation layer directly touch, and the encapsulation layer can directly contact the top surface of the passivation layer at the laser patterning portion.

According to some embodiments of the present disclosure, the encapsulation layer may, at the laser patterning portion, a laser isolation surface of each of the light emitting device and the common electrode, a boundary portion between the light emitting device and the common electrode, and a boundary portion between the passivation layer and the light emitting Surround device.

According to some embodiments of the present disclosure, the first substrate may further include a dummy dam structure surrounding the dam structure.

According to some embodiments of the present disclosure, the dummy dam structure may have a first island structure surrounding the dam structure and comprising the same material as a material of the light emitting device, and a second island structure surrounding the first island structure and the same material as a material of the common Having electrode.

According to some embodiments of the present disclosure, the first substrate may further include a passivation layer disposed on the display area and an encapsulation layer including a first encapsulation layer disposed on the common electrode and the laser structuring portion, the dam structure directly contacts an upper surface of the passivation layer, and the The first encapsulation layer can directly contact the upper surface of the passivation layer at the laser structuring section.

According to some embodiments of the present disclosure, the encapsulation layer can furthermore have a second encapsulation layer, which is arranged on the first encapsulation layer in a region that is surrounded by the dam structure, and a third encapsulation layer, which is arranged on the second encapsulation layer.

According to some embodiments of the present disclosure, the third encapsulation layer may directly contact the top surface of the passivation layer at an outer periphery of the dam structure.

A display device according to some embodiments of the present disclosure may include a first substrate comprising a plurality of pixel areas provided in a display area, a passivation layer disposed on the display area, a dam structure disposed on the passivation layer along an edge of the display area , a light emitting device layer comprising a common electrode and a light emitting device disposed on the dam structure and in the plurality of pixel areas, at least one cut line disposed close to the dam structure, and a second substrate having a Back surface of the first substrate is connected, wherein the at least one cut line may be formed by patterning the light emitting device and the common electrode to be concave.

According to some embodiments of the present disclosure, the at least one cut line may isolate each of the light emitting device and the common electrode at a periphery of the dam structure.

According to some embodiments of the present disclosure, the at least one cut line may expose a top surface of the passivation layer.

According to some embodiments of the present disclosure, the first substrate may further include an encapsulation layer disposed on the common electrode and the at least one incision line, and the encapsulation layer may cover the at least one incision line and directly contact an upper surface of the passivation layer.

According to some embodiments of the present disclosure, the first substrate may further include an encapsulation layer disposed on the common electrode and the at least one cut line, and the encapsulation layer may have a laser isolation surface of each of the light emitting device and the common electrode on the at least surround an incision line.

According to some embodiments of the present disclosure, the encapsulation layer may, at the at least one cut line, the laser isolation surface of each of the light emitting device and the common electrode, a boundary portion between the light emitting device and the common electrode, and a boundary portion between the passivation layer and the light emitting Surround device.

According to some embodiments of the present disclosure, the first substrate may further include a dummy dam structure surrounding the dam structure.

According to some embodiments of the present disclosure, the dummy dam structure may have a first island structure surrounding the dam structure and comprising the same material as a material of the light emitting device, and a second island structure surrounding the first island structure and comprising the same material as a material of the common electrode.

In accordance with some embodiments of the present disclosure, the dam structure may be arranged in outermost pixel areas from the plurality of pixel areas.

A multi-display device in accordance with some embodiments of the present disclosure may include a plurality of display modules arranged in at least one direction of a first direction and a second direction transverse to the first direction, each of the plurality of display modules having a first substrate that is a A plurality of pixel areas provided in a display area, a second substrate coupled to the first substrate, and a wiring portion disposed on an outer surface of the first substrate and an outer surface of the second substrate, wherein the first substrate comprises a dam structure disposed along an edge of the display area, a light emitting device layer having a common electrode and a light emitting device disposed on the dam structure and in the plurality of pixel areas, and a laser Patterning portion disposed close to the dam structure, and each of the light emitting device and the common electrode can be isolated by means of the laser patterning portion.

A multi-display device in accordance with some embodiments of the present disclosure may include a plurality of display modules arranged in at least a first direction and a second direction transverse to the first direction, each of the plurality of display modules having a first substrate comprising a plurality of Pixel areas provided in a display area, a passivation layer disposed on the display area, a dam structure disposed on the passivation layer along an edge of the display area, a light emitting device layer having a common electrode and a light emitting device , which is arranged on the dam structure and in the plurality of pixel areas, at least one cut line which is arranged close to the dam structure, and a second substrate which is connected to a rear surface of the first substrate, wherein the min At least one cut line may be shaped to be concave by patterning the light emitting device and the common electrode.

According to some embodiments of the present disclosure, the dam structure may be arranged in an outermost pixel area of the plurality of pixel areas and, in two adjacent display modules each having side surfaces that touch each other, out of the plurality of display modules, a second interval between central portions of adjacent ones outermost pixel areas in different display modules may be equal to or less than a first interval between central portions of two adjacent pixel areas in a same display module.

According to some embodiments of the present disclosure, each of the plurality of display modules may further include a panel support member, and the panel support member may include a support plate bonded to a back surface of the second substrate and a plurality of fasteners bonded to a back surface the support plate are arranged, wherein the plurality of fastening elements are magnetized by means of a magnet.

The display device according to the present disclosure can be applied to any electronic device that has a display panel. For example, the display device according to the present disclosure can be applied to mobile devices, videophones, smartwatches, watch-phones, portable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic organizers, e-books, portable multimedia players, personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, netbook computers, workstation computers. Navigation devices, automobile navigation devices, automobile display devices, TVs, wallpaper display devices, guidance system devices, gaming machines, notebook computers, monitors, cameras, camcorders, home applications, etc. can be applied.

The feature, structure, and effect of the present disclosure as described above are included in at least one embodiment of the present disclosure, but are not limited to only one embodiment. Furthermore, the feature, structure, and effect described in at least one embodiment of the present disclosure can be carried out by a person skilled in the art by combining or modifying other embodiments. Therefore, content associated with the combination and modification should be construed to fall within the scope of the present disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the scope of the disclosure. Accordingly, it is intended that the present disclosure cover the modifications and variations of this disclosure provided they come within the scope of the appended claims.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• KR 1020190180116 [0001]
• KR 1020130060476 [0139]
• KR 1020130030598 [0139]
• KR 1020160093179 [0144]
• KR 1020170054654 [0144]
• KR 1020180002099 [0144]

Claims (24)

A display device (10) comprising: a first substrate (100) having a plurality of pixel areas (PA) provided in a display area (AA); a second substrate (200) coupled to the first substrate (100); and a wiring section (400) arranged on an outer surface (OS) of the first substrate (100) and an outer surface (OS) of the second substrate (200), wherein the first substrate (100) comprises: a dam structure (105) arranged along an edge of the display area (AA); a light emitting device layer (103) comprising a common electrode (CE) and a light emitting device (ED) disposed on the dam structure (105) and in the plurality of pixel regions (PA); and a laser structuring portion (LPP) disposed close to the dam structure (105), and wherein each of the light emitting device (ED) and the common electrode (CE) are isolated by means of the laser patterning portion (LPP). The display device (10) according to Claim 1 wherein the laser structuring portion (LPP) has an inner structuring portion (IPP) disposed inward of the dam structure (105). The display device (10) according to Claim 2 wherein: the first substrate (100) further comprises an encapsulation layer (106) disposed on the common electrode (CE) and the laser patterning portion (LPP), and the encapsulation layer (106) has a laser isolation surface of each of of the light emitting device (ED) and the common electrode (CE) on the inner patterning portion (IPP). The display device (10) according to Claim 1 wherein the laser structuring portion (LPP) comprises: an inner structuring portion (IPP) disposed inward of the dam structure (105); and an outer structuring portion (OPP) disposed outward from the dam structure (105). The display device (10) according to Claim 4 wherein: the first substrate (100) further comprises an encapsulation layer (106) disposed on the common electrode (CE) and the laser patterning portion (LPP), and the encapsulation layer (106) has a laser isolation surface of each of of the light emitting device (ED) and the common electrode (CE) at each of the inner patterning portion (IPP) and the outer patterning portion (OPP). The display device (10) according to Claim 1 or 2 wherein the first substrate (100) further comprises: a passivation layer (101d) which is arranged on the display area (AA); and an encapsulation layer (106) which is arranged on the common electrode (CE) and the laser patterning portion (LPP), wherein the dam structure (105) directly contacts an upper surface of the passivation layer (101d), and wherein the encapsulation layer (106) directly contacts the upper surface of the passivation layer (101d) at the laser patterning section (LPP). The display device (10) according to Claim 6 wherein the encapsulation layer (106), at the laser patterning portion (LPP), a laser isolation surface of each of the light emitting device (ED) and the common electrode (CE), a boundary portion between the light emitting device (ED) and the common Electrode (CE) and a boundary portion between the passivation layer (101d) and the light emitting device (ED) surrounds. The display device (10) according to one of the Claims 1 until 7th wherein the first substrate (100) further comprises a dummy dam structure (105m) surrounding the dam structure (105). The display device (10) according to Claim 8 wherein the dummy dam structure (105m) comprises: a first island structure (EDa) surrounding the dam structure (105) and comprising the same material as a material of the light emitting device (ED); and a second island structure (CEa) surrounding the first island structure (EDa) and comprising the same material as a material of the common electrode (CE). The display device (10) according to Claim 1 or 2 wherein the first substrate (100) further comprises: a passivation layer (101d) which is arranged in the display area (AA); and an encapsulation layer (106) having a first encapsulation layer (106a) disposed on the common electrode (CE) and the laser patterning portion (LPP), wherein the dam structure (105) is an upper surface of the passivation layer (101d) directly touched, and wherein the first encapsulation layer (106a) directly contacts the upper surface of the passivation layer (101d) at the laser structuring section (LPP). The display device (10) according to Claim 10 wherein the encapsulation layer (106) further comprises: a second encapsulation layer (106b) which is arranged on the first encapsulation layer (106a) in a region which is surrounded by the dam structure (105); and a third encapsulation layer (106c) arranged on the second encapsulation layer (106b). The display device (10) according to Claim 11 wherein the third encapsulation layer (106c) directly contacts the upper surface of the passivation layer (101d) at an outer periphery of the dam structure (105). A display device (10) comprising: a first substrate (100) having a plurality of pixel areas (PA) arranged in a display area (AA); a passivation layer (101d) arranged in the display area (AA); a dam structure (105) which is arranged on the passivation layer (101d) along an edge of the display area (AA); a light emitting device layer (103) comprising a common electrode (CE) and a light emitting device (ED) disposed on the dam structure (105) and in the plurality of pixel regions (PA); at least one cut line (LPP) located close to the dam structure (105); and a second substrate (200) connected to a back surface of the first substrate (100), wherein the at least one cut line (LPP) is formed by patterning the light emitting device (ED) and the common electrode (CE) to be concave. The display device (10) according to Claim 13 wherein the at least one cut line (LPP) isolates each of the light emitting device (ED) and the common electrode (CE) at a periphery of the dam structure (105). The display device (10) according to Claim 13 or 14th wherein the at least one cut line (LPP) exposes an upper surface of the passivation layer (101d). The display device (10) according to one of the Claims 13 until 15th wherein: the first substrate (100) further comprises an encapsulation layer (106) which is arranged on the common electrode (CE) and the at least one incision line (LPP), and the encapsulation layer (106) the at least one incision line (LPP). covered and directly touched an upper surface of the passivation layer (101d). The display device (10) according to one of the Claims 13 until 15th wherein: the first substrate (100) further comprises an encapsulation layer (106) disposed on the common electrode (CE) and the at least one incision line (LPP), and the encapsulation layer (106) on the at least one incision line (LPP) ) surrounds a laser isolation surface of each of the light emitting device (ED) and the common electrode (CE). The display device (10) according to Claim 17 wherein the encapsulation layer (106), at the at least one cut line (LPP), the laser isolation surface of each of the light emitting device (ED) and the common electrode (CE), a boundary portion between the light emitting device (ED) and the common Electrode (CE) and a boundary portion between the passivation layer (101d) and the light emitting device (ED) surrounds. The display device (10) according to one of the Claims 13 until 18th wherein the first substrate (100) further comprises a dummy dam structure (105m) surrounding the dam structure (105). The display device (10) according to Claim 19 wherein the dummy dam structure (105m) comprises: a first island structure (EDa) surrounding the dam structure (105) and made of the same material as a material of the light emitting device (ED); and a second island structure (CEa) surrounding the first island structure (EDa) and comprising the same material as a material of the common electrode (CE). The display device (10) according to one of the Claims 1 until 20th wherein the dam structure (105) is arranged in outermost pixel areas (PAo) of the plurality of pixel areas (PA). A multi-display device comprising: a plurality of display modules (10-1, ..., 10-4) arranged in at least one of a first direction and a second direction transverse to the first direction, each of the plurality of display modules (10-1, ..., 10-4) the display device (10) according to one of the Claims 1 until 20th having. The multi-display device according to Claim 22 wherein the dam structure (105) is arranged in outermost pixel areas (PAo) of the plurality of pixel areas (PA), and wherein, in two adjacent display modules each having side surfaces touching each other, of the plurality of display modules (10-1 , ..., 10-4), a second interval between central portions of adjacent outermost pixel areas (PAo) in different display modules is equal to or less than a first interval between central portions of two adjacent pixel areas in the same display module. The multi-display device according to Claim 22 or 23 wherein each of the plurality of display modules (10-1, ..., 10-4) further comprises a panel support member (600), and wherein the panel support member (600) comprises: a support plate (610) connected to a back surface of the second substrate (200) is bonded; and a plurality of fasteners (630) disposed on a rear surface of the support plate (610), the plurality of fasteners (630) being magnetized by means of a magnet.

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