DE102020119159A1 - CONDITIONING STRUCTURE AND PROCEDURES FOR EDUCATING THE SAME - Google Patents

Abstract

A package comprises a first die having a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends over the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or the plurality of first bond pad vias, wherein a second barrier layer extends over each first bond pad vias between a first bond pad and the first bond pad via, and a second die comprising one or more second bond pads, wherein a second bond pad with a first bond pad of the first This is related.

Description

PRIORITY CLAIM AND CROSS-REFERENCES

This application claims priority from U.S. Provisional Patent Application No. 62 / 893.971 , filed on August 30, 2019, which is incorporated in this application in its entirety by reference.

BACKGROUND

In wafer-wafer bonding technology, various processes have been developed to connect two package components (such as wafers) to one another. Some wafer bonding methods include fusion bonding, eutectic bonding, direct metal bonding, hybrid bonding, and the like. In fusion bonding, an oxide surface of one wafer is bonded to an oxide surface or a silicon surface of another wafer. In eutectic bonding, two eutectic materials are placed together and high pressure and temperature are applied. The eutectic materials are therefore melted. When the molten eutectic materials solidify, the wafers bond. With direct metal-to-metal bonding, two metal pads are pressed against one another at an elevated temperature and the diffusion between the metal pads causes the metal pads to bond. In hybrid bonding, the metal pads of two wafers are connected to one another by direct metal-to-metal bonding, and an oxide surface of one of the two wafers is connected to an oxide surface or a silicon surface of the other wafer.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Indeed, the various features may be arbitrarily enlarged or reduced in size for clarity of explanation.

1 to 9 10 illustrate cross-sectional views of intermediate stages in a process of forming a device structure in accordance with some embodiments.

10 to 17th 10 illustrate cross-sectional views of intermediate stages in a process of forming a die structure in accordance with some embodiments.

18A , 18B , 19A , 19B , 20A , 20B and 21 illustrate cross-sectional views of packages having the structures in accordance with some embodiments.

22nd to 26th illustrate cross-sectional views of intermediate stages in a process of forming a package structure in accordance with some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples of implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are of course only examples that are not to be understood as restrictive. For example, forming a first feature or a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and it may also include embodiments in which further features are formed between the first and second features so that the first and second features do not have to be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for simplicity and clarity and does not by itself dictate any relationship between the various embodiments and / or configurations illustrated.

Furthermore, spatially relative terms such as “below”, “below”, “lower”, “above”, “upper” and the like may be used herein for ease of description to describe the relationship of an element or feature to one or more other element (s ) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or in operation in addition to the orientation illustrated in the figures. The device may be otherwise oriented (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein may be construed accordingly.

A bonding structure and method are provided in accordance with some embodiments. Bond pad vias (BPVs) are formed over metal pads in a series of processing steps and then bond pads are formed over the BPVs in a subsequent series of processing steps. By forming the BPVs and the bond pads separately, the metal pads with which the BPVs are connected, formed closer together, and / or have a smaller area. Furthermore, the BPVs or the bond pads can also be formed closer together and / or with a smaller area. This can reduce the size of a die or package. The respective bond pads of two connected dies may be formed with different areas, such as such that misalignment between the two dies has little or no effect on contact resistance at the junction between the respective bond pads.

1 to 9 illustrate the cross-sectional views of the intermediate stages in the formation of a device structure 100 (please refer 9 ) according to some embodiments. 1 illustrates a substrate 102 according to some embodiments. In 1 to 9 are multiple device structures in some embodiments 100 on a single substrate 102 formed and then singulated to individual device structures 100 to build. In the 1 to 8th With " 100 “Labeled regions indicate regions in which the device structures 100 out 9 are formed, and the region labeled “104” shows a scribe line region 104 between adjacent device structures 100 .

The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, an insulator substrate (SOI substrate), a semiconductor wafer, or the like, which may be doped (e.g. with a p- or n-dopant) or undoped. In general, an SOI substrate includes a layer of semiconductor material formed on an insulating layer. The insulation layer can be, for example, a buried oxide layer (BOX layer), a silicon oxide layer or the like. The insulating layer is provided on a substrate, usually a silicon substrate or a glass substrate. Other substrates, such as a multilayer or sloping substrate, can also be used. In some embodiments, the semiconductor material of the substrate may be silicon; Germanium; a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof.

In some embodiments, the substrate 102 and utilizing features formed thereon to form a device die, integrated circuit die, or the like. In such embodiments, integrated circuit devices can be on the top surface of the substrate 102 be educated. Exemplary integrated circuit devices may include complementary metal oxide semiconductor (CMOS) transistors, fin field effect transistors (FinFETs), resistors, capacitors, diodes, the like, or a combination thereof. The details of the integrated circuit devices are not illustrated herein. In other embodiments, the substrate 102 used to form an interposer structure. In such embodiments, there are no active devices such as transistors on the substrate 102 educated. Passive devices such as capacitors, resistors, inductors or the like can be in the substrate 102 be educated. The substrate 102 may in some embodiments also be a dielectric substrate in which the substrate 102 Is part of an interposer structure. In some embodiments, vias (not shown) may be formed that extend through the substrate 102 extend to components on opposite sides of the substrate 102 connect to.

In 2 is an interconnect structure 108 above the substrate 102 educated. The interconnect structure 108 provides routing and electrical connections between devices that are in the substrate 102 are formed, and can e.g. B. be a redistribution structure or the like. The interconnect structure 108 can have multiple layers of insulation 110 which may be inter-metal dielectric layers (IMD layers), which are described in more detail below. Each of the insulation layers 110 includes one or more conductive features 113 , which may be metal lines and / or vias formed therein in a metallization layer. In other embodiments, the metal lines can be redistribution layers, for example. The conductive features 113 can be electrically connected to the active and / or passive devices of the substrate through the contacts (not shown in the figures) 102 be coupled.

Some sections of the conductive features 113 that are in the top layer of insulation 110 the interconnect structure 108 may be formed with a relatively larger area than the other conductive features 113 within the interconnect structure 108 . The conductive characteristics of the interconnect structure 108 that are in the top layer of insulation 110 are formed are in 2 separately as metal pads 112 designated. The metal pads 112 can be used as for the connection of the following conductive features (e.g. conductive pads 118 , Bond pad vias (BPVs) 128 or the like) with the interconnect structure 108 be used. In some embodiments, the conductive features can be the topmost insulation layer 110 also include metal lines or vias that are in 2 are not shown separately. The metal pads 112 can with a width W1 be formed between about 2 microns and about 10 microns is wide or has an area between approximately 4 μm ² and approximately 100 μm ² . Adjacent metal pads 112 can move a distance D1 be separated, which is between about 2 µm and about 20 µm in size. Other dimensions or distances are possible. In some cases, the techniques described herein can allow metal pads 112 a smaller width W1 or have a smaller area. In some cases, the techniques described herein can include forming metal pads 112 allow that by a smaller distance D1 are separated. By making a smaller or tighter metal pad 112 the dimensions (e.g. the "footprint") of the device structure 100 be reduced. Furthermore, the routing distance between features can be reduced, resulting in a higher speed operation of the device structure 100 can improve.

In some embodiments, the insulation layers 110 be formed from a low-k material that has a k-value less than about 3.0. The insulation layers 110 may be formed from an extra-low-k dielectric (ELK) that has a k value less than 2.5. In some embodiments, the insulation layers 110 be formed from an oxygen-containing and / or carbon-containing dielectric with a low k value, hydrogen silses quioxane (HSQ), methyl silses quioxane (MSQ), the like or a combination thereof. In some embodiments, some or all of the insulation layers are 110 formed from low-k dielectrics such as silicon oxide, silicon carbide (SiC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), or the like. In some embodiments, etch stop layers (not shown), which may be formed from silicon carbide, silicon nitride, or the like, are placed between isolation layers 110 educated. In some embodiments, the insulation layers are 110 formed from a porous material such as SiOCN, SiCN, SiOC, SiOCH or the like and can be formed by spin-on coating or a deposition process such as plasma enhanced vapor deposition (PECVD), CVD, PVD or the like. In some embodiments, the interconnect structure 108 comprise one or more types of layers, such as diffusion barrier layers (not shown).

In some embodiments, the interconnect structure 108 be formed using a single and / or a dual damascene process, a via-first process, or a metal-first process. In one embodiment is an insulation layer 110 and openings (not shown) are formed therein using acceptable photolithography and etching techniques. Diffusion barrier layers (not shown) can be formed in the openings and can comprise a material such as TaN, Ta, TiN, Ti, CoW, or the like, and can be formed in the openings using a deposition process such as CVD, atomic layer deposition (ALD), or the like. A conductive material can be formed in the openings from copper, aluminum, nickel, tungsten, cobalt, silver, combinations thereof, or the like and can be formed over the diffusion barrier layers in the openings using an electrochemical plating process, CVD, ALD, PVD, the like, or a combination be formed from it. After the conductive material is formed, excess conductive material can be removed using, for example, a planarization process such as CMP, so that conductive features 113 in the openings of the respective insulation layer 110 lag behind. The process can then be repeated to add additional layers of insulation 110 and conductive features 113 to form in it. In some embodiments, the top insulation layer 110 and the metal pads formed therein 112 with a thickness greater than a thickness of the other insulation layers 110 the interconnect structure 108 are formed. In some embodiments, one or more of the top conductive features are dummy metal lines or dummy metal pads 112 electrically from the substrate 102 are isolated.

In 3rd is a passivation layer 114 above the interconnect structure 108 and one or more openings are in the passivation layer 114 educated. The passivation layer 114 may comprise one or more layers of one or more materials. For example, the passivation layer 114 one or more layers of silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination. The passivation layer 114 can be formed by any suitable process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. In some embodiments, the passivation layer 114 with a thickness greater than a thickness of the topmost insulation layer 110 are formed. The openings in the passivation layer 114 can be formed using a suitable photolithographic and etching process. For example, a photoresist can be applied over the passivation layer 114 be formed and patterned, and then the patterned photoresist used as an etch mask. The passivation layer 114 can be etched using a wet etch process and / or a dry etch process. The openings are formed to accommodate sections of the metal pads 112 for electrical connection to be disclosed.

In 4th are conductive pads in some embodiments 118 above the Passivation layer 114 educated. One or more conductive pads 118 can be formed so that they pass through the openings in the passivation layer 114 extend to make electrical connection with one or more of the metal pads 112 the interconnect structure 108 to manufacture. In some embodiments, the conductive pads 118 can be formed by first depositing a cover layer of a conductive material such as aluminum. For example, CVD, PVD or the like can be used, a layer of aluminum over the passivation layer 114 , the openings and the metal pads 112 to be deposited. A layer of photoresist (not separately illustrated) can then be formed over the aluminum layer and the aluminum layer can be etched to form the conductive pads 118 to build. Conductive pads 118 formed from aluminum in this way can be referred to as "aluminum pads".

In other embodiments, the conductive pads 118 formed by first placing a seed layer over the passivation layer 114 and the openings is formed. In some embodiments, the seed layer is a metal layer that includes one or more layers that can be formed from various materials. The seed layer can be formed using PVD or the like, for example. A photoresist is formed and patterned on the seed layer, and conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. In some embodiments, the conductive material can be formed by a plating process, such as using an electroplating or electroless plating process, or the like. The conductive material can include one or more materials, such as copper, titanium, tungsten, gold, cobalt, the like, or a combination thereof. The photoresist and portions of the seed layer on which the conductive material is not formed are then removed using, for example, a suitable ash or stripping process, such as the use of an oxygen plasma or the like. When the photoresist is removed, remaining exposed portions of the seed layer can be removed, such as by using an acceptable etch process, such as a wet etch process or a dry etch process. The remaining portions of the seed layer and conductive material form the conductive pads 118 . The conductive pads 118 may be formed using other techniques in other embodiments, and all such techniques are considered to fall within the scope of this disclosure.

In some embodiments, the conductive pads 118 that are electrically connected to the interconnect structure 108 used as test pads before further processing. For example, the conductive pads 118 probed as part of a wafer acceptance test, circuit test, known good die test (KGD test), or the like. The probing can be done to determine the function of the active or passive devices of the 102 or the respective electrical connections within the substrate 102 or the interconnect structure 108 (e.g. the conductive features 113 ) to verify. The probing can be done by contacting a probe needle 119 to the conductive pads 118 respectively. The probe needle 119 can be part of a probe card containing multiple probe needles 119 which can be connected to test equipment, for example.

In some embodiments, the conductive material of the conductive pads can be 118 differs from the conductive material of the metal pads 112 distinguish.

For example, the conductive pads 118 Be aluminum and the metal pads 112 can be copper, but other conductive materials can also be used. In some embodiments, the conductive pads 118 have a width W2 between approximately 2 μm and approximately 30 μm or a length (for example at right angles to the width) between approximately 20 μm and approximately 100 μm. In some embodiments, the conductive pads 118 from an adjacent metal pad 112 through a distance D2 are separated, which is between approx. 2 µm and approx. 30 µm. The embodiments described in this disclosure can have a smaller separation distance between conductive pads 118 and adjacent metal pads 112 without increasing the possibility of causing processing defects such as short circuits. In this way, the dimensions of the device structure 100 can be reduced without reducing the yield.

With a view to 5 is a dielectric layer 122 over the passivation layer 114 and the conductive pads 118 educated. The dielectric layer 122 may be formed from one or more layers of one or more dielectrics, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, the like, or a combination thereof. In some embodiments, the dielectric layer can 122 be formed from phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), tetraethylorthosilicate (TEOS), the like or a combination thereof. The dielectric layer 122 can be formed by a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. The dielectric layer 122 may be formed with a greater thickness than the conductive pads 118 so that the material of the dielectric layer 122 laterally the conductive pads 118 surrounds and so the dielectric layer 122 can be planarized (see below) without the conductive pads 118 to disclose.

In 6th are openings in some embodiments 124 in the dielectric layer 122 educated. The openings 124 put the metal pads 112 open to allow subsequently formed bond pad vias (BPVs) 128 an electrical connection with the interconnect structure 108 through the metal pads 112 produce. In some embodiments, the openings lay 124 the conductive pads 118 open and the FOPI 128 make an electrical connection with the interconnect structure 108 through the conductive pads 118 her (see e.g. 20A to 21 ). The openings 124 can be formed using acceptable photolithography and etching techniques. For example, the photolithography process can include forming photoresist (not shown) over the dielectric layer 122 Pattern the photoresist with openings that fill the openings 124 correspond, widening the openings 124 through the dielectric layer 122 and the passivation layer 114 to the metal pads 112 and then remove the photoresist.

With a view to 7th are, according to some embodiments, bond pad vias (BPVs) 128 in the openings 124 educated. The FOPI 128 can have similar dimensions as the openings 124 in which they are formed and may be of a similar shape (e.g., tapered profile). In some embodiments, this includes forming the BPVs 128 first the formation of a first barrier layer 127 inside the openings 124 . The first barrier layer 127 can for example be a lining, a diffusion barrier layer, an adhesive layer or the like. The first barrier layer 127 may comprise one or more layers comprising titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof. The first barrier layer 127 can be used as a cover layer over the dielectric layer 122 and inside the openings 124 to be deposited. The first barrier layer 127 may be formed by a deposition process such as PECVD, PVD, the like, or combinations thereof.

The formation of the FOPI 128 may include depositing a conductive material over the first barrier layer 127 include. The conductive material can include cobalt, copper, a copper alloy, titanium, silver, gold, tungsten, aluminum, nickel, the like, or combinations thereof. The conductive material of the BPVs 128 may be formed by a deposition process such as PECVD, PVD, the like, or combinations thereof. In some embodiments, the conductive material is the BPVs 128 by depositing a seed layer (not shown) over the first barrier layer 127 which may include copper, copper alloy, titanium, or the like, and then filling the remaining openings 124 for example, using an electroless plating process or the like.

After the conductive material is formed, a planarization process, such as a grinding process, a chemical mechanical polishing (CMP) process, or the like, may be performed to remove excess material from a surface of the dielectric layer 122 to remove. The remaining first barrier layer 127 and the conductive material thus form the BPVs 128 . In this way the FOPI can 128 be formed using a single damascene process. In some embodiments, some “dummy” BPVs 128 (not shown) may be formed without electrical connection to the metal pads 112 to have. In some cases, dummy BPVs can be used 128 Reduce uneven loading and improve surface planarity after the planarization step that removes excess material.

The FOPI 128 can have a width W ₃ between approximately 1 μm and approximately 5 μm, although other widths are also possible. In some embodiments, the BPVs 128 have a tapered profile, such as an upper width W ₃ A that is between about 1 µm and about 5 µm and a lower width W ₃ B that is between about 0.5 and about 4 µm. The width W _{3 of} a BPV 128 can be between about 50% and about 95% of the width W _{1 of} its associated metal pad 112 lie (see 2 ). The FOPI 128 can be formed so that the lateral distance D ₃ between a side wall of a BPV 128 and the adjacent side wall of its associated metal pad 112 between approx. 1 µm and approx. 5 µm, although other distances are also possible. In some cases this can be done by forming the BPVs 128 separated from the bond pads 316 (please refer 17th below) the metal pads 112 be formed with a smaller width W ₁ that is closer in size to the width W _{3 of} the BPVs 128 lies. This can reduce the lateral separation between features such as conductive pads 118 , Metal pads 112 , BPVs 128 and / or bond pads 316 allow (see 17th ). Furthermore, the distance D _{3 can be} reduced so that the BPVs 128 closer to the edges of the metal pads 112 can be formed.

With a view to 8th becomes a tie layer 126 over the dielectric layer 122 educated. The connection layer 126 may be formed from one or more layers of one or more dielectrics and may be a silicon-containing material, such as silicon oxide. In some embodiments, the connection layer 126 comprise one or more layers of other materials such as silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, the like, or a combination thereof. The connection layer 126 can be formed by a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. In some embodiments, the connection layer comprises 126 a different material than the dielectric layer 122 .

In 9 a separation process takes place along the scribe line regions 104 for separating adjacent device structures 100 . The singulation process can include a dicing process, a sawing process, a laser process, the like, or a combination thereof. In some embodiments, there are singulated device structures 100 , which were probed and found to be Known Good Die (KGD), as described above in 4th described, used in subsequent process steps to make the structures 300 to form (see 15th ).

10 to 17th illustrate the cross-sectional views of the intermediate stages in the formation of a diestructure 300 (please refer 17th ) showing the device structure 100 includes, according to some embodiments. In 10 is the device structure 100 according to some embodiments with a carrier 202 connected. The carrier 202 may be a silicon substrate (e.g. a silicon wafer), a glass substrate, an organic substrate (e.g. a panel), or the like. In some embodiments, one or more layers, such as oxide layers or etch stop layers, may be on the carrier 202 that are formed in the 10 to 13th as layers 204 you can see. In some embodiments, is a dielectric layer 208 on the carrier 202 formed, and optional alignment features 210 within the dielectric layer 208 be educated. In some embodiments, the dielectric layer can 208 from silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like or a combination thereof. The dielectric layer 208 can be formed by a deposition process such as CVD, PECVD, PVD, the like, or a combination thereof. In some embodiments, the dielectric layer is 208 formed from a further material than the subsequently formed connecting layer 212 , and can serve as a buffer layer for absorbing loads. In some embodiments, the are alignment features 210 Metal features that are in the dielectric layer 208 are formed. The alignment features 210 can be used as alignment marks for aligning subsequent placement (e.g., using a pick and place process) and bonding of the device structure 100 be used. The alignment features 210 can be formed using a damascene process or other suitable process, for example.

A tie layer 212 can then over the dielectric layer 208 be educated. The connection layer 212 may be formed from one or more layers of one or more dielectrics such as silicon oxide or the like. The connection layer 212 can be formed by a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. The connection layer 212 may comprise the same material as the tie layer 126 , or a material other than the tie layer 126 . The combination of the carrier 202 , the dielectric layer 208 and the tie layer 212 is referred to herein as the first support structure 250 designated.

Still referring to 10 is the device structure 100 on the first support structure 250 placed, for example using a pick-and-place process. The alignment features 210 can be used during placement to structure the fixture 100 align. The device structure 100 is placed so that the connection layer 126 and the tie layer 212 stay in contact. A plasma cleaning process or a wet chemical cleaning process can be performed prior to placement on the tie layer 126 or the tie layer 212 to activate the surfaces. After the placement is made the connection layer 126 the device structure 100 with the connection layer 212 Connected via direct bonding (e.g. “fusion bonding” or “dielectric-dielectric bonding”), which, for example, is Si-O-Si bonds between the connecting layer 126 and the tie layer 212 can form. In some embodiments, the connection layer 126 and the tie layer 212 be pressed together to simplify the bonding process. The bonding process can take place at room temperature (e.g. at a temperature of approx. 21 ° C to approx. 25 ° C), although higher temperatures can also be used. In some embodiments, annealing occurs after the bond, which is the connection between the connection layer 126 and the tie layer 212 can strengthen.

With a view to 11 become dielectric regions 214 (otherwise referred to as "gap filler dielectric" regions) around the device structure, in some embodiments 100 made around. In some embodiments, the dielectric regions 214 from one or more layers of silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like or a combination thereof. The dielectric of the dielectric regions 214 may be formed by a deposition process such as PECVD, PVD, the like, or a combination thereof. In some embodiments, the dielectric may be formed by dispensing a flowable dielectric (e.g., a flowable oxide) and then curing the flowable dielectric. The flowable dielectric can be dispensed using a lamination process, a spin coating process, or the like. After the dielectric is formed, a planarization process (e.g., a CMP or grinding process) can be performed to remove excess dielectric from over the substrate 102 the device structure 100 remove and dielectric regions 214 to build. After performing the planarization process, the dielectric regions 214 and the substrate 102 have flat (e.g. coplanar) surfaces. In some embodiments, the planarization process also thins the substrate 102 out.

With a view to 12th becomes a dielectric layer 220 on the dielectric regions 214 and the substrate 102 educated. In some embodiments, there are optional alignment features 222 within the dielectric layer 220 educated. In some embodiments, the dielectric layer can 220 from silicon oxide, PSG, BSG, BPSG, FSG, silicon nitride, the like or a combination thereof. The dielectric layer 220 can be formed by a deposition process such as CVD, PECVD, PVD, the like, or a combination thereof. In some embodiments, the dielectric layer is 220 formed from a further material than the subsequently formed connecting layer 224 , and can serve as a buffer layer for absorbing loads. In some embodiments, the are alignment features 222 Metal features that are in the dielectric layer 220 are formed. The alignment features 222 can be formed using a damascene process or other suitable process, for example.

A tie layer 224 can then over the dielectric layer 220 be educated. The connection layer 224 may be formed from one or more layers of one or more dielectrics such as silicon oxide or the like. The connection layer 224 may be formed from similar materials or using similar techniques as for the tie layer above 126 described.

With a view to 13th According to some embodiments, the structure is flipped and with a second support structure 350 connected, and then the first support structure 250 away. The second support structure 350 can for example be a tie layer 306 include that over a beam 302 is formed. The carrier 302 may be a silicon substrate (e.g. a silicon wafer), a glass substrate, an organic substrate (e.g. a panel), or the like. The connection layer 306 may be formed from one or more layers of one or more dielectrics, and may include a silicon-containing material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, SiOC, SiOCH, SiCH, the like, or a combination thereof. The connection layer 306 can be formed by a deposition process such as CVD, PECVD, PVD, ALD, the like, or a combination thereof. The connection layer 306 may comprise the same material as the tie layer 224 , or a material other than the tie layer 224 .

Still referring to 13th the structure is turned over, and the connecting layer 224 is, according to some embodiments, on the connection layer 306 the second support structure 350 placed. A plasma cleaning process or a wet chemical cleaning process can be performed prior to placement on the tie layer 224 or the tie layer 306 to activate the surfaces. After the placement is made the connection layer 224 with the connection layer 306 Connected via direct bonding (e.g. “fusion bonding” or “dielectric-dielectric bonding”), which for example is Si-O-Si bonds between the connecting layer 224 and the tie layer 306 can form. In some embodiments, the connection layer 224 and the tie layer 306 be pressed together to simplify the bonding process. The bonding process can take place at room temperature (e.g. at a temperature of approx. 21 ° C to approx. 25 ° C), although higher temperatures can also be used. In some embodiments, annealing occurs after the bond, which is the connection between the connection layer 224 and the tie layer 306 can strengthen.

In 14th become the first support structure according to some embodiments 250 and the tie layer 126 away. In some embodiments, a planarization process (e.g., a CMP or grinding process) can be performed around the carrier 202 , the dielectric layer 208 , the connection layer 212 and the tie layer 126 to remove. As in 14th As shown, the planarization process can affect the BPVs 128 and the dielectric layer 122 disclose. Sections of the Dielectric layers 214 are also removed by the planarization process, leaving the areas of the remaining dielectric regions 214 just with the dielectric layer 122 and the FOPI 128 are. In some embodiments, one or more etching processes (e.g., dry etching processes or wet etching processes) can be used to create portions of the first support structure 250 remove before running the planarization process. In some embodiments, an etch process may be through a layer such as the interconnect layer 212 , the dielectric layer 208 or an etch stop layer within the carrier 202 (if present) must be stopped.

With a view to 15th becomes a bonding layer 312 over the dielectric regions 214 , the dielectric layer 122 and the FOPI 128 educated. The bonding layer 312 may be formed from one or more layers of one or more dielectrics such as silicon oxide or the like. The bonding layer 312 may be formed from similar materials or using similar techniques as for the tie layer above 126 or the tie layer 224 described. In some embodiments, the bonding layer is 312 formed with a thickness between about 0.2 nm and about 1 nm. The thickness of the bonding layer 312 can be the thickness of the subsequently formed bond pads 316 determine (see 17th ).

In 16 are openings in some embodiments 314 in the bonding layer 312 educated. The openings 314 lay the FOPI 128 open to allow subsequently formed bond pads 316 an electrical connection with the interconnect structure 108 by the FOPI 128 produce. The openings 314 can be formed using acceptable photolithography and etching techniques. For example, the photolithography process can include forming photoresist (not shown) over the interconnect layer 312 Pattern the photoresist with openings that fill the openings 314 correspond, widening the openings 314 through the connection layer 312 to the BPVs 128 and then remove the photoresist.

With a view to 17th become bond pads in accordance with some embodiments 316 in the openings 314 formed to a thistructure 300 to build. In some embodiments, includes forming the bond pads 316 first the formation of a second barrier layer 315 inside the openings 314 . The second barrier layer 315 can for example be a lining, a diffusion barrier layer, an adhesive layer or the like. The second barrier layer 315 may comprise one or more layers comprising titanium, titanium nitride, tantalum, tantalum nitride, the like, or combinations thereof. The second barrier layer 315 can be used as a top layer over the tie layer 312 and inside the openings 314 to be deposited. The second barrier layer 315 may be formed by a deposition process such as PECVD, PVD, the like, or combinations thereof. The second barrier layer 315 may, in some embodiments, be made of a material similar to that of the first barrier layer 127 be educated. As in 17th shown extends because the BPVs 128 in a separate process step prior to the formation of the bond pads 316 are formed every other barrier layer 315 over the top of a BPV 218 which may include extending over the top surfaces of the first barrier layer 127 extends. This will become the first barrier layer 127 a BPV 128 and the second barrier layer 315 a bond pad 316 formed separately instead of the FOPI 128 and the bond pads 316 share a single continuous barrier layer formed in a single step.

The formation of the bond pads 316 may include depositing a conductive material over the second barrier layer 315 include. The conductive material can comprise copper or a copper alloy, for example. The conductive material can include other materials such as titanium, silver, gold, tungsten, aluminum, nickel, cobalt, the like, or combinations thereof. The conductive material of the bond pads 316 may be formed by a deposition process such as PECVD, PVD, the like, or combinations thereof. In some embodiments, the conductive material is the bond pads 316 by depositing a seed layer (not shown) over the second barrier layer 315 which may include copper, copper alloy, titanium, or the like, and then filling the remaining openings 314 for example, using an electroless plating process or the like. The bond pads 316 may, in some embodiments, be made of a material similar to that of the BPVs 128 be educated.

After the conductive material is formed, a planarization process, such as a grinding process, a chemical mechanical polishing (CMP) process, or the like, may be performed to remove excess material from a surface of the bonding layer 312 to remove. The remaining second barrier layer 315 and the conductive material thus forms the bond pads 316 . In this way the bondpads 316 be formed using a single damascene process. In some embodiments, some “dummy” bondpads 316 (not shown) be formed without an electrical connection to the BPVs 128 and / or the metal pads 112 to have. In some cases, you can use dummy bond pads 316 unequal Reduce stress and improve surface planarity after the planarization step that removes excess material.

In some embodiments, the bond pads 316 have a width W ₄ between approximately 0.2 μm and approximately 5 μm, although other widths are also possible. In some embodiments, the width W _{4 of} a bond pad 316 between approx. 120% and approx. 200% of the width W _{3 of} your associated BPV 128 lie (see 7th ). In some embodiments, the bond pads 316 be formed so that the lateral distance D ₄ between a side wall of a bond pad 316 and the adjacent sidewall of their associated BPV 128 between approx. 0.5 µm and approx. 2 µm, although other distances are also possible. In some embodiments, the lateral separation can be between adjacent bond pads 316 have a distance D ₅ which is between approximately 2 μm and approximately 7 μm. In some cases, the bond pads 316 by forming the BPVs 128 separated from the bond pads 316 be formed with a smaller separation distance D _{5 as described herein.} In some cases this can be done by making up the BPVs 128 in a separate process step from the bond pads 316 the lateral separation (e.g., the distance) between features such as conductive pads 118 , Metal pads 112 , BPVs 128 and / or bond pads 316 and reducing the sizes of such features without risking electrical shorts or other process flaws.

With view on 18A through B is a package according to some embodiments 500 shown that the first thistructure 300 and a second thistructure 400 includes that are connected to each other. 18B shows a package 500 similar to that out 18A , however, for illustrative purposes, some features are included in 18B are shown with a larger alignment distance than in 18A . The first structure 300 of the package 500 may be similar to the thestructure 300 be that for 17th has been described. In some embodiments, the second includes the structure 400 Dielectric regions 402 (otherwise known as "gap filler dielectric" regions), a device structure 440 , a bonding layer 412 and one or more bond pads 410 . The second structure 400 out 18A through B is an example and the second is the structure 400 or components thereof (e.g. the device structure 440 ) may have different structures or different types of structures than shown without departing from the scope of this disclosure.

The device structure 440 may be similar to the device structure previously described for 100 . For example, the device structure 440 a substrate 442 that is similar to the substrate 102 , which may include integrated circuit devices formed thereon. In some embodiments, substrate vias (TSVs) can be 446 through the substrate 442 extend. The TSVs 446 can be formed, for example, by forming openings that extend through the substrate using a suitable photolithography and etching process 442 extend. The openings can then be filled with a conductive material, such as copper or the like, which can be formed using a suitable process such as a plating process. In some embodiments, the device structure comprises 440 Metal pads 444 or conductive pads 450 that are similar to the metal pads 112 or the conductive pads 118 the device structure 100 could be.

The dielectric regions 402 can be similar to the previously described dielectric regions 214 such as by being formed of silicon oxide or the like. The bonding layer 412 may be formed from one or more layers of one or more dielectrics such as silicon oxide or the like. The bonding layer 412 may be formed from similar materials or using similar techniques as for the tie layer above 126 , Connection layer 224 or the bonding layer 312 described. The bond pads 410 may be formed from a conductive material such as copper, a copper alloy, or the like. The bond pads 410 can also comprise a barrier layer (not shown). The bond pads 410 may, in some embodiments, be formed from one or more similar materials, or using similar techniques, as above for the bond pads 316 described.

In some embodiments, the bond pads 410 have a width W ₅ between approximately 1 μm and approximately 5 μm, although other widths are also possible. In some embodiments, the width W _{5 of} a bond pad 410 between approx. 95% and approx. 150% of the width W _{4 of} its associated bond pad 316 lie. In this way, the width W _{5 of} the bond pads 410 be greater than the width W _{4 of} the bond pads 316 . After bonding the bond pads 410 to the bond pads 316 the bondpads 410 laterally over the bond pads 316 as in 18th shown extend beyond. 18A shows bond pads 410 for example on bond pads 316 centered, but in other cases there may be some lateral displacement between a bond pad 410 and a bond pad 316 are present. A shift can be, for example, a pick-and-place overlay shift during the placement of the second diaphragm structure 400 on the first thistructure 300 lie. For example, in 18B a bond pad 410 than by a distance S1 against a bond pad 316 shown shifted. The distance S1 corresponds to the lateral distance between the center of the bond pad 410 (e.g. B. at half the width W ₅ ) and the middle of the bond pad 316 (e.g. at half the width W ₄ ). In some cases the formation of bond pads 410 that are wider than bond pads 316 increase the possibility of having the entirety of the upper surfaces of the bond pads 316 with the bond pads 410 connected when there is a shift between the first thestructure 300 and the second structure 400 is present. In some cases, the maximum displacement distance (e.g. S1) remains for the entire area of a bond pad 316 remains connected by the difference between the width W _{5 of} the bond pad 410 and the width W _{4 of} the bond pad 316 specified. Connect the entire upper surfaces of the bond pads 316 can reduce the contact resistance between the bond pads 316 and the bond pads 410 and thus the electrical output of the package 500 improve. In this way, undesirable effects due to the displacement by forming bond pads can be avoided 410 with a larger width than that of the bond pads 316 be reduced.

Other shifts are possible. For example shows 18A Bond pads 316 for example on BPVs 128 centered, but in other cases there may be some lateral displacement between a bond pad 316 and a BPV 128 are present. For example, in 18B a bond pad 316 than by a distance S2 against a BPV 128 shown shifted. The distance S2 corresponds to the lateral distance between the center of the bond pad 316 (e.g. at half the width W ₄ ) and the middle of the BPV 128 (e.g. at half the width W ₃ ). In some cases the formation of bond pads 316 that are wider than BPVs 128 increase the possibility that the entirety of the upper surfaces of the BPVs 128 through the overlying bond pads 316 are covered when there is a shift between the bond pads 316 and the FOPI 128 is present. In some cases, the maximum displacement distance (e.g. S2) remains for the entire top surface of a BPV 128 through an overlying bond pad 316 remains covered by the difference between the width W _{4 of} the bond pad 316 and the width W _{3 of} the BPV 128 specified. Covering the entire upper surfaces of the BPVs 128 can reduce the contact resistance between the bond pads 316 and the FOPI 128 and thus the electrical output of the package 500 improve. In this way, undesirable effects due to the displacement by forming bond pads can be avoided 316 with a greater breadth than that of the BPVs 128 be reduced.

The second structure 400 can also be a redistribution structure 452 include, including dielectric layers 460 and 462 and metallization structures 454 and 456 . The redistribution structure 452 can be designed to combine the various features such as the device structure 440 and vias 408 (described below) to form functional circuit arrangements. The metallization structures can also be referred to as redistribution layers or redistribution lines. More or fewer dielectric layers and metallization structures than can be shown in the redistribution structure 452 are formed. If fewer dielectric layers and metallization structures are to be formed, steps and the process can be repeated as explained below. If more dielectric layers and metallization structures are to be formed, the steps and process can be repeated as explained below.

As an example of forming the redistribution structure 452 can the metallization structure 454 be formed first. Around the metallization structure 454 will form a seed layer over the device structure 400 and the dielectric regions 402 educated. In some embodiments, the seed layer is a metal layer that can be a single layer or a composite layer that includes multiple sublayers formed from different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be formed using PVD or the like, for example. A photoresist is then formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed for patterning. The structure of the photoresist corresponds to the metallization structure 454 . The structuring forms openings through the photoresist for exposing the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating or the like. The conductive material can include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying sections of the seed layer form the metallization structure 454 . The photoresist and portions of the seed layer on which the conductive material will not be formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. When the photoresist is removed, exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as wet or dry etching.

The dielectric layer 460 is then applied to the metallization structure 454 , the device 440 and the dielectric layers 402 deposited. In some embodiments, the dielectric layer is 460 formed from a photosensitive material such as PBO, polyimide, BCB or the like, which can be patterned using a lithography mask. The dielectric layer 460 can be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 460 is then structured. The structuring forms openings, the sections of the metallization structure 454 disclose. The patterning can be done by an acceptable process, such as by exposing the dielectric layer to light 124 when the dielectric layer 460 is a photosensitive material, or by etching, for example using an anisotropic etching. If the dielectric layer 460 is a photosensitive material, the dielectric layer 460 can be developed after exposure.

The metallization structure 456 is then placed on top of the patterned dielectric layer 460 and extends into the openings in the dielectric layer 460 to the metallization structure 454 to contact. The metallization structure 456 can be formed in a manner similar to the metallization structure 454 is similar, and may be made of a similar material as the metallization structure 454 are formed. The dielectric layer 462 can on the metallization structure 456 and the dielectric layer 460 are formed. The dielectric layer 462 can be formed in a manner similar to the dielectric layer 460 is similar, and may be made of a similar material as the dielectric layer 460 are formed. The redistribution structure 452 may be formed using different materials or techniques than those described in this example.

In some embodiments, the second includes the structure 400 one or more vias 408 which is partially or entirely through the second thestructure 400 extend to deal with the redistribution structure 452 or other features on opposite sides of the second die structure 400 connect to. A second structure 400 may, in some embodiments, be zero, one, two, or more than two vias 408 include. The second structure 400 out 18th According to some embodiments also includes sub-bump metallizations (UBMs) 418 and external connectors 420 who participated in the redistribution structure 452 are formed. The UBMs 418 make an electrical connection with conductive features within the second die structure 400 ready, and the external connector 420 (e.g. solder balls, bumps or the like) are on the UBMs 418 educated. In some embodiments, the are UBMs 418 not before forming the external connectors 420 and in some embodiments the external connectors are 420 not on the second thistructure 400 educated.

The illustrated second structure 400 is an illustrative example, and it will be recognized that all suitable dies, chips, devices, or the like are contemplated within the scope of this disclosure. In some embodiments, the second structure can be 400 be formed in a manner similar to the first die structure 300 is. For example, the second structure 400 BPVs include (not individually labeled), which are formed in a first process step, and the bond pads 410 can be formed via the BPVs in a separate process step, as above for 7th and 17th described.

In some embodiments, the second is the structure 400 using e.g. B. Direct bonding or hybrid bonding with the first diestructure 300 connected to Package 500 to build. Before the bonding is carried out, a surface treatment can be applied to the second diestructure 400 or the first thestructure 300 to activate the surfaces. In some embodiments, the surface treatment includes plasma treatment. The plasma treatment can take place in a vacuum environment (for example a vacuum chamber, not shown). The process gas that is used to generate a plasma can be a hydrogen-containing gas that includes a first gas that includes hydrogen (H2) and argon (Ar), a second gas that includes H ₂ and nitrogen (N ₂ ) , or a third gas _{comprising H 2} and helium (He). The plasma treatment can also be carried out using pure or essentially pure H2, Ar or N ₂ as the process gas which is applied to the surfaces of the bond pads 316/410 and the bonding layers 312/412 treated. The second structure 400 or the first thestructure 300 can be treated with the same surface treatment process, or with different surface treatment processes, or can be left untreated. In some embodiments, the second structure can be 400 or the first thestructure 300 cleaned after surface treatment. Cleaning may include, e.g. B. dry cleaning and cleaning / rinsing with deionized water.

Next, a pre-bond process can be performed with the second die structure 400 and the first structure 300 are executed. The second structure 400 on is the first thestructure 300 placed, for example using a pick-and-place process. The alignment features 222 can be used during placement to make the second thestructure 400 align. The second structure 400 and the first thestructure 300 are aligned so that the bonding pads 410 and / or the Vias 408 the second structure 400 on the bonding pads 316 the first thestructure 300 are aligned. After the alignment, the second structure 400 and the first thestructure 300 are pressed against each other. The compressive force can be less than about 5 Newtons per die in some embodiments, but a greater or lesser force can be used. The pre-bonding process can take place at room temperature (e.g. at a temperature of approx. 21 ° C to approx. 25 ° C), although higher temperatures can also be used. The pre-bond time can be less than about 1 minute in some embodiments.

After the pre-bonding, the bonding layer 412 the second structure 400 and the bonding layer 312 the first thestructure 300 connected to each other and form a package 500 . The connection between the bonding layers 312/412 can be reinforced in a subsequent tempering step. The package 500 can be tempered at a temperature of approx. 300 ° C to approx. 400 ° C and for a period of between approx. 1 hour and approx. 2 hours. Metals can be in the bond pads during annealing 316 and 410 diffuse, so that metal-metal connections are also formed. Connections between the bond pads 316 and corresponding vias 408 can be formed similarly. Therefore, the resulting connections between the first diestructure 300 and the second structure 400 Hybrid connections. In some embodiments, after annealing, there is no material interface between the bond pads 316 and the corresponding bond pads 410 or vias 408 available. In some embodiments, a singulation can be carried out on the package after the bonding 500 .

18A shows a via 408 for example on a bond pad 316 centered, but in other cases there may be some lateral displacement between a via 408 and a bond pad 316 are present. For example, in 18B a via 408 than by a distance S ₃ against a bond pad 316 shown shifted. The distance S ₃ corresponds to the lateral distance between the center of the via 408 and the middle of the bond pad 316 (e.g. at half the width W ₄ ). In some cases the formation of bond pads 316 that are wider than vias 408 increase the possibility that the entirety of the surfaces of the vias 408 with the corresponding bond pads 316 connected when there is a shift between the bond pads 316 and the vias 408 is present. In some cases, the maximum shift distance (e.g. S ₃ ) remains for the entire area of a via 408 with a corresponding bond pad 316 remains connected by the difference between the width W _{4 of} the bond pad 316 and the width of the via 408 specified.

19A through B, 20A through B, and 21 illustrate packages 510 , 520 and 530 each having a first thestructure 300 include those with a second diestructure 400 is connected, according to some embodiments. For each of the packages 510 , 520 and 530 can the first thestructure 300 and the second structure 400 similar to the first thistructure 300 and the second structure 400 be like for 18A to B, and the first die and the second die may be connected in a similar manner as for 18A to B. All such variations in forming packages are contemplated within the scope of this disclosure.

First is facing 19A , the package 510 similar to the package 500 out 18A except that the bond pads 410 the second structure 400 have a width W6 which is smaller than the width W ₄ (see 17th ) of the bond pads 316 the first thestructure 300 . 19B shows a package 510 similar to that out 19A , however, for illustrative purposes, some features are included in 19B are shown with a larger alignment distance than in 19A . In some embodiments, the bond pads 410 have a width W6 between approx. 1.5 µm and approx. 5 µm, although other widths are also possible. In some embodiments, the width W6 of a bond pad may be 410 between approx. 40% and approx. 90% of the width W _{4 of} its associated bond pad 316 lie. In this way, the width W6 of the bond pads 410 be smaller than the width W _{4 of} the bond pads 316 . After bonding the bond pads 410 to the bond pads 316 the bondpads 316 laterally over the bond pads 410 as in 19A shown extend beyond.

19A shows a bond pad 410 for example on a bond pad 316 centered, but in other cases there may be some lateral displacement between a bond pad 410 and a bond pad 316 are present. For example, in 19B a bond pad 410 than by a distance S ₄ against a bond pad 316 shown shifted. The distance S ₄ corresponds to the lateral distance between the center of the bond pad 410 (e.g. at half the width W6) and the middle of the bond pad 316 (e.g. at half the width W ₄ ). In some cases the formation of bond pads 410 that are less wide than bond pads 316 increase the possibility of having the entirety of the upper surfaces of the bond pads 410 with the bond pads 316 connected when there is a shift between the first thestructure 300 and the second structure 400 is present. In some cases, the maximum shift _{distance (e.g. S 4} ) remains for the entire area of a bond pad 410 remains connected by the difference between the width W6 of the bond pad 410 and the width W _{4 of} the bond pad 316 specified. Connect the entire bonding surfaces of the bond pads 410 can reduce the contact resistance between the bond pads 316 and the bond pads 410 and thus the electrical output of the package 510 improve. In this way, undesirable effects due to the displacement caused by the formation of bond pads can be avoided 410 with a smaller width than that of the bond pads 316 be reduced.

Well are facing that 20A up to B and 21 the packages 520 and 530 similar to the package 500 from the 18A to B, except that the FOPI 128 the conductive pads 118 contact and establish an electrical connection with the interconnect structure 108 through the conductive pads 118 produce. Figures AB show a package 520 , in which the bond pads 410 the second structure 400 have a width that is greater than the bond pads 316 the first thestructure 300 , similar to Package 500 out 18A to 18B . 20B shows a package 520 similar to that out 20A , however, for illustrative purposes, some features are included in 20B are shown with a larger alignment distance than in 20A . 21 shows a package 530 , in which the bond pads 410 the second structure 400 have a width that is smaller than the bond pads 316 the first thestructure 300 , similar to the package 510 out 19th . A shift similar to that for that 18A to B, 19A to B and 20A can also be used for the package 530 be available that for 21 is described, but is not shown in a separate figure.

The conductive pads 118 that the FOPI 128 contacts can be formed in a similar manner as the conductive pad 118 that above for 3rd to 4th is shown. For example, the passivation layer 114 be structured, the metal pads 112 and then the conductive pads 118 that are over the metal pads 112 are formed to disclose. The FOPI 128 can be formed in a similar way as the BPVs 128 out 6th to 7th . For example, openings 124 in the dielectric layer 122 be formed except that the openings are the conductive pads 118 instead of the metal pads 112 disclose. The first barrier layer 127 and the conductive material of the BPVs 128 can then in the openings 124 as for 7th be formed as described. As in 20A through B and 21 are some conductive pads 118 possibly not with a BPV 128 connected. In some embodiments, the lateral separation can be between adjacent conductive pads 118 have a distance D6 which is between approx. 2 µm and approx. 100 µm.

In some cases, the bond pads 316 by forming the BPVs 128 separated from the conductive pads 118 be formed as described herein with a smaller separation distance and / or a separation distance D6. In some cases, the FOPI can 128 by forming the BPVs 128 making them the conductive pads 118 contact can be formed with a smaller size and a smaller separation distance. For example, the smaller depth of the openings 124 for contacting the conductive pads 118 allow a more precise photolithographic structuring. In some embodiments, conductive pads 118 formed by BPVs 128 to be contacted, have a smaller width than conductive pads 118 not by BPVs 128 are contacted. For example, the conductive pads 118 that are not probed are formed with a smaller width. In some embodiments, the conductive pads 118 who are made to order by BPVs 128 to be contacted, have a width W2 'which is between approximately 1% and approximately 90% less than the width W2 of the other conductive pads 118 .

20A shows a BPV 128 for example on a conductive pad 118 centered, but in other cases there may be some lateral displacement between a BPV 128 and a conductive pad 118 are present. For example, in 20B a BPV 128 than by a distance S ₅ against a conductive pad 118 shown shifted. The distance S ₅ corresponds to the lateral distance between the center of the BPV 128 (e.g. at half the width W ₃ ) and the center of the conductive pad 118 (e.g. at half the width W2 '). In some cases, the forming of the BPVs allowed 128 in a separate process step from that of the bond pads 316 the formation of the BPVs 128 with a smaller width (e.g. W ₃ ). The formation of BPVs 128 that are narrower in width (e.g., narrower in width than corresponding conductive pads 118 ) can increase the likelihood that the totality of the areas of the BPRs 128 with the conductive pads 118 connected when there is misalignment. In some cases, the maximum displacement distance remains (e.g. S ₅ ) for which the entire area of a BPV 128 remains connected by the difference between the width W _{3 of} the BPV 128 and the width W2 of the corresponding conductive pad 118 specified. Connect the entire bonding surfaces of the BPVs 128 can reduce the contact resistance between the BPVs 128 and the conductive pads 118 and thus the electrical output of the package 520 improve. In this way, the size or spacing of some conductive features of an interconnected package can be reduced without increasing the risk of undesirable effects from displacement or other process imperfections.

The 22nd to 26th According to some embodiments, illustrate intermediate steps in the formation of a package structure 1000 who have favourited a Package 600 includes. 22nd illustrates a first thistructure 300 and a second thistructure 400 in a package 600 were connected. The first structure 300 and a second thistructure 400 can be similar to the first thestructure 300 or the second thestructure 400 be that previously for the 17th to 21 have been described. The package 600 can be similar to the packages 500 , 510 , 520 or 530 be that previously for the 18A to 21 but with external connectors 420 not on the second thistructure 400 are formed. As in 22nd shown includes the package 600 Contact pads 602 that is on the second thestructure 400 are what electrical connections are formed with the package 600 allowed.

22nd also illustrates a support substrate 721 with an adhesive layer 723 and a polymer layer 725 over the adhesive layer 723 . In some embodiments, the carrier substrate comprises 721 for example silicon-based materials such as glass or silicon oxide, or other materials such as aluminum oxide, combinations of any of these materials, or the like. The carrier substrate 721 may be planar for attachment of devices such as the package 600 to record. The adhesive layer 723 is on the carrier substrate 721 placed in order to ensure the adhesion of overlying structures (e.g. the polymer layer 725 ) to help. In some embodiments, the adhesive layer 723 a light-to-heat converting (LTHC) material or an ultraviolet adhesive which loses its adhesive properties when exposed to ultraviolet light. Other types of adhesives such as pressure sensitive adhesives, radiation curable adhesives, epoxy adhesives, combinations thereof, or the like can also be used. The adhesive layer 723 can be in semi-liquid or gel form, which is easily deformable under pressure, on the carrier substrate 721 be applied.

The polymer layer 725 will be over the adhesive layer 723 placed and used to protect the package 600 provide. In some embodiments, the polymer layer can 725 Polybenzoxazole (PBO), however any suitable material such as polyimide or a polyimide derivative may alternatively be used. The polymer layer 725 For example, it can be placed to a thickness of between about 2 µm and about 15 µm, such as about 5 µm, using a spin coating process, but any suitable method and thickness can be used instead.

In some embodiments, vias such as dielectric vias (TDVs) 727 over the polymer layer 725 educated. In some embodiments, a seed layer (not shown) is first over the polymer layer 725 educated. The seed layer is a thin layer of conductive material that aids in the formation of a thicker layer during subsequent processing steps. In some embodiments, the seed layer may include a layer of titanium that is about 500 Å thick, followed by a layer of copper that is about 3,000 Å thick. The seed layer can be created using processes such as sputtering, evaporation, or PECVD processes, depending on the materials desired. Once the seed layer is formed, photoresist (not shown) can be formed over the seed layer and patterned. The TDVs 727 are then formed with the patterned photoresist. In some embodiments, the include TDVs 727 one or more conductive materials such as copper, tungsten, other conductive metals, or the like, and can be formed, for example, by electroplating, electroless plating, or the like. In some embodiments, an electroplating process is used in which the seed layer and photoresist are immersed or submerged in an electroplating solution. When the TDVs 727 formed using the photoresist and the seed layer, the photoresist can be removed using a suitable removal process. In some embodiments, a plasma ash process can be used to remove the photoresist, which can increase the temperature of the photoresist until the photoresist undergoes thermal decomposition and can be removed. Any other suitable process, such as wet stripping, can alternatively be used. Removal of the photoresist can expose the underlying portions of the seed layer. When the TDVs 727 exposed portions of the seed layer are then removed, for example using a wet or dry etch process. The TDVs 727 can be formed with a height of between approx. 180 µm and approx. 200 µm, with a critical dimension of approx. 190 µm and a distance of approx. 300 µm.

After making the TDVs 727 becomes the package 600 on the polymer layer 725 attached. In some embodiments, the package 600 z. B. be placed using a pick-and-place process. Any suitable method of placing the package 600 however, it can be used.

23 illustrates an encapsulation of the package 600 and the TDVs 727 with an encapsulation material 729 . The encapsulation material 729 may be a molding compound such as a resin, polyimide, PPS, PEEK, PES, a heat-resistant crystal resin, combinations thereof, or the like. 24 illustrates a thinning of the encapsulation material 729 to the TDVs 727 and the Package 600 to disclose. The thinning can e.g. Be performed using a CMP process or some other process. The thinning of the encapsulation material 729 can use the contact pads 602 of the package 600 disclose.

25th illustrates formation of a redistribution structure 800 with one or more layers over the encapsulation material 729 . In some embodiments, the redistribution structure 800 be formed by initially a first redistribution passivation layer 801 over the encapsulation material 729 is formed. In some embodiments, the first redistribution passivation layer 801 Polybenzoxazole (PBO), however any suitable material such as polyimide or a polyimide derivative such as a low temperature cured polyimide may alternatively be used. The first redistribution passivation layer 801 For example, it can be placed to a thickness of between about 5 µm and about 17 µm, such as about 7 µm, using a spin coating process, but any suitable method and thickness can be used instead.

When the first redistribution passivation layer 801 the first redistribution vias 803 through the first redistribution passivation layer 801 be formed to make electrical connections with the package 600 and the TDVs 727 to undertake. For example, the first redistribution vias 803 be formed to make electrical contact with the contact pads 602 to manufacture. In some embodiments, the first redistribution vias 803 be formed using a damascene process, a dual damascene process, or some other process. After forming the first redistribution vias 803 becomes a first redistribution layer 805 over and in electrical communication with the first redistribution vias 803 educated. In some embodiments, the first redistribution layer 805 can be formed by initially forming a titanium-copper alloy seed layer (not shown) by a suitable forming process such as CVD or sputtering. A photoresist (i.e., not shown) can then be formed to cover the seed layer and the photoresist can then be patterned to expose the portions of the seed layer that are where the first redistribution layer is located 805 should be placed.

Once the photoresist has been formed and patterned, a conductive material such as copper can be formed on the seed layer by a deposition process such as plating. The conductive material can be formed to have a thickness between about 1 µm and about 10 µm, such as about 4 µm. However, while the material and methods discussed are suitable for forming the conductive material, these materials are exemplary only. Any other suitable materials, such as AlCu or Au, and any other suitable processes of formation, such as CVD or PVD, can alternatively be used to form the first redistribution layer 805 to build.

After forming the first redistribution layer 805 may have a second redistribution passivation layer 807 be formed and patterned to help create the first redistribution layer 805 to isolate. In some embodiments, the second redistribution passivation layer 807 similar to the first redistribution passivation layer 801 such as a positive tone PBO, or may be different from the first redistribution passivation layer 801 such as a negative tone material such as a polyimide cured at low temperature. The second redistribution passivation layer 807 can be applied to a thickness of approx. 7 µm. After the placement, the redistribution passivation layer 807 be structured to make openings such. B. using a photolithographic masking and etching process or if the material of the second redistribution passivation layer 807 is photosensitive by exposing and developing the material of the second redistribution passivation layer 807 , to build. Any suitable material and method of structuring can be used.

After the second redistribution passivation layer 807 has been structured, a second redistribution layer can be used 809 be formed to extend through the openings formed in the second redistribution passivation layer 807 and an electrical connection to the first redistribution layer 805 to manufacture. In some embodiments, the second redistribution layer 809 can be formed using materials and processes similar to the first redistribution layer 805 are. For example, a seed layer can be applied and covered by a patterned photoresist, a conductive material such as copper can be applied to the seed layer, the patterned photoresist can be removed, and the seed layer can be used using the conductive material as a mask to be etched. In some embodiments, the second redistribution layer is 809 etched to a thickness of approx. 4 µm. However, any suitable material or process of manufacture can be used.

After forming the second redistribution layer 809 becomes a third redistribution passivation layer 811 over the second Redistribution layer 809 applied to help the second redistribution layer 809 to isolate and protect. In some embodiments, the third redistribution passivation layer 811 be formed from similar materials and in a similar manner as the second redistribution passivation layer 807 with a thickness of approx. 7 µm. For example, the third redistribution passivation layer 811 may be formed from PBO or a low temperature cured polyimide as above with respect to the second redistribution passivation layer 1007 has been applied and structured as described. However, any suitable material or process of manufacture can be used.

After the third redistribution passivation layer 811 has been structured, a third layer of redistribution can be implemented 813 be formed to extend through the openings formed in the third redistribution passivation layer 811 and an electrical connection to the second redistribution layer 809 to manufacture. In some embodiments, the third redistribution layer 813 can be formed using materials and processes similar to the first redistribution layer 805 are. For example, a seed layer can be applied and covered by a patterned photoresist, a conductive material such as copper can be applied to the seed layer, the patterned photoresist can be removed, and the seed layer can be used using the conductive material as a mask to be etched. In some embodiments, the third is redistribution layer 813 etched to a thickness of 5 µm. However, any suitable material or process of manufacture can be used.

After forming the third redistribution layer 813 may have a fourth redistribution passivation layer 815 above the third redistribution layer 813 be formed to help the third redistribution layer 813 to isolate and protect. In some embodiments, the fourth redistribution passivation layer 815 be formed from similar materials and in a similar manner as the second redistribution passivation layer 807 . For example, the fourth redistribution passivation layer 815 may be formed from PBO or a low temperature cured polyimide as above with respect to the second redistribution passivation layer 807 has been applied and structured as described. In some embodiments, the fourth redistribution passivation layer is 815 etched to a thickness of approx. 8 µm. However, any suitable material or process of manufacture can be used.

In other embodiments, the redistribution vias and redistribution layers may be of the redistribution structure 800 can be formed using a damascene process, such as a double damascene process. For example, a redistributed passivation layer can be placed over the encapsulation agent 729 be educated. The first redistribution passivation layer is then patterned using one or more photolithographic steps to form both openings for vias and openings for conductive lines within the first redistribution passivation layer. A conductive material may be formed in the via openings and the conductive line openings to form the first redistribution vias and the first redistribution layer. Further redistribution passivation layers can be formed over the first redistribution passivation layer, and further sets of redistribution vias and conductive lines can be formed in the further redistribution passivation layers, as described for the first redistribution passivation layer, and thus the redistribution structure 800 form. These or other techniques can be used in the redistribution structure 800 to build.

25th further illustrates a formation of sub-bump metallizations 819 and third external connections 817 to make electrical contact with the third redistribution layer 813 to manufacture. In some embodiments, the sub-bump metallizations 819 each represent three layers of conductive materials, such as a layer of titanium, a layer of copper and a layer of nickel. However, one of ordinary skill in the art will recognize that there are numerous suitable arrangements of materials and layers, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper, or an arrangement of copper / nickel / Gold, which is responsible for the formation of the sub-bump metallizations 819 suitable. Any suitable materials or layers of material used for the sub-bump metallization 819 are entirely intended to be included within the scope of the embodiments.

In some embodiments, the sub-bump metallizations are 819 by forming each layer over the third redistribution layer 813 and along the interior of the openings through the fourth redistribution passivation layer 815 generated. The formation of each layer can be done using a plating process, such as electrochemical plating, but other formation processes, such as sputtering, evaporation, or a PECVD process, depending on the desired materials can be used. The sub-bump metallization 819 can be formed to have a thickness between about 0.7 µm and about 10 µm, such as about 5 µm.

In some embodiments, the third external connectors 817 on the underbump metallization 819 and a ball grid array (BGA) comprising a eutectic material such as solder, but any suitable material can be used. In some embodiments, the third external connector 817 Solder balls can be the third external connector 817 be formed using a ball drop method, such as a direct ball drop method. In another embodiment, the solder balls can be formed by initially forming a layer of tin by any suitable method such as evaporation, electroplating, printing, solder transfer and then performing reflow to shape the material into the desired bump shape. When the third external connector 817 a test can be run to ensure that the structure is suitable for further processing.

26th illustrates bonding of a device package 900 with the TDVs 727 through the polymer layer 725 . Before bonding the device package 900 become the carrier substrate 721 and the adhesive layer 723 from the polymer layer 725 away. The polymer layer 725 is also structured around the TDVs 727 to disclose. In some embodiments, the polymer layer can 725 z. B. can be structured using a laser drilling process. In one such process, a protective layer such as a light-to-heat conversion layer (LTHC) or a Hogomax layer (not separately illustrated) is first placed over the polymer layer 725 deposited. After protection, a laser is applied to the sections of the polymer layer 725 directed to be removed to the underlying TDVs 727 to expose. During the laser drilling process, the drilling energy can be in a range from 0.1 mJ to approx. 30 mJ, and a drilling angle of approx. 0 degrees (perpendicular to the polymer layer 725 ) up to approx. 85 degrees to the right angle to the polymer layer 725 lie. In some embodiments, the pattern can be formed to provide openings over the TDVs 727 with a width between about 100 µm and about 300 µm, such as about 200 µm.

In another embodiment, the polymer layer 725 by initially applying a photoresist (not individually illustrated) to the polymer layer 725 and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) to initiate a chemical reaction, patterned, thereby inducing a physical change in the portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to take advantage of the physical changes and selectively remove either the exposed portion of the photoresist or the unexposed portion of the photoresist, depending on the structure desired, and the underlying exposed portion of the polymer layer 725 is z. B. removed with a dry etching process. Any other suitable method of structuring the polymer layer 725 however, it can be used.

In some embodiments, the device package comprises 900 a substrate 902 and one or more stacked dies 910 (e.g. 910A and 910B) that come with the substrate 902 are coupled. Even if just a set of stacked dies 910A / 910B As illustrated, in other embodiments, multiple stacked dies 910 (each of which has one or more stacked dies) arranged side by side and with a same face of the substrate 902 be coupled. The substrate 902 can consist of a semiconductor material such as silicon, germanium, diamond or the like. In some embodiments, interconnect materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like can also be used. Furthermore, the substrate 902 be a silicon-on-insulator (SOI) substrate. In general, an SOI substrate comprises a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. The substrate 902 is based in an alternative embodiment on an insulation core such as a glass fiber reinforced resin core. An exemplary core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide triazine resin (BT resin) or, alternatively, other circuit board (PCB) materials or films. Build-up films such as Ajinomoto Build-Up Film (ABF) or other laminates can be used for the substrate 902 be used.

The substrate 902 may include active and passive devices (not shown). A wide variety of devices, such as transistors, capacitors, resistors, combinations thereof, and the like, can be used to meet the structural and functional design requirements for the device package 900 to create. The devices can be formed using any number of methods.

The substrate 902 can also be metallization layers or conductive vias (not shown). The metallization layers can be formed over the active and passive devices and interconnect the various devices to form functional circuitry. The metallization layers can be formed from alternating layers of dielectric (e.g., low-k dielectric) and conductive material (e.g., copper), with vias connecting the layers of conductive material and being formed by any suitable process ( such as deposition, damascene, dual damascene or the like). In some embodiments, the substrate is 902 essentially free of active and passive devices.

The substrate 902 can bond pads 904 on a first side of the substrate 902 to get the stacked dies 910 to pair, and bond pads 906 on a second side of the substrate 902 , the second side being the first side of the substrate 902 opposite to the external connections 901 to couple, exhibit. In some embodiments, the bond pads 904 and 906 by forming cutouts (not shown) in layers of dielectric (not shown) on the first and second sides of the substrate 902 educated. The cutouts can be made to accommodate the bond pads 904 and 906 to be embedded in the dielectric layers. In other embodiments, the cutouts are omitted because the bond pads 904 and 906 may be formed on the dielectric layer. In some embodiments, the bond pads include 904 and 906 a thin seed layer (not shown) of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of the bond pads 904 and 906 can be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In one embodiment, the conductive material is the bond pads 904 and 906 Copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In one embodiment, the bond pads are 904 and bond pads 906 UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers exist, such as an arrangement of chromium / chromium-copper alloy / copper / gold, an arrangement of titanium / titanium tungsten / copper or an arrangement of copper / nickel / gold can be used to form the bond pads 904 and 906 be used. Any suitable materials or layers of material used for the bond pads 904 and 906 are fully intended to be included in the scope of the current application. In some embodiments, the conductive vias extend through the substrate 902 and couple at least one of the bond pads 904 with at least one of the bond pads 906 .

In the illustrated embodiment, the stacked are dies 910 with the substrate 902 by wire connections 912 coupled, but other connections such as conductive bumps can be used. In one embodiment, the stacked are dies 910 stacked memory this. For example, the stacked dies 910 Memories such as low performance double data rate memory modules (LP-DDR memory modules) such as LPDDR1, LPDDR2, LPDDR3, LPDDR4 or the like memory modules.

The stacked dies 910 and the wire connections 912 can with a molding material 914 be encapsulated. The molding material 914 can be stacked on the dies 910 and the wire connections 912 be formed for example by die casting. In some embodiments, the molding material is 914 a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A hardening process can be carried out to the molding material 914 to harden. The hardening process can be a thermal hardening, a UV hardening, the like or a combination thereof.

In some embodiments the stacked dies are 910 and the wire connections 912 in the molding material 914 buried and after the molding material has hardened 914 For example, a planarization step such as grinding is carried out to remove excess portions of the molding material 914 and a substantially flat surface for the device package 900 provide.

In some embodiments, external connections can be used 901 be formed to provide an external connection between the device package 900 and Z. B. the TDVs 727 provide. The external connections 901 may be contact bumps such as microbumps or controller collapse chip connection bumps (C4 bumps) and may comprise a material such as tin or other suitable materials such as silver or copper. In some embodiments, the external connections 901 Tin solder bumps can make the external connections 901 by initially forming a layer of tin by any suitable method such as evaporation, electroplating, printing, solder transfer, ball replacement or the like to a thickness of e.g. B. about 100 microns are formed. When a layer of tin has been formed on the structure, reflow is carried out to shape the material into the desired bump shape.

When the external connections 901 are formed, the external connections 901 at the TDVs 727 aligned and placed on top, and a connection is made. For example, in some embodiments that require external connections 901 Solder bumps are the bonding process that involve a reflow process, which increases the temperature of the external connections 901 is increased to a point where the external connections 901 liquefy and flow, making them the device package 900 to the TDVs 727 bond when the external connections 901 harden again. An encapsulation material 903 can be formed around the device package 900 to encapsulate and protect. The encapsulation material 903 can be between the polymer layer 725 and the device package 900 and may represent an underfill in some embodiments. In this way a package structure 1000 are formed.

Embodiments can achieve advantages. By forming the bond pad vias (BPVs) and bond pads of a die in two different processing steps, the size and / or separation (e.g., spacing) of features such as metal lines, conductive pads, the BPVs, and / or the bond pads can be reduced. For example, by forming the BPVs in a first photolithography and etching step, closer to other features such as conductive pads (e.g., aluminum pads) can be formed without an increased likelihood of process defects such as electrical shorts. In this way, the size of a die or a package comprising a die can be reduced. Furthermore, the routing density of the die or the package can be increased. In some cases, a first bond pad of a first die can be formed such that its entire bonding surface is connected to the corresponding second bond pad of a second die, even if a displacement occurs during the bonding process. For example, the first bond pad of the first die can have a width that is smaller than the second bond pad, so that the entire bonding area of the first bond pad remains in contact with the second bond pad, even if there is a certain displacement between the first bond pad and the second bond pad . In this manner, a package including connected dies can have improved contact resistance between connected pads when displacement occurs.

In one embodiment, a device comprises an interconnect structure over a semiconductor substrate, the interconnect structure having first conductive pads, a first dielectric layer over the interconnect structure, bond pad vias in the first dielectric layer, each bond pad vias of the bond pad vias having a first barrier layer extending along sidewalls of the first dielectric layer extending over a first conductive pad of the first conductive pads, and comprising a first conductive material over the first barrier layer, wherein a top surface of the first conductive material and a top surface of the first barrier layer are coplanar, a second dielectric layer over the first dielectric layer, and first bond pads within the second dielectric layer, with each first bond pad having a second barrier layer extending along sidewalls of the second dielectric layer and on top of the first lei The conductive material and the first barrier layer of a first bond pad via of the bond pad vias, the second barrier layer completely covering the top surface of the first conductive material and the top surface of the first bond pad via, and comprising a second conductive material over the second barrier layer. In one embodiment, the device further comprises a third dielectric layer, which extends over sidewalls of the first dielectric layer, the interconnect structure and the semiconductor substrate. In one embodiment, the second dielectric layer extends over the third dielectric layer and the first dielectric layer. In one embodiment, the device further comprises an aluminum pad within the first dielectric layer, wherein the aluminum pad contacts a first conductive pad of the first conductive pads. In one embodiment, a bond pad via contacts the aluminum pad. In one embodiment, the device further comprises a passivation layer that extends over the first conductive pads, wherein the bond pad vias extend through the passivation layer. In one embodiment, adjoining first conductive pads are laterally separated by a distance which is between 2 μm and 20 μm. In one embodiment, the second barrier layer comprises titanium, titanium nitride, tantalum or tantalum nitride.

In one embodiment, a package comprises a first die having a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends over the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends over each first bond pad via between a first bond pad and the first bond pad via, and a second die that includes one or more second bond pads, wherein a second bond pad is connected to a first bond pad of the first die. In one embodiment, the first die comprises a first bonding layer, wherein the first bond pad is arranged within the first bonding layer, the second die comprises a second bonding layer, wherein the second bond pad is arranged within the second bonding layer, and the first bonding layer is with the second bonding layer connected. In one embodiment, a width of the first bond pad is between 95% and 150% of a width of the second bond pad. In one embodiment, a width of the second bond pad is between 95% and 150% of a width of the first bond pad. In one embodiment, the second die further comprises a via, the via being connected to the first bond pad of the first die. In one embodiment, the package further comprises a conductive pad on the first metallization layer, wherein the conductive pad comprises a different conductive material than the one or more first bond pad vias. In one embodiment, the conductive pad is laterally separated from an adjacent first bond pad via by a distance which is between 2 μm and 100 μm.

In one embodiment, a method includes forming an interconnect structure on a top surface of a semiconductor substrate, the interconnect structure including a first conductive pad, forming a first dielectric layer over the interconnect structure, etching the first dielectric layer to form a first opening that exposes the first conductive pad, Depositing a first barrier layer within the first opening in the first dielectric layer, depositing a first conductive material within the first opening and on the first barrier layer, forming a second dielectric layer over the first dielectric layer, etching the second dielectric layer to form a second opening that the first exposing conductive material, depositing a second barrier layer within the second opening in the second dielectric layer, depositing a second conductive material within the second opening and on the second Barrier layer, and bonding a semiconductor die to the second dielectric layer, the semiconductor die comprising a bonding layer and a bond pad, wherein the bond connects the bonding layer of the semiconductor die to the second dielectric layer and bonds the bond pad of the semiconductor die to the second conductive material. In one embodiment, the method comprises, after depositing the first conductive material, forming a sacrificial layer over the first dielectric layer and the first conductive material, attaching the sacrificial layer to a first carrier structure, thinning the semiconductor substrate and removing the first carrier structure and the sacrificial layer, wherein the second dielectric layer is formed over the first dielectric layer after the sacrificial layer is removed. In one embodiment, the method includes forming a passivation layer over the interconnect structure and forming a conductive pad over the passivation layer, wherein the first dielectric layer is formed over the conductive pad and the passivation layer. In one embodiment, the bond pad of the semiconductor die has a lateral width that is smaller than the second conductive material. In one embodiment, the bond pad of the semiconductor die has a lateral width that is greater than the second conductive material.

The above describes features of several embodiments that will enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or changing other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also understand that such respective constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions, and alterations therein without departing from the spirit and scope of this disclosure.

QUOTES INCLUDED IN THE DESCRIPTION

This list of the documents listed by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent literature cited

• US 62/893971 [0001]

Claims (20)

Apparatus comprising: an interconnect structure over a semiconductor substrate, the interconnect structure including a plurality of first conductive pads; a first dielectric layer over the interconnect structure; multiple bond pad vias within the first dielectric layer, each bond pad vias of the multiple bond pad vias having: a first barrier layer extending along sidewalls of the first dielectric layer and over a first conductive pad of the plurality of first conductive pads; and a first conductive material over the first barrier layer, wherein a top surface of the first conductive material and a top surface of the first barrier layer are coplanar; a second dielectric layer over the first dielectric layer; and a plurality of first bond pads within the second dielectric layer, wherein each first bond pad of the plurality of bond pads comprises: a second barrier layer extending along sidewalls of the second dielectric layer and on the first conductive material and the first barrier layer of a first bond pad via of the plurality of bond pad vias, the second barrier layer completely covering the top surface of the first conductive material and the top surface of the first bond pad via , and a second conductive material over the second barrier layer. Device off Claim 1 , further comprising a third dielectric layer extending over sidewalls of the first dielectric layer, the interconnect structure and the semiconductor substrate. The device of claim 2, wherein the second dielectric layer extends over the third dielectric layer and the first dielectric layer. The device of any preceding claim, further comprising an aluminum pad within the first dielectric layer, the aluminum pad contacting a first conductive pad of the plurality of first conductive pads. Device off Claim 4 , wherein one bond pad vias of the plurality of bond pad vias contacts the aluminum pad. The device of claim 1, further comprising a passivation layer extending over the plurality of first conductive pads, the plurality of bond pad vias extending through the passivation layer. The device of one of the preceding claims, wherein adjacent first conductive pads of the plurality of first conductive pads are laterally separated by a distance which is between 2 µm and 20 µm. Device according to one of the preceding claims, wherein the second barrier layer comprises titanium, titanium nitride, tantalum or tantalum nitride. Package comprising: a first die comprising: a first metallization layer; one or more first bond pad vias on the first metallization layer, a first barrier layer extending over the first metallization layer between each first bond pad vias and the first metallization layer; and one or more first bond pads on the one or more first bond pad vias, a second barrier layer extending over each first bond pad vias between a first bond pad and the first bond pad vias; and a second die comprising one or more second bond pads, wherein a second bond pad is connected to a first bond pad of the first die. Package from Claim 9 , wherein the first die comprises a first bonding layer, wherein the first bond pad is arranged within the first bonding layer, wherein the second die comprises a second bonding layer, wherein the second bond pad is arranged within the second bonding layer, and wherein the first bonding layer is connected to the second bonding layer is. Package from Claim 9 or 10 , wherein a width of the first bond pad is between 95% and 150% of a width of the second bond pad. Package from one of the Claims 9 to 11 , wherein a width of the second bond pad is between 95% and 150% of a width of the first bond pad. Package from one of the Claims 9 to 12th , wherein the second die further comprises a via, wherein the via is connected to the first bond pad of the first die. Package from one of the Claims 9 to 13th , further comprising a conductive pad on the first metallization layer, wherein the conductive pad comprises a different conductive material than the one or more first bond pad vias. Package from Claim 14 , wherein the conductive pad is laterally separated from an adjacent first bond pad via by a distance which is between 2 μm and 100 μm. Method comprising: Forming an interconnect structure on a top surface of a semiconductor substrate, the interconnect structure comprising a first conductive pad; Forming a first dielectric layer over the interconnect structure; Etching the first dielectric layer to form a first opening exposing the first conductive pad; Depositing a first barrier layer within the first opening in the first dielectric layer; Depositing a first conductive material within the first opening and on the first barrier layer; Forming a second dielectric layer over the first dielectric layer; Etching the second dielectric layer to form a second opening exposing the first conductive material; Depositing a second barrier layer within the second opening in the second dielectric layer; Depositing a second conductive material within the second opening and on the second barrier layer; and Bonding a semiconductor die to the second dielectric layer, the semiconductor die comprising a bonding layer and a bond pad, wherein the bond connects the bonding layer of the semiconductor die to the second dielectric layer and bonds the bond pad of the semiconductor die to the second conductive material. Procedure according to Claim 16 further comprising: after depositing the first conductive material, forming a sacrificial layer over the first dielectric layer and the first conductive material; Attaching the sacrificial layer to a first support structure; Thinning the semiconductor substrate; and removing the first support structure and the sacrificial layer, wherein the second dielectric layer is formed over the first dielectric layer, after the sacrificial layer is removed. Procedure according to Claim 16 or 17th , further comprising: forming a passivation layer over the interconnect structure; and forming a conductive pad over the passivation layer, wherein the first dielectric layer is formed over the conductive pad and the passivation layer. Method according to one of the Claims 16 to 18th wherein the bond pad of the semiconductor die has a lateral width which is less than the second conductive material. Method according to one of the Claims 16 to 19th wherein the bond pad of the semiconductor die has a lateral width that is greater than the second conductive material.

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