DE102021120389A1 - SEMICONDUCTOR PACKAGE AND METHOD TO MAKE THESE - Google Patents

Abstract

Packaged semiconductor devices comprising high thermal conductivity molding material and methods of forming the same are disclosed. In one embodiment, a semiconductor device includes a first redistribution structure; a first die overlying and electrically coupled to the first redistribution structure; a first via located over and electrically coupled to the first redistribution structure; an insulating layer extending along the first redistribution structure, the first die, and the first via; and an encapsulation material over the insulating layer, the encapsulation material enclosing portions of the first via and the first die, the encapsulation material including conductive fillers in a concentration ranging from 70% to about 95% by volume.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefit of the provisional applications filed on March 26, 2021 U.S. Application No. 63/166,350 entitled "Semiconductor Package Structure and Manufacturing Method Thereof," which is hereby incorporated by reference into this application.

BACKGROUND

The semiconductor industry has grown rapidly with continued improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, or the like). Much of the improvement in integration density comes from iteratively reducing the minimum element size, allowing more components to be integrated in a given area. As the need for shrinking electronic devices has increased, so has the need for smaller and more creative packaging techniques for semiconductor dies. An example of such package systems is “package-on-package” (PoP) technology. In a PoP device, an upper semiconductor package is stacked on a lower semiconductor package to provide a high level of integration and component density. The PoP technology generally enables the production of the semiconductor devices with enhanced functions and small footprints on a printed circuit board (PCB).

character list

• Aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for the sake of clarity of explanation.
• 1 until 25 12 illustrate cross-sectional views of intermediate steps during processes of forming package components, according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples for practicing various elements of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, only examples and should not be construed as limiting. For example, forming a first member or a second member in the following description may include embodiments where the first and second members are formed in face-to-face contact, and may also include embodiments where other members are between the first and second members can be formed so that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and/or letters of the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or devices discussed.

Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like may be used herein for ease of description to indicate the relationship of one element or elements to one or more other element(s). ) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in a different orientation) and the spatially relative terms used herein shall be construed accordingly.

Various embodiments provide packaged semiconductor devices with improved heat dissipation and methods of forming the same. The method includes forming an interconnect structure, forming a via over the interconnect structure, and attaching a semiconductor die to the interconnect structure. An insulating layer is formed over the interconnect structure, via and semiconductor die, and a molding material is formed over the insulating layer. The insulating layer may be electrically insulating and may isolate the via and any exposed conductive elements of the interconnect structure and semiconductor die from each other. As a result, electrically conductive materials can be used for the mold material. The insulating layer can also reduce the stress between the molding material and the underlying structures, allowing materials with higher coefficients of thermal expansion to be used for the molding material. The greater flexibility in choosing materials for the mold material allows the use of materials with higher thermal conductivities for the mold material. This in turn improves warmth dissipation, improves the quality of the devices, increases the device performance and reduces the defects of the devices.

1 Figure 12 illustrates a cross-sectional view of an integrated circuit die 50. The integrated circuit die 50 is further processed into an integrated circuit package. The integrated circuit die 50 can be a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SoC), an application processor (AP), a microcontroller, an application-specific integrated circuit die (ASIC) or the like), a memory die (e.g., a dynamic random access memory die (DRAM die), a static random access memory die (SRAM die), a high bandwidth memory die (HBM die) or the like), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor (e.g., a microelectromechanical system (MEMS) die), a signal processing (e.g., a digital signal processing (DSP) die) die) or the like), a front-end die (e.g., an analog front-end die (AFE die)), the like, or a combination thereof.

The integrated circuit die 50 can be formed in a wafer, which can include various device regions that are singulated in subsequent steps to form multiple integrated circuit dies. The integrated circuit die 50 can be processed into integrated circuits according to applicable manufacturing processes. The integrated circuit die 50 includes, for example, a semiconductor substrate 52, such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. Semiconductor substrate 52 may include other semiconductor materials, such as germanium; a compound semiconductor such as silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and/or indium antimonide; an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates can also be used. The semiconductor substrate 52 has an active area (e.g. the in 1 surface facing up), sometimes referred to as a front surface, and an inactive surface (e.g., the one in 1 down-facing surface), sometimes referred to as a back surface.

Devices 54 (represented by a transistor) may be formed on the active area of the semiconductor substrate 52 . Devices 54 may be active devices (e.g., transistors, diodes, or the like), capacitors, resistors, or the like. An interlayer dielectric (ILD) 56 is located over the active area of the semiconductor substrate 52. The ILD 56 encloses the devices 54 and may cover them. The ILD 56 may include one or more dielectric layers formed from materials such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like.

Conductive connectors 58 extend through ILD 56 to electrically and physically connect devices 54 . For example, if the devices 54 are transistors, the conductive plugs 58 may connect the gate and source/drain regions of the transistors together. The conductive plugs 58 may be formed from tungsten, cobalt, nickel, copper, silver, gold, aluminum, or similar materials, or combinations thereof. An interconnect structure 60 is located over the ILD 56 and conductive plugs 58. The interconnect structure 60 connects the devices 54 together to form an integrated circuit. The interconnect structure 60 can be formed by metallization structures in dielectric layers on the ILD 56, for example. The metallization structures include metal lines and vias formed in one or more low-K dielectric layers. The metallization structures of the interconnect structure 60 are electrically connected to the devices 54 via the conductive plugs 58 .

The integrated circuit die 50 also includes pads 62, such as aluminum pads, to which external connections are made. Pads 62 are on the active side of integrated circuit die 50, such as in and/or on interconnect structure 60. One or more passivation films 64 are on integrated circuit die 50, such as on portions of interconnect structure 60 and of pads 62. Apertures extend through passivation films 64 to pads 62. Connectors 66, such as conductive pillars (formed, for example, of a metal such as copper), extend through the apertures in passivation films 64 and are physically and electrically connected connected to the respective pads 62. Die connectors 66 may be formed, for example, by plating or the like. Die connectors 66 electrically couple the respective integrated circuits of integrated circuit die 50.

Optionally, solder regions (e.g., solder balls or solder bumps) may be disposed on the pads 62. The solder balls can be used to run chip probe (CP) tests on the integrated th circuit that 50 are used. A CP check of the integrated circuit die 50 can be performed to determine whether the integrated circuit die 50 is a known good die (KGD). Thus, only the integrated circuit dies 50 that are KGDs are further processed and packaged, while the dies that fail the CP test are not packaged. After testing, the soldering regions can be removed in further processing steps.

A dielectric layer 68 may (or may not) be on the active side of integrated circuit die 50, such as on passivation films 64 and dieconnectors 66. Dielectric layer 68 laterally encapsulates dieconnectors 66, and dielectric layer 68 terminates laterally with each integrated circuit Circuit die 50. First, the dielectric layer 68 may obscure the die connectors 66 such that the top surface of the dielectric layer 68 overlies the top surfaces of the die connectors 66. FIG. In some embodiments where solder regions are disposed on the die connectors 66, the dielectric layer 68 may also obscure the solder regions. Alternatively, the solder regions may be removed prior to forming the dielectric layer 68.

The dielectric layer 68 may be a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) or the like, a nitride such as silicon nitride or the like, an oxide such as silicon oxide, phosphorus silicate glass (PSG), borosilicate glass (BSG), boron doped phosphorus silicate glass (BPSG) or the like or a combination thereof. The dielectric layer 68 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), or the like. In some embodiments, die connectors 66 are exposed through dielectric layer 68 during formation of integrated circuit die 50 . In some embodiments, die connectors 66 remain hidden and are exposed during a subsequent process of packaging integrated circuit die 50 . By exposing the die connectors 66, any soldering regions present on the die connectors 66 can be removed.

In some embodiments, integrated circuit die 50 is a stacked device that includes multiple semiconductor substrates 52 . Integrated circuit die 50 may be, for example, a memory device such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module, or the like that includes multiple memory dies. In such embodiments, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by substrate vias (TSVs) (also referred to as silicon vias). Each of the semiconductor substrates 52 may (but need not) have an interconnect structure 60 .

the 2 until 25 12 illustrate cross-sectional views of fabricating an integrated circuit package with improved heat dissipation, according to some embodiments. In 2 A support substrate 102 is seen and a release layer 104 is formed on the support substrate 102 . The support substrate 102 may be a glass support substrate, a ceramic support substrate, or the like. The carrier substrate 102 can be a wafer, so that a plurality of packages can be formed on the carrier substrate 102 at the same time. In some embodiments, one or more of the integrated circuit dies 50 may be packaged to form an integrated circuit package in each of multiple package regions on the wafer. The finished integrated circuit packages can also be referred to as integrated fanout packages (InFO packages).

The release layer 104 may be formed from a polymer-based material that may be removed along with the support substrate 102 from overlying structures formed in subsequent steps. In some embodiments, release liner 104 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat conversion (LTHC) release coating. In other embodiments, release liner 104 may be an ultraviolet (UV) adhesive that loses its adhesive properties when exposed to UV light. The release liner 104 may be applied and cured as a liquid, may be a laminate film that is laminated to the support substrate 102, or the like. The top surface of release layer 104 can be planarized and have a high degree of planarity.

In 3 a front side redistribution structure 124 is formed on the release layer 104 . Front side redistribution structure 124 includes dielectric layers 106, 110, 114, and 118 and metallization structures 108, 112, 116, and 120 (including conductive pads 120A and 120B). The metallization structures 108, 112, 116 and 120 may also be referred to as redistribution layers or redistribution lines. In the 3 Illustrated front side redistribution structure 124 includes four layers of dielectric and four layers of metallization structures. More or fewer dielectric layers and metallization structures may be formed in the front side redistribution structure 124 . If less dielectric layers and metallization structures are to be formed, steps and the process discussed below may be omitted. If more dielectric layers and metallization structures are to be formed, the steps and processes discussed below may be repeated.

The front side redistribution structure 124 may be formed by depositing the dielectric layer 106 onto the isolation layer 104 . In some embodiments, the dielectric layer 106 may be formed from a photosensitive material such as PBO, polyimide, BCB, or the like that may be patterned with a lithography mask. The dielectric layer 106 may be formed by spin coating, lamination, CVD, the like, or a combination thereof.

The metallization structure 108 is formed on the dielectric layer 106 . The metallization structure 108 may be formed by forming a seed layer (not separately illustrated) over the dielectric layer 106 . The seed layer can be a metal layer, which can be a single layer or a composite layer that includes multiple intermediate layers that can be formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer can be deposited by physical vapor deposition (PVD) or the like. A photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The structure of the photoresist corresponds to the metallization structure 108. The patterning forms openings through the photoresist for exposing the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating (e.g., electroplating or electroless plating) or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying portions of the seed layer form the metallization structure 108. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by any acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, exposed portions of the seed layer are removed using an acceptable etching process, such as wet or dry etching.

The dielectric layer 110 is deposited onto the metallization structure 108 and the dielectric layer 106 . Dielectric layer 110 may be formed from the same or similar materials as dielectric layer 106 . Openings can be structured through the dielectric layer 110 in order to expose the underlying metallization structure 108 . The openings can be patterned through the dielectric layer 110 with an acceptable process. In embodiments where the dielectric layer 110 includes a photosensitive material, the dielectric layer 110 may be exposed to a patterned energy source (e.g., a patterned light source) and developed to form the openings that extend through the dielectric layer 110 . In some embodiments, a patterned mask may be formed over the dielectric layer 110, and the dielectric layer 110 may be patterned through the patterned mask by using an etch process, such as an etching process. B. an anisotropic etch, is used to form the openings that extend through the dielectric layer 110 therethrough.

The metallization structure 112 is formed on the dielectric layer 110 and the metallization structure 108 . The metallization structure 112 includes portions on and along a top surface of the dielectric layer 110 (e.g., conductive traces) and portions that extend through the dielectric layer 110 (e.g., conductive vias). The portions of metallization structure 112 that extend through dielectric layer 110 may be electrically coupled to metallization structure 108 and may be in physical contact therewith. Metallization structure 112 may be formed from the same materials and in the same or similar manner as metallization structure 108 . In some embodiments, metallization structure 112 has a different size than metallization structure 108. For example, the traces and/or conductive vias of metallization structure 112 may be wider or thicker than the traces of metallization structure 108. Furthermore, metallization structure 112 may be formed with a greater spacing be than the metallization structure 108.

The dielectric layer 114 is deposited onto the metallization structure 112 and the dielectric layer 110 . The dielectric layer 114 can be patterned to expose the metallization pattern 112 . Dielectric layer 114 may be formed from materials formed and patterned in the same or similar manner as dielectric layer 110 .

The metallization structure 116 is formed on the dielectric layer 114 and the metallization structure 112 . The metallization structure 116 includes portions on and along a top surface of the dielectric layer 114 (e.g., conductive traces) and portions that extend through the dielectric layer 114 (e.g., conductive vias). The portions of metallization structure 116 that extend through dielectric layer 114 may be electrically coupled to metallization structure 112 and may be in physical contact therewith. Metallization structure 116 may be formed from the same materials and in the same or similar manner as metallization structure 108 . In some embodiments, metallization structure 116 has a different size than metallization structure 108 and metallization structure 112. For example, the traces and/or conductive vias of metallization structure 116 may be wider or thicker than the traces and/or conductive vias of metallization structure 108 and of metallization structure 112. Furthermore, metallization structure 116 may be formed at a greater spacing than metallization structure 108 and metallization structure 112.

The dielectric layer 118 is deposited onto the metallization structure 116 and the dielectric layer 114 . The dielectric layer 118 can be structured in such a way that openings are formed which expose the metallization structure 116 . Dielectric layer 118 may be formed from materials formed and patterned in the same or similar manner as dielectric layer 110 .

The metallization structure 120 is formed in the openings that extend through the dielectric layer 118 . In some embodiments, the metallization structure 120 may be formed on the dielectric layer 118 and the metallization structure 116 . Metallization structure 120 may be formed from the same materials and in the same or similar manner as metallization structure 108 . After forming the metallization structure 120 , a planarization process may be performed on the metallization structure 120 to align the top surfaces of the metallization structure 120 with the top surfaces of the dielectric layer 118 . The planarization process can be a chemical mechanical polishing (CMP), a grinding process, or the like. The metallization structure 120 may include conductive pads 120A followed by vias (such as vias 126 described below with reference to FIG 4 to be discussed) may be formed, and conductive pads 120B to which subsequent conductive connectors (such as conductive connectors 128 discussed below with reference to FIG 5 to be discussed) can be connected.

In 4 Formed on the conductive pads 120A of the metallization structure 120 are vias 126 (also referred to as molded via interconnects (TMIs)). Vias 126 may extend away from the top dielectric layer of front side redistribution structure 124 (eg, dielectric layer 118). To form vias 126, for example, over front side redistribution structure 124, e.g. B. on the dielectric layer 118 and the metallization structure 120, a seed layer (not separately illustrated) is formed. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer that includes multiple sub-layers formed from different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. For example, the seed layer may be formed using physical vapor deposition (PVD) or the like. In some embodiments, such as when vias 126 are as wide or narrower than underlying conductive pads 120A, a separate seed layer may be omitted and conductive pads 120A may serve as a seed layer.

A photoresist is formed and patterned on the seed layer (if present) and the front side redistribution structure 124 . The photoresist can be formed by spin coating or the like and can be exposed to light for patterning. The pattern of the photoresist corresponds to the vias 126. The patterning creates openings through the photoresist to expose the seed layer or conductive pads 120A. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating such as electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by any acceptable ashing or stripping process, such as using oxygen plasma or the like. When the photoresist is removed, exposed portions of the seed layer (if any) are removed using an acceptable etching process, such as wet or dry etching. The remaining sections of the seed Layer and the conductive material form the vias 126.

Wire bond structures may also be used in place of vias 126 in some embodiments. For example, a wire bond structure (not separately illustrated) may be formed on each of the conductive pads 120A. Each of the wire bond structures may include a bond ball formed on the respective conductive pad 120A and a metal wire attached to the respective bond ball.

In 5 Two integrated circuit dies 50 are interconnected in the illustrated package region. Even though 5 Illustrating two integrated circuit dies 50 connected in the illustrated package region, any number of integrated circuit dies 50 may be connected in any of multiple package regions on a wafer. In 5 For example, integrated circuit dies 50 are arranged face down such that the front sides of integrated circuit dies 50 face conductive pads 120B and the back sides of integrated circuit dies 50 face away from conductive pads 120B. The integrated circuit dies 50 are connected to the conductive pads 120B by conductive connectors 128. FIG. Conductive connectors 128 are formed over conductive pads 120B. The conductive connectors 128 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip interconnect bumps (C ₄ bumps), microbumps, with the "Electroless Nickel-Electroless Palladium-Immersion Gold" technique (ENEPIG) formed bumps or the like. The conductive connectors 128 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 128 are formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed, reflow can be performed to form the material into the desired bump shapes. In some embodiments, the conductive connectors 128 include metal pillars (such as copper pillars) that may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solderless and have vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cover layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof. The metal cover layer can be formed by a plating process.

In 6 An underfill 130 is formed between the integrated circuit dies 50 and the front face redistribution structure 124 . The underfill 130 may enclose the conductive connectors 128 . The underfill 130 may be formed by a capillary flow process after the integrated circuit dies 50 are attached, or it may be formed by a suitable deposition process before the integrated circuit dies 50 are attached. In some embodiments, the underfill 130 may be formed from a polymeric material and may increase the bond strength of the integrated circuit dies 50 to the front face redistribution structure 124 .

In 7 an insulating layer 132 is formed over the h vias 126, the integrated circuit dies 50, the underfill 130, and the front side redistribution structure 124, and an encapsulation material 134 is formed over the insulating layer 132. FIG. The insulating layer 132 may be a conformal layer. In some embodiments, the insulating layer 132 may be deposited by CVD, plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), PVD, sputtering, spin coating, thermal spray, or the like. The insulating layer 132 may be formed from an electrically insulating material. In some embodiments, the insulating layer 132 may be formed from a material with a high thermal conductivity, such as a thermal conductivity greater than 10 W/m·K. In the embodiments where the insulating layer 132 is formed from a material with high thermal conductivity, the insulating layer 132 may be aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, aluminum oxide (Al ₂ O ₃ ), magnesium oxide (MgO ), combinations or multiple layers thereof, or the like. In some embodiments, the insulating layer 132 may be formed from a material with a relatively low thermal conductivity, such as a thermal conductivity of less than about 10 W/m•K, a thermal conductivity in the range of about 1 W/m•K to about 10 W /m•K or something like that. In the embodiments where the insulating layer 132 is formed from a material with relatively low thermal conductivity, the insulating layer 132 may comprise silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON _x ), combinations or multiple layers thereof, or the like . In some embodiments, insulating layer 132 may include a polymeric material. The insulating layer 132 can have a thermal conductivity in the range from about 1 W/m·K to about 100 W/m·K, an electrical conductivity in the range from about 10 ⁷ Ω·cm to about 10 ¹⁴ Ω·cm, and a coefficient of thermal expansion (CTE) in the range of about 0.1 ppm/°C to about 10 ppm/°C.

The encapsulation material 134 is then formed over the insulating layer 132 . The encapsulation material 134 may be a molding material, an epoxy resin, or the like. In some embodiments, the encapsulation material 134 may be a mixture of epichlorohydrin with bisphenol-A (BPA), bisphenol-A diglycidyl ether (DGEBA), bisphenol-F (BPF), phenols, thiols, anhydrides, amines, aliphatic alcohols, fillers, combinations thereof or the like. The encapsulation material 134 may be applied by compression molding, transfer molding, or the like and formed to obscure or cover the vias 126 and/or the integrated circuit dies 50. The encapsulation material 134 can be applied in liquid or semi-liquid form and subsequently cured.

The encapsulation material 134 may be formed from materials with high thermal conductivity, which improves heat dissipation through the encapsulation material 134 . For example, in some embodiments, the encapsulation material 134 may be formed from a mixture of epoxy and conductive filler materials that may include graphite, graphene, carbon nanotubes, conductive particles (e.g., copper (Cu), silicon (Si), silver (Ag), Gold (Au), iron (Fe), tungsten (W), combinations thereof, or the like), combinations thereof, or the like. In some embodiments, the graphite filler materials may include flakes less than 1 μm in size. The graphene fillers can be monolayer or multilayer and can include flakes less than 10 µm in size. The carbon nanotube filler materials can be single-walled or multi-walled and can include sizes of less than 50 μm. The conductive filler materials can have a thermal conductivity ranging from about 10 W/m•K to about 1,000 W/m•K, an electrical conductivity ranging from about 10 ^-3 Ω•cm to about 10 ¹⁴ Ω•cm, and a coefficient of thermal expansion (CTE ) in the range of about 1 ppm/°C to about 10 ppm/°C. The encapsulation material 134 may include the conductive filler materials in a concentration of about 5% to about 95% by volume. In some embodiments, the encapsulation material 134 may include the conductive filler materials in a concentration of about 70% to about 95% by volume, a concentration of about 5% to about 40% by volume, or a concentration of about 30% to about 70% by volume. Including the conductive filler materials within the prescribed concentration ranges can improve heat dissipation through the encapsulation material 134 . In some embodiments, the encapsulation material 134 may further include non-conductive filler materials such as AlN, diamond, BN, BeO, magnesium oxide (MgO), Al ₂ O ₃ , SiO ₂ , silicon (Si), silicon nitride (SiN _x ), combinations thereof, or the like.

The thermal conductivity of encapsulation material 134 may be greater than the thermal conductivity of insulating layer 132. In some embodiments, encapsulation material 134 may have a thermal conductivity greater than about 40 W/m•K, a thermal conductivity ranging from about 40 W/m•K to about 100 W/m•K, from about 5 W/m•K to about 200 W/m•K, or from about 100 W/m•K to about 200 W/m•K, or the like. The encapsulation material 134 may have an electrical conductivity ranging from about 10 ^-3 Ω·cm to about 10 ¹⁴ Ω·cm and a coefficient of thermal expansion (CTE) ranging from about 0.1 ppm/°C to about 20 ppm/°C.

Forming the insulating layer 132 over the vias 126, the integrated circuit dies 50, and the front side redistribution structure 124 allows greater flexibility in the choice of materials for the encapsulation material 134. For example, the insulating layer 132, being formed from an electrically insulating material, prevents short circuits between the Vias 126, the integrated circuit dies 50 and the front face redistribution structure 124, even if the encapsulation material 134 is formed of an electrically conductive material. The insulating layer 132 forms a buffer layer between the encapsulation material 134 and the vias 126, the integrated circuit dies 50 and the front side redistribution structure 124, thereby reducing stress. As a result, the encapsulation material 134 can be formed from materials with higher coefficients of thermal expansion. The greater flexibility in choosing materials for the encapsulation material 134 allows the use of materials with high thermal conductivities for the encapsulation material 134, which improves the heat dissipation from the integrated circuit dies 50. This improves device performance and reduces device errors.

The insulating layer 132 may have a thickness t ₁ of about 10 nm to about 100 nm. Forming insulating layer 132 with a thickness less than the prescribed range may result in difficulties in forming insulating layer 132 and may be insufficient to achieve the benefits of insulating layer 132 (e.g., providing electrical isolation between vias 126, the integrated circuit dies 50 and the front face redistribution structure 124 and providing a buffer layer between the encapsulation material 134 and the underlying structures). Furthermore, the insulating layer 132 may be formed of a material having a lower Having thermal conductivity than the material of the encapsulation material 134. If the insulating layer 132 is formed thicker than the prescribed range, the combined thermal conductivity of the insulating layer 132 and the encapsulating material 134 decreases.

In 8th a planarization process is performed on the encapsulation material 134 and the insulating layer 132 . As in 9 1, the planarization process may expose vias 126. FIG. Vias 126 pass through insulating layer 132 and encapsulation material 134 and may be referred to as vias 126 hereinafter. In some embodiments, at least a portion of the insulating layer 132 on the backsides of the integrated circuit dies 50 may remain. In some embodiments, portions of the encapsulation 134 may also remain over the backsides of the integrated circuit dies 50, or the encapsulation material 134 and insulating layer 132 may be planarized such that the backsides of the integrated circuit dies 50 are exposed. Material may also be removed from vias 126 by the planarization process. The top surfaces of vias 126, insulating layer 132, and encapsulation material 134 may be level after the planarization process (e.g., within process variations). In some embodiments, the planarization process may be a CMP, a grinding process, or the like.

In 9 A backside redistribution structure 144 is formed on the encapsulation material 134, the vias 126 and the insulating layer 132. FIG. Backside redistribution structure 144 includes dielectric layer 138 and metallization structures 136 and 140. Metallization structures 136 and 140 may also be referred to as redistribution layers or redistribution lines. In the 9 Illustrated backside redistribution structure 144 includes a dielectric layer and two layers of metallization structures. More or fewer dielectric layers and metallization structures may be formed in the backside redistribution structure 144 . If fewer dielectric layers and metallization structures are to be formed, steps and the process may be repeated as discussed below. If more dielectric layers and metallization structures are to be formed, the steps and processes discussed below may be repeated.

The backside redistribution structure 144 may be formed by forming the metallization structure 136 on the encapsulation material 134, the insulating layer 132, and the vias 126. FIG. Metallization structure 136 may be formed from the same materials and in the same or similar manner as metallization structure 108 . After the metallization structure 136 is formed and patterned, the metallization structure 136 may include portions that extend along the top surfaces of the encapsulation material 134 , the insulating layer 132 , and the vias 126 . The metallization structure 136 may be electrically coupled to the vias 126 .

The dielectric layer 138 is deposited onto the metallization structure 136, the encapsulation material 134, the insulating layer 132 and the vias 126. FIG. Dielectric layer 138 may be formed from the same or similar materials as dielectric layer 106 . Openings can be structured through the dielectric layer 138 in order to expose the metallization structure 136 lying underneath. The openings can be patterned through the dielectric layer 138 with any acceptable process. In embodiments where the dielectric layer 138 includes a photosensitive material, the dielectric layer 138 may be exposed to a patterned energy source (e.g., a patterned light source) and developed to form the openings that extend through the dielectric layer 138 . In some embodiments, a patterned mask may be formed over the dielectric layer 138, and the dielectric layer 138 may be patterned through the patterned mask by using an etch process, such as an etching process. B. an anisotropic etch, is used to form the openings that extend through the dielectric layer 138 therethrough.

The metallization structure 140 is formed in the openings that extend through the dielectric layer 138 . In some embodiments, the metallization structure 140 may be formed on the dielectric layer 138 and the metallization structure 136 . Metallization structure 120 may be formed from the same materials and in the same or similar manner as metallization structure 108 . After forming the metallization structure 140 , a planarization process may be performed on the metallization structure 140 to align the top surfaces of the metallization structure 140 with the top surfaces of the dielectric layer 138 . The planarization process can be a CMP, a grinding process, or the like.

A first package component 100 is thus formed in the illustrated package region. The first package component 100 includes the integrated circuit dies 50, the encapsulation material 134, the insulating layer 132, the vias and gen 126, the front redistribution structure 124 and the rear redistribution structure 144.

In 10 conductive connectors 146 are formed over metallization structure 140 . The conductive connectors 146 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip interconnect bumps (C ₄ bumps), microbumps, with the "Electroless Nickel-Electroless Palladium-Immersion Gold" technique (ENEPIG) formed bumps or the like. The conductive connectors 146 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connectors 146 are formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed, reflow can be performed to form the material into the desired bump shapes. In some embodiments, the conductive connectors 146 include metal pillars (such as copper pillars) that may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solderless and have vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cover layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof. The metal cover layer can be formed by a plating process.

In 11 a second package component 200 is connected to the conductive connectors 146 . The second package component 200 is coupled to the first package component 100 to form an integrated circuit device stack in the illustrated package region. The second package component 200 includes a substrate 202 and one or more stacked dies 210 (e.g., a first stacked die 210A and a second stacked die 210B) bonded to the substrate 202 . Although a set of stacked dies 210 (e.g., first stacked die 210A and second stacked die 210B) is illustrated, in some embodiments, multiple sets of stacked dies 210 (each comprising one or more stacked dies) may be arranged side-by-side and with a Surface of the substrate 202 may be connected. The substrate 202 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may be used. The substrate 202 may be a silicon on insulator (SOI) substrate. In general, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In some embodiments, the substrate 202 may be based on an insulating core, such as a fiberglass reinforced resin core. The core material may be a fiberglass such as FR4. In some embodiments, the core material may include bismaleimide triazine (BT) resin, other printed circuit board (PCB) materials or films, or the like. For the substrate 202, build-up films such as Ajinomoto build-up film (ABF) or other laminates can be used.

The substrate 202 may include active and passive devices (not separately illustrated). A wide variety of devices such as transistors, capacitors, resistors, combinations thereof, and the like may be used to create the structural and functional design requirements for the second package component 200 . The devices can be formed using any method.

The substrate 202 may also include layers of metallization (not separately illustrated) and conductive vias 208 . The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. The metallization layers may be formed of alternating layers of dielectrics (e.g., low-k dielectrics) and conductive materials (e.g., copper), with the layers of conductive materials being interconnected by vias. The metallization layers may be formed by any suitable process (such as deposition, damascene process, dual damascene process, or the like). In some embodiments, substrate 202 is substantially free of active and passive devices.

The substrate 202 may include bond pads 204 on a first side of the substrate 202 and bond pads 206 on a second side of the substrate 202 opposite the first side. Bond pads 204 may be used to connect to stacked dies 210 and bond pads 206 to connect to conductive connectors 146 . In some embodiments, such as B. the embodiment illustrated by the bond pads 206, the bond pads 204 and the bond pads 206 are formed by forming cutouts (not illustrated separately) in dielectric layers (not illustrated separately) on the first and second sides of the substrate 202 . The cutouts may be formed to embed the bond pads 204 and the bond pads 206 in the dielectric layers. In other embodiments, such as the embodiment illustrated by bond pads 204, the cutouts are omitted since bond pads 204 and bond pads 206 may be formed on the dielectric layers. In some embodiments, bond pads 204 and bond pads 206 include a thin seed layer (not separately illustrated) of copper, titanium, nickel, gold, palladium, the like, or a combination thereof. The conductive material of bond pads 204 and bond pads 206 may be deposited over the thin seed layer. The conductive material may be formed by an electrochemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In some embodiments, the conductive material of bond pads 204 and bond pads 206 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In some embodiments, the bond pads 204 and the bond pads 206 are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other configurations of materials and layers may be used for the bond pads 204 and the bond pads 206, such as a chromium/chromium-copper alloy/copper/gold configuration, a titanium/titanium tungsten/copper configuration, or a copper/copper configuration. Nickel/Gold. Any suitable materials or material layers that can be used for bond pads 204 and bond pads 206 are fully intended to be included within the scope of the current application. In some embodiments, conductive vias 208 extend through substrate 202 and couple at least one of bond pads 204 to at least one of bond pads 206.

In the illustrated embodiment, the stacked dies 210 are coupled to the substrate 202 by wire bonds 212, however other connections such as conductive bumps may be used. In some embodiments, the stacked dies 210 are stack dies. The stacked dies 210 may include, for example, memory dies such as low-power double data rate (LP-DDR) memory modules (e.g., LPDDR ₁ , LPDDR ₂ , LPDDR ₃ , LPDDR ₄ ), DRAM dies, combinations thereof, or be like that.

The stacked dies 210 and wire bonds 212 may be encapsulated with a molding material 214 . In some embodiments, the molding material 214 may be molded to the stacked dies 210 and the wire bonds 212 by compression molding. In some embodiments, the molding material 214 is a molding compound, a polymer, an epoxy, a silicon oxide material, the like, or a combination thereof. A curing process may be performed to harden the molding material 214 . The curing process can be thermal curing, UV curing, the like, or a combination thereof. In some embodiments, the stacked dies 210 and the wire bonds 212 are hidden in the molding material 214 . After the molding material 214 has been cured, a planarization step, such as e.g., grinding, is performed to remove excess portions of the molding material 214 and create a planar surface for the second package component 200. FIG.

After the second package component 200 is formed, the second package component 200 may be bonded to the first package component 100 via the conductive connectors 146, the bond pads 206, and the metallization structure 140. FIG. In some embodiments, the stacked dies 210 may be connected to the integrated circuit dies 50 by the wire bonds 212, the bond pads 204, the conductive vias 208, the bond pads 206, the conductive connectors 146, the backside redistribution structure 144, the vias 126, and the frontside redistribution structure 124.

In some embodiments, a solder resist (not separately illustrated) is formed on the second side of the substrate 202 . The conductive connectors 146 may be disposed in openings in the solder resist that may be electrically and mechanically connected to conductive elements (e.g., the bond pads 206) in the substrate 202. The solder resist can be used to protect areas of the substrate 202 from external damage. In some embodiments, an oxide flux (not separately illustrated) is formed on the conductive connectors 146 before reflowing with at least a portion of the epoxy portion of the epoxy flux remaining after attaching the second package component 200 to the first package component 100 .

In 12 An encapsulation material 148 is formed between the first package component 100 and the second package components 200 enclosing the conductive connectors 146 . In some embodiments (not separately illustrated), the encapsulation material 148 may further surround the second package component 200 and the encapsulation ment material 148 are formed around the first package component 100 . The encapsulation material 148 may be a molding material, epoxy, mold underfill, or the like. The encapsulation material 148 may be applied by compression molding, injection molding, or the like. The encapsulation material 148 is also formed in gap regions between the second package component 200 and the underlying first package component 100 . The encapsulation material 148 can be applied in liquid or semi-liquid form and subsequently harden.

In 13 For example, the carrier substrate peel is performed to separate (also referred to as “peel”) the carrier substrate 102 from the first of the first package components 100 (eg, the dielectric layer 106). In some embodiments, the debonding includes projecting a light, such as a laser light or a UV light, onto the release layer 104 such that the release layer 104 decomposes under the heat of the light and the carrier substrate 102 can be removed. A major surface of the dielectric layer 106 can be exposed after removing the carrier substrate 102 and the release layer 104 .

After the support substrate 102 and release liner 104 are removed, UBMs 160 and conductive connectors 162 for external connection to the front side redistribution structure 124 are formed. The UBMs 160 include bump portions on and along the major surface of the dielectric layer 106 and via portions that extend through the dielectric layer 106 . The via portions of the UBMs 160 may be electrically coupled to and in physical contact with the metallization structures 108 . As a result, the UBMs 160 are electrically connected to the vias 126 and the integrated circuit dies 50 through the front face redistribution structure 124 . The UBMs 160 can be formed from the same materials and in the same or similar manner as the metallization structure 108 .

Conductive connectors 162 are formed on the UBMs 160 . The conductive connectors 162 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip interconnect bumps (C ₄ bumps), microbumps, with the "Electroless Nickel-Electroless Palladium-Immersion Gold" technique (ENEPIG) formed bumps or the like. The conductive connectors 162 may be a conductive material, such as. B. solder, copper, aluminum, gold, nickel, silver, palladium, tin or a combination thereof. In some embodiments, the conductive connectors 162 are formed by initially forming a solder layer through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once the solder layer has been formed on the structure, reflow can be performed to shape the material into the desired bump shapes. In some embodiments, the conductive connectors 162 include metal pillars (such as copper pillars) that may be formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars can be solderless and have vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cover layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof. The metal cover layer can be formed by a plating process.

In 13 Furthermore, the first package component 100 is mounted on a substrate 300 . The substrate 300 can be made of a semiconductor material such as silicon, germanium, diamond, or the like. In some embodiments, composite materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations thereof, and the like may also be used. Furthermore, the substrate 300 may be a silicon on insulator (SOI) substrate. In general, an SOI substrate includes a layer of semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. In some embodiments, the substrate 300 may be based on an insulating core, such as a glass fiber reinforced resin core. In some embodiments, the core material can be a fiberglass resin such as FR4. In some embodiments, the core material may include bismaleimide triazine (BT) resin, other printed circuit board (PCB) materials, or other films. For the substrate 300, build-up films such as Ajinomoto build-up film (ABF) or other laminates can be used.

The substrate 300 may include active and passive devices (not separately illustrated). A wide variety of devices such as transistors, capacitors, resistors, combinations of these devices, and the like may be included. The devices can be formed using any method. The substrate 300 may also include metallization layers (not illustrated separately). The metallization layers may be formed over the active and passive devices and are designed to connect the various devices to form functional circuitry. the Metallization layers may be formed from alternating layers of dielectrics (e.g., low-k dielectrics) and conductive materials (e.g., copper), with the layers of conductive materials being interconnected by vias. The metallization layers may be formed by any suitable process (such as deposition, damascene processing, dual damascene processing, or the like). In some embodiments, the substrate 300 is essentially free of active and passive devices.

The substrate 300 may include bond pads 302 formed on a first side of the substrate 300 opposite the first package component 100 . In some embodiments, the bond pads 302 may be formed by forming cutouts (not separately illustrated) in dielectric layers (not separately illustrated) on the first side of the substrate 300 . The cutouts may be formed such that the bond pads 302 may be embedded in the dielectric layers. In some embodiments, the cutouts are omitted and the bond pads 302 may be formed on the dielectric layers. In some embodiments, the bond pads 302 include a thin seed layer (not separately illustrated) of copper, titanium, nickel, gold, palladium, or the like, or a combination thereof. The conductive materials of the bond pads 302 can be deposited on the thin seed layer. The conductive materials may be formed by an electrochemical plating process, an electroless plating process, CVD, ALD, PVD, the like, or a combination thereof. In one embodiment, the conductive materials of the bond pads 302 include copper, tungsten, aluminum, silver, gold, or a combination thereof.

In some embodiments, the bond pads 302 are UBMs that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. Other arrangements of materials and layers exist, such as a chromium/chromium-copper alloy/copper/gold arrangement, a titanium/titanium-tungsten/copper arrangement, or a copper/nickel/gold arrangement may be used to form the bond pads 302 . Any suitable materials or material layers that can be used for the bond pads 302 are intended to be included within the scope of this application.

The substrate 300 is electrically coupled and physically attached to the first package component 100 via the bond pads 302 , the conductive connectors 162 and the UBMs 160 . The substrate 300 may be placed over the first package component 100 and a reflow process may be performed to reflow the conductive connectors 162 and bond the bond pads 302 to the UBMs 160 through the conductive connectors 162 .

An underfill 164 can then be formed between the first package component 100 and the substrate 300 and encloses the bond pads 302, the UBMs 160, and the conductive connectors 162. The underfill 164 can reduce stress and protect the connections resulting from the reflow of the conductive connector 162 develop. The underfill 164 may be formed by a capillary flow process after the first package component 100 is attached to the substrate 300, or formed by a suitable deposition process before the first package component 100 is attached.

By including the insulating layer 132 disposed between the encapsulation material 134 and each of the vias 126, the integrated circuit dies 50 and the metallization structure 120, the use of a wider variety of materials for the encapsulation material 134 becomes possible. The insulating layer 132 provides electrical insulation, for example, so that electrically conductive materials can be used for the encapsulation material 134 . Furthermore, the insulating layer 132 can provide a physical buffer layer so that the encapsulation material 134 can use materials with high coefficients of thermal expansion. As a result, materials with high thermal conductivity can be used for the encapsulation material 134, which increases the heat dissipation through the encapsulation material 134. This improves device performance and reduces device errors.

the 14 and 15 12 illustrate an embodiment in which the integrated circuit dies 50A are bonded directly to the front face redistribution structure 124 (without the conductive connectors 128 and the underfill 130 disposed therebetween). In 14 the integrated circuit dies 50A with the in 4 illustrated front side redistribution structure 124, and an insulating layer 132 and an encapsulation material 134 are formed over the resulting structure. The integrated circuit dies 50A may be the same or similar to the integrated circuit dies 50 discussed above. The integrated circuit dies 50A are arranged face down such that the front faces of the integrated circuit dies 50A face the conductive pads 120B and the back faces of the integrated circuit dies 50A point away from the conductive pads 120B.

In some embodiments, the integrated circuit dies 50A are bonded to the conductive pads 120B of the metallization structure 120 in a hybrid connection facility. For example, a dielectric layer 68 of integrated circuit die 50A may be bonded directly to dielectric layer 118 of front side redistribution structure 124, and die connectors 66 of integrated circuit die 50A may be bonded directly to conductive pads 120B. In one embodiment, the bond between dielectric layer 68 and dielectric layer 118 may be an oxide-to-oxide bond or the like. The hybrid bonding process also bonds the die connectors 66 of the integrated circuit dies 50A directly to the conductive pads 120B through direct metal-to-metal bonding. Thus, the electrical connection between the integrated circuit dies 50A and the front face redistribution structure 124 is made through the physical connection of the die connectors 66 to the conductive pads 120B.

For example, the hybrid bonding process may begin with a surface treatment of the dielectric layer 118 of the front side redistribution structure 124 and/or the dielectric layer 68 of the integrated circuit die 50A. The surface treatment can include a plasma treatment. The plasma treatment can be carried out in a vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., a deionized water rinse or the like) that may be applied to the dielectric layer 118 and/or the dielectric layer 68 of the integrated circuit die 50A. The hybrid bonding process can then continue with the alignment of the die connectors 66 to the conductive pads 120B. Next, hybrid bonding includes a pre-bonding step in which die connectors 66 are brought into physical contact with conductive pads 120B. Pre-bonding can be performed at room temperature (e.g., between about 21°C and about 25°C). The hybrid bonding process is continued by performing an anneal at a temperature of about 150°C to about 400°C for a period of about 0.5 hour to about 3 hours. The anneal causes the metal of die connectors 66 (e.g., copper) and the metal of conductive pads 120B (e.g., copper) to diffuse together, forming the direct metal-to-metal connection. The anneal may also form covalent bonds between dielectric layer 68 and dielectric layer 118 . In some embodiments, other bonding parameters and/or methods (e.g., solder bonding) may also be used.

After the integrated circuit dies 50A are bonded to the front-side redistribution structure 124, the insulating layer 132 and encapsulation material 134 may be formed over the vias 126, the integrated circuit dies 50A, and the front-side redistribution structure. The insulating layer 132 may be formed from the same or similar materials as referred to in FIG 7 was discussed. Similarly, the encapsulation material 134 may be formed from the same or similar materials as referred to in FIG 7 was discussed.

15 illustrates the structure of 14 , after the above with reference to the 8th until 13 discussed processes have been carried out. Directly bonding integrated circuit dies 50A to frontside redistribution structure 124 simplifies the process of bonding integrated circuit dies 50A to frontside redistribution structure 124, eliminates the steps required to form underfill 130, and reduces the height of the final structure. Furthermore, including the insulating layer 132 disposed between the encapsulation material 134 and each of the vias 126, the integrated circuit die 50A, and the metallization structure 120 allows a greater variety of materials to be used for the encapsulation material 134. The insulating layer 132 provides electrical insulation, for example ready, so that electrically conductive materials can be used for the encapsulation material 134 . Furthermore, the insulating layer 132 can provide a physical buffer layer so that the encapsulation material 134 can use materials with high coefficients of thermal expansion. As a result, materials with high thermal conductivity can be used for the encapsulation material 134, which increases the heat dissipation through the encapsulation material 134. This improves device performance and reduces device errors.

the 16 until 18 12 illustrate an embodiment where multiple integrated circuit dies 50B and 50C are bonded to front face redistribution structure 124 along with interconnect dies 70. FIG. In the 16 and 17 the integrated circuit dies 50B and 50C and the connection dies 70 with the in 4 illustrated front side redistribution structure 124 and an insulating layer 132 and an encapsulation material 134 formed over the resulting structure. Integrated circuit die 50B and 50C may be identical or similar to integrated circuit die 50 discussed above. The integrated circuit dies 50B and 50C are arranged face down such that the front faces of the integrated circuit dies 50B and 50C face the conductive pads 120B and the back faces of the integrated circuit dies Circuit dies 50B and 50C facing away from conductive pads 120B. Furthermore, the integrated circuit dies 50B may include substrate vias (TSVs) 67 (also referred to as silicon vias) that extend through the semiconductor substrate 52 of the integrated circuit dies 50B.

The connection dies 70 may be local silicon interconnects (LSIs), large scale integration packages, interposer dies, or the like. Interconnect dies 70 include substrates 72 with conductive elements formed in and/or on substrates 72 . The substrates 72 may be semiconductor substrates, dielectric layers, or the like. Connection dies 70 may include substrate vias (TSVs) 74 (also referred to as silicon vias) that extend into or through substrate 72 . In the in the 16 until 18 In the illustrated embodiment, the TSVs 74 extend through the substrate 72 and are exposed on both the front and back sides of the connection dies 70. FIG.

The integrated circuit dies 50B may be bonded to the front face redistribution structure 124 through conductive connectors 128 and an underfill 130 by processes similar or identical to those described above with reference to FIG 5 and 6 were discussed. Connection dies 70 may be bonded to integrated circuit dies 50B and integrated circuit dies 50C may be bonded to connection dies 70 by hybrid bonding processes consistent with those referenced above with reference to FIG 14 discussed are identical or similar. Specifically, the TSVs 74 of interconnection dies 70 may be bonded to the TSVs 67 of integrated circuit dies 50B by metal-to-metal bonding; substrates 72 of interconnection dies 70 may be bonded to semiconductor substrates 52 of integrated circuit dies 50B by oxide-to-oxide bonding; die connectors 66 of integrated circuit dies 50C may be bonded to TSVs 74 of interconnection dies 70 by metal-to-metal bonding; and the dielectric layers 68 of the integrated circuit dies 50C may be bonded to the substrates 72 of the interconnection dies 70 by oxide-to-oxide bonding. 16 Figure 12 illustrates an embodiment where the integrated circuit dies 50B and 50C and the interconnection dies 70 have the same width. 17 Figure 11 illustrates an embodiment where interconnection dies 70 may have a smaller width than integrated circuit dies 50B and integrated circuit dies 50C may have an equal or lesser width than interconnection dies 70. FIG. More generally, the width of each of the dies stacked across the front side redistribution structure 124 may be equal to or less than the width of an underlying die on which the die is stacked. Although in the 16 and 17 While three dies are illustrated in each stack, any number of interconnection dies 70 and integrated circuit dies 50B and 50C may be included.

After integrated circuit dies 50B and 50C and interconnect dies 70 are bonded to front face redistribution structure 124, insulating layer 132 and encapsulation material 134 may be formed over vias 126, integrated circuit dies 50B and 50C, interconnect dies 70 and front face redistribution structure 124. The insulating layer 132 may be formed from the same or similar materials as referred to in FIG 7 was discussed. Similarly, the encapsulation material 134 may be formed from the same or similar materials as referred to in FIG 7 was discussed.

18 illustrates the structure of 16 , after the above with reference to the 8th until 13 discussed processes have been carried out. By including the insulating layer 132 located between the encapsulation material 134 and each of the vias 126, the integrated circuit dies 50B and 50C, the connection dies 70 and the metallization structure 120, the use of a wider variety of materials available for the encapsulation material 134 becomes possible. The insulating layer 132 provides electrical insulation, for example, so that electrically conductive materials can be used for the encapsulation material 134 . Furthermore, the insulating layer 132 can provide a physical buffer layer so that the encapsulation material 134 can use materials with high coefficients of thermal expansion. As a result, materials with high thermal conductivity can be used for the encapsulation material 134, which increases the heat dissipation through the encapsulation material 134. This improves device performance and reduces device errors. Additionally, providing stacked dies surrounded by the encapsulation material 134 improves heat dissipation from all of the encapsulated dies and provides improved functionality of the package structure.

the 19 until 21 12 illustrate an embodiment where interconnect dies 70A are bonded directly to front face redistribution structure 124 and integrated circuit dies 50D are bonded directly to interconnect dies 70A or directly to interconnect dies 70B bonded directly to interconnect dies 70A. In 19 the integrated circuit dies 50D are bonded to the connection dies 70A, and the stacks are bonded to the integrated circuit dies 50D and the connection dies 70A are connected to the in 4 illustrated front side redistribution structure 124 bonded. An insulating layer 132 and an encapsulation material 134 are formed over the resulting structure. In 20 the integrated circuit dies 50D are bonded with the connection dies 70B, the connection dies 70B are bonded with the connection dies 70A, and the stacks with the integrated circuit dies 50D, the connection dies 70B and the connection dies 70A are connected with the in 4 illustrated front side redistribution structure 124 bonded. An insulating layer 132 and an encapsulation material 134 are formed over the resulting structure. Integrated circuit die 50D may be the same or similar to integrated circuit die 50 discussed above. Integrated circuit die 50B and 50C are arranged face down such that the front faces of integrated circuit die 50B and 50C face conductive pads 120B and the Backsides of integrated circuit dies 50B and 50C face away from conductive pads 120B. Connection dies 70A and 70B may be identical or similar to connection dies 70 discussed above.

Interconnect dies 70A may be bonded to front face redistribution structure 124 by hybrid bonding processes consistent with those referenced above 14 discussed are identical or similar. Specifically, the TSVs 74 of the interconnect dies 70A can be bonded to the conductive pads 120B of the front side redistribution structure 124 by metal-to-metal bonding and the substrates 72 of the interconnect dies 70A can be bonded to the dielectric layer 118 of the front side redistribution structure 124 by oxide-to-oxide bonding will. The connection dies 70B may be bonded to the connection dies 70A by hybrid bonding processes similar to those referenced above 14 correspond to or are similar to those discussed. Specifically, the TSVs 74 of interconnection dies 70B can be bonded to the TSVs 74 of interconnection dies 70A by metal-to-metal bonding, and the substrates 72 of interconnection dies 70B can be bonded to the substrates 72 of interconnection dies 70A by oxide-to-oxide bonding . The integrated circuit dies 50D can be bonded to the connection dies 70A or 70B by hybrid bonding processes similar to those referenced above 14 discussed are identical or similar. Specifically, the die connectors 66 of the integrated circuit dies 50D can be bonded to the TSVs 74 of the interconnection dies 70A or 70B by metal-to-metal bonding, and the dielectric layers 68 of the integrated circuit dies 50D can be bonded to the substrates 72 of the interconnection dies 70A or 70B by oxide-to-metal bonding -Oxide bonds are bonded.

19 12 illustrates an embodiment where each of the integrated circuit dies 50D and interconnection dies 70A have the same width, and each of the integrated circuit dies 50D is bonded to the front face redistribution structure 124 by a single interconnection die 70A. 20 12 illustrates an embodiment where interconnection dies 70B may have a smaller width than interconnection dies 70A and integrated circuit dies 50D may have an equal or lesser width than interconnection dies 70B. More generally, the width of each of the dies stacked across the front side redistribution structure 124 may be equal to or less than the width of an underlying die on which the die is stacked. In 20 Furthermore, each of the integrated circuit dies 50D is bonded to the front side redistribution structure 124 by a connection die 70B and a connection die 70A. Although in 19 two dies in each stack and in 20 As three dies are illustrated in each stack, any number of interconnection dies 70A, interconnection dies 70B and integrated circuit dies 50D may be included.

After integrated circuit dies 50D and interconnect dies 70A and 70B are bonded to front face redistribution structure 124, insulating layer 132 and encapsulation material 134 may be formed over vias 126, integrated circuit dies 50D, interconnect dies 70A and 70B, and front face redistribution structure 124. The insulating layer 132 may be formed from the same or similar materials as referred to in FIG 7 was discussed. Similarly, the encapsulation material 134 may be formed from the same or similar materials as referred to in FIG 7 was discussed.

21 illustrates the structure of 19 , after the above with reference to the 8th until 13 discussed processes have been carried out. By including the insulating layer 132 disposed between the encapsulation 134 and each of the vias 126, the integrated circuit dies 50D, the connection dies 70A and 70B, and the metallization structure 120, the use of a wider variety of materials for the encapsulation material 134 becomes possible. The insulating layer 132 provides electrical insulation, for example, so that electrically conductive materials can be used for the encapsulation material 134 . Furthermore, the insulating layer 132 can provide a physical buffer layer so that the encapsulation material 134 can use materials with high coefficients of thermal expansion. As a result, materials with high thermal conductivity can be used for the encapsulation material 134, which the Heat dissipation through the encapsulation material 134 increased. This improves device performance and reduces device errors. Additionally, providing stacked dies surrounded by the encapsulation material 134 improves heat dissipation from all of the encapsulated dies and provides improved functionality of the package structure.

the 22 until 25 illustrate an embodiment in which an insulating layer 408 (in Figs 23 until 25 illustrated) is formed along the sidewalls of the vias 126 without being formed over the rest of the front face redistribution structure 125 or the integrated circuit dies 50. FIG. In 22 a mask layer 402 and a photoresist 404 over the in 3 illustrated front side redistribution structure 124 is formed. The mask layer 402 may include, for example, silicon nitride, silicon oxynitride, or the like. In some embodiments, mask layer 402 may be a polymer layer. The mask layer 402 can be formed, for example, by spin coating, lamination, CVD, ALD, or the like. Photoresist 404 is formed over mask layer 402 . Photoresist 404 may be formed by depositing a photosensitive layer over mask layer 402 by spin coating or the like.

Photoresist 404 and mask layer 402 can then be patterned. Photoresist 404 may be patterned by exposing photoresist 404 to a patterned energy source (e.g., a patterned light source) and developing photoresist 404 to remove an exposed or unexposed portion of photoresist 404 . Apertures 406 exposing mask layer 402 and extending through photoresist 404 are formed. The mask layer 402 may be etched using the photoresist 404 as a mask with any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The mask layer 402 can be etched with an anisotropic etching process.

In 23 the photoresist 404 is removed and an insulating layer 408 is formed along the sidewalls of the mask layer 402 in the openings 406 . Photoresist 404 may be removed by any acceptable ashing or stripping process, such as using oxygen plasma or the like. Insulating layer 408 may be formed from materials deposited in the same or similar manner as insulating layer 132 . After insulating layer 408 is deposited, insulating layer 408 may be etched to expose conductive pads 120A of front side redistribution structure 124 . The insulating layer 408 may have a thickness 12 of about 10 nm to about 100 nm. Forming insulating layer 408 with a thickness less than the prescribed range may result in difficulties in forming insulating layer 408 and may be insufficient to achieve the benefits of insulating layer 408 (e.g., providing electrical isolation for subsequently formed vias , such as vias 126, referenced below 24 be discussed). Furthermore, insulating layer 408 may be composed of a material that has a lower thermal conductivity than the material of a subsequently formed encapsulation material (such as encapsulation material 134, discussed below with reference to FIG 25 will be discussed). When insulating layer 408 is formed thicker than the prescribed range, the combined thermal conductivity of insulating layer 408 and encapsulation material 134 decreases.

In 24 , vias 126 are formed on the conductive pads 120A of the metallization structure 120 filling the openings 406 . Vias 126 may extend away from the top dielectric layer of front side redistribution structure 124 (e.g., dielectric layer 118) and extend between portions of insulating layer 408 formed on opposite sidewalls of each of openings 406. To form vias 126, a seed layer (not separately illustrated) is formed in openings 406 over conductive pads 120A and insulating layer 408, and over mask layer 402, for example. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer that includes multiple sub-layers formed from different materials. In a particular embodiment, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using PVD or the like, for example. In some embodiments, such as when vias 126 are as wide or narrower than underlying conductive pads 120A, a separate seed layer may be omitted and conductive pads 120A may serve as a seed layer. A conductive material is then formed over the seed layer and fills the openings 406. The conductive material may be formed by plating, such as electroplating or electroless plating or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. After the conductive material is formed, a planarization process can be performed on the conductive material and the seed layer. The planarization process can be a CMP, a grinding process or the like. The remaining portions of the seed layer and conductive material form vias 126. The top surfaces of vias 126, insulating layer 408, and mask layer 402 may be level after the planarization process (e.g., within process variations).

In 25 the mask layer 402 is removed and the data above with reference to FIG 5 until 13 are performed (omitting the processes used to form the insulating layer 132). The mask layer 402 may be removed by an etch process, such as an isotropic or anisotropic etch process or the like. The inclusion of insulating layer 408 located between encapsulation material 134 and vias 126 allows for the use of a wider variety of encapsulation material 134 materials. The insulating layer 408 provides electrical insulation, for example, such that electrically conductive materials can be used for the encapsulation material 134 . Furthermore, the insulating layer 408 can provide a physical buffer layer so that the encapsulation material 134 can use materials with high coefficients of thermal expansion. As a result, materials with high thermal conductivity can be used for the encapsulation material 134, which increases the heat dissipation through the encapsulation material 134. This improves device performance and reduces device errors. Also, forming the insulating layer 408 only along the sidewalls of the vias 126 improves the precision of the deposition of the insulating layer 408 and reduces the material usage for the insulating layer 408. However, if the insulating layer 408 is formed only along the sidewalls of the vias 126, the cost may increase compared to embodiments in which the insulating layer 132 is formed.

The embodiments can bring various advantages. For example, when the insulating layer is formed over underlying vias, redistribution structures, and integrated circuit die, a broader range of materials can be used for the encapsulation material formed over the insulating layer. The insulating layer can provide electrical insulation and a physical buffer between the encapsulation material and the underlying structures, so that the encapsulation can be formed from electrically conductive materials or materials with higher coefficients of thermal expansion, respectively. This allows materials with higher thermal conductivity to be used for the encapsulation, improving heat dissipation through the encapsulation material, increasing device performance, and reducing device failures.

According to one embodiment, a semiconductor device includes a first redistribution structure; a first die overlying and electrically coupled to the first redistribution structure; a first via located over and electrically coupled to the first redistribution structure; an insulating layer extending along the first redistribution structure, the first die, and the first via; and an encapsulation material over the insulating layer, the encapsulation material enclosing portions of the first via and the first die, the encapsulation material including conductive fillers in a concentration ranging from 70% to about 95% by volume. In one embodiment, the encapsulation material has a thermal conductivity greater than 40 W/m•K. In one embodiment, a top surface of the encapsulation material is level with a top surface of the first via and the top surface of the insulating layer, and the top surface of the encapsulation material is above the top surface of the first die. In one embodiment, the insulating layer extends along the sidewalls of the first via, the top surface of the first redistribution structure, and the top surface and sidewalls of the first die. In one embodiment, the first die is bonded to the first redistribution structure by oxide-to-oxide bonds and metal-to-metal bonds. In one embodiment, the first die is bonded to the first redistribution structure by conductive connectors, the semiconductor device further includes a first underfill enclosing the conductive connectors, and the insulating layer extends along sidewalls of the first underfill. In one embodiment, the insulating layer has a thickness of 10 nm to 100 nm and the encapsulation material has a thermal conductivity of 40 W/m•K to 100 W/m•K.

According to another embodiment, a semiconductor device comprises a first integrated circuit die; a front side redistribution structure on a front side of the first integrated circuit die; a backside redistribution structure on a backside of the first integrated circuit die; a molding material encapsulating the first integrated circuit die between the front side redistribution structure and the back side redistribution structure, the molding material having a thermal conductivity greater than 40 W/m•K; a via that is itself extending through the molding material, wherein the via is electrically coupled to the front redistribution structure and the back redistribution structure; and an insulating layer covering sidewalls of the via, the insulating layer separating the via from the molding material. In one embodiment, the molding material includes conductive particles selected from copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe), and tungsten (W), and the molding material includes the conductive particles in a concentration of 70 to 95% by volume. In one embodiment, the molding material has a thermal conductivity between 40 W/m•K and 100 W/m•K and the insulating layer has a thermal conductivity lower than the thermal conductivity of the molding material. In one embodiment, the insulating layer comprises at least one of the following materials: aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond, or aluminum oxide (Al ₂ O ₃ ). In one embodiment, the semiconductor device further comprises an interconnection die bonded to the first integrated circuit die by metal-to-metal bonds and oxide-to-oxide bonds. In one embodiment, the molding material physically contacts the front side redistribution structure, the back side redistribution structure, and the first integrated circuit die. In one embodiment, the insulating layer covers a top surface of the front side redistribution structure and a back and sidewalls of the first integrated circuit die, and the insulating layer separates the front side redistribution structure and the first integrated circuit die from the molding material.

According to another embodiment, a method includes forming a via over a redistribution structure; bonding a semiconductor die to the redistribution structure adjacent to the via; depositing an insulating layer over the via, the redistribution structure, and the semiconductor die, the insulating layer electrically isolating the via, the redistribution structure, and the semiconductor die from one another; and preparing a molding compound by mixing an epoxy and conductive fillers, the conductive fillers being 70 to 95% by volume of the molding material; applying the molding material over the insulating layer, the molding material configured to conduct heat away from the semiconductor die. In one embodiment, the insulating layer is deposited by a conformal deposition process. In one embodiment, the method further includes planarizing the molding material and the insulating layer to expose the via. In one embodiment, bonding the semiconductor die to the redistribution structure includes reflowing conductive interconnects between the semiconductor die and the redistribution structure and forming an underfill material enclosing the conductive interconnects, with the insulating layer being deposited on the sidewalls of the underfill material. In one embodiment, bonding the semiconductor die to the redistribution structure includes forming oxide-to-oxide bonds and metal-to-metal bonds between the semiconductor die and the redistribution structure. In one embodiment, bonding the semiconductor die to the redistribution structure includes bonding a diestack to the redistribution structure, wherein the diestack includes the semiconductor die and an interconnection die, and the insulating layer is further deposited on the interconnection die.

The above delineates elements of several embodiments that will allow those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to carry out the same purposes and/or achieve the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such corresponding constructions do not depart from the spirit and scope of this disclosure and that they can make various changes, substitutions and modifications thereto without departing from the spirit and scope of this disclosure.

QUOTES INCLUDED IN DESCRIPTION

This list of documents cited by the applicant was generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Patent Literature Cited

• US63166350 [0001]

Claims (20)

A semiconductor device comprising: a first redistribution structure; a first die overlying and electrically coupled to the first redistribution structure; a first via located over and electrically coupled to the first redistribution structure; an insulating layer extending along the first redistribution structure, the first die, and the first via; and an encapsulation material over the insulating layer, the encapsulation material enclosing portions of the first via and the first die, the encapsulation material having conductive fillers in a concentration ranging from 70% to about 95% by volume. semiconductor device claim 1 , wherein the encapsulation material has a thermal conductivity greater than 40 W/m•K. semiconductor device claim 1 or 2 wherein a top surface of the encapsulation material is level with a top surface of the first via and top surfaces of the insulating layer, and wherein the top surface of the encapsulation material overlays a top surface of the first die. A semiconductor device according to any one of the preceding Claims 1 until 3 , wherein the insulating layer extends along sidewalls of the first via, a top surface of the first redistribution structure, and a top surface and sidewalls of the first die. A semiconductor device according to any one of the preceding Claims 1 until 4 , where the first die is bonded to the first redistribution structure by oxide-to-oxide bonds and metal-to-metal bonds. A semiconductor device according to any one of the preceding Claims 1 until 4 wherein the first die is bonded to the first redistribution structure via conductive connectors, the semiconductor device further includes a first underfill enclosing the conductive connectors, and wherein the insulating layer extends along sidewalls of the first underfill. A semiconductor device according to any one of the preceding Claims 1 until 6 , wherein the insulating layer has a thickness in the range from 10 nm to 100 nm and wherein the encapsulation material has a thermal conductivity in the range from 40 W/m•K to 100 W/m•K. A semiconductor device comprising: a first integrated circuit die; a front side redistribution structure on a front side of the first integrated circuit die; a backside redistribution structure on a backside of the first integrated circuit die; a molding material encapsulating the first integrated circuit die between the front side redistribution structure and the back side redistribution structure, the molding material having a thermal conductivity greater than 40 W/m•K; a via extending through the molding compound, the via being electrically coupled to the front redistribution structure and the back redistribution structure; and an insulating layer covering sidewalls of the via, the insulating layer separating the via from the molding material. semiconductor device claim 8 , wherein the molding material has conductive particles selected from copper (Cu), silicon (Si), silver (Ag), gold (Au), iron (Fe) and tungsten (W), and wherein the molding material has the conductive particles in a concentration in the range of 70 to 95% by volume. semiconductor device claim 8 or 9 , wherein the molding material has a thermal conductivity in the range of 40 W/m•K to 100 W/m•K and wherein the insulating layer has a thermal conductivity lower than the thermal conductivity of the molding material. A semiconductor device according to any one of the preceding Claims 8 until 10 , wherein the insulating layer comprises at least one of the following elements: aluminum nitride (AlN), boron nitride (BN), beryllium oxide (BeO), diamond or aluminum oxide (Al ₂ O ₃ ). A semiconductor device according to any one of the preceding Claims 8 until 11 , further comprising an interconnect die bonded to the first integrated circuit die by metal-to-metal bonds and oxide-to-oxide bonds. A semiconductor device according to any one of the preceding Claims 8 until 12 wherein the molding material is in physical contact with the front side redistribution structure, the back side redistribution structure and the first integrated circuit die. A semiconductor device according to any one of the preceding Claims 8 until 13 wherein the insulating layer covers a top surface of the front side redistribution structure and a back side and sidewalls of the first integrated circuit, and the insulating layer covers the front side redistribution structure and the first integrated circuit which separates from the mold material. Method comprising: forming a via over a redistribution structure; bonding a semiconductor die to the redistribution structure adjacent to the via; depositing an insulating layer over the via, the redistribution structure, and the semiconductor die, the insulating layer electrically isolating the via, the redistribution structure, and the semiconductor die from one another; preparing a molding compound by mixing an epoxy and conductive fillers, the conductive fillers being 70 to 95% by volume of the molding material; applying the molding material over the insulating layer, the molding material configured to conduct heat away from the semiconductor die. procedure after claim 15 , wherein the insulating layer is deposited by a conformal deposition process. procedure after claim 15 or 16 , further comprising planarizing the molding material and the insulating layer to expose the via. Method according to any of the preceding Claims 15 until 17 wherein bonding the semiconductor die to the redistribution structure comprises: reflowing conductive connectors between the semiconductor die and the redistribution structure; and forming an underfill material enclosing the conductive connectors, wherein the insulating layer is deposited on sidewalls of the underfill material. Method according to any of the preceding Claims 15 until 17 wherein bonding the semiconductor die to the redistribution structure comprises forming oxide-to-oxide bonds and metal-to-metal bonds between the semiconductor die and the redistribution structure. Method according to any of the preceding Claims 15 until 19 wherein bonding the semiconductor die to the redistribution structure comprises bonding a diestack to the redistribution structure, the diestack comprising the semiconductor die and an interconnection die, wherein the insulating layer is further deposited on the interconnection die.

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