DE102019202870A1 - Parallelization method, parallelization tool and multi-core microcomputer - Google Patents

Abstract

A parallelization method for generating a parallel program (31a1) of a multi-core microcomputer (31) from a single program of a single-core microcomputer includes: a first scheduling procedure (10a to 10e) for analyzing a dependency on processing units (A1 to A3, B1 to B2, C1 to C4) in the single program, allocating the processing units to cores of the multi-core microcomputer, and determining a first execution plan of the processing units; and a second scheduling procedure (10f) for determining a second execution plan of an abnormality diagnosis process for a hardware of the multi-core microcomputer in an idle time of a core in which no processing unit is executed. The second execution plan is determined on the condition that other hardware used by one processing unit executed in parallel with the idle time in another core does not overlap with the hardware as a diagnostic object in the abnormality diagnosing process.

Description

The present invention relates to a parallelization method and a parallelization tool for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer, and relates to a multi-core microcomputer for executing the parallel program generated from the single program.

JP 2015-01807 A describes a parallelization compilation method as an example of a parallelization method for generating a parallel program for a multi-core microcomputer from a single program for a single-core microcomputer.

In the parallelization compilation method of this type, lexical analysis and syntactic analysis of a source code of a single program are performed for development into an intermediate language, and a dependency on several macro-tasks is analyzed and optimized using the intermediate language. In the conventional parallelization compilation method, a parallel program is generated by assigning the macro tasks to cores and scheduling the macro tasks based on the dependency of the macro tasks and an execution time of each macro task.

In recent years, particularly in the field of automotive engineering, there has been a demand to provide a monitoring device or the like for monitoring the operation of a control device to prevent a malfunction (malfunction) of a control system with respect to a control target device, thereby ensuring the reliability. However, in the parallel program generated by the conventional parallelization method, no mechanism for monitoring the operation of the control device for ensuring functional safety is considered.

It is an object of the present invention to provide a parallelization method, a parallelization tool, and a multi-core microcomputer capable of monitoring, by executing a parallel program in the multi-core microcomputer, whether a processing operation in the multi-core microcomputer is normally performed.

According to a first aspect of the present invention, a parallelization method for generating a parallel program for a multi-core microcomputer having a plurality of cores from a single program for a single-core microcomputer includes: a first scheduling procedure for analyzing a dependency of a plurality of processing units included in the single program for assigning the processing units to the cores on the basis of an analyzed dependency of the processing units, and for determining a first execution plan of the processing units; and a second scheduling procedure for determining a second execution plan of an abnormality diagnosis process for executing the abnormality diagnosis process of a hardware of the multi-core microcomputer at an idle time of one of the cores in which no processing unit is executed based on the first execution plan of the processing units in the cores Planning procedure is determined. The parallel program for executing the processing units and the abnormality diagnosis process in the cores is generated in accordance with the first and second execution plans determined by the respective first and second scheduling procedures. In the second scheduling procedure, the second execution plan of the abnormality diagnosis process for executing the abnormality diagnosis process in the idle time is determined on the condition that other hardware used by one processing unit is executed in parallel with the idle time in another one of the cores that is not the one The kernel in the idle time in which no processing unit is executed is not covered with the hardware as a diagnostic object in the abnormality diagnosing process.

As described above, in the parallelization method according to the present invention, the parallel program for executing the processing units and the abnormality diagnosis process in the cores is generated according to the execution plan of the processing units and the execution plan of the abnormality diagnosis process. For this reason, with the execution of the parallel program including the abnormality diagnosis process of the multi-core microcomputer, it is possible to diagnose whether the hardware of the multi-core microcomputer is normally operated, and it is possible to monitor whether the processing operation of the multi-core microcomputer containing the hardware used, is normal.

Specifically, in the parallelization method according to the present invention, the execution plan of the abnormality diagnosis process in the second scheduling procedure is determined such that the abnormality diagnosis process in the idle time is executed under the condition that the hardware executed by the processing unit, which is executed in parallel with the idle time, does not overlap with the hardware to be diagnosed in the abnormality diagnosing process in the core other than the core which is in the idle time, in which the processing unit is not running. This makes it possible to generate a parallel program capable of executing the abnormality diagnosis process of the hardware without affecting the execution of the unit processing using the hardware.

According to a second aspect of the present invention, a parallelization tool for generating a parallel program for a multi-core microcomputer having a plurality of cores from a single program for a single-core microcomputer includes: a first scheduling unit for analyzing a dependency of a plurality of processing units included in the single program for assigning the processing units to the cores on the basis of an analyzed dependency of the processing units, and for determining a first execution plan of the processing units; and a second scheduling unit for determining a second execution plan of an abnormality diagnosis process for executing the abnormality diagnosis process of a hardware of the multi-core microcomputer at an idle time of one of the cores in which no processing unit is executed, based on the first execution plan of the processing units in the cores Planning unit was determined. The parallel program for executing the processing units and the abnormality diagnosis process in the cores is generated in accordance with the first and second execution plans determined by the respective first and second scheduling units. The second scheduling unit determines the second execution plan of the abnormality diagnosis process for executing the abnormality diagnosis process in the idle time under the condition that other hardware used by one processing unit executed in parallel with the idle time is in one of the cores other than the one of the cores in the idle time, in which no processing unit is executed, does not overlap with the hardware as a diagnostic object in the abnormality diagnosing process.

As described above, the parallel program generated by the parallelization tool according to the present invention includes the processing units and the abnormality diagnosis process. For this reason, with the execution of the parallel program including the abnormality diagnosing process by the multi-core microcomputer, it is possible to diagnose whether the hardware of the multi-core microcomputer is normally operated, and it is possible to monitor whether the processing operation of the multi-core microcomputer containing the multi-core microcomputer Hardware used is normal.

Specifically, the second scheduling unit in the parallelization tool according to the present invention determines the execution plan of the abnormality diagnosis process such that the abnormality diagnosis process is performed in the idle time under the condition that the hardware used by the processing unit that is executed in parallel with the idle time becomes is not covered with the hardware to be diagnosed in the abnormality diagnosing process in the other than the core serving as the idle time in which the processing unit is not executed. For this reason, the parallelization tool can generate a parallel program capable of executing the abnormality diagnosis process of the hardware without affecting the execution of the unit processing using the hardware.

According to a third aspect of the present invention, a multi-core microcomputer executes a parallel program for a multi-core microcomputer having a plurality of cores, which is generated from a single program for a single-core microcomputer having a core. The parallel program includes a plurality of processing units included in the single program and an abnormality diagnosing process of a hardware of the multi-core microcomputer. The processing units are assigned to the cores. A first execution plan of the processing units is determined based on a dependency of the processing units. A second execution plan is determined for executing the abnormality diagnosis process in an idle time of one of the cores in which no processing unit is executed on the basis of the first execution plan of the processing units in the cores. The second execution plan is determined to execute the abnormality diagnosis process in the idle time under the condition that other hardware used by one processing unit executed in parallel with the idle time in another of the cores than the one of the cores in which none Processing does not overlap with the hardware as a diagnostic object in the abnormality diagnosis process.

As described above, since the parallel program includes the abnormality diagnosis process, by executing the parallel program, the multi-core microcomputer can diagnose whether the hardware of the multi-core microcomputer is being normally operated, and can also monitor whether the Processing operation by the multi-core microcomputer using the hardware is normal.

In the abnormality diagnosing process, the execution schedule in the parallel program is determined such that the abnormality diagnosing process is executed in the idle time under the condition that the hardware used by the processing unit that is executed in parallel with the idle time does not overlap with the hardware to be diagnosed in the abnormality diagnosis process in the core other than the core serving as the idle time in which the processing unit is not executed. For this reason, with the execution of the parallel program, the multi-core microcomputer can execute the abnormality diagnosis process of the hardware without affecting the execution of the unit processing using the hardware.

• 1 ein Blockdiagramm, das eine schematische Konfiguration eines Computers als ein automatisches Parallelisierungswerkzeug gemäß einer Ausführungsform zeigt;
• 2 ein Blockdiagramm, das die Funktionalität des Computers als das automatische Parallelisierungswerkzeug gemäß der Ausführungsform darstellt;
• 3 ein Diagramm, das ein Beispiel des Ergebnisses eines Analysierens einer Abhängigkeit einer jeweiligen Verarbeitungseinheit für eine jeweilige Aufgabe in einem einzelnen Programm zeigt;
• 4 ein Diagramm, das ein Beispiel einer Planung der Zuordnung von mehreren Verarbeitungseinheiten zu mehreren Kernen und einer Ausführungsreihenfolge einer ersten Planungseinheit zeigt;
• 5 ein Flussdiagramm, das einen Planaktualisierungsprozess zum zusätzlichen Einfügen eines Abnormitätsüberwachungsprozesses zeigt, der von einer zweiten Planungseinheit auszuführen ist;
• 6 ein Diagramm, das ein Ergebnis eines Einfügens des Abnormitätsdiagnoseprozesses in eine Leerlaufzeit in dem Ausführungsplan von mehreren Verarbeitungseinheiten und eines Aktualisierens des Ausführungsplans durch die zweite Planungseinheit zeigt; und
• 7 ein Blockdiagramm, das eine schematische Konfiguration einer fahrzeugeigenen Vorrichtung gemäß der Ausführungsform zeigt.

The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings. Show it:

• 1 10 is a block diagram showing a schematic configuration of a computer as an automatic parallelizing tool according to an embodiment;
• 2 a block diagram illustrating the functionality of the computer as the automatic parallelization tool according to the embodiment;
• 3 Fig. 12 is a diagram showing an example of the result of analyzing a dependency of each processing unit on a respective task in a single program;
• 4 Fig. 12 is a diagram showing an example of planning the assignment of multiple processing units to multiple cores and an execution order of a first scheduling unit;
• 5 5 is a flowchart showing a schedule updating process for additionally inserting an abnormality monitoring process to be executed by a second scheduling unit;
• 6 12 is a diagram showing a result of inserting the abnormality diagnosis process into an idle time in the execution plan of a plurality of processing units and updating the execution plan by the second scheduling unit; and
• 7 10 is a block diagram showing a schematic configuration of an on-vehicle device according to the embodiment.

Hereinafter, embodiments of the invention will be described with reference to the drawings. In the present embodiment, an example will be described in which a computer 10 as a parallelization tool a parallel program 31a1 That for a multi-core microcomputer 31 is parallelized, the first core 31c and a second core 31d generated from a single program for a single-core microcomputer having a core. The number of cores that are in the multi-core microcomputer 31 is not limited to two, but may be three or more.

As described above, there is a background for generating the parallel program 31a1 the individual program tends to increase the number of programs year by year due to the refinement of a controller, but there is no limit to improving the performance of the single processor. In other words, for example, when trying to improve the processing capacity by increasing an operating frequency of the single processor, there is no limit to an increase in the operating frequency, and an increase in the operating frequency leads to an increase in the amount of heat generated and an increase in power consumption. For this reason, it is considered effective to use a multi-core microcomputer for improving the processing capacity by increasing the number of cores.

In this regard, if a developer of the program has to appropriately allocate processing to these cores and plan the processing so as to maximize the capability of the multi-core, the burden of developing the program increases. To reduce the development burden of such a program, it is technically significant to have the parallel program 31a1 automatically generate from the single program. In addition, the parallel program 31a1 automatically generated from the single program, allowing existing software items developed for the single processor to be effectively used.

First, a configuration of the computer 10 regarding 1 described. The computer 10 corresponds to a parallelization tool for performing a parallelization method and generates a parallel program 31a1 from a single program. In the present embodiment, the computer generates 10 the parallel program 31a1 written in a C language based on a single program written in the C language. For this reason, the parallel program 31a1 ' that in a ROM 31a an on-vehicle device 30 (Multi-core microcomputer 31 ) and from the multi-core microcomputer 31 is executed, further through a compiler 20 compiled and translated into binary codes as in 2 is shown.

However, the present invention is not limited to the above configuration. The single program may be written in a programming language different from the C language. The parallel program 31a1 For example, it may be written in an intermediate language that is used when analyzing a single program. Alternatively, the computer 10 generate both a parallel program written in the C language and a parallel program written in the intermediate language. Besides, the computer can 10 a function of the compiler 20 take over and the parallel program 31a1 'generate directly in the binary code.

As it is in 1 shown, the computer contains 10 an ad 11 , an HDD (hard disk) 12 , a CPU 13 , a ROM 14 , a ram 15 , an input device or input device 16 , a reading unit 17 and similar. The computer 10 can store a stored content in the storage medium 18 is stored, by means of the reading unit 17 read. As it is in 1 For example, an automatic parallelization compiler is shown 1 in the storage medium 18 saved. Because the computer 10 and the storage medium 18 the same as a personal computer 100 and a storage medium 180 are described in JP 2015 - 01 807 A, reference is made to JP 2015 - 01 807 A for details.

The automatic parallelization compiler 1 is a software for causing the computer 10 a procedure for generating the parallel program 31a1 performs. Therefore, the computer can 10 the parallelization method by the automatic parallelization compiler 1 To run. In other words, the automatic parallelization compiler 1 is a program that contains a parallelization procedure. The computer 10 runs the automatic parallelization compiler 1 as a parallelization tool to the parallel program 31a1 to create.

The following is with reference to 2 each function and a processing procedure for generating the parallel program 31a1 from a single program that is in the computer 10 as the parallelization tool is described. 2 is a diagram showing each function and the processing procedure of the computer 10 as function blocks shows. As it is in 2 is shown, the computer instructs 10 Functions as a lexical analysis unit 10a , syntactic-semantic analysis unit 10b , Dependency analysis unit 10c , Core allocation unit 10d , first planning unit 10e and second planning unit 10f on.

As it is in 2 shown, the computer analyzes 10 According to the present embodiment, the entire single program for controlling a control target device is not concurrently generated to generate a parallel program, but generates the parallel program for the single program which is divided for each independent processing function (task). The single program, which is subdivided for each task, contains several processing units and can realize the processing function intended for a particular task with the execution of the processing units. As described above, the processing units cooperate with each other for the purpose of realizing a destination processing function, and include, for example, a subsequent processing unit that refers to variable data processed in a previous processing unit, a subsequent processing unit to be executed after a condition branch of the previous processing unit , and similar.

In this example, the processing unit refers to a core configuration unit or function that is a minimum unit at the time of allocation to a respective core. The core configuration unit may be referred to as a processing block, macro task, or just a processing unit. A relationship between the core configuration unit and the function satisfies: Core configuration unit ≥ function. In other words, the function may be a core configuration unit itself or may be a higher-level function or a subordinate function included in the core configuration unit.

The lexical analysis unit 10a and the syntactic-semantic analysis unit 10b carry out a lexical analysis, an analysis of a syntax and a semantics, which are intended for a source code of the individual program, which in the C Language is written, and develop the source code in the intermediate language. The intermediate language used by the lexical analysis unit 10a and the syntactic-semantic analysis unit 10b is developed contains general commands. As the lexical analysis unit 10a and the syntactic-semantic analysis unit 10b FE3 the JP 2015 - 01 807 A will be in terms of details on the JP 2015 - 01 807 A directed.

The dependency analysis unit 10c analyzes the dependency of the processing unit (s), which is included in the single program extended into the intermediate language and extracts the processing unit (s) that can be executed in parallel. The dependency includes a data dependency such as a processing unit to be executed later with reference to variable data to be updated in a processing unit to be executed earlier, and a control dependency such as a process unit to be later executed as a conditional branch target of a processing unit to be executed earlier. The processing units having such a dependency must be executed in a processing order according to the dependency. In the present embodiment, the single program, which is divided for each task as described above, is to be parallelized. The processing units included in the single program divided for each task have a data dependency and a control dependency.

In the example that is in 3 For example, task A includes processing units A1 to A3 , and the processing units A2 and A3 have a dependency on the processing unit A1 on. The processing unit A2 and the processing unit A3 are processing units that can be executed in parallel. The task B contains processing units B1 to B2 , and the processing unit B2 has a dependency on the processing unit B1 on. It also contains the task C processing units C1 to C4 , wherein the processing unit C2 a dependency on the processing unit C1 and the processing unit C4 a dependency on the processing unit C3 having. The processing units C1 and C2 and the processing units C3 and C4 can be executed in parallel.

The core allocation unit 10d maps multiple processing units to the first core 31c and the second core 31d on the basis of the analysis result, that of the dependency analysis unit 10c is obtained. Here assigns the core allocation unit 10d for example, the processing units are such that the processing units that can be executed in parallel are of the first core 31c and the second core 31d be executed in parallel. Based on 3 will be an example of assignment of the processing units A1 to A3 . B1 to B2 and C1 to C4 to the first core 31c and the second core 31d when analyzing the dependency of the processing units for each task is described. First, the core allocation unit maps 10d under the processing units A1 to A3 the task A the processing units A1 and A2 the first core 31c and assigns the processing unit A3 parallel to the processing unit A2 executable, the second core 31d to. The core allocation unit 10d maps the processing units B1 and B2 the task B the first core 31c to, assigns to the processing units C1 to C4 for the task C the processing units C1 and C2 the first core 31c and assigns the processing units C3 and C4 parallel to the processing units C1 and C2 can be performed, the second core 31d to.

The first planning unit 10e leads planning or scheduling of the processing units A1 to A3 . B1 to B2 and C1 to C4 through, the first core 31c and the second core 31d assigned. In particular, the first planning unit determines 10e the execution plans of the processing units A1 to A3 . B1 to B2 and C1 to C4 that the first core 31c and the second core 31d based on the execution times and dependencies of the processing units A1 to A3 . B1 to B2 and C1 to C4 , The dependency analysis unit 10c , the core allocation unit 10d and the first planning unit 10e correspond MP5 the JP 2015 - 01 807 A , and so on the details JP 2015 - 01 807 A directed.

4 shows an example of a planning result of the first planning unit 10e , As described above, each of the processing units has A1 to A3 Task A has a dependency according to which the processing unit A2 and the processing unit A3 from the processing unit A1 depend. According to the example in 4 is shown, the processing unit A3 that in the second core 31d is executed, extending from the first core 31c differs in which the processing unit A1 is executed, scheduled to execute by a synchronization process upon completion of the processing unit A1 starts. The synchronization process can be realized, for example, in that the first core 31c Completion information in the RAM 31b writes when the processing unit A1 has ended, and in that the second core 31d the execution of the processing unit A3 starts when the termination information is out of RAM 31b be read out and confirmed. Alternatively, the first core 31c as a synchronization process the second core 31d a termination signal after the completion of the processing unit A1 report.

In the example that is in 4 is shown after completion of each of the processing units A1 to A3 the task A the task to be performed in the task B changed, and the processing units B1 to B2 the task B be for the Execution planned. After finishing the processing units B1 to B2 the task B becomes the task to be performed C changed, and the processing units C1 to C4 the task C are scheduled for execution.

In the embodiment which is in 4 is shown, the processing unit A1 Task A has a function for accessing variable data stored in the RAM 31b are saved and by a symbol P and to write the variable data. The processing unit A2 Task A has a function of accessing variable data stored in the RAM 31b are stored and by the characters X and Z and writing the variable data. In addition, the processing unit instructs B1 the task B a function for accessing variable data represented by the symbol W on, to perform a write, and the processing unit B2 has a function for accessing variable data represented by the symbol Q be represented to perform a letter. However, the access to the respective variable data is not limited to the above-described example and includes not only the case of a function for writing but also a case of a function for reading.

As it is in 2 shown, the computer contains 10 According to the present embodiment, a second planning unit 10f , The second planning unit 10f adds an abnormality diagnosis process to a hardware of the multi-core microcomputer 31 into an idle time in an execution plan of the processing units that make up the parallel program that is the first scheduling unit 10e has been planned and updates the execution plan of the parallel program. In other words, the second planning unit 10f determines the execution plan of the abnormality diagnosis process based on the execution plan of the processing units in the first core 31c and the second core 31d that of the first planning unit 10e was determined, such that the abnormality diagnosis process of the hardware of the multi-core microcomputer 31 in parallel with the idle time of the core in which no processing unit is executed. In other words, the second planning unit 10f (the computer 10 ) holds a program as an abnormality diagnosis process to be inserted, searches for an idle time during which the abnormality diagnosis process can be executed, and associates the abnormality diagnosis process with the searched idle time. As a result contains the parallel program 31a1 , its execution plan by the second planning unit 10f has been updated, the abnormality diagnosis process of the hardware of the multi-core microcomputer 31 in addition to the processing units of a respective task included in the single program.

The following is the abnormality diagnosis process of the hardware of the multi-core microcomputer 31 described. The abnormality diagnosing process is for diagnosing whether there is an abnormality in the hardware of the multi-core microcomputer 31 occurred, which is the parallel program 31a1 performs. As described above, the computer generates 10 serving as the parallelization tool according to the present embodiment, the parallel program 31a1 including the abnormality diagnosing process for diagnosing the abnormality of the hardware of the multi-core microcomputer 31 contains. For this reason, the multi-core microcomputer 31 with the execution of the generated parallel program 31a1 diagnose whether an abnormality has occurred in their own hardware and the hardware is normally operated, and thus can monitor whether the processing operation of the multi-core microcomputer 31 that uses the appropriate hardware is done normally.

As a specific example of the hardware abnormality diagnosing process, a rewrite checking process (overwrite checking process) of a RAM 31b to be named. In other words, the hardware to be diagnosed in the abnormality diagnosis process is a RAM 31b , the rewritable memory of the multi-core microcomputer 31 and the rewrite verification process as the abnormality diagnosis process checks whether the data is normal in the RAM 31b can be written. The rewrite verification process may be performed, for example, with the following four steps. First, as a first step, a value of the variable data is extracted from a suitable area of the RAM 31b in which the value of the variable data to be diagnosed is stored, and the variable data is saved in another storage area. Subsequently, as a second step, a test value is written in the appropriate area from which the variable data was read out. Then, as a third step, the written test value is read out of the appropriate range, and it is determined whether the read-out value coincides with the test value. Finally, as a fourth step, the saved value is used to rewrite the appropriate range to the value of the original variable data. In this way, the rewrite checking process checks if the memory area of the RAM 31b , which is used to store the variable data, can be individually rewritten or rewritten.

In the present embodiment, information (RAM information) 19 in terms of the memory area of the RAM 31b who the Rewrite verification needed for the second planning unit 10f provided. More specifically, in the single program, information in which symbol data used as a symbol indicating the variable data is collected is the second scheduling unit 10f as RAM information 19 fed, who need the rewrite verification. If the parallel program 31a1 is written in the C language or the intermediate language, the respective variable data is designated by a corresponding symbol. Which memory area of the RAM 31b of the multi-core microcomputer 31 The variable data represented by the symbols stores is only through the compiler 20 by converting the functions, the symbols of the variables and the like into special address information. For this reason, the second planning unit 10f Information provided in which symbols indicating the variable data as RAM information 19 are grouped, who need the rewrite check.

As RAM information 19 Those who need the rewrite check are grouped together symbols indicating the variable data to be used when the single program is generated, and the grouped information can be used. In this case, the grouped information can be considered the RAM information 19 in the computer 10 be entered. If the computer 10 the individual program can analyze the computer 10 alternatively, extract and group the symbols indicating the used variable data and the extracted symbols as RAM information 19 use. As a result, in the rewrite checking process, it can be checked whether the memory area used for storing the variable data defined by the single program can be individually rewritten.

The second planning unit 10f may perform a common rewrite verification process for all the variable data or may perform a different rewrite verification process for the respective variable data. For example, the test values may be different, or the number of checks may differ for different rewrite verification processes. In this case, the second planning unit 10f automatically map the different rewrite verification processes to the different variable data, or the RAM information 19 that in the second planning unit 10f may include information designating the rewrite verification process to be used for the respective variable data.

The memory area of the RAM 31b to be subjected to the rewrite checking process may include not only a memory area in which the variable data used in the single program is stored, but also a memory area in which other data of the RAM is stored 31b are stored. In contrast, not all memory areas of the RAM 31b in which the variable data is stored undergo the rewrite checking process, but the storage areas of the variable data which are less affected can be excluded from the rewrite checking process even if the data is damaged.

The following is an example of special processing contents of the schedule update process in which the second scheduling unit 10f additionally the hardware abnormality monitoring process into the planned result of the first planning unit 10e to update the plan, with reference to the flowchart of 5 described.

First, select the second planning unit 10f in step S100 an information part of the RAM from the inputted RAM information 19 out. Subsequently, in step S110 time information necessary for executing the abnormality diagnosis process for verifying the rewriting of the memory area of the RAM 31b is required, in which the selected information of the RAM, that is, the symbol representing the selected variable data, is stored. The time information needed to execute the abnormality diagnosis process is determined in advance and prepared as data together with the abnormality diagnosis process.

In step S120 becomes in the first core 31c and in the second core 31d the idle time of the core in which no processing unit is executed, based on the planning result of the first planning unit 10e searched. Then leads the second planning unit 10f the processing described below is based on the searched idle time of the one core.

First, in step S130 determines whether the processing unit to be executed by another core is in the same memory area of the RAM 31b which is to be diagnosed in the abnormality diagnosis process at the sought idle time of the one core. In other words, it is determined whether or not the processing unit to be executed in another core performs processing on the same symbol as the symbol indicating the variable data described in step S100 were selected. In the example that is in 6 shown is a third one Abnormitätsdiagnoseprozess CK3 from the first to fourth abnormality diagnosis processes CK1 to CK4 for the symbol W providing the variable data. It is assumed that it is determined whether the third abnormality diagnosis process CK3 in the idle time of the second core 31d can be inserted, which corresponds to a period of time during which the processing unit B1 in the first core 31c as the other core is performed. As it is in 6 is shown contains the processing unit B1 a process of writing the symbol W that specifies the variable data. Therefore, a RAM memory area overlapping in the third abnormality diagnosing process overlaps CK3 to diagnose, and a RAM memory area pointed to by the processing unit B1 is accessed. If the third abnormality diagnosis process CK3 in the idle time of the second core 31d is inserted as a destination, for this reason, the RAM access in the processing unit B1 in the first core 31c by the rewriting process of the RAM memory area by the third abnormality diagnosing process CK3 influenced, and there is a possibility that the processing unit B1 can not be done normally.

Therefore, if in the determination process in step S130 it is determined that the memory area of the RAM 31b is provided for the abnormality diagnosis process and the memory area of the RAM 31b is accessed by the processing units to be executed in another kernel (positive determination result), the processing proceeds to the step S150 , In step S150 It is assumed that the idle time of the core, in step S120 is not suitable for performing the rewrite checking process of the RAM memory area for the selected variable data, and a next idle time is searched for. Then the processing in step S130 again with the next idle time searched for as the destination.

In the example that is in 6 For example, it is assumed that as the next idle time for inserting the third abnormality diagnosis process CK3 the idle time of the second core 31d , which corresponds to the length of time during which the processing unit B2 in the first core 31c is performed, searched or found. In this case, the processing unit contains B2 just a process to write the symbol Q that specifies the variable data. For this reason, the result of the determination in the determination processing is in step S130 negative such that the memory area of the RAM 31b to be subjected to the abnormality diagnosing process does not match the memory area of the RAM 31b covered by the processing unit being executed in the other core. In this case, the second planning unit proceeds 10f for processing in step S140 ,

In step S140 determining whether the idle time of the searched kernel is shorter than the time required to execute the abnormality diagnosing process, and in step S110 was obtained. When it is determined that the idle time is shorter (positive determination result), the execution of the abnormality diagnosis process in the idle time of the core as a destination can not be completed. For this reason, the process moves to the step S150 and the idle time of the core is changed by searching for the idle time of the next core. If, on the other hand, in the determination process in step S140 is determined that the idle time of the core is not shorter (negative determination result), the process goes to step S160 ,

In step S160 adds the second planning unit 10f An abnormality diagnosing process for verifying the rewriting of the RAM memory area for the selected variable data into the idle time of the specific core and updates it from the first scheduling unit 10e certain plan. Therefore, the computer can 10 as a parallelization tool with the generation of the parallel program 31a1 According to the updated plans, generate the parallel program capable of rewriting the memory area of the RAM 31b without affecting the execution of unit processing in another core.

In the next step S170 It is determined whether another core for executing a processing unit for accessing the same RAM memory area as the abnormality diagnosis process before and after the idle time of the core into which the abnormality diagnosis process has been inserted is scheduled. If it is determined that another core is planned in the above manner (positive determination result), the process goes to the step S180 , On the other hand, if it is determined that no other core is planned in the above manner (negative determination result), the process goes to the step S200 , In step S180 It is determined whether the synchronization process between the inserted abnormality diagnosis process and the processing unit for accessing the same RAM memory area is set before and after the abnormality diagnosis process. When it is determined that the synchronization process is not set, the process goes to step S190 , On the other hand, when it is determined that the synchronization process is set, the process goes to the step S200 ,

In step S190 the synchronization process is added between the abnormality diagnosis process and the processing unit for accessing the same RAM memory area before and after the abnormality diagnosis process. With the addition of the synchronization process, if the parallel program 31a1 is executed, the abnormality diagnosing process is executed after the unit processing for accessing the same RAM memory area is completed and / or the unit processing for accessing the same RAM memory area is executed after the abnormality diagnosis process is completed. As a result, the execution time of the abnormality diagnosis process can be reliably prevented from overlapping with the execution time of the unit processing for accessing the RAM memory area to be diagnosed in the abnormality diagnosis process.

For example, if the execution plan of the processing units A1 to A3 . B1 to B2 and C1 to C4 as in 3 shown by the first planning unit 10e is determined, it is assumed that the first abnormality diagnosis process CK1 in the idle time of the second core 31d is inserted according to the period during which the processing unit A1 in the first core 31c is done as it is in 6 is shown. As it is in 6 is shown in this case after the processing of the first abnormality diagnosis process CK1 the first core 31c for the execution of the processing unit A2 which plans a process for accessing the same RAM memory area as the first abnormality diagnosing process CK1 contains. For this reason, the result of the determination in step S170 positive. However, the synchronization process already occurred between the first abnormality diagnosis process CK1 and the processing unit A2 established. As the result of the determination in step S180 is positive, therefore, the process in step S190 not executed.

If, on the other hand, as it is in 6 3, the third abnormality diagnosis process is shown CK3 in the idle time of the second core 31d is inserted, which corresponds to the length of time during which the processing unit B2 in the first core 31c is performed, the processing unit B1 including the processing for accessing the same RAM memory area for execution in the first core 31c before the execution of the third abnormality diagnosis process CK3 planned. As it is in 3 In addition, there is no synchronization process between the processing unit B1 and the processing unit B2 set or fixed. For this reason, in step S180 determines that the synchronization process between the third abnormality diagnosis process CK3 and the processing unit B1 is not fixed. Accordingly, the processing in step S190 executed, and the synchronization process is between the processing unit B1 and the third abnormality diagnosis process CK3 set as it is in 6 is shown.

Finally, the second planning unit determines 10f in step S200 whether the selection of all RAM information (all symbols corresponding to all variable data) in the given RAM information 19 contained, was terminated. If it is determined that the selection of all the RAM information has not yet been completed, the process returns to the processing in step S100 and a RAM information item is selected from the RAM pieces of information that has not yet been selected. Then the processing is in the steps S110 to S200 repeated as described above.

The following is the configuration of the on-vehicle device 30 described. As it is in 7 shown contains the on-board device 30 a multi-core microcomputer 31 , a communication unit 32 , a sensor unit 33 and an input-output port 34 , The multi-core microcomputer 31 contains a ROM 31a , a ram 31b , a first core 31c and a second core 31d , The on-board device 30 For example, it may be used for an engine control device or a hybrid control device mounted on a motor vehicle. The following describes an example in which the on-vehicle device 30 is used for an engine control device.

The first core 31c and the second core 31d run a parallel program 31a1 'in the ROM 31a is stored to perform, for example, an engine control. More specifically, control the first core 31c and the second core 31d a fuel injection amount, an ignition timing, an intake air amount and the like by driving the respective actuators as control target devices. The ROM 31a also stores constant data and the like used in the engine control. The RAM 31b temporarily stores variable data and the like, and it is accessed as needed when the multi-core microcomputer 31 the parallel program 31a1 'executes. The communication unit 32 communicates with another ECU connected via an in-vehicle LAN or the like. The sensor unit 33 contains various sensors for detecting a state of the internal combustion engine. The input-output port 34 transmits and receives various signals for controlling the internal combustion engine.

The parallel program 31a1 'from the multi-core microcomputer 31 the on-board device 30 is executed contains the abnormality diagnosis process of the hardware of the multi-core microcomputer 31 as described above. For this reason, the multi-core microcomputer 31 with the execution of the parallel program 31a1 'Diagnose if the hardware of the multi-core microcomputer 31 is operated normally. As a result, the multi-core microcomputer 31 monitor whether the processing plant, the hardware of the multi-core microcomputer 31 used, performed normally. When a RAM abnormality is detected by the rewrite verification process as the abnormality diagnosis process, the multi-core microcomputer can 31 the use of the RAM memory area in which the abnormality is detected can prevent or prevent the abnormality processing such as resetting the multi-core microcomputer 31 or perform the fail-safe processing such as a fuel cut.

In the abnormality diagnosis process, the execution plan is determined such that the abnormality diagnosis process in the idle time in the parallel program 31a1 is executed under the condition that the hardware used by the processing unit that is executed in parallel with the idle time does not overlap with the hardware to be diagnosed in the abnormality diagnosing process in the core other than the core, which is referred to as the idle time is used in which the processing unit is not executed. For this reason, the multi-core microcomputer 31 with the execution of the parallel program 31a1 ' perform the abnormality diagnosis process of the hardware without affecting the execution of the unit processing using the hardware.

In a case where a unit processing using hardware to be diagnosed in the abnormality diagnosis process is scheduled to be executed for at least a period of time before and after execution of the abnormality diagnosis process in cores other than a core executing the abnormality diagnosis process, contains that from the multi-core microcomputer 31 to be executed parallel program 31a1 ' a synchronization process for starting execution of the abnormality diagnosis process after the unit processing using the hardware is completed, and / or a synchronization process for starting execution of the unit processing using the hardware after the abnormality diagnosis process is ended. If the multi-core microcomputer 31 the parallel program 31a1 ' For this reason, the execution time of the abnormality diagnosis process can be prevented from overlapping with the execution time of the unit processing using the hardware to be diagnosed by the abnormality diagnosis process.

Above, a preferred embodiment of the present invention has been described. However, the present invention is not limited to the above embodiments, but various modifications are possible without departing from the scope of the invention.

(Modification 1)

For example, in the embodiment described above, an example was described in which the rewrite checking process of the RAM 31b is performed as an abnormality diagnosing process. However, the abnormality diagnosing process may be a process of diagnosing abnormality of a hardware of the multi-core microcomputer 31 its not the ram 31b is. In the abnormality diagnosing process, for example, a writable flash ROM may be used as a diagnosis target. In addition, the abnormality diagnosing process may be a process of checking whether a counter circuit or an A / D converter operating in the multi-core microcomputer 31 is installed, is operated as a diagnostic target normal.

Note that a flowchart or the processing of the flowchart of the present application includes sections (also referred to as steps) each indicated by S100, for example. In addition, each section can be divided into several subsections, while multiple sections can be combined into a single section. In addition, any portion so configured may also be referred to as a device, module, or device.

While the present invention has been described with respect to embodiments thereof, it is to be understood that the invention is not limited to the embodiments and constructions. The present invention covers various modifications and equivalent arrangements. In addition to the various combinations and configurations, other configurations and combinations including more, less or a single element are also possible within the scope of the present invention.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• JP 201501807A [0026, 0030]

Claims (16)

A parallelization method for generating a parallel program (31a1) for a multi-core microcomputer (31) having a plurality of cores (31c, 31d) from a single program for a single-core microcomputer, the method comprising: a first scheduling procedure (10a to 10e) for analyzing a dependency of a plurality of processing units (A1 to A3, B1 to B2, C1 to C4) included in the single program for allocating the processing units to the cores on the basis of an analyzed dependency the processing units and for determining a first execution plan of the processing units; and a second scheduling procedure (10f) for determining a second execution plan of an abnormality diagnosing process for executing the abnormality diagnosis process of a hardware of the multi-core microcomputer at an idle time of one of the cores in which no processing unit is executed on the basis of the first execution plan of the processing units in the cores the first planning procedure is determined, where generating the parallel program for executing the processing units and the abnormality diagnosis process in the cores according to the first and second execution schedules determined by the respective first and second scheduling procedures; and the second execution plan of the abnormality diagnosis process is determined in the second scheduling procedure such that the abnormality diagnosis process in the idle time is executed under the condition that another hardware executed by one processing unit that is executed in parallel with the idle time is in one of the cores other than the one one of the cores in the idle time in which no processing unit is executed is not covered with the hardware as a diagnostic object in the abnormality diagnosis process. Parallelization method according to Claim 1 wherein the second execution plan of the abnormality diagnosis process in the second scheduling procedure is determined such that the abnormality diagnosis process is performed in the idle time under the condition that a time required for executing the abnormality diagnosis process is shorter than the idle time. Parallelization method according to Claim 1 or 2 wherein, in a case where, during at least one of a period before and a time after execution of the abnormality diagnosis process in another of the cores than the one of the cores executing the abnormality diagnosis process, a processing unit that detects the hardware as a diagnosis object in the The second scheduling procedure also includes: adding at least one of a synchronization process for starting execution of the abnormality diagnosis process after termination of the processing unit that uses the hardware and a synchronization process for starting the execution of the processing unit that processes the hardware used after completing the abnormality diagnostic process. Parallelization method according to one of Claims 1 to 3 wherein the hardware as the diagnostic object in the abnormality diagnosis process is a rewritable memory (31b) of the multi-core microcomputer; and the abnormality diagnosing process is a rewrite checking process for checking whether data can be normally written in the rewritable memory. Parallelization method according to Claim 4 wherein the rewrite checking process checks whether a memory area used for storing data defined by the single program is individually rewritable. A parallelization tool for generating a parallel program (31a1) for a multi-core microcomputer (31) having a plurality of cores (31c, 31d) from a single program for a single-core microcomputer, said parallelization tool comprising: a first planning unit (10a-10e) for analyzing a dependency of a plurality of processing units (A1 to A3, B1 to B2, C1 to C4) included in the single program for allocating the processing units to the cores on the basis of an analyzed dependency of the processing units, and for determining a first execution plan processing units; and a second scheduling unit (10f) for determining a second execution schedule of an abnormality diagnosis process for executing the abnormality diagnosis process of a hardware of the multi-core microcomputer at an idle time of one of the cores in which no processing unit is executed on the basis of the first execution plan of the processing units in the cores is determined by the first scheduling unit, wherein the parallel program for executing the processing units and the abnormality diagnosis process is generated in the cores according to the first and second execution schedules determined by the respective first and second scheduling units; and the second scheduling unit determines the second execution plan of the abnormality diagnosis process for executing the abnormality diagnosis process in the idle time under the condition that another hardware used by one processing unit that is executed in parallel with the idle time is in one of the cores other than the one of the cores Cores in the idle time, in which no processing unit is executed, not covered with the hardware as a diagnostic object in the abnormality diagnosis process. Parallelization tool after Claim 6 wherein the second scheduling unit determines the second execution plan of the abnormality diagnosis process for executing the abnormality diagnosis process in the idle time under the condition that a time required for executing the abnormality diagnosis process is shorter than the idle time. Parallelization tool after Claim 6 or 7 wherein, in a case where at least one of a time period before and a time after execution of the abnormality diagnosis process in another of the cores than the one of the cores executing the abnormality diagnosis process, a processing unit that uses the hardware as the diagnosis object in the The second planning unit uses at least one of a synchronization process for starting the execution of the abnormality diagnosis process after completion of the processing unit that uses the hardware and a synchronization process for starting the execution of the processing unit that uses the hardware after the abnormality diagnosis process scheduled to execute Terminate the abnormality diagnostic process. Parallelization tool according to one of Claims 6 to 8th wherein the hardware as the diagnostic object in the abnormality diagnosis process is a rewritable memory (31b) of the multi-core microcomputer; and the abnormality diagnosing process is a rewrite checking process for checking whether data can be normally written in the rewritable memory. Parallelization tool after Claim 9 wherein the rewrite checking process checks whether a memory area used for storing data defined by the single program is individually rewritable. A multi-core microcomputer for executing a parallel program (31a1) for a multi-core microcomputer (31) having a plurality of cores (31c, 31d) from a single program for a single-core microcomputer having a core, wherein the parallel program includes a plurality of processing units (A1 to A3, B1 to B2, C1 to C4) included in the single program and an abnormality diagnosing process of a hardware of the multi-core microcomputer; the processing units are assigned to the cores; determining a first execution plan of the processing units based on a dependency of the processing units; determining a second execution plan based on the first execution plan of the processing units in the cores such that the abnormality diagnosis process is executed in an idle time of one of the cores in which no processing unit is executed; and the second execution plan is determined such that the abnormality diagnosis process in the idle time is executed under the condition that another hardware used by one processing unit that is executed in parallel with the idle time is in one of the cores other than the one of the cores in which no processing unit is executed, is not covered with the hardware as a diagnostic object in the abnormality diagnosis process. Multicore microcomputer after Claim 11 wherein the multi-core microcomputer is used for an on-vehicle device (30) for controlling an on-vehicle device mounted in a vehicle; and the on-vehicle device is controlled by executing the parallel program. Multicore microcomputer after Claim 11 or 12 wherein the second execution plan of the abnormality diagnosis process is determined such that the abnormality diagnosis process in the idle time is performed under the condition that a time required for executing the abnormality diagnosis process is shorter than the idle time. Multicore microcomputer after one of the Claims 11 to 13 wherein, in a case where at least one of a period before and a time after execution of the abnormality diagnosis process, a processing unit in another of the cores than the core executing the abnormality diagnosis process that uses the hardware as the diagnosis object in the abnormality diagnosis process the execution is scheduled, the parallel program of at least one of a synchronization process for starting the execution of the abnormality diagnosis process after completion of the A processing unit using the hardware and a synchronization process for starting the execution of the processing unit using the hardware after completing the abnormality diagnosis process; and the multi-core microcomputer executes the synchronization process to prevent an execution period of the abnormality diagnosis process from overlapping with an execution period of the processing unit that uses the hardware as the diagnosis object in the abnormality diagnosis process. Multicore microcomputer after one of the Claims 11 to 14 wherein the hardware as the diagnostic object in the abnormality diagnosis process is a rewritable memory (31b) of the multi-core microcomputer; and the abnormality diagnosing process is a rewrite checking process for checking whether data can be normally written in the rewritable memory. Multicore microcomputer after Claim 15 wherein the rewrite checking process checks whether a memory area used for storing data defined by the single program is individually rewritable.

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