DE102019120605B4 - MEMORY CIRCUIT AND METHOD OF PRODUCTION THEREOF - Google Patents

Abstract

A memory circuit comprising: a first sense device (102) coupled to a first bit line (BL, 420a), the first sense device comprising: a first transistor (N3, N3-0) coupled to a first word line (WLR, WLRo ) connected is; anda second transistor (N4, N4-0) connected to the first word line (WLR, WLRo); anda first programming device (104) connected to the first reading device (102), the first programming device (104) comprising:a third transistor (N1, N1-0) connected to a second word line (WLP, WLPo). ; anda fourth transistor (N2, N2-0) connected to the second word line (WLP, WLPo);wherein:the first transistor (N3, N3-0) has a first terminal, a second terminal and a third terminal; andthe second transistor (N4, N4-0) has a first terminal, a second terminal and a third terminal,the first terminal of the first transistor (N3, N3-0), the first terminal of the second transistor (N4, N4-0) and the first word line (WLR, WLRo) are connected together,the second terminal of the first transistor (N3, N3-0) is connected to the second terminal of the second transistor (N4, N4-0), andthe third terminal of the first transistor ( N3, N3-0) is connected to at least the third connection of the second transistor (N4, N4-0).

Description

BACKGROUND

The semiconductor integrated circuit (IC) industry has spawned a wide variety of devices to solve problems in a number of different areas. Some of these devices, such as memory cells, are designed to store data. Non-volatile memory is a type of memory that is programmed to record data therein. A non-volatile memory is able to retain data after the power supply is interrupted. There are various types of non-volatile memory, including, for example, memory that can be programmed many times (also referred to as MTP memory), memory that can be programmed once (OTP), or the like. As memory cells become progressively smaller and more complex, the resistance of conductive lines within those devices is also changing, affecting the characteristics of those devices and the overall memory cell performance.

the U.S. 2013/0 077 376 A1 describes a one-time programmable memory cell consisting of six transistors. In this case, a first transistor, a second transistor and a third transistor are connected in series, so that these transistors form a first series circuit. A fourth transistor, a fifth transistor and a sixth transistor are also connected in series and form a second series circuit. The first series connection and the second series connection of the memory cell are connected in parallel between a BIAS voltage and a bit line. The first and fourth transistors are used to control whether the BIAS voltage is applied to the second and fifth transistors. The gates of the second and fourth transistors are connected to a programming word line. The gates of the third and sixth transistors are connected to a read word line.

the U.S. 2017/0 207 228 A1 describes a non-volatile memory structure including a first PMOS transistor and a first floating gate transistor on a first active area in a substrate, a second PMOS transistor and a second floating gate transistor on a second active area in the substrate, and includes an n-type erase region in the substrate. A source line is connected to the sources of the first and second PMOS transistors. A bit line is connected to the drains of the first and second floating gate transistors. A word line is connected to the gates of the first and second PMOS transistors. An erase line is connected to the n-type erase region.

character list

• 1A ist ein Schaltbild einer Speicherzelle gemäß einigen Ausführungsformen.
• 1B ist ein Schaltbild einer äquivalenten Speicherzellenschaltung gemäß einigen Ausführungsformen.
• 2A ist ein Schaltbild eines Speicherzellenarrays gemäß einigen Ausführungsformen.
• 2B ist ein Schaltbild eines Speicherzellenarrays gemäß einigen Ausführungsformen.
• 2C ist ein Schaltbild eines Speicherzellenarrays gemäß einigen Ausführungsformen.
• 3 ist ein Schaltbild eines Speicherzellenarrays gemäß einigen Ausführungsformen.
• 4A-4C sind Ansichten eines Layoutdesigns gemäß einigen Ausführungsformen.
• 5A-5C sind schematische Ansichten eines Layoutdesigns gemäß einigen Ausführungsformen.
• 6 ist eine schematische Ansicht eines Layoutdesigns gemäß einigen Ausführungsformen.
• 7A, 7B, 7C, 7D und 7E sind Querschnittansichten einer integrierten Schaltung gemäß einigen Ausführungsformen.
• 8 ist ein Flussdiagramm eines Verfahrens zum Ausbilden oder Herstellen einer Speicherschaltung gemäß einigen Ausführungsformen.
• 9 ist ein Flussdiagramm eines Verfahrens zum Generieren eines Layoutdesigns einer Speicherschaltung gemäß einigen Ausführungsformen.
• 10 ist eine schematische Ansicht eines Systems zum Entwerfen eines IC-Layoutdesigns gemäß einigen Ausführungsformen.
• 11 ist ein Blockdiagramm eines IC-Fertigungssystems und eines zugehörigen IC-Fertigungsflusses gemäß mindestens einer Ausführungsform der vorliegenden Offenbarung.

Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It is noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased in the interests of better understanding of the explanations.

• 1A 12 is a circuit diagram of a memory cell, according to some embodiments.
• 1B 12 is a circuit diagram of an equivalent memory cell circuit, according to some embodiments.
• 2A 12 is a circuit diagram of a memory cell array, according to some embodiments.
• 2 B 12 is a circuit diagram of a memory cell array, according to some embodiments.
• 2C 12 is a circuit diagram of a memory cell array, according to some embodiments.
• 3 12 is a circuit diagram of a memory cell array, according to some embodiments.
• 4A-4C 10 are views of a layout design according to some embodiments.
• 5A-5C 12 are schematic views of a layout design according to some embodiments.
• 6 12 is a schematic view of a layout design, according to some embodiments.
• 7A , 7B , 7C , 7D and 7E 12 are cross-sectional views of an integrated circuit, according to some embodiments.
• 8th 1 is a flow diagram of a method of forming or manufacturing a memory circuit according to some embodiments.
• 9 1 is a flow diagram of a method for generating a layout design of a memory circuit, according to some embodiments.
• 10 12 is a schematic view of a system for creating an IC layout design, according to some embodiments.
• 11 Figure 12 is a block diagram of an IC manufacturing system and associated IC fabricator flow according to at least one embodiment of the present disclosure.

DETAILED DESCRIPTION

The following disclosure provides various embodiments or examples for implementing features of the provided subject matter. Specific examples of components, materials, values, steps, configurations, or the like are described below in order to simplify the present disclosure. Other components, materials, values, steps, arrangements, or the like are contemplated. For example, in the following description, formation of a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact and also include embodiments in which additional features are formed between the first and second features may be formed such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in the various examples. This repetition is for the purpose of simplicity and understanding and does not automatically dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, for ease of description, spatially relative terms such as “beneath”, “below”, “lower”, “above”, “upper” and the like may be used throughout this document to indicate the relationship of one element or feature to another element (s) or feature (s) as shown in the figures to describe. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative terms used in this document may likewise be interpreted accordingly.

According to some embodiments, a memory circuit comprises a first reading device connected to a first bit line and a first programming device connected to the first reading device. In some embodiments, the first reading device includes a first transistor connected to a first wordline and a second transistor connected to the first wordline. In some embodiments, the first programming device includes a third transistor connected to a second wordline and a fourth transistor connected to the second wordline. In some embodiments, the first transistor and the second transistor are configured to share the first wordline. In some embodiments, the third transistor and the fourth transistor are configured to share the second wordline.

In some embodiments, the second transistor is connected in parallel with the first transistor. In some embodiments, by connecting the first transistor and the second transistor in parallel and sharing the first wordline, the first transistor and the second transistor have an equivalent resistance that is less than an individual resistance of the first transistor and the second transistor. Therefore, since the equivalent resistance of the first transistor and the second transistor is reduced, a read current or a write current of the memory circuit is increased, resulting in the memory circuit having improved read or write performance compared to other solutions.

In some embodiments, the third transistor is connected in parallel with the fourth transistor. In some embodiments, by connecting the third transistor and the fourth transistor in parallel and sharing the second wordline, the third transistor and the fourth transistor have an equivalent resistance that is less than an individual resistance of the third transistor and the fourth transistor. Therefore, since the equivalent resistance of the third transistor and the fourth transistor is reduced, a read current or a write current of the memory circuit is increased, resulting in the memory circuit having improved read or write performance compared to other solutions.

MEMORY CELL

1A 10 is a circuit diagram of a memory cell 100A according to some embodiments.

In some embodiments, memory cell 100A is an antifuse memory cell. In some embodiments, memory cell 100A is a fuse memory cell. In some embodiments, memory cell 100A is also referred to as a one-time programmable (OTP) memory cell. The memory cell 100A includes a read circuit 102 and a program circuit 104 . The read circuit 102 is connected between the programming circuit 104 and a bit line BL. One terminal of the read circuit 102 is connected to the bit line BL to transfer data from/to of the bit line BL to receive/transmit. The memory cell 100A is configured to store a logical “1” or a logical “0” based on the resistance of the programming circuit 104 of the memory cell. Other types of memory are within the scope of various embodiments.

The read circuit 102 includes at least one n-metal oxide semiconductor (NMOS) transistor N1 or one NMOS transistor N2. The programming circuit 104 includes at least one NMOS transistor N3 or one NMOS transistor N4. Other transistors or types of transistors or other numbers of transistors in at least one of read circuitry 102 and programming circuitry 104 are within the scope of the present disclosure. For example, in some embodiments, at least one of read circuitry 102 and programming circuitry 104 includes one or more p-type MOS (PMOS) transistors.

In some embodiments, the transistors in the programming circuit 104 are connected in parallel with each other. For example, in some embodiments, NMOS transistor N1 and NMOS transistor N2 are connected in parallel with each other.

In some embodiments, the transistors in read circuit 102 are connected in parallel with each other. For example, in some embodiments, NMOS transistor N1 and NMOS transistor N2 are connected in parallel with each other.

A first source/drain of the NMOS transistor N3 and a first source/drain of the NMOS transistor are connected to each other and are further connected to the bit line BL. A gate of the NMOS transistor N3 and a gate of the NMOS transistor N4 are connected to each other and are further connected to the read word line WLR. Each of a second NMOS transistor N3 source/drain, a second NMOS transistor source/drain, a second NMOS transistor N1 source/drain, a second NMOS transistor N1 source/drain Transistors N2 are connected together.

A first source/drain of the NMOS transistor N1 and a first source/drain of the NMOS transistor N2 are connected to each other. A gate of the NMOS transistor N1 and a gate of the NMOS transistor N2 are connected to each other and are further connected to a programming word line WLP.

Reference WLR in the present disclosure denotes a read word line throughout the specification. The reference designation WLP in the present disclosure denotes a programming word line throughout the specification. In some embodiments, when read word line features are referred to as WLR0 and WLR1, read word line WLR0 and WLR1 indicates that two different read word lines (e.g., WLR0 and WLR1) are written from corresponding memory cells. Similarly, when programming word line features are denoted as WLP0 and WLP1, programming word line WLP0 and WLP1 indicates that two different programming word lines (e.g., WLP0 and WLP1) are written from corresponding memory cells.

In some embodiments, the read word line WLR is also referred to as a "select word line", "word line gate line", and the like. In some embodiments, the programming wordline WLP is also referred to as "programming gate line", "antifuse gate line", "antifuse control line" and the like.

In some embodiments, NMOS transistors N3 and N4 are also referred to as "select transistors" and NMOS transistors N1 and N2 are also referred to as "programming transistors".

In some embodiments, a programming operation of memory cell 100A includes providing a ground voltage (e.g., oV) to bit line BL, providing a select voltage Vdd to read word line WLR, and providing a programming voltage Vp to program word line WLP. In some embodiments, the magnitude of the programming voltage Vp is greater than that of the selection voltage Vdd.

In the programming operation, in some embodiments, when the NMOS transistors N3 and N4 are turned on in response to the selection voltage Vdd being applied to the read word line WLR and the ground voltage being applied to the bit line BL, the programming voltage Vp is applied to a gate oxide layer (e.g. gate oxide layer 760 as in 7A-7E shown) of the NMOS transistors N1 and N2 applied. If the programming voltage Vp is greater than a withstand voltage range of the gate oxide film, then the gate oxide film of the NMOS transistors N1 and N2 is broken down. In some embodiments, the broken gate oxide layer is formed as a low resistance resistor. Thus, memory cell 100A generates a programming current that is driven by the turned on teten transistors N3 and N4 flows to the bit line BL.

In some embodiments, during a read operation of the memory cell 100A, the ground voltage (e.g., oV) is provided to the bit line BL, the select voltage Vdd is provided to the read word line WLR, and a read voltage Vr is provided to the program word line WLP. In the read operation, in some embodiments, when the NMOS transistors N3 and N4 are turned on in response to the select voltage Vdd, the NMOS transistors N1 and N2 generate a read current in response to the read voltage Vr. Thus, the memory cell 100A generates the read current flowing through the NMOS transistors N3 and N4 to the bit line BL. In some embodiments, a sense amplifier (not shown) coupled to memory cell 100A is able to correctly determine the data stored in memory cell 100A based on a magnitude of read current flowing through bit line BL. In some embodiments, the magnitude of the select voltage Vdd is the same as that of the read voltage Vr.

The above implementations of read circuit 102 and program circuit 104 are for purposes of illustration. Various other implementations of sense circuit 102 and programming circuit 104 are within the contemplated scope of the present disclosure. For example, in some embodiments, depending on various manufacturing processes, the read circuit 102 and the program circuit 104 are implemented with other types of MOS transistors, such as, but not limited to, fin field effect transistors (FinFETs) or the like.

The configuration of antifuse memory cell 100A as presented above for programming and reading operations is also presented for purposes of illustration. Various other configurations of antifuse memory cell 100A are within the contemplated scope of the present disclosure. For example, different voltage values are provided to one or more of bitline BL, programming wordline WLP, or read wordline WLR in some embodiments.

As in 1A As shown, the NMOS transistors N1-0 and N2-0 share the programming word line WLP and are connected in parallel with each other and therefore have an equivalent resistance smaller than an individual resistance of the NMOS transistor N1-0 or the NMOS transistor N2- 0 is As the equivalent resistance of NMOS transistors N1-0 and N2-0 is reduced, the read current I _readT of memory cell 100A is therefore increased, resulting in at least memory cell 100A, memory cell array 200A-200C ( 2A-2C ), the array of memory cells 302 ( 3 ), the integrated circuit 700 ( 7 ) have improved reading performance compared to other solutions.

Similarly, in some embodiments, since the equivalent resistance of NMOS transistors N1-0 and N2-0 is less than the individual resistance of NMOS transistors N1-0 and N2-0, a write current (not shown) during a write operation is the at least memory cell 100A, memory cell array 200A-200C ( 2A-2C ), the array of memory cells 302 ( 3 ), the integrated circuit 700 ( 7 ) or the NMOS transistors N1 and N2 is increased. In some embodiments, increasing the write current (not shown) applied to at least memory cell 100A, memory cell array 200A-200C ( 2A-2C ), the array of memory cells 302 ( 3 ), the integrated circuit 700 ( 7 ) is provided to at least the memory cell 100A, the memory cell array 200A-200C ( 2A-2C ), the array of memory cells 302 ( 3 ), the integrated circuit 700 ( 7 ) have improved write performance compared to other solutions.

1B 10 is a circuit diagram of an equivalent circuit of memory cell 100A, according to some embodiments.

In some embodiments, the equivalent circuitry 100B of memory cell 100A is shown for a read operation of memory cell 100A. Compared to memory cell 100A 1A the NMOS transistor N2 is off 1A in 1B replaced by a resistor R1, and the NMOS transistor N1 off 1A is in 1B replaced by a resistor R2. The resistor R1 corresponds to a resistance of the NMOS transistor N2, and the resistor R2 corresponds to a resistance of the NMOS transistor N1.

Compared to memory cell 100A 1A the equivalent circuit 100B further includes a resistor R _BL . The resistance R _BL corresponds to a resistance of the bit line BL.

In some embodiments, during a read operation, NMOS transistors N3 and N4 are turned on and resistors R1 and R2 (eg, NMOS transistors N1 and N2) conduct a respective read current Ireadi and Iread2 through respective NMOS transistors N3 and N4 and the resistor R _BL to the bit line BL.

The resistors R1 and R2 are connected in parallel with each other. Similarly, NMOS transistors N3 and N4 are connected in parallel with each other.

Resistor _R1 is connected between the source of NMOS transistor N4 and programming word line WLP. A read current Ireadi is configured to flow to node 106 through resistor R1 and NMOS transistor N4.

The resistor R ₂ is connected between the source of the NMOS transistor N3 and the programming word line WLP. A read current Iread2 is configured to flow to node 106 through resistor R2 and NMOS transistor N3.

Node 106 is connected to the drains of NMOS transistors N3 and N4 at node 106 . Node 106 is also connected to bit line BL through resistor R _BL . The read current at node 106 is equal to the sum of read currents Ireadi and Iread2 or read current IreadT. In other words, resistors R1 and R2 and corresponding NMOS transistors N3 and N4 are formed in a current divider configuration.

As in 1B As shown, resistors R1 and R2 share programming word line WLP and are connected in parallel and therefore have an equivalent resistance Req (not labeled) that is less than a resistance of resistor R1 or resistor R2. Therefore, since the equivalent resistance Req of the NMOS transistors N1 and N2 is reduced, the read current I _{readT is} increased, resulting in the memory cell 100A or 100B having an improved read performance compared to other solutions.

Similarly, in some embodiments, since the equivalent resistance Req (not labeled) of memory cell 100A is less than the resistance of resistor R1 or resistor R2, during a write operation, a write current (not shown) flowing through memory cell 100A or NMOS Transistors N1 and N2 is provided increased. In some embodiments, increasing the write current (not shown) provided to memory cell 100A results in memory cell 100A having improved write performance compared to other solutions.

MEMORY CELL ARRAY

2A FIG. 2 is a circuit diagram of a memory cell array 200A according to some embodiments.

Memory cell array 200A includes memory cell 202, memory cell 204, bit line BLo, read word line WLR1, read word line WLR1, program word line WLP0, and program word line WLP1.

Programming word line WLP0, read word line WLR0, and bit line BLo are out of corresponding program word line WLP, read word line WLR, and bit line BL 1A similar and therefore a similar detailed description is omitted. The programming word line WLP1 and the reading word line WLR1 are out of the corresponding programming word line WLP and the reading word line WLR 1A similar and therefore a similar detailed description is omitted.

The memory cells 202 and 204 are arranged side by side and are connected to different read word lines as well as different program word lines. Memory cell 202 is connected to read word line WLR0 and program word line WLP0. Memory cell 204 is connected to read word line WLR1 and program word line WLP1. Memory cells 202 and 204 are connected to the same bit line BLo at nodes 206 and 208, respectively.

Memory cell 202 has a configuration similar to that of memory cell 100A 1A is similar and therefore a similar detailed description is omitted. In other words, the connections of the NMOS transistors N1-0, N2-0, N3-0 and N4-0 are corresponding connections of respective NMOS transistors N1, N2, N3 and N4 1A similar. As a result, the connections of the NMOS transistors N1-0, N2-0, N3-0 and N4-0 in 2 not further described in this document for the sake of brevity. In some embodiments, memory cell 202 is configured to store one bit of data. In some embodiments, memory cell 204 is configured to store one bit of data.

Memory cell 202 includes NMOS transistors N1-0, N2-0, N3-0, and N4-0. The gates of the NMOS transistors N1-0, N2-0 are connected to the programming word line WLP0. The gates of NMOS transistors N3-0, N4-0 are connected to read word line WLR0.

Memory cell 204 is a variant of memory cell 100A or memory cell 202. For example, memory cell 204 is a mirror image of memory cell 202 with respect to a Y-axis Y. Therefore, the connections of the NMOS transistors are N1-1, N2-1, N3 -1 and N4-1 the corresponding ones Connections of the respective NMOS transistors N1, N2, N3 and N4 1A or similar to the respective connections of the respective NMOS transistors N1-0, N2-0, N3-0 and N4-0 of the memory cell 202. As a result, the connections of the NMOS transistors N1-1, N2-1, N3-1 and N4-1 in 2 not further described in this document for the sake of brevity.

Memory cell 204 includes NMOS transistors N1-1, N2-1, N3-1, and N4-1. The gates of the NMOS transistors N1-1, N2-1 are connected to the programming word line WLP1. The gates of the NMOS transistors N3-1, N4-1 are connected to the read word line WLR1.

A source/drain of each of the NMOS transistors N3-0, N4-0, N3-1 and N4-1 is connected to the same bit line BLo. A source/drain terminal of each of the NMOS transistors N3-0 and N4-0 are connected together and further connected at node 206 to the bit line BLo. A source/drain terminal of each of the NMOS transistors N3-1 and N4-1 are connected together and further connected at node 208 to the bit line BLo.

NMOS transistors N1-0 and N2-0 of memory cell 202 and NMOS transistors N1-1 and N2-1 of memory cell 204 are arranged on opposite sides of memory cell array 200A.

2 B 10 is a circuit diagram of a memory cell array 200B according to some embodiments.

Memory cell array 200B is a variant of memory cell array 200A. In comparison with the memory cell array 200A, the memory cell 202' replaces the memory cell 202, the memory cell 204' replaces the memory cell 204, and therefore a similar detailed description is omitted.

Compared to memory cell 202, memory cell 202' has no NMOS transistors N2-0 and N4-0. Compared to memory cell 204, memory cell 202' further includes NMOS transistors N6-1 and N5-1.

In some embodiments, the connections of NMOS transistors N6-1, N5-1 are similar to corresponding connections of corresponding NMOS transistors N4-1, N2-1 or corresponding NMOS transistors N3-1 and N4-1 2A . Consequently, for the sake of brevity, the connections of the NMOS transistors N6-1, N5-1 will not be further described in this document. In some embodiments, memory cell 202' is configured to store one bit of data. In some embodiments, memory cell 204' is configured to store one bit of data.

As in 2 B As shown, the NMOS transistors N1-1, N2-1 and N5-1 share the programming word line WLP and are connected in parallel with each other and therefore have an equivalent resistance smaller than an individual resistance of the NMOS transistors N1-1, N2-1. 1 and N5-1. Therefore, since the equivalent resistance of the NMOS transistors N1-1, N2-1 and N5-1 is reduced, the read current I _readT of the memory cell 204' is increased, with the result that the memory cell 204' has an improved performance compared to other solutions reading performance.

Similarly, in some embodiments, since the equivalent resistance of NMOS transistors N1-1, N2-1, and N5-1 is less than the individual resistance of NMOS transistors N1-1, N2-1, and N5-1, during a write operation a write current (not shown) provided to at least memory cell 204' is increased. In some embodiments, increasing the write current (not shown) provided to at least memory cell 204' results in at least memory cell 204' having improved write performance compared to other solutions.

In some embodiments, by providing different transistor counts in memory cell 202' and memory cell 204', memory cell array 200B allows for a flexible design that is adaptable based on the application. For example, in some embodiments, including a memory cell 202' of smaller size, but also including a larger memory cell 204' that has better read or better write performance than memory cell 202' compared to other solutions that have less flexible configurations, a hybrid solution that is customizable based on the application. Furthermore, in some embodiments, at least memory cell 204' or memory cell 202' has even more transistors than those in FIG 2 B shown on. Other transistors or transistor types or other transistor counts in at least one of memory cell 202' and memory cell 204' are within the scope of the present disclosure.

2C FIG. 2 is a circuit diagram of a memory cell array 200C according to some embodiments.

Memory cell array 200C is a variant of memory cell array 200A. Compared with the memory cell array 200A replaces the Memory cell 202'' the memory cell 202, the memory cell 204'' replaces the memory cell 204 and therefore a similar detailed description is omitted.

Compared to memory cell 204, memory cell 204'' does not include NMOS transistors N2-1 and N4-1. Compared to memory cell 202, memory cell 202'' further includes NMOS transistors N6-0 and N5-0.

In some embodiments, the connections of NMOS transistors N6-0, N5-0 are corresponding connections of corresponding NMOS transistors N4-0, N2-0 or corresponding NMOS transistors N3-0 and N4-0 2A similar. Consequently, for the sake of brevity, the connections of the NMOS transistors N6-0, N5-0 will not be further described in this document. In some embodiments, memory cell 202'' is configured to store one bit of data. In some embodiments, memory cell 204'' is configured to store one bit of data.

As in 2C As shown, the NMOS transistors N1-0, N2-0 and N5-0 share the programming word line WLP and are connected in parallel with each other and therefore have an equivalent resistance smaller than an individual resistance of the NMOS transistors N1-0, N2-0. 0 and N5-0. Therefore, since the equivalent resistance of the NMOS transistors N1-0, N2-0 and N5-0 is reduced, the read current I _readT of the memory cell 202'' is increased, resulting in the memory cell 202'' having a improved reading performance.

Similarly, in some embodiments, since the equivalent resistance of NMOS transistors N1-0, N2-0, and N5-0 is less than the individual resistance of NMOS transistors N1-0, N2-0, and N5-0, during a write operation a write current (not shown) provided to at least memory cell 202'' is increased. In some embodiments, increasing the write current (not shown) provided to at least memory cell 202'' results in at least memory cell 202'' having improved write performance compared to other solutions.

In some embodiments, by providing different transistor counts in memory cell 202'' and memory cell 204'', memory cell array 200C allows for a flexible design that is adaptable based on the application. For example, in some embodiments, including a memory cell 204'' of smaller size, but also including a larger memory cell 202'' that has better read or better write performance than memory cell 204'', compared to other solutions that are less flexible Having configurations, a hybrid solution that is adaptable based on the application. Furthermore, in some embodiments, at least the memory cell 202'' has even more transistors than the in 2C shown on. Other transistors or transistor types or other transistor counts in at least one of memory cell 202'' and memory cell 204'' are within the scope of the present disclosure.

3 FIG. 3 is a circuit diagram of a memory cell array 300 according to some embodiments.

For example, memory cell 100A is off 1A usable as one or more memory cells in the memory cell array 300 .

Memory cell array 300 comprises an array of memory cells 302[0,0], 302[0,1],..., 302[M-1,N-1] (collectively referred to as "array of memory cells 302") with M rows and N columns, where N is a positive integer corresponding to the number of columns in the array of memory cells 302 and M is a positive integer corresponding to the number of rows in the array of memory cells 302. The rows of cells in the array of memory cells 302 are arranged in a first direction X. The columns of cells in the array of memory cells 302 are arranged in a second direction Y. The second direction Y differs from the first direction X. In some embodiments, the second runs Direction Y perpendicular to the first direction X. The memory cell 100A 1A can be used as one or more memory cells in the array of memory cells 302. The memory cell arrays 200A, 200B and 200C 2A-2C can be used as at least one pair of adjacent memory cells in a same row in the array of memory cells 302. In some embodiments, an adjacent memory cell is a memory cell that is directly adjacent to another memory cell. In some embodiments, an adjacent memory cell is a memory cell that is adjacent to another memory cell.

In some embodiments, each memory cell 302[0,0], 302[0,1],..., 302[M-1,N-1] in the array of memory cells 302 has a corresponding memory cell 100A

1A connected to a corresponding program word line WLP, a corresponding read word line WLR and a corresponding bit line BL.

Various types of memory cells in the array of cells 302 fall within the contemplated scope of the present disclosure. Various configurations of the array of memory cells 302 fall within the contemplated scope of the present disclosure. Furthermore, in some embodiments, the array of memory cells 302 includes multiple groups of different types of memory cells.

Memory cell array 300 further includes N programming word lines WLP[0],...WL[Ni] (collectively referred to as set of programming word lines WLP') and N read word lines WLR[o],...WLR[Ni] (collectively referred to as read word line WLR' designated) on. Each column 0,...,N-1 in the array of cells 302 is connected to a corresponding programming word line WLP[o],...WLP[N-1] and a corresponding read word line WLR[0],...WLR[ N-1] overlapped. Each programming wordline WLP' or read wordline WLR' extends in the second direction Y and runs across a column of cells (eg, column 0,...,N-1). In some embodiments, the programming wordline WLP is off 1A usable as one or more of the programming word lines WLP[o],...WL[Ni], and the read word line WLR is usable as one or more of the read word lines WLR[0],...WLR[Ni].

The memory cell array 300 further includes M bit lines BL[0],...BL[M-1] (collectively referred to as bit lines BL'). Each row 0,...,M-1 in the array of cells 302 is overlapped by a corresponding bit line BL[0],...,BL[Mi]. Each bit line BL' extends in the first direction X and across a corresponding row of cells (eg, row 0,...,M-1). In some embodiments, bit line BL is off 1A can be used as one or more bit lines BL[o], ..., BL[Mi]. Various configurations of the bit lines BL', read word lines WLR', or program word lines WLP' in the array of memory cells 302 fall within the contemplated scope of the present disclosure.

Other configurations of memory cell array 300 are within the contemplated scope of the present disclosure.

LAYOUT DESIGN OF MEMORY CELL ARRAY

4A-4C 10 are views of a layout design 400 according to some embodiments. Layout design 400 is a layout diagram of memory cell array 200A in FIG 2A . The layout design 400 can be used to manufacture the memory cell array 200A.

4A is a view of layout design 400. For ease of illustration, in 4A some of the marked items 4B-4C not marked. In some embodiments 4A-4C in 4A-4C additional elements not shown.

4B-4C 4 are views of a corresponding portion 400B-400C of layout design 400. FIG 4A , simplified for simplicity of illustration. Section 400B exhibits one or more features of layout design 400 4A 12, comprising the active (OD) level, the POLY(PO) level, the metal-over-diffusion (MD) level, and the Mo level of layout design 400. Portion 400C corresponds to layout design 400 of FIG 4A , but has additional markings used in 4A are not shown for the sake of simplicity of illustration.

The layout design 400 includes active region layout structures 402a and 402b (collectively referred to as “set of active region layout structures 402”) extending in a first X direction. The active region layout structures 402a, 402b of the set of active region layout structures 402 are separated from each other in a second direction Y, which is different from the first direction X. The set of active region layout structures 402 can be used to create a corresponding set of active regions 702 ( 7 ) of the integrated circuit 700 to produce. In some embodiments, the active region layout structures 402a, 402b of the set of active region layout structures 402 can be used to form corresponding active regions 702a, 702b of the set of active regions 702 ( 7 ) of the integrated circuit 700 to produce. In some embodiments, the set of active region layout structures 402 is referred to as an oxide diffusion (OD) region, which defines the source or drain diffusion regions of the integrated circuit 700 .

In some embodiments, the active region layout structure 402a of the set of active region layout structures 402 is usable to source and drain regions of each of the NMOS transistor N1-0, the NMOS transistor N2-0, the NMOS transistor N3- 0 and the NMOS transistor N4-0 2 to manufacture. In some embodiments, the active region layout structure 402b of the set of active region layout structures 402 is usable to source and drain regions of each of the NMOS transistor N1-1, the NMOS transistor N2-1, the NMOS transistor N3- 1 and the NMOS transistor N4-1 2 to manufacture.

In some embodiments, the set of active region layout structures 402 is on a arranged on the first layout level. In some embodiments, the first layout level corresponds to an active level or an OD level of one or more of the layout design 400 or 600 ( 4 or 6 ) or the integrated circuit 700 ( 7 ).

Other configurations or sets of structures in the set of active region layout structures 402 are within the scope of the present disclosure.

The layout design 400 further includes at least the gate layout structure 404a, 404b, 4040, 404d, 404e, or 404f (collectively referred to as “set of gate layout structures 404”) extending in the second Y direction.

In some embodiments, each of the layout patterns of the set of gate layout patterns 404 is separated from an adjacent one of the set of gate layout patterns 404 in the first direction X by a "poly pitch" (not labeled). The set of gate layout structures 404 can be used to construct a corresponding set of gates 704 ( 7 ) of the integrated circuit 700 to produce. In some embodiments, the gate layout structure 404a, 404b, 4040, 404d, 404e, 404f of the set of gate layout structures 404 is usable to form a corresponding gate 704a, 704b, 704c, 704d, 704e, 704f of the set of gates 704 ( 7 ) of the integrated circuit 700 to produce.

The set of gate layout structures 404 is arranged on a second layout level. In some embodiments, the second layout level is different than the first layout level. In some embodiments, the second layout level corresponds to a POLY level of one or more of the layout designs 400 or 600 ( 2 or 6 ) or the integrated circuit 700 ( 7 ).

The set of gate layout structures 404 overlaps the set of active region layout structures 402. The set of active region layout structures 402 is below the set of gate layout structures 404. In some embodiments, the gate layout structure 404a is arranged over a first side of the layout design 400 , and the gate layout structure 404f is arranged over a second side of the layout design 400, opposite the first side. In some embodiments, gate layout structure 404a overlaps a first side of each of active region layout structures 402a and 402b, and gate layout structure 404f overlaps a second side of each of active region layout structures 402a and 402b.

The gate layout structure 404b can be used to form the gate of the NMOS transistor N1-0 and the gate of the NMOS transistor N2-0 2 to manufacture. In some embodiments, the gate layout structure 404b can be used to form the gate of NMOS transistor N1 and the gate of NMOS transistor N2 1A to manufacture. In some embodiments, the gate layout structure 404b can be used to turn off at least the programming wordline WLP 1A , the programming word line WLP0 off 2 or the programming word lines WLP' 3 to manufacture.

Gate layout structure 404c can be used to form the gate of NMOS transistor N3-0 and the gate of NMOS transistor N4-0 2 to manufacture. In some embodiments, the gate layout structure 404c can be used to form the gate of NMOS transistor N3 and the gate of NMOS transistor N4 1A to manufacture. In some embodiments, the gate layout structure 404c can be used to turn off at least the read word line WLR 1A , the read word line WLR0 off 2 or the read word lines WLR' 3 to manufacture.

The gate layout structure 404d can be used to form the gate of the NMOS transistor N3-1 and the gate of the NMOS transistor N4-1 2 to manufacture. In some embodiments, the gate layout structure 404d can be used to form the gate of NMOS transistor N3 and the gate of NMOS transistor N4 1A to manufacture. In some embodiments, the gate layout structure 404d can be used to turn off at least the read word line WLR 1A , the read word line WLR1 off 2 or the read word lines WLR' 3 to manufacture.

The gate layout structure 404e can be used to form the gate of the NMOS transistor N1-1 and the gate of the NMOS transistor N2-1 2 to manufacture. In some embodiments, the gate layout structure 404e can be used to form the gate of NMOS transistor N1 and the gate of NMOS transistor N2 1A to manufacture. In some embodiments, the gate layout structure 404e can be used to turn off at least the programming wordline WLP 1A , the programming word line WLP1 off 2 or the programming word lines WLP' 3 to manufacture.

Other configurations, arrangements on other layout levels or sets of structures in the set of gate layout structures 404 fall within the scope of the present disclosure.

The layout design 400 further includes at least one metal-over-diffusion layout structure 410a, 410b, 410c, 410d, or 410e (collectively referred to as "set of metal-over-diffusion layout structures 410") extending in the second direction Y At least one of the layout structures of the set of metal-over-diffusion layout structures 410 overlaps the set of active region layout structures 402.

The set of metal-over-diffusion layout structures 410 can be used to form a corresponding set of contacts 710 ( 7 ) of the integrated circuit 700 to produce. In some embodiments, the metal-over-diffusion layout structures 410a, 410b, 410C, 410d, or 4100 of the set of metal-over-diffusion layout structures 410 are usable to form corresponding contacts 710a, 710b, 710c, 710d, or 710e of the set of contacts 710 ( 7 ) of the integrated circuit 700 to produce.

In some embodiments, each of the layout patterns of the set of metal-over-diffusion layout patterns 410 is separated from an adjacent layout pattern of the set of metal-over-diffusion layout patterns 410 in at least the first X direction. In some embodiments, each of the layout patterns of the set of metal-over-diffusion layout patterns 410 is sandwiched between a pair of gate layout patterns of the set of gate layout patterns 402 . For example, metal-over-diffusion layout structure 410a is disposed between gate layout structures 404a and 404b.

In some embodiments, the set of metal-over-diffusion layout structures 410 is arranged on a third layout level. In some embodiments, the third layout level corresponds to a metal-over-diffusion (MD) level of one or more of the layout designs 400 or 600 ( 4 or 6 ) or the integrated circuit 700 ( 7 ). In some embodiments, the third layout level is different than the first layout level. In some embodiments, the third layout level is the same as the second layout level and includes the MD level and the POLY level.

In some embodiments, the metal-over-diffusion layout structure 410a can be used to form at least one drain or one source of each of NMOS transistor N1-0 and NMOS transistor N2-0 2 to manufacture. In some embodiments, the metal-over-diffusion layout structure 410a can be used to form at least one drain or one source of each of NMOS transistor N1 and NMOS transistor N2 1A to manufacture.

In some embodiments, the metal-over-diffusion layout structure 410b can be used to form at least a drain or a source of each of the NMOS transistor N1-0, the NMOS transistor N2-0, the NMOS transistor N3 -0 and the NMOS transistor N4-0 2 to manufacture. In some embodiments, the metal-over-diffusion layout structure 410b can be used to provide at least a drain or a source of each of the NMOS transistor N1, the NMOS transistor N2, the NMOS transistor N3, and the NMOS Transistor N4 off 1A to manufacture.

In some embodiments, the metal-over-diffusion layout structure 410c can be used to form at least one drain or one source of each of NMOS transistor N3-0, NMOS transistor N4-0, NMOS transistor N3-0 -1 and the NMOS transistor N4-1 2 to manufacture. In some embodiments, the metal-over-diffusion layout structure 4100 can be used to form at least one drain or one source of each of NMOS transistor N3 and NMOS transistor N4 1A to manufacture.

In some embodiments, the metal-over-diffusion layout structure 410d can be used to form at least a drain or a source of each of the NMOS transistor N3-1, the NMOS transistor N4-1, the NMOS transistor N1 -1 and the NMOS transistor N2-1 2 to manufacture. In some embodiments, the metal-over-diffusion layout structure 410d can be used to form at least one drain or one source of each of the NMOS transistor N1, the NMOS transistor N2, the NMOS transistor N3, and the NMOS Transistor N4 off 1A to manufacture.

In some embodiments, the metal-over-diffusion layout structure 4100 can be used to form at least one drain or one source of each of NMOS transistor N1-1 and NMOS transistor N2-1 2 to manufacture. In some embodiments, the metal-over-diffusion layout structure 4100 can be used to form at least one drain or one source of each of NMOS transistor N1 and NMOS transistor N2 1A to manufacture.

Other configurations, arrangements at other layout levels, or sets of structures in the set of metal-over-diffusion layout structures 410 are within the scope of the present disclosure.

The layout design 400 further includes at least one cue layout pattern 420a, 420b, 420C, or 420d (hereinafter referred to as “set of cue layout patterns 420”) extending in the first X direction. In some embodiments, the set of cue layout structures 420 extends in two directions (e.g., first direction X or second direction Y).

The set of conductive feature layout structures 420 can be used to create a corresponding set of conductive structures 720 ( 7 ) of the integrated circuit 700 to produce. In some embodiments, the directional feature layout structures 420a, 420b, 420c, 420d of the set of directional feature layout structures 420 are usable to define corresponding directional features 720a, 720b, 720c, 720d of the set of directional feature 720 ( 7 ) of the integrated circuit 700 to produce. In some embodiments, the routing feature layout structure 420a can be used to turn off at least the bit line BLo 2 , the bit line BL off 1A or the bit lines BL' off 3 to manufacture.

The set of conductive feature layout structures 420 overlaps at least the set of gate layout structures 204 or the set of metal-over-diffusion layout structures 210. The set of conductive feature layout structures 420 is arranged on a fourth layout level. In some embodiments, the fourth layout level is different from at least the first layout level, the second layout level, or the third layout level. In some embodiments, the fourth layout level corresponds to a metal zero (Mo) level of one or more of the layout designs 400 or 600 ( 4 or 6 ) or the integrated circuit 700 ( 7 ). Other layout levels fall within the scope of the present disclosure. Other configurations, arrangements at other layout levels, or sets of structures in the set of cue layout structures 420 are within the scope of the present disclosure.

In some embodiments, the conductive feature layout structure 420a overlaps each of the gate layout structures in the set of gate layout structures 404 and each of the metal-over-diffusion layout structures in the set of metal-over-diffusion layout structures 410. The conductive feature layout structure 420b overlaps gate layout structures 404b, 404c, 404d, and 404e and metal-over-diffusion layout structures 410b, 410c, and 410d. The conductive feature layout structure 420c overlaps the gate layout structures 404a, 404b and 404c and the metal-over-diffusion layout structures 410a and 410b. The conductive feature layout structure 420d overlaps the gate layout structures 404d, 404e and 404f and the metal-over-diffusion layout structures 410d and 410e.

Other configurations or sets of structures in the set of routing feature layout structures 420 are within the scope of the present disclosure.

The layout design 400 further includes at least one via layout structure 430a, 430b, or 430c (collectively referred to as “set of via layout structures 430”). The set of via layout structures 430 can be used to create a corresponding set of vias 730 ( 7 ) to produce. In some embodiments, via layout structures 430a, 430b, 430c of via set layout structures 430 are usable to form corresponding vias 730a, 730b, 730c of via set 730 ( 7 ) of the integrated circuit 700 to produce.

In some embodiments, the set of via layout structures 430 is between the set of conductive feature layout structures 420 and the set of gate layout structures 404. The via layout structures 430a, 43ob, 430c are between corresponding conductive feature layout structures 420b, 420c, 420d and corresponding ones Gate layout structures 404c, 404b, 404e. In some embodiments, via layout pattern 430a, 430b, 430c is located where a corresponding conductive feature layout pattern 420b, 420c, 420d overlaps corresponding gate layout patterns 404c, 404b, 404e.

The set of via layout structures 430 is at a via-over-gate (VG) level of one or more of the layout designs 400 or 600 ( 4 or 6 ) or the integrated circuit 700 ( 7 ) arranged. In some embodiments, the VG level is between the Mo level and the POLY level. In some embodiments, the VG level is between the fourth layout level and the second layout level. Other layout levels are within the scope of the present disclosure.

Other configurations, arrangements at other layout levels, or sets of structures in the set of via layout structures 430 are within the scope of the present disclosure.

The layout design 400 further includes at least the via layout structure 432a (collectively referred to as “set of via layout structures 432”). The set of via layout structures 432 can be used to form a corresponding set of vias 732 ( 7 ) to produce. In some embodiments, via layout structures 432a of set of via layout structures 432 are usable to form corresponding vias 732a of set of vias 732 ( 7 ) of the integrated circuit 700 to produce.

In some embodiments, the set of via layout patterns 432 is between the set of conductive feature layout patterns 420 and the set of metal-over-diffusion layout patterns 410. The via layout pattern 432a is between the corresponding conductive feature layout pattern 420a and the corresponding metal over-diffusion layout structures 410c. In some embodiments, the via layout pattern 432a is arranged where the corresponding conductive feature layout pattern 420a overlaps the corresponding metal-over-diffusion layout patterns 410c.

The set of via layout structures 432 is at a via-over-diffusion (VD) level of one or more of the layout designs 400 or 600 ( 4 or 6 ) or the integrated circuit 700 ( 7 ) arranged. In some embodiments, the VD plane is between the Mo plane and the MD plane. In some embodiments, the VD level is between the fourth layout level and the third layout level. Other layout levels are within the scope of the present disclosure.

Other configurations, arrangements at other layout levels, or sets of structures in the set of via layout structures 432 are within the scope of the present disclosure.

The layout design 400 further includes a memory cell region 401 and a memory cell region 401'.

In some embodiments, memory cell region 401 ( 4C ) depicts a layout diagram of memory cell 202 of memory cell array 200A 2A . In some embodiments, the memory cell region 401' ( 4C ) depicts a layout diagram of memory cell 204 of memory cell array 200A 2A . In some embodiments, memory cell region 401 can be used to select memory cell 202 of memory cell array 200A 2A to manufacture. In some embodiments, memory cell region 401' can be used to select memory cell 204 of memory cell array 200A 2A to manufacture. In some embodiments, memory cell region 401 ( 4C ) or the memory cell region 401' ( 4C ) of layout design 400 depicts a layout diagram of memory cell 100A 1A . In some embodiments, memory cell region 401 or memory cell region 401' of layout design 400 can be used to construct memory cell 100A 1A to manufacture.

In some embodiments, memory cell region 401 includes the layout structures of layout design 400 usable to construct memory cell 202 of memory cell array 200A 2A to manufacture. For example, in some embodiments memory cell region 401 includes at least gate layout structure 404a, gate layout structure 404b, gate layout structure 404c, a portion of active region layout structure 402a, a portion of active region layout structure 402b, the metal-over-diffusion layout pattern 410a, metal-over-diffusion layout pattern 410b, at least a portion of metal-over-diffusion layout pattern 410c, via layout pattern 430a, via layout pattern 43ob, via layout pattern 430c, via layout pattern 432a, the directional sign layout structure 420a, the directional sign layout structure 420b or the directional sign layout structure 420c.

In some embodiments, memory cell region 401' includes the layout structures of layout design 400 usable to construct memory cell 204 of memory cell array 200A 2A to manufacture. For example, in some embodiments, memory cell region 401' includes at least gate layout structure 404d, gate layout structure 404e, gate layout structure 404f, another portion of active region layout structure 402a, another portion of active region layout structure 402b, metal-over -diffusion layout structure 410d, the metal-over-diffusion layout structure 4100, at least a portion of the metal-over-diffusion layout structure 410e, the via layout structure 430c, the via layout structure 432a, the conductive feature layout structure 420a, the conductive feature- Layout structure 420b or the key feature layout structure 420d.

Memory cell region 401 includes regions 406a and 406b. In some embodiments, region 406a includes the layout structures of layout design 400 that can be used to form NMOS transistor N1-0 and NMOS transistor N1-0 NMOS transistor N3-o of memory cell 202 off 2 to manufacture. In some embodiments, region 406b includes the layout structures of layout design 400 that can be used to construct NMOS transistor N2-0 and NMOS transistor N4-0 of memory cell 202. FIG 2 to manufacture.

In some embodiments, region 406a includes at least gate layout structure 404a, gate layout structure 404b, gate layout structure 404c, a portion of active region layout structure 402a, metal-over-diffusion layout structure 410a, metal-over-diffusion layout structure 410b, at least a portion of metal-over-diffusion layout structure 410c, via layout structure 430a, via layout structure 432a, conductive feature layout structure 420a, or conductive feature layout structure 420b.

In some embodiments, region 406b includes at least gate layout pattern 404a, gate layout pattern 404b, gate layout pattern 404c, a portion of active region layout pattern 402b, metal-over-diffusion layout pattern 410a, metal-over-diffusion layout structure 410b, at least a portion of metal-over-diffusion layout structure 410c, via layout structure 43ob, via layout structure 432a, conductive feature layout structure 420a, or conductive feature layout structure 420c.

Memory cell region 401' includes regions 408a and 408b. In some embodiments, region 408a includes the layout structures of layout design 400 that can be used to construct NMOS transistor N3 - 1 and NMOS transistor N1 - 1 of memory cell 202 2 to manufacture. In some embodiments, region 408b includes the layout structures of layout design 400 that can be used to construct NMOS transistor N2-1 and NMOS transistor N4-1 of memory cell 202. FIG 2 to manufacture.

In some embodiments, region 408a includes gate layout structure 404d, gate layout structure 404e, gate layout structure 404f, another portion of active region layout structure 402a, metal-over-diffusion layout structure 410d, metal-over-diffusion layout structure 4100, at least a portion of metal-over-diffusion layout structure 4100, via layout structure 432a, conductive feature layout structure 420a, or conductive feature layout structure 420b.

In some embodiments, region 408b includes at least gate layout structure 404d, gate layout structure 404e, gate layout structure 404f, another portion of active region layout structure 402b, metal-over-diffusion layout structure 410d, metal-over- Diffusion layout structure 4100, at least a portion of metal-over-diffusion layout structure 4100, via layout structure 430c, via layout structure 432a, conductive feature layout structure 420a, or conductive feature layout structure 420d.

Other configurations, arrangements at other layout levels, or sets of structures in the layout design 400 are within the scope of the present disclosure. For example, in some embodiments, the layout design 400 may be modified to include other numbers of at least one of region 406a and region 406b (see e.g 5A-5C ) in the memory cell region 401 of the layout design 400. FIG. Similarly, in some embodiments, the layout design 400 may be modified to include other numbers of at least one of region 408a and region 408b (see e.g 5A-5C ) in the memory cell region 401 ′ of the layout design 400 .

5A-5C 12 are schematic views of a layout design according to some embodiments.

5A 500A is a schematic view of a layout design of a memory cell according to some embodiments. 5B FIG. 5 is a schematic view of a layout design 500R of a memory cell according to some embodiments. 5C 500C is a schematic view of a layout design of a memory cell according to some embodiments. Point out for simplicity of illustration 5A-5C additional elements not shown.

Layout design 500A is another representation of layout design 400 from FIG 4A-4C . For example, compared to the layout design, 400 is off 4A-4C The layout design 500A is similar to the layout design 400, however, in the layout design 500A, the layout structures of FIG 4A-4C not shown. The layout design 500A includes a memory cell region 502 and a memory cell region 504 . In some embodiments, memory cell regions 502 and 504 are similar to corresponding memory cell regions 401 and 401', and therefore a similar detailed description is omitted. In some embodiments, a number of regions (506a, 506b) in the memory memory cell region 502 equal to a number of regions (508a, 508b) in memory cell region 504.

Memory cell region 502 includes region 506a and region 506b. In some embodiments, regions 506a and 506b are similar to corresponding regions 406a and 406b and therefore similar detailed description is omitted. In some embodiments, each of region 506a and region 506b has a corresponding programming transistor region MNP and a corresponding reading transistor region MNR.

As in 5A As illustrated, memory cell region 502 is a portion of a layout design that can be used to construct memory cell 202 ( 2A ) adapted to store 1 bit of data and having 2 programming transistors (MNP or NMOS transistors N1-0 and N2-0) and 2 reading transistors (MNR or NMOS transistors N3-o and N4-0).

Memory cell region 504 includes region 508a and region 508b. In some embodiments, regions 508a and 508b are similar to corresponding regions 408a and 408b, and therefore similar detailed description is omitted. In some embodiments, each of region 508a and 508b has a corresponding programming transistor region MNP and a corresponding reading transistor region MNR.

As in 5A As illustrated, memory cell region 504 is a portion of a layout design that can be used to construct memory cell 204 ( 2 ) adapted to store 1 bit of data and having 2 programming transistors (MNP or NMOS transistors N1-1 and N2-1) and 2 reading transistors (MNR or NMOS transistors N3-1 and N4-1).

In some embodiments, a number of programming transistor regions MNP in at least region 506a, 506b, 508a, or 508b is equal to a number of read transistor regions MNR in at least region 506a, 506b, 508a, or 508b. In some embodiments, a number of program transistor regions MNP in at least region 506a, 506b, 508a or 508b is different from a number of read transistor regions MNR in at least region 506a, 506b, 508a or 508b.

In some embodiments, a number of programming transistor regions MNP in at least region 506a, 506b, 508a, or 508b is equal to a number of programming transistor regions MNP in another of regions 506a, 506b, 508a, or 508b. In some embodiments, a number of programming transistor regions MNP in at least 506a, 506b, 508a, or 508b is different from a number of programming transistor regions MNP in another of regions 506a, 506b, 508a, or 508b.

In some embodiments, a number of read transistor regions MNR in at least region 506a, 506b, 508a, or 508b is equal to a number of read transistor regions MNR in another of regions 506a, 506b, 508a, or 508b. In some embodiments, a number of read transistor regions MNR in at least region 506a, 506b, 508a, or 508b is different from a number of read transistor regions MNR in another of regions 506a, 506b, 508a, or 508b.

5B FIG. 5 is a schematic view of a layout design 500B of the memory cell array 200B according to some embodiments.

In some embodiments, layout design 500B represents a number of regions (506a') in memory cell region 502' that is different than a number of regions (508a', 508b', 508c') in memory cell region 504'. In some embodiments, a number of regions (506a') in memory cell region 502' is less than a number of regions (508a', 508b', 508c') in memory cell region 504'. In some embodiments, a number of regions (506a') in memory cell region 502' is greater than a number of regions (508a', 508b', 508c') in memory cell region 504'.

In some embodiments, by having different numbers of regions in memory cell region 502' and memory cell region 504', layout design 500B allows for a more flexible design than other solutions.

The 500B layout design is a variant of the 400 layout design 4A-4C and the layout design 500A 5A . Compared to the layout design 500A, the memory cell region 502' replaces the memory cell region 502 and the memory cell region 504' replaces the memory cell region 504, and therefore a similar detailed description is omitted.

The memory cell region 502' includes a region 506a'. Region 506a' is a variant of region 506a of FIG 5A . In some embodiments, region 506a' is similar to region 506a or 406a and therefore similar detailed description is omitted.

As in 5B As illustrated, memory cell region 502' is a portion of a layout design that can be used to fabricate a memory cell similar to memory cell 202' of memory cell array 200B 2 B is similar, where the memory cell is configured to store 1 bit of data and has 1 programming transistor (MNP or NMOS transistor N1-0) and 1 reading transistor (MNR or NMOS transistor N3-0).

Other numbers of regions are within the scope of the present disclosure. For example, in some embodiments, memory cell region 502' has a number of regions other than 1 region (e.g., region 506a').

The memory cell region 504' has a region 508a', a region 508b', a region 508c'. Regions 508a' and 508b' are a variant of corresponding regions 508a and 508b of FIG 5A . In some embodiments, region 508a' is similar to region 508a or 408a, region 508b' is similar to region 508b or 408b, region 508c' is similar to region 508a or 508b, and therefore similar detailed description is omitted.

As in 5B As shown, memory cell region 504' is a portion of a layout design that can be used to fabricate memory cell 204' configured to store 1 bit of data and 3 programming transistors (MNP or NMOS transistors N1-1, N2- 1, N5-1) and 3 read transistors (NMOS transistors N3-1, N4-1, N6-1).

Other numbers of regions are within the scope of the present disclosure. For example, in some embodiments, memory cell region 504' has a number of regions other than 3 regions (e.g., region 508a', region 508b', or region 508c').

In some embodiments, each of the regions 506a', 508a', 508b', and 508c' has a corresponding programming transistor region MNP and a corresponding reading transistor region MNR.

In some embodiments, a number of programming transistor regions MNP or a number of reading transistor regions MNR in at least region 506a', 508a', 508b' or 508c' may be similar to the description above for 5A to be set and is therefore omitted for the sake of brevity.

5C FIG. 5 is a schematic view of a layout design 500C of the memory cell array 200C according to some embodiments.

Layout design 500B is a variant of layout design 500B 5B . In some embodiments, layout design 500C provides a number of regions (e.g., 506a'', 506b'', 506c'') in memory cell region 502'' that are greater than a number of regions (508a'') in memory cell region 504''. is, and therefore a similar detailed description is omitted for the sake of brevity.

Compared to the layout design 500A, the memory cell region 502" replaces the memory cell region 502 and the memory cell region 504" replaces the memory cell region 504, the regions 506a", 506b" replace the corresponding regions 506a, 506b, the region 508a" replaces the Region 508a, region 506c'' is similar to region 502a and therefore a similar detailed description is omitted.

In some embodiments, by having different numbers of regions in memory cell region 502'' and memory cell region 504'', layout design 500C allows for a more flexible design than other solutions.

Other configurations, arrangements at other layout levels, or sets of structures in the layout design 500A, 500B, or 500C are within the scope of the present disclosure.

6 6 is a schematic view of a layout design 600 according to some embodiments.

In some embodiments, the layout design 600 exhibits 6 represents a pair of adjacent layout designs (eg, a first layout design 602, a second layout design 604) that can be used to fabricate 4 adjacent memory cells in the same row.

The 600A layout design is a variant of the 400 layout design 4A-4C . For example, the layout design has 600 compared to the layout design has 400 4A-4C , an additional layout design (eg the second layout design 604). For the sake of simplicity of illustration 6 additional elements not shown.

The layout design 600 includes a first layout design 602 , a second layout design 604 and a gate layout structure 606 .

In some embodiments, first layout design 602 corresponds to layout design 400 of FIG 4A-4C , and therefore a similar detailed description is omitted.

In some embodiments, the second layout design 604 is similar to the first layout design 602 and therefore a similar detailed description is omitted. For example, in some embodiments, the second layout design 604 is a mirror image of the layout design 602 rotated about the X-axis.

The gate layout structure 606 is composed of at least one gate layout structure of the set of gate layout structures 404 4A-4C similar and therefore a similar detailed description is omitted. The gate layout structure 606 is arranged between the first layout design 602 and the second layout design 604 .

In some embodiments, the layout design 600 can be used to fabricate 4 adjacent memory cells in the memory cell array 300 arranged in the same row. For example, in some embodiments, the first layout design 602 can be used to fabricate memory cells 302[0,0] and 302[0,1], and the second layout design 604 can be used to fabricate memory cells 302[0,2] and 302[0 ,3] to produce. In some embodiments, the first layout design 602 can be used to fabricate memory cells other than memory cells 302[0,0] and 302[0,1] in memory cell array 300, and the second layout design 604 can be used to fabricate memory cells other than memory cells 302 [0,2] and 302[0,3] in the memory cell array 300 to be fabricated.

Other configurations, arrangements at other layout levels, or sets of structures in the layout design 600 are within the scope of the present disclosure.

INTEGRATED CIRCUIT

7A , 7B , 7C , 7D and 7E 7 are cross-sectional views of an integrated circuit 700 according to some embodiments. 7A Figure 4 is a cross-sectional view of integrated circuit 700 according to layout design 400 along plane AA', 7B Fig. 4 is a cross-sectional view of the integrated circuit 700 according to the layout design 400 along a plane BB', 7C Fig. 4 is a cross-sectional view of the integrated circuit 700 according to the layout design 400 along a plane C-C', 7D 12 is a cross-sectional view of the integrated circuit 700 according to the layout design 400 along a plane D-D', and 7E FIG. 4 is a cross-sectional view of integrated circuit 700 according to layout design 400 along plane EE′, according to some embodiments. The integrated circuit 700 is manufactured by the 400 or 600 layout design.

Components identical or similar to those in one or more of 1A-1B , 2-3 , 4A-4C , 5A-5C and 6 are denoted by the same reference numerals and therefore a similar detailed description is omitted.

The integrated circuit 700 is manufactured by the 400 or 600 layout design. The structural relationships, including orientation, lengths, and widths, as well as the designs of the integrated circuit 700 from FIG 7A-7E are the structural relationships and configurations of the memory cell 100A 1A , of the memory cell array 200A-200C 2A-2C , of the memory cell array 300 3 , the layout design 400 off 4A-4C , the layout sections 500A-500C 5A-5C and the layout design 600 6 similar and will not be included in each of the for the sake of brevity 1A , 2-3 , 4A-4C or 5A-5C described.

The integrated circuit 700 includes at least the active region 712a, 712b, 712c, 712d, or 712e (collectively referred to as "set of active regions 712") in a well region 702a. In some embodiments, the well region 702a is in a substrate 750. In some embodiments For example, the substrate 750 comprises a silicon substrate or any other applicable semiconductor material substrate In some embodiments, the well region 702a comprises a p-type dopant or an n-type dopant.

The set of active regions 712 extends in the second direction Y and is arranged on the first layout level of the integrated circuit 700 . All active regions of the set of active regions 712 are separated from each other in the first X direction. In some embodiments, the set of active regions 712 of the integrated circuit 700 is referred to as an oxide definition (OD) region, which defines the source or drain diffusion regions of the integrated circuit 700. FIG. In some embodiments, the set of active regions 712 includes an n-type dopant in the well region 702a (e.g., p-type) and corresponds to source or drain regions of the NMOS transistors N2-0, N2-1, N4-o, or N4- 1 off 2 . In some embodiments, the set of active regions 712 includes a p-type dopant in the well region 702a (e.g., n-type) and corresponds to source or drain regions of PMOS transistors (not shown) corresponding to NMOS transistors N2-0, N2-1, N4-0 or N4-1 off 2 are similar. Other amounts or configurations of the set of active regions 712 are within the scope of the present disclosure.

The integrated circuit 700 includes at least the active region 714a, 714b, 714c, 714d, or 714e (collectively referred to as “set of active regions 714”) in a well region 702b. In some embodiments, well region 702b is in substrate 750. In some embodiments, well region 702b includes an n-type dopant or a p-type dopant.

The set of active regions 714 extends in the second direction Y and is arranged on the first layout level of the integrated circuit 700 . All active regions of the set of active regions 714 are separated from each other in the first X direction. In some embodiments, the set of active regions 714 of the integrated circuit 700 is referred to as the OD region, which defines the source or drain diffusion regions of the integrated circuit 700. FIG. In some embodiments, the set of active regions 714 includes an n-type dopant in the well region 702b (eg, p-type) and corresponds to the source or drain regions of the NMOS transistors N1-0, N1-1, N3-0, or N3 -1 off 2 . In some embodiments, the set of active regions 714 includes a p-type dopant in the well region 702b (e.g., n-type) and corresponds to source or drain regions of PMOS transistors (not shown) corresponding to NMOS transistors N1-0, N1-1, N3-0 or N3-1 off 2 are similar. Other amounts or configurations of the set of active regions 714 are within the scope of the present disclosure.

The integrated circuit 700 further includes at least one gate oxide layer 760 extending in the first X direction. In some embodiments, gate oxide layer 760 covers a top surface of well region 750. In some embodiments, gate oxide layer 760 comprises an insulating material, a dielectric material, or the like.

The integrated circuit 700 further includes at least the gate 704a, 704b, 704c, 704d, 704e, or 704f (collectively referred to as "set of gates 704") extending in the second direction Y, overlapping at least the gate oxide layer 760, and is arranged on the second layout level of the integrated circuit 700 . In some embodiments, the set of gates 704 overlaps the set of active regions 712 and 714.

Each of the gates of the set of gates 704 is separated from an adjacent gate of the set of gates 404 in the second direction Y by a poly pitch (not shown).

Gate 704b corresponds to the gate of NMOS transistors N1-0 and N2-0 3 . Gate 704c corresponds to the gate of NMOS transistors N3-0 and N4-0 3 . Gate 704d corresponds to the gate of NMOS transistors N3-1 and N4-1 3 . Gate 704e corresponds to the gate of NMOS transistors N1-1 and N2-1 3 . In some embodiments, at least the gate 704a or 704f is formed as a dummy gate as part of a dummy transistor. In some embodiments, a dummy transistor is a non-functional transistor.

In some embodiments, the gate 704b is off at least the programming wordline WLP 1A , the programming word line WLPo off 2 or the programming word lines WLP' 3 . In some embodiments, gate 704c is off at least read word line WLR 1A , the read word line WLRo off 2 or the read word lines WLR' 3 . In some embodiments, the gate 704d is off at least the read word line WLR 1A , the read word line WLR1 off 2 or the read word lines WLR' 3 . In some embodiments, the gate 704e is at least the program wordline WLP off 1A , the program word line WLP1 off 2 or the program word lines WLP' 3 .

Other amounts or configurations of the set of gates 704 are within the scope of the present disclosure.

The integrated circuit 700 further includes at least one contact 710a, 710b, 710c, 710d, or 710e (collectively referred to as "set of contacts 710") that extends in the second direction Y, overlaps the set of active regions 712 and 714, and has the third layout level of the integrated circuit 700 is arranged.

In some embodiments, each of the contacts 710a, 710b, 710c, 710d, 710e of the set of contacts 710 is separated from an adjacent contact of the set of contacts 710 in at least the first direction X.

In some embodiments, contact 710a electrically connects active regions 712a and 714a. In some embodiments, contact 710a is a source or drain of NMOS transistor N1-0 and a source or drain of NMOS transistor N2-0 off 2 .

In some embodiments, contact 710b electrically connects active regions 712b and 714b. In some embodiments, contact 710b is a source or drain of NMOS transistor N1-0, a source or drain of NMOS transistor N2-0, a source or drain of NMOS transistor N3- O or a source or drain of the NMOS transistor N4-o 2 .

In some embodiments, contact 710c electrically connects active regions 712c and 714c. In some embodiments, contact 710c is a source or drain of NMOS transistor N3-1, a source or drain of NMOS transistor N4-1, a source or drain of NMOS transistor N3- 0 or a source or drain of NMOS transistor N4-0 2 .

In some embodiments, contact 710d electrically connects active regions 712d and 714d. In some embodiments, contact 710d is a source or drain of NMOS transistor N3-1, a source or drain of NMOS transistor N4-1, a source or drain of NMOS transistor N1- 1 or a source or drain of the NMOS transistor N2-1 2 .

In some embodiments, contact 710d electrically connects active regions 712d and 714d. In some embodiments, contact 710d is a source or drain of NMOS transistor N2-1 and a source or drain of NMOS transistor N1-1 off 2 .

Other amounts or configurations of the set of contacts 710 are within the scope of the present disclosure.

The integrated circuit 700 further includes at least the conductive structure 720a, 720b, 720c, or 720d (collectively referred to as “set of conductive structures 720”) extending at least in the first X direction. The set of conductive structures 720 is arranged on the fourth layout level. In some embodiments, the fourth layout level of integrated circuit 700 is the metal zero (Mo) level. In some embodiments, the Mo plane is disposed over at least one of the active region, the POLY plane, and the MD plane of the integrated circuit 700. FIG. Other layout levels fall within the scope of the present disclosure.

In some embodiments, the conductive structure 720a is at least the bit line BLo off 2 , the bit line BL off 1A or the bit lines BL' off 3 .

The set of conductive structures 720 overlaps at least the set of gates 704 or the set of contacts 710. In some embodiments, the conductive structure 720a overlaps each of the gates in the set of gate layout structures 404 and each of the contacts in the set of contacts 710.

Conductive structure 720b overlaps gates 704b, 704c, 704d and 704e and contacts 710b, 7100 and 710d. Conductive structure 720c overlaps gates 704a, 704b and 704c and contacts 710a and 710b. Conductive structure 720d overlaps gates 704d, 704e and 704f and contacts 710d and 710e.

Other amounts or configurations of the set of conductive structures 720 are within the scope of the present disclosure.

The integrated circuit 700 further includes at least one via 730a, 730b, or 730c (collectively referred to as “set of vias 730”) extending in a third Z direction.

In some embodiments, set of vias 730 electrically connects at least one conductive structure of set of conductive structures 720 to at least one gate of set of gates 704 .

In some embodiments, the set of vias 730 is arranged between the set of conductive structures 720 and the set of gates 704 . The via 730a, 730b, 730c is between the corresponding conductive structure 720b, 720c, 720d and the corresponding gate 704c, 704b, 704e. In some embodiments, the via 730a, 730b, 730c is located where a respective conductive structure 720b, 720c, 720d overlaps a respective gate 704c, 704b, 704e.

The set of vias 730 is located at the VG level of the integrated circuit 700 . Other layout levels fall within the scope of the present disclosure.

In some embodiments, the conductive structure 720b, 720c, 720d is electrically connected to the corresponding gate 704c, 704b, 704e through the corresponding via 730a, 730b, 730c.

Other configurations, arrangements at other layout levels, or quantities of vias in the set of vias 730 are within the scope of the present disclosure.

The integrated circuit 700 further includes at least one via 732a (collectively "set of vias 732" denoted) extending in the third direction Z.

In some embodiments, set of vias 732 electrically connects at least one conductive structure of set of conductive structures 720 to at least one contact of set of contacts 710. In some embodiments, conductive structure 720a is electrically connected to contact 7100 through via 732a.

In some embodiments, the set of vias 732 is between the set of conductive structures 720 and the set of contacts 710. The via 732a is between the conductive structure 720a and the contact 710c. In some embodiments, via 732a is located where conductive structure 720a overlaps contact 7100 .

The set of vias 732 is located at the VD level of the integrated circuit 700 . Other layout levels fall within the scope of the present disclosure.

Other configurations, arrangements at other layout levels, or quantities of vias in the set of vias 732 are within the scope of the present disclosure.

In some embodiments, at least gate 704a, gate 704b, gate 704c, active region 712a, active region 712b, a portion of active region 712c, active region 714a, active region 714b, a portion of active region 714c, contact 710a, the Contact 710b, a portion of contact 710c, via 730a, via 730b, via 730c, via 732a, conductive feature 720a, conductive feature 720b, or conductive feature 720c is part of a memory cell 790a.

In some embodiments, at least gate 704d, gate 704e, gate 704f, a portion of active region 712c, active region 712d, active region 712e, a portion of active region 714c, active region 714d, active region 714e, a portion of contact 710c , contact 710d, contact 710e, via 730c, via 732a, conductive feature 720a, or conductive feature 720d is part of a memory cell 790b.

In some embodiments, memory cells 790a and 790b are off, corresponding to memory cells 202 and 204 2 or corresponding memory cells 302[0,0] and 302[0,1]. 3 similar and therefore a similar detailed description is omitted.

PROCEEDINGS

8th 8 is a flow diagram of a method 800 for forming or manufacturing a memory circuit according to some embodiments. It is understood that additional operations before, during and/or after the in 8th The methods 800 illustrated may be performed and that some other operations may only be briefly described in this document. In some embodiments, method 800 may be used to construct memory circuits, such as memory cell 100A ( 1A ), the memory cell array 200A-200C ( 2A-2C ) or at least one memory cell in an array of cells 302 ( 3 ) or integrated circuits, such as the 700 integrated circuit ( 7 ), to train. In some embodiments, the method 800 can be used to create integrated circuits that have similar structural relationships as one or more of the layout designs 400 ( 4 ) or 600 ( 6 ) or the layout design 500A-500C ( 5A-5C ) have to train.

In operation 802 of the method 800, a layout design of a memory circuit is generated. Operation 802 is performed by a processing device (e.g., processor 1002 ( 10 )) configured to execute instructions to generate a layout design. In some embodiments, the layout design of the method 800 includes one or more of the layout designs 400 or 600. In some embodiments, the layout design of the present application includes features that 5A-5C are similar. In some embodiments, the layout design of the present application is in a Graphics Database System (GDSII) file format.

In operation 804 of the method 800, the memory circuit is fabricated based on the layout design. In some embodiments, act 804 of method 800 includes fabricating at least one mask based on the layout design and fabricating the memory circuit based on the at least one mask.

In some embodiments, layout design 400, 500A-500C, or 600 is a standard cell. In some embodiments, one or more of acts 802 or 804 are not performed.

9 9 is a flowchart of a method 900 for generating a layout design an integrated circuit according to some embodiments. It is understood that additional operations before, during and/or after the im 9 The method 900 illustrated may be performed and that some other operations may only be briefly described in this document. In some embodiments, method 900 is an embodiment of operation 802 of method 800. In some embodiments, method 900 may be used to create one or more layout structures of layout design 400, 500A-500C, or 600 of a memory circuit (e.g., memory cell 100A, memory cell array 200A-200C to generate at least one memory cell of the array of cells 302 of the memory cell array 300) or an integrated circuit (eg integrated circuit 700).

In act 902 of the method 900, a first programmer layout is generated or placed. In some embodiments, the first programmer layout includes at least region 406a, 406b, 408a, or 408b. In some embodiments, generating the first programming device layout includes generating a first transistor layout design corresponding to fabricating a first transistor of the first programming device and generating a second transistor layout design corresponding to fabricating a second transistor of the first programming device. In some embodiments, the first transistor of the first programming device of operation 902 includes at least NMOS transistor N1-0, N2-0, N1-1, or N2-1. In some embodiments, the first transistor and the second transistor of method 900 are configured to share a first gate and are connected in parallel with each other. In some embodiments, operation 902 is performed for each region (406a, 406b, 408a, 408b) that has a transistor layout design as shown in FIG 4A-4C has shown repeatedly. In some embodiments, act 902 is performed for other programmer layouts that have corresponding transistor layout designs as shown in FIG 4A-4C have shown repeatedly.

In act 904 of the method 900, a first reader layout is generated or placed. In some embodiments, the first reader layout includes at least region 406a, 406b, 408a, or 408b. In some embodiments, generating the first reader layout includes generating a third transistor layout design corresponding to fabricating a third transistor of the first reader and generating a fourth transistor layout design corresponding to fabricating a fourth transistor of the first reader. In some embodiments, the third transistor of the first read device of operation 904 includes at least NMOS transistor N3-0, N4-0, N3-1, or N4-1. In some embodiments, the third transistor and the fourth transistor of method 900 are configured to share a second gate and are connected in parallel with each other. In some embodiments, the first reader layout is adjacent to the first reader layout. In some embodiments, operation 904 is performed for each region (406a, 406b, 408a, 408b) that has a transistor layout design as shown in FIG 4A-4C has shown repeatedly. In some embodiments, act 904 is performed for other programmer layouts that have corresponding transistor layout designs as shown in FIG 4A-4C have shown repeatedly.

In some embodiments, at least act 902 or 904 further comprises generating or placing a first active region layout structure and a second active region layout structure extending in the first X direction, arranged on the first layout level and separated in the second Y direction are. In some embodiments, the first active region layout structure of act 902 or 904 includes active region layout structure 402a or 402b. In some embodiments, the second active region layout structure of act 902 or 904 includes active region layout structure 402a or 402b.

In act 906 of the method 900, a first wordline layout pattern is generated or placed on the layout design 400 or 600. FIG. In some embodiments, the first wordline layout structure includes at least one of the set of gate layout structures 402 .

In act 908 of the method 900, a second wordline layout pattern is generated or placed on the layout design 400 or 600. FIG. In some embodiments, the second wordline layout structure includes at least one of the set of gate layout structures 402 .

In operation 910 of the method 900, a bit line layout structure is generated or placed on the layout design 400 or 600. FIG. In some embodiments, the bit line layout structure includes at least one of the set of routing feature layout structures 420 . In some embodiments, act 910 includes generating or placing a set of signage layout structures. In some embodiments, the set of directional feature layout structures of operation 910 includes the set of directional feature layout structures 420 .

In operation 912 of the method 900, a set of via layout structures is generated or placed on the layout design 400 or 600. FIG. In some embodiments, the set of via layout structures includes at least one of the set of via layout structures 430 or 432 .

In act 914 of the method 900, a set of metal-over-diffusion layout structures is generated or placed on the layout design 400 or 600. FIG. In some embodiments, the set of metal-over-diffusion layout structures includes at least one of the set of metal-over-diffusion layout structures 410 .

In some embodiments, one or more of acts 902, 904, 906, 908, 910, 912, or 914 are not performed.

One or more of the acts of methods 800-900 are performed by a processing device configured to process instructions for fabricating a memory circuit, such as memory cell 100A, memory cell array 200A-200C, or at least one memory cell of array of cells 302 of memory cell array 300, or an integrated circuit, for example integrated circuit 700.

In some embodiments, one or more acts of methods 800-900 are performed using the same processing device as that used in one or more other acts of methods 800-900. In some embodiments, to perform one or more acts of methods 800-900, a different processing device than that used to perform one or more other acts of methods 800-900 is used.

10 1000 is a schematic view of a system 1000 for designing and manufacturing an IC layout design, according to some embodiments. In some embodiments, the system 1000 generates or places one or more IC layout designs described in this document. In some embodiments, the system 1000 manufactures one or more ICs based on the one or more IC layout designs described in this document. The system 1000 includes a hardware processor 1002 and a non-transitory computer-readable storage medium 1004 encoded with, ie, storing, computer program code 1006, ie, a set of executable instructions. The computer-readable storage medium 1004 is configured to be coupled to production machines for manufacturing the integrated circuit. The processor 1002 is electrically connected to the computer-readable storage medium 1004 by a bus 1008 . The processor 1002 is also electrically connected to an I/O interface 1010 through the bus 1008 . A network interface 1012 is also electrically connected to processor 1002 through bus 1008 . The network interface 1012 is connected to a network 1014 such that the processor 1002 and the computer-readable storage medium 1004 are able to connect to external elements via the network 1014 . Processor 1002 is configured to execute computer program code 1006 encoded on computer-readable storage medium 1004 to cause system 1000 to perform some or all of the operations described in method 800 or 900 is.

In some embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and/or any suitable processing unit.

In some embodiments, computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and/or semiconductor system (or device or apparatus). For example, computer-readable storage medium 1004 includes semiconductor or solid state memory, magnetic tape, removable computer disk, random access memory (RAM), read only memory (ROM), magnetic hard disk, and/or optical disk. In some embodiments using optical disks, the computer-readable storage medium 1004 comprises compact disk read only memory (CD-ROM), compact disk read/write memory (CD-R/W) and/or or a digital video disc (DVD).

In some embodiments, storage medium 1004 stores computer program code 1006 configured to cause system 1000 to perform method 800 or 900. In some embodiments, storage medium 1004 also stores information needed to perform method 800 or 900, as well as information generated during performance of method 800 or 900, such as layout design 1016 and user interface 1018 and production unit 1020, and/or a Set of executable instructions to perform operation of method 800 or 900. In some embodiments, the layout design 1016 includes a or multiple layout structures of layout design 400 or 600.

In some embodiments, storage medium 1004 stores instructions (e.g., computer program code 1006) for interfacing with production machines. The instructions (e.g., computer program code 1006) enable processor 1002 to generate production instructions that can be read by production machines to effectively implement method 800 or 900 during a production process.

System 1000 includes I/O interface 1010 . The I/O interface 1010 is connected to external circuits. In some embodiments, I/O interface 1010 includes a keyboard, keypad, mouse, trackball, trackpad, and/or cursor direction keys for communicating information and commands to processor 1002 .

The system 1000 also has the network interface 1012 that is connected to the processor 1002 . Network interface 1012 allows system 1000 to communicate with network 1014 to which one or more other computer systems are connected. As network interface 1012 can be used: wireless network interfaces such as BLUETOOTH, WIFI, WIMAX, GPRS or WCDMA; or wired network interfaces such as ETHERNET, USB or IEEE-13104. In some embodiments, the method 800 or 900 is implemented in two or more systems 1000 and information such as layout design, user interface, and unit of production is exchanged between the different systems 1000 through the network 1014 .

The system 1000 is configured to receive information related to a layout design through the I/O interface 1010 or the network interface 1012 . The information is transmitted through bus 1008 to processor 1002 to provide a layout design for fabricating an IC (e.g., memory cell 100A, memory cell array 200A-200C, at least one memory cell of array of cells 302 of memory cell array 300, or integrated circuit 700). determine. The layout design is then stored in computer readable medium 1004 as layout design 1016 . The system 1000 is configured to receive information related to a user interface through the I/O interface 1010 or the network interface 1012 . The information is stored in computer-readable medium 1004 as user interface 1018 . The system 1000 is configured to receive information related to a production unit through the I/O interface 1010 or the network interface 1012 . The information is stored in the computer-readable medium 1004 as a unit of production 1020 . In some embodiments, production entity 1020 includes production information used by system 1000 .

In some embodiments, the method 800 or 900 is implemented as a standalone software application for execution by a processor. In some embodiments, the method 800 or 900 is implemented as a software application that is part of an additional software application. In some embodiments, the method 800 or 900 is implemented as a plugin for a software application. In some embodiments, the method 800 or 900 is implemented as a software application that is a portion of an EDA tool. In some embodiments, the method 800 or 900 is implemented as a software application used by an EDA tool. In some embodiments, the EDA tool is used to generate a layout design of the integrated circuit device. In some embodiments, the layout design is stored on a non-transitory computer-readable medium. In some embodiments, the layout design is generated using a tool such as the VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc. or any other suitable layout generation tool. In some embodiments, the layout design is generated based on a netlist created based on the schematic design. In some embodiments, method 800 or 900 is implemented by a manufacturing device to fabricate an integrated circuit using a set of masks fabricated based on one or more layout designs generated by system 1000 . In some embodiments, the system 1000 is a manufacturing device to manufacture an integrated circuit by using a set of masks manufactured based on one or more layout designs of the present disclosure. In some embodiments, the system generates 1000 from 10 IC layout designs that are smaller than other solutions. In some embodiments, the system generates 1000 from 10 Layout designs of an IC (eg, memory cell 100A, memory cell array 200A-200C, at least one memory cell of array of cells 302 of memory cell array 300, or integrated circuit 700) that take up less space than other solutions.

11 11 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an associated IC manufacturing flow, in accordance with at least one embodiment of the present disclosure.

In 11 the IC manufacturing system 1100 includes entities such as a design house 1120, a mask house 1130, and an IC manufacturer/producer ("Fab") 1140 that interact with each other in the design, development, and manufacturing cycles and/or services associated with manufacturing an IC device 1160. The entities in the system 1100 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network has wired and/or wireless communication paths. Each entity interacts with one or more of the other entities and provides services and/or receives services from one or more of the other entities. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC fab 1140 are owned by a single larger corporation. In some embodiments, two or more of the design house 1120, the mask house 1130, and the IC fab 1140 coexist in a common facility and share common resources.

The design house (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric structures designed for an IC device 1160. FIG. The geometric structures correspond to structures of metal, oxide, or semiconductor layers that form the various components of the IC device 1160 to be fabricated. The different layers combine to form different IC features. For example, a portion of the IC design layout 1122 includes various IC features, such as an active region, a gate electrode, a source electrode, and a drain electrode, metal lines or vias of an interlayer connection, and openings for contact pads formed in a semiconductor substrate (e.g a silicon wafer) and various material layers arranged on the semiconductor substrate. The design house 1120 implements an appropriate design process to form the IC design layout 1122 . The design process includes one or more of logical design, physical design, or placement and routing. The IC design layout 1122 resides in one or more data files containing information about the geometric structures. For example, the IC design layout 1122 can be expressed in a GDSII file format or a DFII file format.

The mask house 1130 includes data generation 1132 and mask manufacture 1134. The mask house 1130 uses the IC design layout 1122 to manufacture one or more masks to be used to manufacture the various layers of the IC device 1160 according to the IC design layout 1122. The mask house 1130 performs mask data creation 1132, translating the IC design layout 1122 into a representative data file ("RDF"). The mask data creation 1132 provides the RDF for the mask creation 1134 . Mask making 1134 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) or semiconductor wafer. The design layout is edited by the mask data builder 1132 to meet specific characteristics of the mask writer and/or IC fab 1140 requirements. In 11 mask data creation 1132 and mask creation 1134 are shown as separate elements. In some embodiments, mask data creation 1132 and mask creation 1134 may be collectively referred to as mask data creation.

In some embodiments, mask data creation 1132 includes optical proximity correction (OPC) using lithography enhancement techniques to compensate for artifacts such as those that may arise from diffraction, interference, other process effects, and the like. OPC aligns IC design layout 1122. In some embodiments, mask data creation 1132 further includes resolution enhancement (RET) techniques, such as oblique illumination, sub-resolution assist features, phase shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging task.

In some embodiments, the mask data creation 1132 includes a mask rule checker (MRC) that checks the IC design layout that has undergone processes in the OPC with a set of mask creation rules that include certain geometric and/or connectivity-related constraints to ensure certain margins to to account for variability in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout to compensate for constraints during mask fabrication 1134 , which can undo some of the modifications made by the OPC to comply with mask generation rules.

In some embodiments, mask data creation 1132 includes a lithography process check (LPC) that simulates the processing implemented by IC fab 1140 to fabricate IC device 1160 . The LPC simulates this processing based on the IC design layout 1122 to create a simulated manufactured device, such as IC device 1160 . The processing parameters in LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture the IC, and/or other aspects of the manufacturing process. The LPC takes into account various factors, such as aerial image contrast, depth of field ("DOF"), mask error enhancement factor ("MEEF"), other appropriate factors, and the like, or combinations thereof. In some embodiments, after a simulated manufactured device is created using LPC, if the simulated device does not conform enough in shape to meet design rules, repeat OPC and/or MRC to further refine the IC design layout 1122 .

It should be understood that the foregoing description of mask data generation 1132 has been simplified for clarity. In some embodiments, data creation 1132 includes additional features, such as a logic operation (LOP) to modify the IC design layout according to manufacturing rules. Additionally, the processes applied to the IC design layout 1122 during data creation 1132 can be performed in several different orders.

After mask data creation 1132 and during mask fabrication 1134, a mask or group of masks are fabricated based on the modified IC design layout. In some embodiments, an electron beam (e-beam) or multiple e-beam mechanism is used to form a pattern on a mask (photomask or reticle) based on the modified IC design layout. The mask can be formed using various technologies. In some embodiments, the mask is formed using binary technology. In some embodiments, a mask pattern has opaque regions and clear regions. A beam, such as an ultraviolet (UV) beam, used to expose the image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque region and transmitted by the clear regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the mask. In another example, the mask is formed using phase shifting technology. In the phase shift mask (PSM), various features in the pattern formed on the mask are designed to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuated PSM or an alternating PSM. The mask(s) generated by the mask fabrication 1134 is (are) used in a number of processes. For example, such mask(s) is(are) used in an ion implantation process to form various doped regions in the semiconductor wafer, in an etch process to form various etch regions in the semiconductor wafer, and/or in other suitable processes.

The IC Fab 1140 is an IC manufacturing entity that includes one or more manufacturing facilities for manufacturing a variety of IC products. In some embodiments, IC fab 1140 is a semiconductor foundry. For example, there may be one manufacturing facility for the front-end manufacture of a plurality of IC products (Front-End-of-Line (FEOL) manufacture), while a second manufacturing facility for the back-end manufacture for the interconnection of the IC products with each other and the packaging (back-end-of-line (BEOL) manufacturing) and a third manufacturing facility may provide other services to the foundry entity.

The IC fab 1140 uses the mask (or masks) manufactured by the mask house 1130 to manufacture the IC device 1160. FIG. Thus, the IC fab 1140 at least indirectly uses the IC design layout 1122 to manufacture the IC device 1160. In some embodiments, a semiconductor wafer 1142 is fabricated by the IC fab 1140 using the mask (or masks) to form the IC device 1160 . The semiconductor wafer 1142 includes a silicon substrate or other suitable substrate on which layers of material are formed. The semiconductor wafer also includes one or more various doped regions, dielectric features, multi-level interconnects, and the like (formed at subsequent fabrication steps).

The system 1100 is shown as having the design house 1120, the mask house 1140, or the IC fab 1140 as separate components or entities. However, it is understood that one or more of the design house 1120, the mask house 1130, or the IC fab 1140 are part of the same component or entity.

Details regarding an integrated circuit (IC) manufacturing system (e.g., System 1100 from 11 ) and an associated IC manufacturing flow are e.g. in U.S. 9,256,709 B2 , issued February 9, 2016, in the U.S. 2015/0278429 A1 , published October 1, 2015, in the U.S. 2010/0040838 A1 , published February 18, 2010, and in U.S. 7,260,442 B2 , granted August 21, 2007.

Those of ordinary skill in the art will readily appreciate that one or more of the disclosed embodiments can provide one or more advantages set forth above. After reading the foregoing description, those of ordinary skill in the art will be able to make various changes, substitutions for equivalents, and various other embodiments broadly disclosed in this document. Accordingly, it is intended that the protection accorded thereto be limited only by the definition contained in the appended claims and equivalents thereof.

One aspect of this description relates to a memory circuit. In some embodiments, the memory circuit includes a first reading device and a first programming device. In some embodiments, the first reading device is connected to a first bit line. In some embodiments, the first programming device is connected to the first reading device. In some embodiments, the first reading device includes a first transistor connected to a first wordline and a second transistor connected to the first wordline. In some embodiments, the first programming device includes a third transistor connected to a second wordline and a fourth transistor connected to the second wordline. In some embodiments, the second transistor is connected in parallel with the first transistor. In some embodiments, the fourth transistor is connected in parallel with the third transistor. In some embodiments, the first transistor has a first terminal, a second terminal, and a third terminal. In some embodiments, the second transistor has a first terminal, a second terminal, and a third terminal. In some embodiments, the first terminal of the first transistor, the first terminal of the second transistor and the first word line are connected to each other. In some embodiments, the second terminal of the first transistor is connected to the second terminal of the second transistor. In some embodiments, the third terminal of the first transistor is connected to at least the third terminal of the second transistor. In some embodiments, the third transistor has a first terminal, a second terminal, and a third terminal. In some embodiments, the fourth transistor has a first terminal, a second terminal, and a third terminal. In some embodiments, the first terminal of the third transistor, the first terminal of the fourth transistor and the second word line are connected to each other. In some embodiments, the second terminal of the third transistor, the second terminal of the fourth transistor, the third terminal of the first transistor, and the third terminal of the second transistor are connected together. In some embodiments, the third terminal of the third transistor, the third terminal of the fourth transistor, and the first bit line are connected to each other. In some embodiments, the memory circuit further includes a second reading device and a second programming device. In some embodiments, the second reading device is connected to the first bit line. In some embodiments, the second reading device includes a fifth transistor connected to a third wordline and a sixth transistor connected to the third wordline. In some embodiments, the second programming device is connected to the second reading device. In some embodiments, the second programming device includes a seventh transistor connected to a fourth wordline and an eighth transistor connected to the fourth wordline. In some embodiments, the fifth transistor has a first terminal, a second terminal, and a third terminal. In some embodiments, the sixth transistor has a first terminal, a second terminal, and a third terminal. In some embodiments, the first terminal of the fifth transistor, the first terminal of the sixth transistor and the first word line are connected to each other. In some embodiments, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor. In some embodiments, the third terminal of the fifth transistor is connected to at least the third terminal of the sixth transistor. In some embodiments, the seventh transistor has a first terminal, a second terminal, and a third terminal. at man In some embodiments, the eighth transistor has a first connection, a second connection and a third connection. In some embodiments, the first connection of the seventh transistor, the first connection of the eighth transistor and the second word line are connected to one another. In some embodiments, the second terminal of the seventh transistor, the second terminal of the eighth transistor, the third terminal of the fifth transistor, and the third terminal of the sixth transistor are connected together. In some embodiments, the third terminal of the seventh transistor, the third terminal of the eighth transistor and the first bit line are connected to each other. In some embodiments, each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises an n-metal oxide semiconductor (NMOS) transistor. In some embodiments, each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a p-metal oxide semiconductor (PMOS) transistor.

Another aspect of this specification relates to a memory cell array. In some embodiments, the memory cell array includes a first bit line, a first word line, a second word line, and a first memory cell. In some embodiments, the first bit line extends in a first direction. In some embodiments, the first word line extends in a second direction different from the first direction. In some embodiments, the second wordline extends in the second direction. In some embodiments, the first memory cell is connected to the first bit line, the first word line, and the second word line. In some embodiments, the first memory cell includes a first reading device and a first programming device. In some embodiments, the first reading device is connected to the first bit line and the second word line. In some embodiments, the first programming device is connected to the first word line and the first reading device. In some embodiments, the first programming device includes a first transistor and the second transistor. In some embodiments, the first transistor is connected to the first wordline. In some embodiments, the second transistor is connected in parallel with the first transistor and connected to the first wordline. In some embodiments, the first memory cell further includes a first read device connected to the first bit line and the second word line. In some embodiments, the first reading device includes a third transistor connected to the second wordline, the first bitline, the first transistor, and the second transistor. In some embodiments, the first reading device further includes a fourth transistor and the fifth transistor. In some embodiments, the fourth transistor is connected to the second wordline, the first bitline, the first transistor, and the second transistor. In some embodiments, the fifth transistor is connected to the second wordline, the first bitline, the first transistor, and the second transistor. In some embodiments, the fourth transistor, the fifth transistor, and the third transistor are connected in parallel with each other. In some embodiments, the memory cell array further includes a third word line, a fourth word line, and a second memory cell. In some embodiments, the third word line extends in the second direction. In some embodiments, the fourth wordline extends in the second direction. In some embodiments, the second memory cell is connected to the first bit line, the third word line, and the fourth word line. In some embodiments, the second memory cell includes a second reading device and a second programming device. In some embodiments, the second reading device is connected to the first bit line and a third word line. In some embodiments, the second programming device is connected to the fourth word line and the first reading device. In some embodiments, a number of transistors in the second programming device is different from a number of transistors in the second reading device. In some embodiments, a number of transistors in at least one of the second programming device and the second reading device is different than a number of transistors in at least one of the first programming device and the first reading device. In some embodiments, the first memory cell is a one-time programmable (OTP) non-volatile memory (NVM).

Yet another aspect of this specification relates to a method of fabricating a memory cell circuit. In some embodiments, the method includes generating, by a processor, a first programming device layout corresponding to manufacturing a first programming device of the memory circuit, generating a first reading device layout corresponding to manufacturing a first reading device of the memory circuit, and manufacturing the memory circuit based on at least the first programmer layout or the first reader layout. In some embodiments, the first reader layout is adjacent to the first reader layout. In some embodiments generating the first programming device layout comprises generating a first transistor layout design corresponding to fabricating a first transistor of the first programming device and generating a second transistor layout design corresponding to fabricating a second transistor of the first programming device. In some embodiments, the first transistor and the second transistor share a first gate and are connected in parallel with each other. In some embodiments, the method further includes generating a second programming device layout that corresponds to fabricating a second programming device of the memory circuit. In some embodiments, generating the second programming device layout includes generating a third transistor layout design that corresponds to fabricating a third transistor of the second programming device and generating a fourth transistor layout design that corresponds to fabricating a fourth transistor of the second programming device. In some embodiments, the third transistor and the fourth transistor share a second gate, and the third transistor is connected in parallel with the fourth transistor. In some embodiments, generating the first transistor layout design, the second layout design, the third transistor layout design, or the fourth layout design includes generating a first active region layout structure in a second active region layout structure and generating a set of gate layout structures. In some embodiments, the first active region layout pattern and the second active region layout pattern extend in a first direction, are arranged on a first layout level, and are separated from each other in a second direction different from the first direction. In some embodiments, the first active region layout structure corresponds to fabricating a first active region of the first transistor and the third transistor. In some embodiments, the second active region layout structure corresponds to fabricating a second active region of the second transistor and the fourth transistor. In some embodiments, the set of gate layout structures extends in a second direction that is different than the first direction. In some embodiments, the set of gate layout structures overlaps the first active region layout structure and the second active region layout structure. In some embodiments, the set of gate layout structures is arranged on a second layout level different from the first layout level. In some embodiments, the set of gate layout structures corresponds to fabricating a set of gates that includes the first gate and the second gate.

Claims (20)

Storage circuit, comprising: a first reading device (102) connected to a first bit line (BL, 420a), the first reading device comprising: a first transistor (N3, N3-0) connected to a first word line (WLR, WLRo); and a second transistor (N4, N4-0) connected to the first word line (WLR, WLRo); and a first programming device (104) connected to the first reading device (102), the first programming device (104) comprising: a third transistor (N1, N1-0) connected to a second word line (WLP, WLPo); and a fourth transistor (N2, N2-0) connected to the second word line (WLP, WLPo); whereby: the first transistor (N3, N3-0) has a first terminal, a second terminal and a third terminal; and the second transistor (N4, N4-0) has a first connection, a second connection and a third connection, the first connection of the first transistor (N3, N3-0), the first connection of the second transistor (N4, N4-0) and the first word line (WLR, WLRo) are connected to one another, the second terminal of the first transistor (N3, N3-0) is connected to the second terminal of the second transistor (N4, N4-0), and the third connection of the first transistor (N3, N3-0) is connected to at least the third connection of the second transistor (N4, N4-0). memory circuit after claim 1 , wherein the second transistor (N4, N4-0) is connected in parallel with the first transistor (N3, N3-0). memory circuit after claim 1 or 2 , wherein the fourth transistor (N2, N2-0) is connected in parallel with the third transistor (N1, N1-0). Memory circuit according to one of the preceding claims, wherein the second terminal of the first transistor (N3, N3-0) and the second terminal of the second transistor (N4, N4-0) are connected to the first bit line (BL, 420a). Memory circuit according to one of the preceding claims, wherein the third transistor (N1, N1-0) has a first terminal, a second terminal and a third terminal; and the fourth transistor (N2, N2-0) has a first terminal, a second terminal and a third terminal, the first terminal of the third transistor (N1, N1-0), the first terminal of the fourth transistor (N2, N2-0) and the second word line (WLP, WLPo) are connected together, the second terminal of the third transistor (N1, N1-0), the second terminal of the fourth transistor (N2, N2-0), the third Connection of the first transistor (N3, N3-0) and the third connection of the second transistor (N4, N4-0) are connected to each other and the third connection of the third transistor (N1, N1-0) and the third connection of the fourth transistor ( N2, N2-0) are connected to each other. A memory circuit according to any one of the preceding claims, further comprising: a second reading device connected to the first bit line (BL, 420a), the second reading device comprising: a fifth transistor (N3-1) connected to a third word line (WLR1); and a sixth transistor (N4-1) connected to the third word line (WLR1); and a second programming device connected to the second reading device, the second programming device comprising: a seventh transistor (N1-1) connected to a fourth word line (WLP1); and an eighth transistor (N2-1) connected to the fourth word line (WLP1). memory circuit after claim 6 , wherein the fifth transistor (N3-1) has a first terminal, a second terminal and a third terminal; and the sixth transistor (N4-1) has a first terminal, a second terminal and a third terminal, the first terminal of the fifth transistor (N3-1), the first terminal of the sixth transistor (N4-1) and the third word line ( WLR1) are connected together, the second terminal of the fifth transistor (N3-1) is connected to the second terminal of the sixth transistor (N4-1) and the first bit line (BL, 420a) and the third terminal of the fifth transistor (N3- 1) is connected to at least the third terminal of the sixth transistor (N4-1). memory circuit after claim 7 , wherein the seventh transistor (N1-1) has a first terminal, a second terminal and a third terminal; and the eighth transistor (N2-1) has a first terminal, a second terminal and a third terminal, the first terminal of the seventh transistor (N1-1), the first terminal of the eighth transistor (N2-1) and the fourth word line ( WLP1) are connected to each other, the second connection of the seventh transistor (N1-1), the second connection of the eighth transistor (N2-1), the third connection of the fifth transistor (N3-1) and the third connection of the sixth transistor (N4 -1) are connected to each other and the third connection of the seventh transistor (N1-1) and the third connection of the eighth transistor (N2-1) are connected to each other. A memory circuit as claimed in any preceding claim, wherein each of the first transistor (N3, N3-0), the second transistor (N4, N4-0), the third transistor (N1, N1-0) and the fourth transistor (N2, N2 -0) comprises an n-metal oxide semiconductor (NMOS) transistor. A memory circuit as claimed in any preceding claim, wherein each of the first transistor (N3, N3-0), the second transistor (N4, N4-0), the third transistor (N1, N1-0) and the fourth transistor (N2, N2 -0) comprises a p-metal oxide semiconductor (PMOS) transistor. Memory cell array, comprising: a first bit line (BL, 420a) extending in a first direction (X); a first word line (WLP, WLPo, 404b) extending in a second direction (Y) different from the first direction (X); a second word line (WLR, WLRo, 404c) extending in the second direction (Y); and a first memory cell (202, 202'') connected to the first bit line (BL, 420a), the first word line (WLP, WLPo, 404b) and the second word line (WLR, WLRo, 404c), the first memory cell having: a first read device (102) connected to the first bit line (BL, 420a) and the second word line (WLR, WLRo, 404c); and a first programming device (104) connected to the first word line (WLP, WLP0, 404b) and to the first reading device (102), the first programming device comprising: a first transistor (N1, N1-0) connected to the first word line (WLP, WLPo, 404b); and a second transistor (N2, N2-0) connected in parallel with the first transistor (N1, N1-0) and connected to the first word line (WLP, WLP0, 404b); wherein the first reading device (102) comprises: a third transistor (N3, N3-0) connected to the second word line (WLR, WLRo, 404c), the first bit line (BL, 420a), the first transistor (N1, N1-0) and the second transistor (N2, N2-0) is connected. memory cell array after claim 11 , the first reading device (102) further comprising: a fourth transistor (N4, N4-0) connected to the the second word line (WLR, WLRo, 404c), the first bit line (BL, 420a), the first transistor (N1, N1-0) and the second transistor (N2, N2-0); wherein the third transistor (N3, N3-0) and the fourth transistor (N4, N4-0) are connected in parallel with each other. memory cell array after claim 12 , wherein the first reading device further comprises: a fifth transistor (N6-0) connected to the second word line (WLRo), the first bit line (BL, 420a), the first transistor (N1-0) and the second transistor (N2- 0), wherein the fourth transistor (N4-0), the fifth transistor (N6-0) and the third transistor (N3-0) are connected in parallel with each other. Memory cell array according to one of Claims 11 until 13 , further comprising: a third word line (WLR1) extending in the second direction (Y); a fourth word line (WLP1) extending in the second direction (Y); a second memory cell (204, 204'') connected to the first bit line (BL, 420a), the third word line (WLR1) and the fourth word line (WLP1), the second memory cell comprising: a second read device connected to the first bit line (BL, 420a) and the third word line (WLR1); and a second programming device connected to the fourth word line (WLP1) and the second reading device. memory cell array after Claim 14 , wherein the number of transistors in the second programming device is different than the number of transistors in the second reading device. memory cell array after Claim 14 wherein the number of transistors in at least one of the second programming device and the second reading device is different than the number of transistors in at least one of the first programming device and the first reading device. Memory cell array according to one of Claims 11 until 16 , wherein the first memory cell (202, 202'') is a one-time programmable non-volatile memory. A method (900) of fabricating a memory circuit (700), the method comprising: generating (902), by a processor, a first programmer layout corresponding to fabricating a first programmer (104) of the memory circuit (700), wherein generating the first programmer layout comprises: generating a first transistor layout design corresponding to fabricating a first transistor (N1, N1-0) of the first programming device (104); and generating a second transistor layout design corresponding to fabricating a second transistor (N2, N2-0) of the first programming device (104), wherein the first transistor (N1, N1-0) and the second transistor (N2, N2-0) are a first gate (704b) in common and connected in parallel with each other; generating (904) a first reader layout corresponding to fabricating a first reader (102) of the memory circuit (700), the first reader layout being adjacent to the first programmer layout; and fabricating the memory circuit (700) based on at least one of the first programmer layout and the first reader layout; wherein the first transistor (N1, N1-0) has a first connection, a second connection and a third connection, the second transistor (N2, N2-0) has a first connection, a second connection and a third connection, the first terminal of the first transistor (N1, N1-0) and the first terminal of the second transistor (N2, N2-0) are connected to the first gate (704b), the second terminal of the first transistor (N1, N1-0) and the second terminal of the second transistor (N2, N2-0) are connected to each other and to the first reading device (102) via a first contact (710b), and the third connection of the first transistor (N1, N1-0) and the third connection of the second transistor (N2, N2-0) are connected to one another via a second contact (710a). Method (900) after claim 18 , further comprising: generating a second programming device layout corresponding to fabricating a second programming device of the memory circuit (700), wherein generating the second programming device layout comprises: generating a third transistor layout design corresponding to fabricating a third transistor (N1-1) of the second programming device ; and generating a fourth transistor layout design corresponding to fabricating a fourth transistor (N2-1) of the second programming device, the third transistor (N1-1) and the fourth transistor (N2-1) sharing a second gate (704e) and the third transistor is connected in parallel with the fourth transistor. Method (900) after claim 19 , wherein generating the first transistor layout design, the second transistor layout design, the third transistor layout design or the fourth transistor layout design comprises: generating a first active region layout structure (402a) and a second active region layout structure (402b) extending in a first direction (X). , are arranged on a first layout level (OD) and are separated from each other in a second direction (Y) different from the first direction, the first active region layout structure (402a) preceding the fabrication of a first active region (702a) of the first Transistor (N1-0) and the third transistor (N1-1) and the second active region layout structure (402b) corresponds to forming a second active region (702b) of the second transistor (N2-0) and the fourth transistor (N2-1) is equivalent to; and generating a set of gate layout structures (404) extending in the second direction (Y), overlapping the first active region layout structure (402a) and the second active region layout structure (402b) and at a second layout level (PO), different from the first layout level (OD), wherein the set of gate layout structures corresponds to fabricating a set of gates including the first gate (704b) and the second gate (704e).

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