DE102019104124A1 - Method and device for minimum common-mode control of a differential data bus with low-side driver strength control - Google Patents

Abstract

The invention relates to a method for reducing common-mode generation in a differential data bus. The edges are synchronized by regulating the driver strength in the low-side path.

Description

Generic term

The invention is directed to a method and an associated device for reducing common-mode generation in a differential data bus.

General introduction

The CAN data bus is a widely used bus system in automobile computer network systems. The CAN data bus is based on two data bus lines (CH, CL), a first data bus line (CH) and a second data bus line (CL). The CAN bus essentially has two states of its data lines (CH, CL). In a first state, the CAN data bus assumes a so-called recessive state. In this case, the voltage potentials of the two data lines (CH, CL) are approximately at the same potential, the recessive potential (CLH _rez ). We refer to here 1 . The drivers of the bus nodes are then switched off and an auxiliary device of the CAN data bus then forces the data bus lines (CH, CL) to the said recessive voltage potential (CLH _rez ) with the aid of relatively high-resistance voltage sources.

The procedure presented here is not limited to this type of data bus.

In 2 an exemplary prior art driver is shown. The exemplary driver from the prior art comprises an upper switch (TH), which is preferably a P-channel MOS transistor and which has the first data line (CH) of the two data lines (CH, CL) of the differential data bus at a high potential (CH _dom ), preferably the supply voltage (VCC), above said recessive voltage potential (CLH _rez ) can draw. (See also 1 .) The exemplary driver from the prior art includes a lower switch (TL), which is preferably an N-channel MOS transistor and which connects the second data line (CL) of the two data lines (CH, CL) of the differential data bus low potential (CL _dom ), preferably the supply ground (GND), below said recessive voltage potential (CLH _rez ).

The upper switch (TH) and the lower switch (TL) are controlled in the prior art by a preferably common transmission signal (TX).

If the transmission signal (TX) is inactive, the upper switch (TH) and the lower switch (TL) are blocked. If this applies to all bus nodes in the bus system, a resistor network, which is preferably present on the bus and is not shown here, draws the first data line (CH) and the second data line (CL) to said average recessive potential (CLH _rez ) as an exemplary auxiliary _device .

If the transmission signal (TX) is active, the upper switch (TH) and the lower switch (TL) are closed, i.e. conductive with low resistance. This raises the first data line (CH) to the higher potential (CH _dom ), i.e. preferably the supply voltage potential (VCC), while the second data line (CL) is raised to the lower potential (CL _dom ), i.e. preferably the supply ground (GND) , is lowered. Said recessive potential (CLH _rez ) of the resistor network is overwritten, since the internal resistance of the exemplary resistor network is higher. This state of the data bus is referred to below as the dominant state. The course of the potential (V) of the voltage potential ( V _CH ) of the first data line (CH) is in the 1 With V _CH designated. It is the potential ( V _CH ) of the first data line (CH) with respect to a reference ground (typ. GND). The course of the potential (V) of the voltage potential ( V _CL ) of the second data line (CL) is in the 1 With V _CL designated. It is the potential ( V _CL ) of the second data line (CL) to a reference ground (typ. GND). This change from the recessive state to the dominant state is in 1 plotted against time (t).

The internal resistance of the voltage sources that determine the bus potential in the recessive state is higher than the internal resistance of the voltage sources that determine the bus potential in the dominant state. A change from the recessive bus state to the dominant bus state, hereinafter referred to as the switch-on process, therefore has a smaller switch-on time constant than a change from the dominant bus state to the recessive bus state, in the following switch-off process, with the same capacitance on the first data bus line (CH) and the second data bus line (CL) called. The time constant for the switch-off process is referred to below as the switch-off time constant.

• Durch die Asymmetrie zwischen der Einschaltzeitkonstante und der Ausschaltzeitkonstante kommt es zu Oberwellen.

Since it is a differential data bus system, the EMC radiation is lower than the EMC radiation of a single-wire data bus system. In reality, however, there are still problems in detail:

• The asymmetry between the switch-on time constant and the switch-off time constant results in harmonics.

As a result of the asymmetry in the switching behavior between the first switch (TH) and the second switch (TL), a common-mode component is modulated in, so that the data bus changes with respect to this common-mode component Data bus modulation behaves like a single-wire data bus and generates and emits considerable radiation components. If, for example, a P-MOS transistor is used as the first switch (TH) and an N-MOS transistor is used as the second switch (TL), there are deviations, for example, due to the different mobility. This relationship was recognized as a problem to be solved within the scope of the elaboration of the invention in order to reduce the actual problem of EMC radiation.

task

The proposal is therefore based on the object of creating a solution which does not have the above disadvantage of common mode generation due to driver asymmetries, or only has it to a reduced extent, and possibly has further advantages.

This object is achieved by a method according to claim 1.

Solution of the task

The basic idea of the invention is to detect the current potential of the first data line (CH) by means of a measuring device (MB) and to obtain a first measured potential value (PMH) and to detect the potential of the second data line (CL) by means of the measuring device (MB) and to receive a second measured potential value (PML) and then to change the properties of the bus driver by counter-regulation so that the problem no longer occurs or only occurs to a lesser extent.

A common-mode measured value (MS) is preferably determined from the first measured potential value (PMH) and the second measured potential value (PML), which then naturally depends on the first measured potential value (PMH) and the second measured potential value (PML).

The invention is illustrated by way of example 3 further explained.

A first solution that is in 3 is shown as an example, the first switch (TH) with a first delayed transmission signal (TXDH), which is delayed by a first time delay value (ΔtH) compared to the transmission signal (TX), and the second switch (TL) with a second delayed transmission signal (TXDL), which is delayed by a second time delay value (ΔtL) compared to the transmission signal (TX), to control. A controller (CTR) regulates the first time delay (ΔtH) by means of a first time delay control line (DCLH) and the second time delay (ΔtL) by means of a second time delay control line (DCLL) in such a way that the common-mode signal on the data bus (CH, CL ) is minimized. The first time delay (ΔtH) and the second time delay (ΔtL) are regulated by the controller (CRT) as a function of the first measured potential value (PMH) and the second measured potential value (PML) and / or the common mode measured value (MS).

If the edge on the first data bus line (CH) is delayed compared to the edge on the second data bus line (CL), either the delay of the first delayed transmission signal (TXDH) is reduced compared to the transmission signal (TX) or the delay of the second delayed transmission signal ( TXDL) compared to the transmit signal (TX). A mixed form of regulation is of course conceivable. Preferably, the control always tries to utilize the control range in such a way that there is still enough leeway for both control forms up to the limits of the control.

If, on the other hand, the edge on the second data bus line (CL) is delayed compared to the edge on the first data bus line (CH), either the delay of the second delayed transmission signal (TXDL) compared to the transmission signal (TX) or the delay of the first delayed transmission signal is reduced (TXDH) increased compared to the transmit signal (TX). A mixed form of regulation is of course conceivable. The control system preferably always tries to utilize the control range in such a way that there is still enough leeway for both control forms up to the limits of the control.

In addition to regulating the time delay values (ΔtH, ΔtL), there is also a second possible solution, which is preferably used in combination with the first solution, since the regulation range is then increased. According to the invention, it was also recognized that instead of a delayed control, the driver strength of the first switch (TH) and / or the driver strength of the second switch (TL) as a function of the first measured potential value (PMH) and / or the second measured potential value (PML) or the common mode measured value (MS) can be varied. This is done using the 4th and 6th shown. The driver strength control can be achieved, for example, by splitting the first switch (TH) into several first sub-switches (TH ₁ , TH ₂ , TH ₃ ), each of which has an on-resistance, and / or that the second switch (TL) is split into several second sub-switches (TL ₁ , TL ₂ , TL ₃ ), each of which has an on-resistance (see 6th ).

For this purpose, a first strength control device (STRH) directs the transmission signal (TX) only to a fraction of the several first sub-switches (TH ₁ , TH ₂ , TH ₃ ), whereby not the entire available driver strength of the first switch (TH), which is formed by the several first sub-switches (TH ₁ , TH ₂ , TH ₃ ), is available. For this purpose, the first strength control device (STRH) splits the transmission signal (TX) into several first modified switching signals which together form the first modified switching signal (TDXTH) in the form of a switching bus of several lines. Each of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) is assigned a line of the first modified switching signal (TDXTH) for controlling its control electrode. The first strength control device (STRH) controls, depending on the value of a first driver strength control line (SCLH), which is fed by the controller (CTR), only part of the lines of the first modified switching signal (TDXTH) with the transmit signal (TX), while the first strength control device (STRH) sets the remaining lines of the first modified switching signal (TDXTH) to such a potential that the remaining first sub-switches (TH ₁ , TH ₂ , TH ₃ ) assigned to the remaining lines of the first modified switching signal (TDXTH) are locked.

A second strength control device (STRL) now forwards the transmission signal (TX) only to a fraction of the several second sub-switches (TH ₁ , TH ₂ , TH ₃ ), whereby not the entire available driver strength of the second switch (TL), which is triggered by the several second Sub-switch (TL ₁ , TL ₂ , TL ₃ ) is formed is available. For this purpose, the second strength control device (STRL) splits the transmission signal (TX) into several second modified switching signals, which together form the second modified switching signal (TDXTL) in the form of a switching bus of several lines. Each of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) is assigned a line of the second modified switching signal (TDXTL) for controlling its control electrode. The second strength control device (STRL) controls depending on the value of a second driver strength control line (SCLL), which is fed by the control (CTR), only part of the lines of the second modified switching signal (TDXTL) with the transmission signal (TX), while the second strength control device (STRL) sets the remaining lines of the second modified switching signal (TDXTL) to such a potential that the remaining second sub-switches (TL ₁ , TL ₂ , TL ₃ ) assigned to the remaining lines of the second modified switching signal (TDXTL) are locked.

If the full driver strength is not available, the shape of the ramp is changed during the transition from the recessive to the dominant bus state, which results in a delay. This non-availability of the full driver strength and thus the control of the driver strength also takes place as a function of the first measured potential value (PMH) and / or the second measured potential value (PML) and / or the common-mode measured value (MS).

The controller (CTR) regulates the driver strength of the first switch (TH) by means of one of the said driver strength control lines (SCLH) in such a way that the common-mode signal is preferably minimized in the form of the common-mode measured value (MS) on the data bus (CH, CL). The first strength control device (STRH) selects which of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) can or cannot be switched on by means of an active transmission signal (TX). This selection of the first strength control device (STRH) depends on the state or the current value of said first driver strength control line (SCLH) of the controller (CTR). The first driver strength control line (SCLH) is preferably a digital data bus. In the simplest case, however, it can only be a single line.

The controller (CTR) regulates the driver strength of the second switch (TL) in an analogous manner by means of a second driver strength control line (SCLL) in such a way that the common-mode signal is preferably minimized in the form of the common-mode measured value (MS) on the data bus (CH, CL). A second strength control device (STRL) selects which of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) can or cannot be switched on by means of an active transmission signal (TX). This selection of the second strength control device (STRL) depends on the state of said second driver strength control line (SCLL) of the controller (CTR). The second driver strength control line (SCLL) is preferably a digital data bus. In the simplest case, however, it can only be a single line.

The controller (CTR) preferably regulates the driver strength of the first switch (TH) by means of the first driver strength control line (SCLH) and of the second switch (TL) by means of the second driver strength control line (SCLL) in the manner dependent on the first potential measurement value (PMH) of the potential ( V _CH ) on the first data line and / or from the second measured potential value (PML) of the potential ( V _CL ) on the second data line (CL) together, so that the common-mode signal is preferably minimized in the form of the common-mode measured value (MS) on the data bus (CH, CL).

The common-mode voltage in the form of the common-mode measured value (MS) is preferably divided by the supply voltage and a first measured value is thus determined. This measured value is referred to below as the symmetry parameter (V _sym ).

The symmetry parameter is determined as follows: $${\text{V}}_{\text{sym}}=\left(\text{PMH}+\text{PML}\right)/{\text{V}}_{\text{cc}}$$

In the example of the 1 is the course of the voltage potential ( V _CH ) on the first data line (CH) by approx. 10 ns compared to the voltage potential curve ( V _CL ) delayed on the second data line (CL).

The differential voltage on the differential data bus is calculated as: $${\text{V}}_{\text{Diff}}={\text{V}}_{\text{CH}}-{\text{V}}_{\text{CL}}$$

By low-pass filtering the symmetry parameter (V _sym ), a filtered differential symmetry parameter (V _{Diff, min} ) is obtained. The first threshold value is calculated from the filtered differential symmetry parameter (V _{Diff, min} ) as follows: $${\text{U}}_{\text{TH}\_\text{H}}=\left({\text{V}}_{\text{Diff},\text{min}}/{\text{R.}}_{\text{L.}}\right){\text{t}}_{\text{res}}/{\text{C.}}_{\text{out}\_\text{H}}$$

Here, R _L stands for the operating resistance value between the first data line (CH) and the second data line (CL).

The temporal size (tres) is specified as a freely selectable size as a design goal. This time variable design (tres) is a target variable for the shortest time delay between a voltage ramp on the first data line (CH) and a voltage ramp on the other side of the second data line (CL).

The capacitance C _{out_H} represents the capacitance of the first data line (CH) related to the signal base, ie to the reference potential.

The capacitance C _{out_L} represents the capacitance of the second data line (CL) based on the signal base, ie on the reference potential.

An analog threshold voltage can be calculated for the second threshold value: $${\text{U}}_{\text{TH}\_\text{L.}}=-\left({\text{V}}_{\text{Diff},\text{min}}/{\text{R.}}_{\text{L.}}\right){\text{t}}_{\text{res}}/{\text{C.}}_{\text{out}\_\text{L.}}$$

The common mode voltage is not suitable as a reference voltage because it is typically not stable enough.

benutzt werden. Bei richtiger Ansteuerung ist der Symmetrieparameter (V_sym) konstant 1. Dieser Wert 1 ist der Regelungszielwert.Instead of the common mode voltage, the symmetry parameter $${\text{V}}_{\text{sym}}=\left(\text{PMH}+\text{PML}\right)/{\text{V}}_{\text{CC}}$$

to be used. If the control is correct, the symmetry parameter (V _sym ) is constant 1. This value 1 is the control target value.

The symmetry _parameter V _sym shows voltage _peaks as a function of the edge direction and the type of data bit edge on the data bus. A data bit edge here means the transition from a recessive state of the data bus to a dominant state of the data bus and / or the transition from a dominant state of the data bus to a recessive state of the data bus.

Typically, a first comparator (CMPH) compares the symmetry parameter (V _sym ) with the first threshold value (U _{TH_H} ) to generate a first comparator output signal (CMPOH) and a second comparator compares the symmetry parameter (V _sym ) with the second threshold value (U _{TH_L} ) for generation a second comparator output signal (CMPOL).

A first low-pass filter (F1) generates a low-pass filtered symmetry _parameter (V _symL ) from the symmetry _parameter (V _sym ) by low-pass filtering.

It is recommended to choose the filter parameters of the first low pass (F1) and its construction in such a way that the cutoff frequency f _{cut of of} the low pass is preferably by a factor 2 higher than the highest possible data frequency fdata. A preferred implementation can, for example, be a second-order low-pass filter with a cutoff frequency f _{cutt of} of 0.5 MHz for 2.5 MHz f _data data rate (= factor 2). A sample & hold device has the same technical effect as a low-pass filter if it is activated at the correct times.

The first method according to the invention, which was presented above, can be summarized in the form of a simple question: Is there a voltage pulse on the signal of the symmetry parameter (V _sym ) or not? If any type of spike detection device (SPD) detects such a voltage pulse, depending on the polarity of the voltage pulse and the type of data edge (recessive to dominant or dominant to recessive) the delay of one of the delayed control signals (TDXH, TDXL) reduced and / or the delay of the other delayed control signal of the delayed control signals (TDXH, TDXL) increased so that the voltage peak on the symmetry signal (V _sym ) subsequently disappears or is at least minimized. This reduction / increase in the delay preferably takes place in such a way that the delay occurs at Occurrence of a voltage pulse is always changed by the same value.

The second method, which is described above, can be summarized in the form of a simple question: Is there a voltage pulse on the signal of the symmetry parameter (V _sym ) or not? If a spike detection device (SPD) of whatever type detects such a voltage pulse, the driver strength of one of the switches (TH, TL) is reduced depending on the polarity of the voltage pulse and the type of data edge (recessive to dominant or dominant to recessive) and / or the driver strength of the other switch of the switches (TH, TL) is increased so that the voltage peak on the symmetry signal (V _sym ) subsequently disappears. This reduction / increase in the driver strength of the switches (TH, TL) preferably takes place in such a way that the reduction / increase in the driver strength of the switches (TH, TL) is always by the amount when a voltage pulse occurs on the signal of the symmetry parameter (V _sym ) same value is changed.

VERSION 1

A first variant corresponds to the upper part of the 3 .

• • Erfassen des Potenzials (V_CH ) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL ) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Verzögern des Sendesignals (TX) zu einem ersten verzögerten Sendesignal (TDXH) um einen ersten zeitlichen Verzögerungswert (ΔtH), wobei der erste zeitliche Verzögerungswert (ΔtH) von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML) abhängt;
• • Verwenden des ersten verzögerten Sendesignals (TDXH) als erstes modifiziertes Schaltsignal (TDXTH);
• • Steuern des ersten Schalters (TH) mit dem ersten modifizierten Schaltsignal (TDXTH).

A first variant of the invention is thus a method for reducing the common mode generation in a differential data bus (CL; CH) with a first data line (CH) and with a second data line (CL) and with a first switch (TH) which is used to connect the first data line (CH) with a first supply voltage (VCC) is used or provided as a function of a first modified switching signal (TDXTH), and with a second switch (TL) which is used to connect the second data line (CL) to a second supply voltage ( GND) is used or provided as a function of a second modified switching signal (TDXTL). The first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX). The data bus (CL, CH) can assume a recessive state and a dominant state. The procedure of the variant 1 comprises the steps:

• • Capturing the potential ( V _CH ) the first data bus line (CH) for determining a first measured potential value (PMH);
• • Capturing the potential ( V _CL ) the second data bus line (CL) for determining a second measured potential value (PML);
• • Delaying the transmission signal (TX) to a first delayed transmission signal (TDXH) by a first time delay value (ΔtH), the first time delay value (ΔtH) depending on the first measured potential value (PMH) and the second measured potential value (PML);
• • Using the first delayed transmission signal (TDXH) as the first modified switching signal (TDXTH);
• • Controlling the first switch (TH) with the first modified switching signal (TDXTH).

• • Erfassen des Potenzials der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Bestimmung eines Symmetrieparameters (V_sym) in Abhängigkeit von dem ersten Potentialmesswert (PMH) und dem zweiten Potenzialmesswert (PML);
• • Verzögern des Sendesignals (TX) zu einem ersten verzögerten Sendesignal (TDXLH) um einen ersten zeitlichen Verzögerungswert (ΔtH), wobei der erste zeitliche Verzögerungswert (ΔtH) von dem Symmetrieparameter (V_sym) abhängt;
• • Verwenden des ersten verzögerten Sendesignals (TDXH) als erstes modifiziertes Schaltsignal (TDXTH);
• • Steuern des ersten Schalters (TH) mit dem ersten modifizierten Schaltsignal (TDXTH).

A first refinement of the process variant 1 additionally includes the determination of a symmetry parameter (V _sym ) as a function of the first measured potential value (PMH) and the second measured potential value (PML) instead of the step of delaying the transmission signal (TX) to a first delayed transmission signal (TDXH) by a first time delay value ( ΔtH), wherein the first time delay value (ΔtH) depends on the first potential measurement value (PMH) and the second potential measurement value (PML), the step of delaying the transmission signal (TX) to a first delayed transmission signal (TDXLH) by a first time delay value ( ΔtH), the first time delay value (ΔtH) depending on the symmetry parameter (V _sym ). This process variant then comprises the steps:

• • Detecting the potential of the first data bus line (CH) to determine a first measured potential value (PMH);
• • Detecting the potential of the second data bus line (CL) to determine a second measured potential value (PML);
• • Determination of a symmetry parameter (V _sym ) as a function of the first measured potential value (PMH) and the second measured potential value (PML);
• • Delaying the transmission signal (TX) to a first delayed transmission signal (TDXLH) by a first time delay value (ΔtH), the first time delay value (ΔtH) depending on the symmetry parameter (V _sym );
• • Using the first delayed transmission signal (TDXH) as the first modified switching signal (TDXTH);
• • Controlling the first switch (TH) with the first modified switching signal (TDXTH).

In a second refinement of the process variant 1 in the form of a refinement of the first refinement of the process variant 1 the symmetry parameter (V _sym ) is formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym = (PMH + PML) / V _CC . Vcc is the potential value of the Supply voltage compared to the reference potential (e.g. GND).

In a third refinement of the process variant 1 in the form of a refinement of the first refinement of the process variant 1 and / or in the form of a refinement of the second refinement of the method variant 1 the proposed method includes the step of generating a filtered differential symmetry parameter (V _{Diff, min} ) from the symmetry signal (V _sym ) by low-pass filtering and using the differential symmetry _parameter (V _{Diff, min} ) to determine a first threshold value (U _{TH_H} ) .

In a fourth refinement of the process variant 1 in the form of a refinement of the third refinement of the process variant 1 the first threshold value (U _{TH_H} ) is determined according to the formula U _{TH_H} = (V _{Diff, min} / R _L ) tres / C _{out_H} .

In a fifth refinement of the process variant 1 In the form of a refinement of the third refinement and / or the fourth refinement, a comparison of the symmetry _signal (V _sym ) with the first threshold value (U _{TH_H} ) is carried out, in particular by means of a first comparator (CMPH), to determine a first comparison value in the form of a first comparator output signal (CMPOH) of the first comparator (CMPH). Instead of the step of delaying the transmission signal (TX) to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) depending on the first measured potential value (PMH) and the second measured potential value (PML), a step of delaying the transmission signal (TX) to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL) is now carried out, the second time delay value (ΔtL) being derived from the first comparison value in the form of the first comparator output signal of the first comparator ( CMPH).

VARIANT 2

This variant corresponds to the lower part of the 3 .

• • Erfassen des Potenzials (V_CH ) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL ) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Verzögern des Sendesignals (TX) zu einem zweiten verzögerten Sendesignal (TDXL) um einen zweiten zeitlichen Verzögerungswert (ΔtL), wobei der zweite zeitliche Verzögerungswert (ΔtL) von dem ersten Potenzialmesswert (V_CH ) und dem zweiten Potenzialmesswert (V_CL ) abhängt;
• • Verwenden des zweiten verzögerten Sendesignals (TDXL) als zweites modifiziertes Schaltsignal (TDXTL);
• • Steuern des zweiten Schalters (TL) mit dem zweiten modifizierten Schaltsignal (TDXTL);

The second variant is a method for reducing the common mode generation in a differential data bus (CL, CH) with a first data line (CH) and with a second data line (CL). At least one driver, which is connected to the data bus, has the first switch (TH), which is used or is provided to connect the first data line (CH) to a first supply voltage (VCC) as a function of a first modified switching signal (TDXTH), and the second switch (TL), which serves or is provided for connecting the second data line (CL) to a second supply voltage (GND) as a function of a second modified switching signal (TDXTL). The first modified switching signal (TDXH) and the second modified switching signal (TDXL) again depend on a transmission signal (TX). The data bus (CL, CH) can assume a recessive state and a dominant state. The procedure of the variant 2 has the following steps:

• • Capturing the potential ( V _CH ) the first data bus line (CH) for determining a first measured potential value (PMH);
• • Capturing the potential ( V _CL ) the second data bus line (CL) for determining a second measured potential value (PML);
• • Delaying the transmission signal (TX) to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), where the second time delay value (ΔtL) depends on the first potential measurement value ( V _CH ) and the second measured potential value ( V _CL ) depends;
• • Using the second delayed transmission signal (TDXL) as the second modified switching signal (TDXTL);
• • Controlling the second switch (TL) with the second modified switching signal (TDXTL);

In a first refinement of the second variant, a symmetry parameter (V _sym ) is additionally determined as a function of the first measured potential value (PMH) and the second measured potential value (PML). The step of delaying the transmission signal (TX) to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) being dependent on the first measured potential value (PMH) and the second measured potential value (PML) now executed differently. Instead, in a modification of the basic method of the second method variant, the transmission signal (TX) is now delayed to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL), however, now being dependent on the additionally determined symmetry parameter (V _sym ) depends;

In a second refinement, the symmetry parameter (V _sym ) is preferably formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym = (PMH + PML) / V _CC (with Vcc as the potential value of the supply voltage) .

A third refinement includes generating a filtered differential symmetry parameter (V _{Diff, min} ) from the signal des Symmetry parameter (V _sym ) through low-pass filtering and the use of the filtered differential symmetry _parameter (V _{Diff, min} ) to determine a second threshold value (U _{TH_L} ).

In a fourth refinement, the second threshold value (U _{TH_L} ) is determined according to the formula U _{TH_L} = (V _{Diff, min} / R _L ) t _res / C _{out_L} .

In a fifth refinement, the symmetry _signal (V _sym ) is compared with the second threshold value (U _{TH_L} ), in particular by means of a second comparator (CMPL), to determine a second comparison value in the form of a second comparator output signal of the second comparator (CMPH). The step of delaying the transmission signal (TX) to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), wherein the second time delay value (ΔtL) depends on the first potential measurement value ( V _CH ) and the second measured potential value ( V _CL ) is not carried out in this form. Rather, instead of this step, the transmission signal (TX) is delayed to a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) now however depending on the second comparison value.

VARIANT 3

This variant corresponds to the 3 .

A third variant combines the method of the first variant with a method of the second variant. A corresponding device is in 3 shown.

VARIANT 4

This variant corresponds to the upper part of the 4th .

• • Erfassen des Potenzials (V_CH ) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL ) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Ändern der ersten Treiberstärke in Abhängigkeit von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML).

A fourth variant of the method is a method for reducing the common mode generation in a differential data bus (CL, CH) with a first data line (CH) and with a second data line (CL). A driver connected to the data bus comprises a first switch (TH) for connecting the first data line (CH) to a first supply voltage (VCC) as a function of a first modified switching signal (TDXTH), which has a first driver strength, and a second switch ( TL) for connecting the second data line (CL) to a second supply voltage (GND) as a function of a second modified switching signal (TDXTL), which has a second driver strength. The first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX). The data bus (CL, CH) can assume a recessive state and a dominant state. This fourth variant of the method comprises the steps:

• • Capturing the potential ( V _CH ) the first data bus line (CH) for determining a first measured potential value (PMH);
• • Capturing the potential ( V _CL ) the second data bus line (CL) for determining a second measured potential value (PML);
• • Changing the first driver strength depending on the first measured potential value (PMH) and the second measured potential value (PML).

In a first refinement of the fourth method, a symmetry parameter (V _sym ) is determined as a function of the first measured potential value (PMH) and the second measured potential value (PML). The method step of changing the first driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) is not carried out in this first refinement of the fourth variant. Instead, the first driver strength is changed as a function of the symmetry parameter (V _sym ).

According to a second refinement of the fourth variant, the symmetry parameter (V _sym ) is formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym = (PML + PMH) / V _CC (with Vcc as the potential value of the supply voltage ).

In a third refinement of the fourth variant, the method comprises the generation of a filtered differential symmetry parameter (V _{Diff, min} ) from the symmetry signal (V _sym ) by low-pass filtering and the use of the differential symmetry parameter (V _{Diff, min} ) for the determination of a first threshold value ( U _{TH_H} ).

In a fourth refinement of the fourth variant, the first threshold value (U _{TH_H} ) is determined according to the formula U _{TH_H} = (V _{Diff, min} / R _L ) tres / C _{out_H} .

In a fifth refinement of the fourth variant of the method, the symmetry _signal (V _sym ) is compared with the first threshold value (U _{TH_H} ), in particular by means of a first comparator (CMPH), in order to determine a first comparison value, in particular in the form of generating a first comparator output signal (CMPOH) of the first comparator (CMPH). The step of changing the first driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) is not carried out in this refinement of the fourth variant. Instead, the first driver strength is changed as a function of the first comparison value, that is to say in particular as a function of the first comparator output signal (CMPOH) of the first comparator (CMPH).

VARIANT 5

This variant corresponds to the lower part of the 4th .

• • Erfassen des Potenzials (V_CH ) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL ) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Verzögern des Sendesignals (TX) zu einem zweiten verzögerten Sendesignal (TDXL) um einen zweiten zeitlichen Verzögerungswert zu erhalten, wobei der zweite zeitliche Verzögerungswert von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML) abhängt;
• • Ändern der zweiten Treiberstärke in Abhängigkeit von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML).

A fifth variant of the method is a method for reducing the common mode generation in a differential data bus with a first data line (CH) and with a second data line (CL). A driver connected to the data bus comprises a first switch (TH) for connecting the first data line (CH) to a first supply voltage (VCC) as a function of a first modified switching signal (TDXTH), which has a first driver strength, and a second switch (TL) for connecting the second data line (CL) to a second supply voltage (GND) as a function of a second modified switching signal (TDXTL)) which has a second driver strength. The first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX). The data bus can adopt a recessive state and a dominant state. The fifth variant of the procedure comprises the steps:

• • Capturing the potential ( V _CH ) the first data bus line (CH) for determining a first measured potential value (PMH);
• • Capturing the potential ( V _CL ) the second data bus line (CL) for determining a second measured potential value (PML);
• • Delaying the transmission signal (TX) to a second delayed transmission signal (TDXL) in order to obtain a second time delay value, the second time delay value depending on the first measured potential value (PMH) and the second measured potential value (PML);
• • Changing the second driver strength depending on the first measured potential value (PMH) and the second measured potential value (PML).

In a first refinement of the fifth variant of the method, a symmetry parameter (V _sym ) is determined as a function of the first measured potential value (PMH) and the second measured potential value (PML). The step of changing the second driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) does not take place in this refinement of the fifth variant. Rather, the second driver strength is now changed as a function of the symmetry parameter (V _sym ).

In a second refinement of the fifth variant of the method, the symmetry parameter (V _sym ) is formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym = (PMH + PML) / V _CC (with Vcc as the potential value the supply voltage).

In a third refinement of the fifth variant of the method, a filtered differential symmetry parameter (V _{Diff, min} ) is generated from the symmetry signal (V _sym ) by low-pass filtering and the differential symmetry parameter (V _{Diff, min} ) is used to determine a second threshold value ( U _{TH_L} );

In a fourth refinement of the fifth variant of the method, the second threshold value (U _{TH_L} ) is determined according to the formula U _{TH_L} = (V _{Diff, min} / R _L ) t _res / C _{out_L} .

In a fifth refinement of the fifth variant of the method, the symmetry _signal (V _sym ) is compared with the second threshold value (U _{TH_L} ), in particular by means of a second comparator, to determine a first comparison value, in particular in the form of a second comparator output signal (CMPOL) of the second Comparator (CMPL). The step of changing the second driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) is not carried out in this way; instead, the second driver strength is changed as a function of the second comparison value, so in particular this can be carried out as a function of the second comparator output signal (CMPOL) of the second comparator (CMPL) happen.

VARIANT 6

This variant corresponds to the 4th .

A sixth variant combines the method of the fourth variant with a method of the fifth variant.

VARIANT 7

This variant corresponds to the upper part of the 5 .

A seventh variant combines the methods of the first to sixth variants.

Finally, it should also be mentioned that a corresponding device can be provided which carries out the first to seventh method variants.

Such a device, a driver for such a data bus (CL, CH), has a first switch (TH), which preferably consists of several sub-switches (TH ₁ , TH ₂ , TH ₃ ), and a second switch (TL). on, which preferably consists of several sub-switches (TL ₁ , TL ₂ , TL ₃ ).

It preferably has a first time delay control line (DLYH) which delays the transmission signal (TX) to the first delayed transmission signal (TDXH) by a first time delay value (ΔtH). The first time delay value (ΔtH) depends on the value on a first time delay control line (DCLH) of the device.

It preferably has a second time delay control line (DLYL) which delays the transmission signal (TX) to the second delayed transmission signal (TDXL) by a second time delay value (ΔtL). The second time delay value (ΔtL) depends on the value on a second time delay control line (DCLL) of the device.

It has a first strength control device (STRH) which sends the first delayed transmission signal (TDXH) to the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) as a function of the value of the first driver strength control line (SCLH) in the form of a first modified switching signal ( TDXTH) distributed. The first modified switching signal (TDXTH) is preferably a bus of lines, each control connection of each first sub-switch (TH ₁ , TH ₂ , TH ₃ ) being assigned one of the lines of the first modified switching signal (TDXTH). Depending on the value of the first driver strength control line (SCLH), some of the lines of the first modified switching signal (TDXTH) are connected to the delayed transmission signal (TDXH), whereby the associated first sub-switches of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) are connected when the Transmission signal (TX) become active. The other lines of the first modified switching signal (TDXTH) are switched in such a way that the associated first sub-switches of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) are not active even when the transmission signal (TX) is active. This models the driver strength. Other forms of driver strength modification, for example using current sources, the current strength of which is regulated by the first driver strength control line (SCLH), are conceivable.

The device has a second strength control device (STRL) which sends the second delayed transmission signal (TDXL) to the second sub-switch (TL ₁ , TL ₂ , TL ₃ ) as a function of the value of the second driver strength control line (SCLL) in the form of a second modified switching signal (TDXTL) distributed. The second modified switching signal (TDXTL) is preferably a bus of lines, with each control connection of every second sub-switch (TL ₁ , TL ₂ , TL ₃ ) being assigned one of the lines of the second modified switching signal (TDXTL). Depending on the value of the second driver strength control line (SCLL), some of the lines of the second modified switching signal (TDXTL) are connected to the delayed transmission signal (TDXL), whereby the associated second sub-switches of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) are connected when the Transmission signal (TX) become active. The other lines of the second modified switching signal (TDXTL) are switched in such a way that the associated second sub-switches of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) do not become active even when the transmission signal (TX) is active. This models the driver strength of the second switch (TL). Other forms of driver strength modification, for example using current sources, the current strength of which is regulated by the second driver strength control line (SCLL), are conceivable.

A controller (CTR), which is part of the device, sets the first time delay value (ΔtH) of the first time delay control line (DLYH) and the second time delay value (ΔtL) of the second time delay control line (DLYL).

Furthermore, the controller (CTR) sets the first driver strength of the first switch (TH) and the second driver strength of the second switch (TH). To do this, it sets the value of the first driver strength control line (SCLH) and the value of the second driver strength control line (SCLL).

The controller sets the value of the first driver strength control line (SCLH) and the value of the second driver strength control line (SCLL) and the first time delay value (ΔtH) of the first time delay control line (DLYH) and the second time delay value (ΔtL) of the second time delay control line (DLYL) as a function from a common mode measurement (MS).

The device has a measuring device (MB) for recording the potential ( V _CH ) of the first data line (CH) in the form of a first measured potential value (PMH) and for detecting the potential ( V _CL ) the second data line (CL) in the form of a second measured potential value (PML). The measuring device (MB) preferably determines a common-mode measured value (MS) therefrom. This common mode measured value (MS) typically corresponds to the symmetry parameter (V _sym ). The control preferably comprises a first filter (F1) which filters the smooth cycle measurement value (MS) or the symmetry parameter (V _sym ) to a filtered differential symmetry parameter (V _{Diff, min} ). The control has a switching threshold generation, which is derived from the filtered differential symmetry parameter (V _{Diff, min} ) preferably a first threshold value (U _{TH_H} ) and a second threshold value (U _{TH_L} ) are generated.

A first comparator (CMPH) compares the common cycle measurement value (MS) or the symmetry parameter (V _sym ) with the first threshold value (U _{TH_H} ) and generates a first comparison result in the form of a first comparator output signal (CMPOH) of the first comparator (CMPH).

A second comparator (CMPL) compares the common cycle measurement value (MS) or the symmetry parameter (V _sym ) with the second threshold value (U _{TH_L} ) and generates a second comparison result in the form of a second comparator output signal (CMPOL) of the first comparator (CMPH).

The controller then preferably sets the value of the first driver strength control line (SCLH) and the first time delay value (ΔtH) of the first time delay control line (DLYH) as a function of the first comparison result in the form of the value of the first comparator output signal (CMPOH) of the first comparator (CMPH) . For example, with each pulse on the first comparator output signal (CMPOH) for each data edge, the first delay time (ΔtH) can be reduced and / or the driver strength of the first switch (TH) can be increased and with each pulse on the second comparator output signal (CMPOL) for each Data edge, the first delay time (ΔtH) can be increased and / or the driver strength of the first switch (TH) can be decreased.

The controller then preferably sets the value of the second driver strength control line (SCLL) and the second time delay value (ΔtL) of the second time delay control line (DLYL) as a function of the second comparison result in the form of the value of the second comparator output signal (CMPOL) of the second comparator (CMPL) . For example, with each pulse on the second comparator output signal (CMPOL) for each data edge, the second delay time (ΔtL) can be reduced and / or the driver strength of the second switch (TL) can be increased and with each pulse on the first comparator output signal (CMPOH) for each Data edge the second delay time (ΔtL) can be increased and / or the driver strength of the second switch (TL) can be decreased.

advantage

Such a driver for such a data bus generates fewer common-mode components, since the control is synchronized by the regulation. The advantages are not limited to this.

Figure list

• 1 shows the temporal course of the first data line potential ( V _CH ) of the first data line (CH) and the time profile of the second data line potential ( V _CL ) the second data line (CL) during the transition from the recessive to the dominant data bus state.
• 2 shows a data bus driver according to the prior art (SdT) described in the introduction.
• 3 shows a data bus driver according to the invention with regulation of the delay.
• 4th shows a data bus driver according to the invention with control of the driver strength.
• 5 shows a data bus driver according to the invention with regulation of the delay and the driver strength.
• 6th shows a first switch (TH) and a second switch (TL) which are set up and provided for charging the first data line (CH) and the second data line (CL) with different driver strengths. The first modified transmission signal (TDXTH) and the second modified transmission signal (TDXTL) are shown with their lines resolved as buses into individual lines.

List of reference symbols

CH

first data bus line of the differential data bus;

CL

second data bus line of the differential data bus;

CH _dom

higher potential of the first data line (CH), which the first data line (CH) assumes in the dominant state of the data bus;

CL _dom

low potential of the second data line (CL), which the second data line (CL) assumes in the dominant state of the data bus;

CLH _rec

recessive potential. The recessive potential is assumed by the first data bus line (CH) and the second data bus line (CL) in the recessive state of the differential data bus;

CMPH

first comparator. The first comparator generates the first comparator output signal (CMPOH) by comparing the symmetry parameter (V _sym ) with the first threshold value (U _{TH_H} );

CMPL

second comparator. The second comparator generates the second comparator output signal (CMPOL) by comparing the symmetry parameter (V _sym ) with the second threshold value (U _{TH_L} );

CMPOH

first comparator output signal of the first comparator (CMPH);

CMPOL

second comparator output signal of the second comparator (CMPL);

C _{out_H}

Capacity of the first data line (CH) based on the signal base, i.e. on the reference potential;

C _{out_L}

Capacity of the second data line (CL) based on the signal base, i.e. on the reference potential;

CTR

Control;

ΔtH

first time delay value by which the transmission signal (TX) is delayed for the first delayed transmission signal (TDXH) in a first time delay control line (DLYH);

ΔtL

second time delay value by which the transmission signal (TX) is delayed for the second delayed transmission signal (TDXL) in a first time delay control line (DLYH);

DCLH

first time delay control line with which the controller (CTR) sets the first time delay value (ΔtH) of the first time delay control line (DLYH);

DCLL

second time delay control line with which the controller (CTR) sets the second time delay value (ΔtL) of the second time delay control line (DLYL);

DLYH

first time delay control line (DLYH) which delays the transmission signal (TX) to the first delayed transmission signal (TDXH) by a first time delay value (ΔtH). The first time delay value (ΔtH) depends on the value on a first time delay control line (DCLH).

F1

first low pass filter;

f _{cut of}

Cutoff frequency of the first low-pass (F1);

f _data

highest possible data frequency;

GND

Supply mass;

MB

Measuring device;

MS

Common mode reading;

PMH

first potential measured value;

PML

second potential measured value;

R _L

Working resistance value between the first data line (CH) and the second data line (CL);

SCLH

first driver strength control line;

SCLL

second driver strength control line;

SPD

Spike detection device;

STRH

first thickness control device;

STRL

second thickness control device;

TDXH

first delayed transmission signal;

TDXL

second delayed transmit signal;

TDXTH

first modified switching signal;

TDXTL

second modified switching signal;

TH

first switch;

TH ₁

first sub-switch of the first sub-switch of the first switch (TH);

TH ₂

second sub-switch of the first sub-switch of the first switch (TH);

TH ₃

third sub-switch of the first sub-switch of the first switch (TH);

TH _n

n-th sub-switch of the first sub-switch of the first switch (TH);

TL

second switch;

TL ₁

first sub-switch of the second sub-switch of the second switch (TL);

TL ₂

second sub-switch of the second sub-switch of the second switch (TL);

TL ₃

third sub-switch of the second sub-switch of the second switch (TL);

TL _n

n-th sub-switch of the second sub-switch of the second switch (TL);

t _res

temporal size design. The temporal size design (t _res ) is specified as a freely selectable size as the design goal. It is a target variable for the shortest time delay between a voltage ramp on the first data line (CH) and a voltage ramp on the other side of the second data line (CL);

TX

Transmit signal;

U _{TH_H}

first threshold;

U _{TH_L}

second threshold;

Vcc

Supply voltage or supply voltage line;

V _CL

Potential of the second data line (CL) with respect to a reference ground (typ. GND);

V _CH

Potential of the first data line (CH) with respect to a reference ground (typ. GND);

V _diff

differential voltage on the data bus. It is defined as V _Diff = V _CH -V _CL ,

V _{diff, min}

filtered symmetry parameter;

V _symL

low-pass filtered symmetry parameter;

V _sym

Symmetry parameters;

Claims (6)

Method for reducing the common mode generation in a differential data bus - with a first data line (CH) and - with a second data line (CL) and - with a first switch (TH) for connecting the first data line (CH) to a first supply voltage (VCC) as a function of a first modified switching signal (TDXTH) which has a first driver strength, and - with a second switch (TL) for connecting the second data line (CL) to a second supply voltage (GND) as a function of a second modified switching signal (TDXTL) ), which has a second driver strength, and - wherein the first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX) and - wherein the data bus can assume a recessive state and a dominant state with the steps - Detecting the potential (V _CH ) of the first data bus line (CH) to determine a first measured potential value (PMH ); - Detecting the potential (V _CL ) of the second data bus line (CL) to determine a second measured potential value (PML); - Changing the second driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML). Procedure according to Claim 1 with the additional steps - determining a symmetry parameter (V _sym ) as a function of the first measured potential value (PMH) and the second measured potential value (PML); - instead of the step of changing the second driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML), changing the second driver strength as a function of the symmetry parameter (V _sym ); Procedure according to Claim 2 - The symmetry parameter (V _sym ) is formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym = (PMH + PML) / V _CC (with Vcc as the potential value of the supply voltage). Method according to one or more of the Claims 2 to 3 comprising the additional steps: - generating a filtered differential symmetry parameter (V _{Diff, min} ) from the symmetry signal (V _sym ) by low-pass filtering; - Use of the differential symmetry _parameter (V _{Diff, min} ) to determine a second threshold value (U _{TH_L} ); Procedure according to Claim 4 - the second threshold value (U _{TH_L} ) being determined according to the formula U _{TH_L} = (V _{Diff, min} / R _L ) t _res / C _{out_L} . Method according to one or more of the Claims 4 to 5 comprising the additional steps: - comparison of the symmetry _signal (V _sym ) with the second threshold value (U _{TH_L} ), in particular by means of a comparator, to determine a first comparison value; instead of the step of changing the second driver strength as a function of the first measured potential value (V _CH ) and the second measured potential value (V _CL ), changing the second driver strength as a function of the second comparison value.

Images