DE102019104123B4 - Method and device for minimum common-mode control of a differential data bus with high-side and low-side driver strength control - Google Patents

Abstract

The invention relates to a method for reducing the generation of common mode in a differential data bus. The edges are synchronized by controlling the driver strength in the high-side and low-side path.

Description

generic term

The invention relates to a method and an associated device for reducing common-mode generation in a differential data bus.

General introduction

The CAN data bus is a widespread bus system in automotive computer network systems. The CAN data bus is based on two data bus lines (CH, CL), a first data bus line (CH) and a second data bus line (CL). The CAN bus essentially has two states of its data lines (CH, CL). In a first state, the CAN data bus assumes a so-called recessive state. In this case, the voltage potentials of the two data lines (CH, CL) are approximately at the same potential, the recessive potential (CLH _rez ). We refer here to 1 . The drivers of the bus nodes are then switched off and an auxiliary device of the CAN data bus then forces the data bus lines (CH, CL) to the said recessive voltage potential (CLH _rez ) with the aid of relatively high-impedance voltage sources.

However, the method presented here is not limited to this type of data bus.

In 2 an exemplary driver from the prior art is shown. The exemplary prior art driver includes a top switch (TH), which is preferably a P-channel MOS transistor, that pulls the first data line (CH) of the two data lines (CH, CL) of the differential data bus to a high potential (CH _dom ), preferably the supply voltage (VCC), can pull above said recessive voltage potential (CLH _rez ). (See also 1 .) The exemplary driver from the prior art comprises a lower switch (TL), which is preferably an N-channel MOS transistor and which switches the second data line (CL) of the two data lines (CH, CL) of the differential data bus to on low potential (CL _dom ), preferably the supply ground (GND), below said recessive voltage potential (CLH _rez ).

In the prior art, the upper switch (TH) and the lower switch (TL) are controlled by a preferably common transmission signal (TX).

If the transmission signal (TX) is inactive, the upper switch (TH) and the lower switch (TL) are blocked. If this applies to all bus nodes in the bus system, a resistance network, which is preferably present on the bus and is not shown here, pulls the first data line (CH) and the second data line (CL) to the said average recessive potential (CLH _rez ).

If the transmission signal (TX) is active, the upper switch (TH) and the lower switch (TL) are closed, i.e. conductive with low resistance. As a result, the first data line (CH) is raised to the higher potential (CH _dom ), i.e. preferably the supply voltage potential (VCC), while the second data line (CL) is raised to the lower potential (CL _dom ), i.e. preferably the supply ground (GND) , is lowered. The said recessive potential (CLH _rez ) of the resistance network is overwritten in this case, since the internal resistance of the exemplary resistance network is higher. This state of the data bus is referred to below as the dominant state. The course of the potential (V) of the voltage potential (V _CH ) of the first data line (CH) is in 1 denoted by V _CH . It is the potential (V _CH ) of the first data line (CH) compared to a reference ground (typically GND). The curve of the potential (V) of the voltage potential (V _CL ) of the second data line (CL) is in FIG 1 denoted by V _CL . It is the potential (V _CL ) of the second data line (CL) compared to a reference ground (typically GND). This shift from the recessive state to the dominant state is in 1 plotted against time (t).

The internal resistance of the voltage sources that determine the bus potentials in the recessive state is higher than the internal resistance of the voltage sources that determine the bus potentials in the dominant state. A change from the recessive bus state to the dominant bus state, referred to below as the switch-on process, therefore has a smaller switch-on time constant with the same capacitance per unit length of the first data bus line (CH) and the second data bus line (CL) than a change from the dominant bus state to the recessive bus state, referred to below as the switch-off process called. The time constant for the switch-off process is referred to below as the switch-off time constant.

• Durch die Asymmetrie zwischen der Einschaltzeitkonstante und der Ausschaltzeitkonstante kommt es zu Oberwellen.

Since it is a differential data bus system, the EMC emissions are lower than the EMC emissions of a single-wire data bus system. In reality, however, there are still problems in detail:

• The asymmetry between the switch-on time constant and the switch-off time constant results in harmonics.

Due to the asymmetry in the switching behavior between the first switch (TH) and the second Switch (TL) modulation of a common-mode component occurs, so that the data bus behaves like a single-wire data bus with regard to this common-mode component of the data bus modulation and generates and emits significant radiation components. If, for example, a P-MOS transistor is used as the first switch (TH) and an N-MOS transistor is used as the second switch (TL), deviations already occur due to the different mobilities, for example. This connection was recognized as a problem to be solved in the context of the elaboration of the invention in order to reduce the actual problem of EMC radiation.

From the U.S. 6,324,044 B1 Delay adjustments for the control signals of a high-side and a low-side driver transistor are known as a function of the position of the edges. From the DE 10 2013 219 176 A1 a driver circuit for a digital signal transmission bus is known. From the DE 10 2014 209 694 A1 a subscriber station for a bus system and a method for increasing the interference immunity in the area of electromagnetic compatibility for a subscriber station are known. US 2014/0 156 893 A1 discloses a system, a device and a method for monitoring the temporal position of the bus edges on a CAN bus.

In this case, however, the symmetry is not evaluated, which leads to poorer radiation characteristics.

task

The proposal is therefore based on the object of creating a solution which does not have the above disadvantage of common-mode generation by driver asymmetries, or only does so to a reduced extent, and possibly has further advantages.

This object is achieved by a method according to claim 1.

solution of the task

The basic idea of the invention is to record the current potential of the first data line (CH) using a measuring device (MB) and to obtain a first measured potential value (PMH) and to record the potential of the second data line (CL) using the measuring device (MB) and to obtain a second measured potential value (PML) and then to change the properties of the bus driver through counter-regulation in such a way that the problem no longer occurs or only occurs to a lesser extent.

A measured potential value (MS) is preferably determined from the first measured potential value (PMH) and the second measured potential value (PML), which then naturally depends on the first measured potential value (PMH) and the second measured potential value (PML).

The invention is based on the exemplary 3 explained further.

A first solution, which in 3 shown by way of example, is now to control the first switch (TH) with a first delayed transmission signal (TXDH), which is delayed by a first time delay value (ΔtH) compared to the transmission signal (TX), and to control the second switch (TL) with a second delayed transmission signal (TXDL), which is delayed by a second time delay value (ΔtL) compared to the transmission signal (TX), to drive. A controller (CTR) regulates the first time delay (ΔtH) using a first time delay control line (DCLH) and the second time delay (ΔtL) using a second time delay control line (DCLL) in such a way that the common mode signal on the data bus (CH, CL ) is minimized. This regulation of the first time delay (ΔtH) and the second time delay (ΔtL) is carried out by the controller (CRT) as a function of the first measured potential value (PMH) and the second measured potential value (PML) and/or the measured common mode value (MS).

If the edge on the first data bus line (CH) is delayed compared to the edge on the second data bus line (CL), then either the delay of the first delayed transmission signal (TXDH) is reduced compared to the transmission signal (TX) or the delay of the second delayed transmission signal ( TXDL) compared to the transmit signal (TX). A mixed form of regulation is of course conceivable. Preferably, the controller always tries to utilize the control range in such a way that there is still enough leeway for both types of control up to the limits of the control.

If, on the other hand, the edge on the second data bus line (CL) is delayed in relation to the edge on the first data bus line (CH), then either the delay in the second delayed transmission signal (TXDL) is reduced in relation to the transmission signal (TX) or the delay in the first delayed transmission signal is reduced (TXDH) increased compared to the transmit signal (TX). A mixed form of regulation is of course conceivable. Preferably, the controller always tries to utilize the control range in such a way that there is still enough leeway for both types of control up to the limits of the control.

In addition to the regulation of the time delay values (ΔtH, ΔtL), there is a second one Possible solution that is preferably used in combination with the first solution, since the control range is then increased. According to the invention, it was also recognized that instead of a delayed activation, the driver strength of the first switch (TH) and/or the driver strength of the second switch (TL) as a function of the first measured potential value (PMH) and/or the second measured potential value (PML) or the measured common mode value (MS) can be varied. This is based on the 4 and 6 shown. The driver strength control can be achieved, for example, by splitting the first switch (TH) into a plurality of first sub-switches (TH ₁ , TH ₂ , TH ₃ ), each of which has an on-resistance, and/or by the second switch (TL) is split into several second sub-switches (TL ₁ , TL ₂ , TL ₃ ), each of which has an on-resistance (see Fig 6 ).

For this purpose, a first strength control device (STRH) directs the transmission signal (TX) to only a fraction of the several first sub-switches (TH ₁ , TH ₂ , TH ₃ ), which means that the entire available driver strength of the first switch (TH) that is controlled by the several first Subswitch (TH ₁ , TH ₂ , TH ₃ ) is formed, is available. For this purpose, the first strength control device (STRH) splits the transmission signal (TX) into a plurality of first modified switching signals, which together form the first modified switching signal (TDXTH) in the form of a switching bus of a number of lines. Each of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) is assigned a line of the first modified switching signal (TDXTH) for driving its control electrode. The first strength control device (STRH) controls depending on the value of a first driver strength control line (SCLH), which is fed by the controller (CTR) only part of the lines of the first modified switching signal (TDXTH) with the transmission signal (TX), while the first strength control device (STRH) sets the remaining lines of the first modified switching signal (TDXTH) to such a potential that the remaining first sub-switches (TH ₁ , TH ₂ , TH ₃ ) are assigned to the remaining lines of the first modified switching signal (TDXTH). are, are blocked.

A second strength control device (STRL) now routes the transmit signal (TX) to only a fraction of the multiple second sub-switches (TH ₁ , TH ₂ , TH ₃ ), thereby not using the entire available drive strength of the second switch (TL) passed through the multiple second Subswitch (TL ₁ , TL ₂ , TL ₃ ) is formed, is available. For this purpose, the second strength control device (STRL) splits the transmission signal (TX) into a number of second modified switching signals, which together form the second modified switching signal (TDXTL) in the form of a switching bus of a number of lines. Each of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) is assigned a line of the second modified switching signal (TDXTL) for driving its control electrode. The second strength control device (STRL) controls only a part of the lines of the second modified switching signal (TDXTL) with the transmission signal (TX) depending on the value of a second driver strength control line (SCLL), which is fed by the controller (CTR), while the second strength control device (STRL) sets the remaining lines of the second modified switching signal (TDXTL) to such a potential that the remaining second sub-switches (TL ₁ , TL ₂ , TL ₃ ) are assigned to the remaining lines of the second modified switching signal (TDXTL). are, are blocked.

By not providing full driver strength, the ramp changes shape when transitioning from recessive to dominant bus states, resulting in a delay. This failure to provide the full driver strength and thus the control of the driver strength also takes place as a function of the first measured potential value (PMH) and/or the second measured potential value (PML) and/or the common mode measured value (MS).

The controller (CTR) regulates the driver strength of the first switch (TH) using one of said driver strength control lines (SCLH) in such a way that the common mode signal is minimized, preferably in the form of the common mode measured value (MS) on the data bus (CH, CL). The first strength control device (STRH) selects which of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) can or cannot be switched on by means of an active transmission signal (TX). This selection of the first strength control device (STRH) depends on the state or the current value of said first driver strength control line (SCLH) of the controller (CTR). The first drive strength control line (SCLH) is preferably a digital data bus. In the simplest case, however, it can also only be a single line.

The controller (CTR) regulates the driver strength of the second switch (TL) in an analogous manner using a second driver strength control line (SCLL) in such a way that the common mode signal is minimized, preferably in the form of the common mode measured value (MS) on the data bus (CH, CL). A second strength control device (STRL) selects which of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) can or cannot be switched on by means of an active transmission signal (TX). This selection of the second strength control device (STRL) depends on the state of said second driver strength control line (SCLL) of the controller (CTR). at the second driver strength control line (SCLL) is preferably a digital data bus. In the simplest case, however, it can also only be a single line.

The controller (CTR) preferably regulates the driver strength of the first switch (TH) by means of the first driver strength control line (SCLH) and of the second switch (TL) by means of the second driver strength control line (SCLL) in a manner dependent on the first potential measurement value (PMH) of the potential (V _CH ) on the first data line and/or from the second potential measurement value (PML) of the potential (V _CL ) on the second data line (CL) together, so that the common mode signal is preferably in the form of the common mode measurement value (MS) on the data bus (CH , CL) is minimized.

The common mode voltage in the form of the common mode measured value (MS) is preferably divided by the supply voltage and a first measured value is thus determined. This measured value is called the symmetry parameter (V _sym ) in the following.

In dem Beispiel der 1 ist der Verlauf des Spannungspotenzials (V_CH) auf der ersten Datenleitung (CH) um ca. 10 ns gegenüber dem Spannungspotenzialverlauf (V_CL) auf der zweiten Datenleitung (CL) verzögert.The symmetry parameter is determined as follows: $${\text{V}}_{\text{sym}}=\left(\text{PMH}+\text{PML}\right)/{\text{V}}_{\text{CC}}$$

In the example of 1 the course of the voltage potential (V _CH ) on the first data line (CH) is delayed by approx. 10 ns compared to the course of the voltage potential (V _CL ) on the second data line (CL).

The differential voltage on the differential data bus is calculated as: $${\text{V}}_{\text{differential}}={\text{V}}_{\text{CH}}-{\text{V}}_{\text{CL}}$$

Hierbei steht R_L für den Arbeitswiderstandswert zwischen der ersten Datenleitung (CH) und der zweiten Datenleitung (CL).A filtered differential symmetry parameter (V _Diff,min ) is obtained by low-pass filtering the symmetry parameter (V _sym ). The first threshold value is calculated from the filtered differential symmetry parameter (V _Diff,min ) as follows: $${\text{u}}_{\text{TH\_H}}=\left({\text{V}}_{\text{differential}\text{, min}}/{\text{R}}_{\text{L}}\right){\text{t}}_{\text{res}}/{\text{C}}_{\text{out\_H}}$$

Here, R _L stands for the load resistance value between the first data line (CH) and the second data line (CL).

The temporal size (tres) is specified as a freely selectable size as a design goal. This time variable design (tres) is a target variable for the shortest time delay between a voltage ramp on the first data line (CH) and a voltage ramp on the other side of the second data line (CL).

The capacitance C _{out_H} represents the capacitance of the first data line (CH) based on the signal base, i.e. on the reference potential.

The capacitance C _{out_L} represents the capacitance of the second data line (CL) in relation to the signal ground, i.e. to the reference potential.

Die Gleichtaktspannung ist als Referenzspannung nicht geeignet, da sie typischerweise nicht stabil genug ist.An analog threshold voltage can be calculated for the second threshold: $${\text{u}}_{\text{TH\_L}}=\left({\text{V}}_{\text{differential}\text{, min}}/{\text{R}}_{\text{L}}\right){\text{t}}_{\text{res}}/{\text{C}}_{\text{out\_L}}$$

The common-mode voltage is not suitable as a reference voltage because it is typically not stable enough.

benutzt werden. Bei richtiger Ansteuerung ist der Symmetrieparameter (V_sym) konstant 1. Dieser Wert 1 ist der Regelungszielwert.Instead of the common-mode voltage, the symmetry parameter $${\text{V}}_{\text{sym}}=\left(\text{PMH}+\text{PML}\right)/{\text{V}}_{\text{CC}}$$

to be used. If the control is correct, the symmetry parameter (V _sym ) is a constant 1. This value 1 is the control target value.

The symmetry parameter V _sym shows voltage spikes on the data bus as a function of the edge direction and the type of data bit edge. A data bit edge here means the transition from a recessive state of the data bus to a dominant state of the data bus and/or the transition from a dominant state of the data bus to a recessive state of the data bus.

Typically, a first comparator (CMPH) compares the symmetry parameter (V _sym ) to the first threshold (U _{TH_H} ) to generate a first comparator output signal (CMPOH) and a second comparator compares the symmetry parameter (V _sym ) to the second threshold (U _{TH_L} ) to generate a second comparator output signal (CMPOL).

A first low-pass filter (F1) generates a low-pass filtered symmetry parameter (V _symL ) from the symmetry parameter (V _sym ) by low-pass filtering.

It is recommended to select the filter parameters of the first low-pass filter (F1) and its construction in such a way that the cut-off frequency f _{cutt of of} the low-pass filter is preferably higher by a factor of 2 than the highest possible data frequency fdata. A preferred implementation can be, for example, a second-order low-pass filter with a limit frequency f _{cut of} 0.5 MHz for a 2.5 MHz f _data data rate (=factor 2). A Sample & Hold device has the same technical effect as a low-pass filter if operated at the right times.

The first method according to the invention presented above can be summarized in the form of a simple question: is there a voltage pulse on the signal of the symmetry parameter (V _sym ) or not? If a spike detection device (SPD) of any kind detects such a voltage pulse, the delay of one of the delayed control signals (TDXH, TDXL) is reduced and/or the delay of the respective other delayed control signal of the delayed control signals (TDXH, TDXL) is increased so that the voltage spike on the symmetry signal (V _sym ) subsequently disappears or is at least minimized. This reduction/increase in the delay preferably takes place in the form that the delay is always changed by the same value when a voltage pulse occurs.

The second method described above can be summarized in the form of a simple question: is there a voltage pulse on the signal of the symmetry parameter (V _sym ) or not? If a spike detection device (SPD) of any kind detects such a voltage pulse, the driver strength of one of the switches (TH, TL) is reduced depending on the polarity of the voltage pulse and depending on the type of data edge (recessive to dominant or dominant to recessive). and/or the driver strength of the respective other switch of the switches (TH, TL) is increased so that the voltage peak on the symmetry signal (V _sym ) subsequently disappears. This reduction/increase in the driver strength of the switches (TH, TL) preferably takes place in such a way that the reduction/increase in the driver strength of the switches (TH, TL) when a voltage pulse occurs on the signal of the symmetry parameter (V _sym ) is always by the same value is changed.

VERSION 1

A first variant corresponds to the upper part of the 3 .

• • Erfassen des Potenzials (V_CH) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Verzögern des Sendesignals (TX) zu einem ersten verzögerten Sendesignal (TDXH) um einen ersten zeitlichen Verzögerungswert (ΔtH), wobei der erste zeitliche Verzögerungswert (ΔtH) von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML) abhängt;
• • Verwenden des ersten verzögerten Sendesignals (TDXH) als erstes modifiziertes Schaltsignal (TDXTH);
• • Steuern des ersten Schalters (TH) mit dem ersten modifizierten Schaltsignal (TDXTH).

A first variant of the invention is therefore a method for reducing common mode generation in a differential data bus (CL; CH) with a first data line (CH) and with a second data line (CL) and with a first switch (TH) which is used to connect the first data line (CH) with a first supply voltage (VCC) depending on a first modified switching signal (TDXTH), and with a second switch (TL) which is used to connect the second data line (CL) to a second supply voltage ( GND) depending on a second modified switching signal (TDXTL) is used or provided. The first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX). The data bus (CL, CH) can assume a recessive state and a dominant state. The method of variant 1 includes the steps:

• • detecting the potential (V _CH ) of the first data bus line (CH) to determine a first measured potential value (PMH);
• • detecting the potential (V _CL ) of the second data bus line (CL) to determine a second potential measured value (PML);
• • Delaying the transmission signal (TX) to form a first delayed transmission signal (TDXH) by a first time delay value (ΔtH), the first time delay value (ΔtH) depending on the first measured potential value (PMH) and the second measured potential value (PML);
• • using the first delayed transmission signal (TDXH) as the first modified switching signal (TDXTH);
• • Controlling the first switch (TH) with the first modified switching signal (TDXTH).

• • Erfassen des Potenzials der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Bestimmung eines Symmetrieparameters (V_sym) in Abhängigkeit von dem ersten Potentialmesswert (PMH) und dem zweiten Potenzialmesswert (PML);
• • Verzögern des Sendesignals (TX) zu einem ersten verzögerten Sendesignal (TDXLH) um einen ersten zeitlichen Verzögerungswert (ΔtH), wobei der erste zeitliche Verzögerungswert (ΔtH) von dem Symmetrieparameter (V_sym) abhängt;
• • Verwenden des ersten verzögerten Sendesignals (TDXH) als erstes modifiziertes Schaltsignal (TDXTH);
• • Steuern des ersten Schalters (TH) mit dem ersten modifizierten Schaltsignal (TDXTH).

A first refinement of method variant 1 also includes the determination of a symmetry parameter (V _sym ) as a function of the first measured potential value (PMH) and the second measured potential value (PML) instead of the step of delaying the transmission signal (TX) to form a first delayed transmission signal (TDXH) by a first time delay value (ΔtH), the first time delay value (ΔtH) depending on the first potential measurement value (PMH) and the second potential measurement value (PML), the step of delaying the transmission signal (TX) to form a first delayed transmission signal (TDXLH) by a first time delay value (ΔtH), the first time delay value (ΔtH) depending on the symmetry parameter (V _sym ). This variant of the method then includes the following steps:

• • detecting the potential of the first data bus line (CH) to determine a first potential measured value (PMH);
• • detecting the potential of the second data bus line (CL) to determine a second potential measured value (PML);
• • Determination of a symmetry parameter (V _sym ) depending on the first power potential reading (PMH) and the second potential reading (PML);
• • Delaying the transmission signal (TX) to form a first delayed transmission signal (TDXLH) by a first time delay value (ΔtH), the first time delay value (ΔtH) depending on the symmetry parameter (V _sym );
• • using the first delayed transmission signal (TDXH) as the first modified switching signal (TDXTH);
• • Controlling the first switch (TH) with the first modified switching signal (TDXTH).

In a second refinement of method variant 1 in the form of a refinement of the first refinement of method variant 1, the symmetry parameter (V _sym ) is calculated from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym =(PMH + PML)/ V _CC formed. Vcc is the potential value of the supply voltage compared to the reference potential (eg GND).

In a third refinement of method variant 1 in the form of a refinement of the first refinement of method variant 1 and/or in the form of a refinement of the second refinement of method variant 1, the proposed method has the step of generating a filtered differential symmetry parameter (V _Diff,min ) from the Symmetry signal (V _sym ) by low-pass filtering and the use of the differential symmetry parameter (V _Diff,min ) for determining a first threshold value (U _{TH_H} ).

In a fourth refinement of method variant 1 in the form of a refinement of the third refinement of method variant 1, the first threshold value (U _{TH_H} ) is determined according to the formula U _{TH_H} =(V _Diff,min /R _L )t _res /C _{out_H} .

In a fifth refinement of method variant 1 in the form of a refinement of the third refinement and/or the fourth refinement, the symmetry signal (V _sym ) is additionally compared with the first threshold value (U _{TH_H} ), in particular by means of a first comparator (CMPH), for Determination of a first comparison value in the form of a first comparator output signal (CMPOH) of the first comparator (CMPH). Instead of the step of delaying the transmission signal (TX) to form a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) depending on the first measured potential value (PMH) and the second measured potential value (PML), a step of delaying the transmission signal (TX) to form a second delayed transmission signal (TDXL) by a second time delay value (ΔtL) is now carried out, the second time delay value (ΔtL) being different from the first comparison value in the form of the first comparator output signal of the first comparator ( CMPH) depends.

VARIANT 2

This variant corresponds to the lower part of the 3 .

• • Erfassen des Potenzials (V_CH) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Verzögern des Sendesignals (TX) zu einem zweiten verzögerten Sendesignal (TDXL) um einen zweiten zeitlichen Verzögerungswert (ΔtL), wobei der zweite zeitliche Verzögerungswert (ΔtL) von dem ersten Potenzialmesswert (V_CH) und dem zweiten Potenzialmesswert (V_CL) abhängt;
• • Verwenden des zweiten verzögerten Sendesignals (TDXL) als zweites modifiziertes Schaltsignal (TDXTL);
• • Steuern des zweiten Schalters (TL) mit dem zweiten modifizierten Schaltsignal (TDXTL);

The second variant is a method for reducing the generation of common mode in a differential data bus (CL, CH) with a first data line (CH) and with a second data line (CL). At least one driver, which is connected to the data bus, has the first switch (TH), which serves or is provided for connecting the first data line (CH) to a first supply voltage (VCC) depending on a first modified switching signal (TDXTH), and the second switch (TL), which serves or is provided for connecting the second data line (CL) to a second supply voltage (GND) as a function of a second modified switching signal (TDXTL). The first modified switching signal (TDXH) and the second modified switching signal (TDXL) again depend on a transmission signal (TX). The data bus (CL, CH) can assume a recessive state and a dominant state. The method of variant 2 has the following steps:

• • detecting the potential (V _CH ) of the first data bus line (CH) to determine a first measured potential value (PMH);
• • detecting the potential (V _CL ) of the second data bus line (CL) to determine a second potential measured value (PML);
• • Delaying the transmission signal (TX) to form a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) depending on the first measured potential value (V _CH ) and the second measured potential value (V _CL );
• • Using the second delayed transmission signal (TDXL) as the second modified switching signal (TDXTL);
• • controlling the second switch (TL) with the second modified switching signal (TDXTL);

In a first refinement of the second variant, a symmetry parameter (V _sym ) is additionally determined as a function of the first measured potential value (PMH) and the second measured potential value (PML). The step of delaying the transmission signal (TX) to form a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) depends on the first potential measurement value (PMH) and the second potential measurement value (PML) is now carried out differently. Instead, in a modification of the basic method of the second method variant, the transmission signal (TX) is now delayed to form a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) now, however, depending on the additionally determined symmetry parameter (V _sym );

In a second refinement, the symmetry parameter (V _sym ) is preferably formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym =(PMH + PML)/V _CC (with Vcc as the potential value of the supply voltage) .

A third refinement includes generating a filtered differential symmetry parameter (V _Diff,min ) from the symmetry parameter (V _sym ) signal by low-pass filtering and using the filtered differential symmetry parameter (V _Diff,min ) to determine a second threshold (U _{TH_L} ) .

In a fourth refinement, the second threshold value (U _{TH_L} ) is determined according to the formula U _{TH_L} =(V _Diff,min / R _L )t _res /C _{out_L} .

In a fifth refinement, the symmetry signal (V _sym ) is compared with the second threshold value (U _{TH_L} ), in particular by means of a second comparator (CMPL), to determine a second comparison value in the form of a second comparator output signal of the second comparator (CMPH). The step of delaying the transmit signal (TX) to a second delayed transmit signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) being dependent on the first potential measurement value (V _CH ) and the second potential measurement value (V _CL ) depends, is now not carried out in this form. Rather, instead of this step, the transmission signal (TX) is delayed to form a second delayed transmission signal (TDXL) by a second time delay value (ΔtL), the second time delay value (ΔtL) now, however, depending on the second comparison value.

VARIATION 3

This variant corresponds to the 3 .

A third variant combines the method of the first variant with a method of the second variant. A corresponding device is in 3 shown.

VARIATION 4

This variant corresponds to the upper part of the 4 .

• • Erfassen des Potenzials (V_CH) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Ändern der ersten Treiberstärke in Abhängigkeit von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML).

A fourth variant of the method is a method for reducing the generation of common mode in a differential data bus (CL, CH) with a first data line (CH) and with a second data line (CL). A driver connected to the data bus comprises a first switch (TH) for connecting the first data line (CH) to a first supply voltage (VCC) in response to a first modified switching signal (TDXTH) having a first drive strength, and a second switch ( TL) for connecting the second data line (CL) to a second supply voltage (GND) in response to a second modified switching signal (TDXTL)) having a second drive strength. The first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX). The data bus (CL, CH) can assume a recessive state and a dominant state. This fourth variant of the method comprises the steps:

• • detecting the potential (V _CH ) of the first data bus line (CH) to determine a first measured potential value (PMH);
• • detecting the potential (V _CL ) of the second data bus line (CL) to determine a second potential measured value (PML);
• • Changing the first driver strength depending on the first potential reading (PMH) and the second potential reading (PML).

In a first refinement of the fourth method, a symmetry parameter (V _sym ) is determined as a function of the first measured potential value (PMH) and the second measured potential value (PML). The method step of changing the first driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) is not carried out in this first refinement of the fourth variant. Instead, the first driver strength is changed as a function of the symmetry parameter (V _sym ).

According to a second refinement of the fourth variant, the symmetry parameter (V _sym ) is formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym =(PML + PMH)/V _CC (with V _CC as the potential value of the supply voltage).

In a third refinement of the fourth variant, the method includes generating a filtered differential symmetry parameter ters (V _Diff,min ) from the symmetry signal (V _sym ) by low-pass filtering and the use of the differential symmetry parameter (V _Diff,min ) for determining a first threshold value (U _{TH_H} ).

In a fourth refinement of the fourth variant, the first threshold value (U _{TH_H} ) is determined according to the formula U _{TH_H} =(V _Diff,min /R _L )t _res /C _{out_H} .

In a fifth refinement of the fourth variant of the method, the symmetry signal (V _sym ) is compared with the first threshold value (U _{TH_H} ), in particular by means of a first comparator (CMPH), to determine a first comparison value, in particular in the form of generating a first comparator output signal (CMPOH) of the first comparator (CMPH). The step of changing the first driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) is not carried out in this refinement of the fourth variant. Instead, the first driver strength is changed as a function of the first comparison value, ie in particular as a function of the first comparator output signal (CMPOH) of the first comparator (CMPH).

VARIATION 5

This variant corresponds to the lower part of the 4 .

• • Erfassen des Potenzials (V_CH) der ersten Datenbusleitung (CH) zur Ermittlung eines ersten Potenzialmesswertes (PMH);
• • Erfassen des Potenzials (V_CL) der zweiten Datenbusleitung (CL) zur Ermittlung eines zweiten Potenzialmesswertes (PML);
• • Verzögern des Sendesignals (TX) zu einem zweiten verzögerten Sendesignal (TDXL) um einen zweiten zeitlichen Verzögerungswert zu erhalten, wobei der zweite zeitliche Verzögerungswert von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML) abhängt;
• • Ändern der zweiten Treiberstärke in Abhängigkeit von dem ersten Potenzialmesswert (PMH) und dem zweiten Potenzialmesswert (PML).

A fifth variant of the method is a method for reducing the generation of common mode in a differential data bus with a first data line (CH) and with a second data line (CL). A driver connected to the data bus comprises a first switch (TH) for connecting the first data line (CH) to a first supply voltage (VCC) in response to a first modified switching signal (TDXTH) having a first drive strength, and a second switch (TL) for connecting the second data line (CL) to a second supply voltage (GND) in response to a second modified switching signal (TDXTL)) having a second drive strength. The first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX). The data bus can have a recessive state and a dominant state. The fifth variant of the method includes the steps:

• • detecting the potential (V _CH ) of the first data bus line (CH) to determine a first measured potential value (PMH);
• • detecting the potential (V _CL ) of the second data bus line (CL) to determine a second potential measured value (PML);
• • delaying the transmission signal (TX) to form a second delayed transmission signal (TDXL) in order to obtain a second time delay value, the second time delay value depending on the first measured potential value (PMH) and the second measured potential value (PML);
• • Changing the second driver strength depending on the first potential reading (PMH) and the second potential reading (PML).

In a first refinement of the fifth variant of the method, a symmetry parameter (V _sym ) is determined as a function of the first measured potential value (PMH) and the second measured potential value (PML). The step of changing the second driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) now does not take place in this form in this refinement of the fifth variant. Instead, the second driver strength is now changed as a function of the symmetry parameter (V _sym ).

In a second refinement of the fifth variant of the method, the symmetry parameter (V _sym ) is formed from the first measured potential value (PMH) and the second measured potential value (PML) according to the formula V _sym =(PMH + PML)/V _CC (with V _CC as potential value of the supply voltage).

In a third refinement of the fifth variant of the method, a filtered differential symmetry parameter (V _Diff,min ) is generated from the symmetry signal (V _sym ) by low-pass filtering and the differential symmetry parameter (V _Diff,min ) is used to determine a second threshold value ( U _{TH_L} );

In a fourth refinement of the fifth variant of the method, the second threshold value (U _{TH_L} ) is determined according to the formula U _{TH_L} =(V _Diff,min /R _L )t _res /C _out-L .

In a fifth refinement of the fifth variant of the method, the symmetry signal (V _sym ) is compared with the second threshold value (U _{TH_L} ), in particular by means of a second comparator, to determine a first comparison value, in particular in the form of a second comparator output signal (CMPOL) of the second Comparator (CMPL). The step of changing the second driver strength as a function of the first measured potential value (PMH) and the second measured potential value (PML) is not carried out in this way; instead, the second driver strength is changed as a function of the second comparison value, i.e. in particular this can be carried out as a function of the second comparator output signal (CMPOL) of the second comparator (CMPL) happen.

VARIATION 6

This variant corresponds to the 4 .

A sixth variant combines the method of the fourth variant with a method of the fifth variant.

VARIATION 7

This variant corresponds to the upper part of the 5 .

A seventh variant combines the methods of the first to sixth variants with one another.

Finally, it should also be mentioned that a corresponding device can be provided which carries out the first to seventh method variants.

Such a device, a driver for such a data bus (CL, CH) has a first switch (TH), which preferably consists of several sub-switches (TH ₁ , TH ₂ , TH ₃ ), and a second switch (TL) on, which preferably consists of several sub-switches (TL ₁ , TL ₂ , TL ₃ ).

It preferably has a first time delay control line (DLYH), which delays the transmission signal (TX) to the first delayed transmission signal (TDXH) by a first time delay value (ΔtH). The first time delay value (ΔtH) depends on the value on a first time delay control line (DCLH) of the device.

It preferably has a second time delay control line (DLYL), which delays the transmission signal (TX) to the second delayed transmission signal (TDXL) by a second time delay value (ΔtL). The second time delay value (ΔtL) depends on the value on a second time delay control line (DCLL) of the device.

It has a first strength control device (STRH) which sends the first delayed transmission signal (TDXH) to the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) as a function of the value of the first driver strength control line (SCLH) in the form of a first modified switching signal ( TDXTH) distributed. The first modified switching signal (TDXTH) is preferably a bus of lines, with each control connection of each first sub-switch (TH ₁ , TH ₂ , TH ₃ ) being assigned one of the lines of the first modified switching signal (TDXTH). Depending on the value of the first driver strength control line (SCLH), some of the lines of the first modified switching signal (TDXTH) are connected to the delayed transmission signal (TDXH), whereby the associated first sub-switches of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) are switched on when the transmission signal (TX) become active. The other lines of the first modified switching signal (TDXTH) are switched in such a way that the associated first sub-switches of the first sub-switches (TH ₁ , TH ₂ , TH ₃ ) do not become active even when the transmission signal (TX) is active. This models the driver strength. Other forms of driver strength modification, for example via current sources whose current strength is regulated by the first driver strength control line (SCLH), are conceivable.

The device has a second strength control device (STRL), which transmits the second delayed transmission signal (TDXL) to the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) depending on the value of the second driver strength control line (SCLL) in the form of a second modified switching signal (TDXTL) distributed. The second modified switching signal (TDXTL) is preferably a bus of lines, with each control connection of every second sub-switch (TL ₁ , TL ₂ , TL ₃ ) being assigned one of the lines of the second modified switching signal (TDXTL). Depending on the value of the second driver strength control line (SCLL), some of the lines of the second modified switching signal (TDXTL) are connected to the delayed transmission signal (TDXL), whereby the associated second sub-switches of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) are switched on when the transmission signal (TX) become active. The other lines of the second modified switching signal (TDXTL) are switched in such a way that the associated second sub-switches of the second sub-switches (TL ₁ , TL ₂ , TL ₃ ) do not become active even when the transmission signal (TX) is active. This models the driver strength of the second switch (TL). Other forms of driver strength modification, for example via current sources whose current strength is regulated by the second driver strength control line (SCLL), are conceivable.

A controller (CTR), which is part of the device, sets the first time delay value (ΔtH) of the first time delay control line (DLYH) and the second time delay value (ΔtL) of the second time delay control line (DLYL).

Furthermore, the controller (CTR) sets the first drive strength of the first switch (TH) and the second drive strength of the second switch (TH). To do this, it sets the value of the first drive strength control line (SCLH) and the value of the second drive strength control line (SCLL).

The controller sets the value of the first drive strength control line (SCLH) and the value of the second drive strength control line (SCLL) and the first time delay value (ΔtH) of the first time delay control line (DLYH) and the second time delay value (ΔtL) of the second time delay control line (DLYL). from a common mode (MS) reading.

The device has a measuring device (MB) for detecting the potential (V _CH ) of the first data line (CH) in the form of a first measured potential value (PMH) and for detecting the potential (V _CL ) of the second data line (CL) in the form of a second potential reading (PML). The measuring device (MB) preferably uses this to determine a measured common-mode value (MS). Typically, this common mode measurement (MS) corresponds to the symmetry parameter (V _sym ). The controller preferably includes a first filter (F1) which filters the common-mode measured value (MS) or the symmetry parameter (V _sym ) to form a filtered differential symmetry parameter (V _Diff,min ). The control has a switching threshold generator which preferably generates a first threshold value (U _{TH_H} ) and a second threshold value (U _{TH_L} ) from the filtered differential symmetry parameter (V _Diff,min ).

A first comparator (CMPH) compares the common-mode measured value (MS) or the symmetry parameter (V _sym ) with the first threshold value (U _{TH_H} ) and generates a first comparison result in the form of a first comparator output signal (CMPOH) of the first comparator (CMPH).

A second comparator (CMPL) compares the common-mode measured value (MS) or the symmetry parameter (V _sym ) with the second threshold value (U _{TH_L} ) and generates a second comparison result in the form of a second comparator output signal (CMPOL) of the first comparator (CMPH).

The controller then sets the value of the first driver strength control line (SCLH) and the first time delay value (ΔtH) of the first time delay control line (DLYH) depending on the first comparison result in the form of the value of the first comparator output signal (CMPOH) of the first comparator (CMPH). . For example, with each pulse on the first comparator output signal (CMPOH) for each data edge, the first delay time (ΔtH) can be reduced and/or the driver strength of the first switch (TH) increased and with each pulse on the second comparator output signal (CMPOL) for each Data edge each the first delay time (.DELTA.tH) are increased and / or the driver strength of the first switch (TH) are reduced.

The controller then preferably sets the value of the second driver strength control line (SCLL) and the second time delay value (ΔtL) of the second time delay control line (DLYL) depending on the second comparison result in the form of the value of the second comparator output signal (CMPOL) of the second comparator (CMPL). . For example, with each pulse on the second comparator output signal (CMPOL) for each data edge, the second delay time (ΔtL) can be reduced and/or the driver strength of the second switch (TL) can be increased and with each pulse on the first comparator output signal (CMPOH) for each Data edge each the second delay time (.DELTA.tL) are increased and / or the driver strength of the second switch (TL) are reduced.

advantage

Such a driver for such a data bus generates fewer common-mode components since the control is synchronized by the control. However, the advantages are not limited to this.

character list

• 1 shows the time profile of the first data line potential (V _CH ) of the first data line (CH) and the time profile of the second data line potential (V _CL ) of the second data line (CL) during the transition from the recessive to the dominant data bus state.
• 2 shows a data bus driver according to the prior art (SdT) described in the introduction.
• 3 shows a data bus driver according to the invention with delay control.
• 4 shows a data bus driver according to the invention with regulation of the driver strength.
• 5 shows a data bus driver according to the invention with regulation of the delay and the driver strength.
• 6 shows a first switch (TH) and a second switch (TL), which are set up and provided for charging the first data line (CH) and the second data line (CL) with different driver strengths. The first modified transmission signal (TDXTH) and the second modified transmission signal (TDXTL) are shown with their lines separated into individual lines as buses.

Reference List

CH

first data bus line of the differential data bus;

CL

second data bus line of the differential data bus;

CHdom

higher potential of the first data line (CH), which the first data line (CH) assumes in the dominant state of the data bus;

CLdom

low potential of the second data line (CL), which the second data line (CL) assumes in the dominant state of the data bus;

CLHrez

recessive potential. The first data bus line (CH) and the second data bus line (CL) assume the recessive potential in the recessive state of the differential data bus;

CMPH

first comparator. The first comparator generates the first comparator output signal (CMPOH) by comparing the symmetry parameter (V _sym ) with the first threshold value (U _{TH_H} );

CMPL

second comparator. The second comparator generates the second comparator output signal (CMPOL) by comparing the symmetry parameter (V _sym ) with the second threshold value (U _{TH_L} );

CMPOH

first comparator output signal of the first comparator (CMPH);

CMPOL

second comparator output signal of the second comparator (CMPL);

Cout_H

Capacity of the first data line (CH) related to the signal base, i.e. to the reference potential;

Cout_L

Capacity of the second data line (CL) related to the signal ground, i.e. to the reference potential;

ctr

Steering;

ΔtH

first time delay value by which the transmission signal (TX) is delayed with respect to the first delayed transmission signal (TDXH) in a first time delay control line (DLYH);

ΔtL

second time delay value by which the transmission signal (TX) is delayed with respect to the second delayed transmission signal (TDXL) in a first time delay control line (DLYH);

DCLH

first time delay control line with which the controller (CTR) sets the first time delay value (ΔtH) of the first time delay control line (DLYH);

DCLL

second time delay control line with which the controller (CTR) sets the second time delay value (ΔtL) of the second time delay control line (DLYL);

DLYH

first time delay control line (DLYH), which delays the transmission signal (TX) to the first delayed transmission signal (TDXH) by a first time delay value (ΔtH). The first time delay value (ΔtH) depends on the value on a first time delay control line (DCLH).

F1

first low-pass filter;

fcutt of

cut-off frequency of the first low-pass filter (F1);

fdata

highest possible data frequency;

GND

supply ground;

MB

measuring device;

MS

common mode reading;

PMH

first potential reading;

PML

second potential reading;

RL

Working resistance value between the first data line (CH) and the second data line (CL);

SCLH

first driver strength control line;

SCLL

second driver strength control line;

SPD

spike detection device;

STRH

first strength control device;

STRL

second strength control device;

TDXH

first delayed transmission signal;

TDXL

second delayed broadcast signal;

TDXTH

first modified switching signal;

TDXTL

second modified switching signal;

th

first switch;

TH1

first sub-switch of the first sub-switches of the first switch (TH);

TH2

second sub-switch of the first sub-switches of the first switch (TH);

TH3

third sub-switch of the first sub-switches of the first switch (TH);

Thn

nth sub-switch of the first sub-switches of the first switch (TH);

tsp

second switch;

TL1

first sub-switch of the second sub-switches of the second switch (TL);

TL2

second sub-switch of the second sub-switches of the second switch (TL);

TL3

third sub-switch of the second sub-switches of the second switch (TL);

TLn

nth sub-switch of the second sub-switches of the second switch (TL);

tres

temporal size design. The temporal size Design(t _res ) is specified as a freely selectable size as a design goal. It is a target value for the shortest time delay between a voltage ramp on the first data line (CH) and a voltage ramp on the other side of the second data line (CL);

TX

broadcast signal;

UTH_H

first threshold;

UTH_L

second threshold;

VCC

supply voltage or supply voltage line;

VCL

Potential of the second data line (CL) relative to a reference ground (typically GND);

VCH

Potential of the first data line (CH) relative to a reference ground (typically GND);

VDiff

differential voltage on the data bus. It is defined as V _Diff= V _CH -V _CL ;

VDiff, min

filtered symmetry parameter;

VsymL

low-pass filtered symmetry parameter;

Vsym

symmetry parameters;

Claims (4)

Method for reducing common mode generation in a differential data bus - with a first data line (CH) and - with a second data line (CL) and - with a first switch (TH) for connecting the first data line (CH) to a first supply voltage (VCC) depending on a first modified switching signal (TDXTH), which has a first driver strength, and - with a second switch (TL) for connecting the second data line (CL) to a second supply voltage (GND) depending on a second modified switching signal (TDXTL ), which has a second driver strength, and - wherein the first modified switching signal (TDXH) and the second modified switching signal (TDXL) depend on a transmission signal (TX) and - wherein the data bus can assume a recessive state and a dominant state with the steps - detecting the potential (V _CH ) of the first data bus line (CH) to determine a first measured potential value (PMH ); - detecting the potential (V _CL ) of the second data bus line (CL) to determine a second measured potential value (PML); - determining a symmetry parameter (V _sym ) as a function of the first measured potential value (PMH) and the second measured potential value (PML); changing the first driver strength depending on the symmetry parameter (V _sym ); Changing the second driver strength depending on the symmetry parameter (V _sym ), - where the symmetry parameter (V _sym ) from the first potential measurement value (PMH) and the second potential measurement value (PML) according to the formula V _sym = (PMH + +PML) / V _CC is formed (with Vcc as the potential value of the supply voltage). procedure after claim 1 comprising the additional steps: - generating a filtered differential symmetry parameter (V _Diff,min ) from the symmetry signal (V _sym ) by low-pass filtering; - Use of the differential symmetry parameter ters (V _Diff,min ) for determining a first threshold value (U _{TH_H} ) and - use of the differential symmetry parameter (V _Diff,min ) for determining a second threshold value (U _{TH_L} ). procedure after claim 2 - the first threshold value (U _{TH_H} ) being determined according to the formula U _{TH_H} =(V _Diff,min /R _L )t _res /C _{out_H} and/or - the second threshold value (U _{TH_L} ) being determined according to the formula U _{TH_L} =( V _Diff,min /R _L )t _res /C _{out_L} is determined. Method according to one or more of the claims 2 until 3 comprising the additional steps: - comparing the symmetry signal (V _sym ) with the first threshold value (U _{TH_H} ), in particular by means of a first comparator (CMPH), to determine a first comparison value, in particular in the form of generating a first comparator output signal (CMPOH) of the first comparator (CMPH); - Comparison of the symmetry signal (V _sym ) with the second threshold value (U _{TH_L} ), in particular by means of a second comparator (CMPL), to determine a second comparison value, in particular in the form of generating a second comparator output signal (CMPOL) of the second comparator (CMPL); - Changing the first driver strength as a function of the first comparison value, ie in particular as a function of the first comparator output signal (CMPOH) of the first comparator (CMPH); - Changing the second driver strength as a function of the second comparison value, ie in particular as a function of the second comparator output signal (CMPOHL) of the second comparator (CMPL).

Images