DE102018220751A1 - MIDDLE-OF-LINE STRUCTURES - Google Patents
MIDDLE-OF-LINE STRUCTURES Download PDFInfo
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- DE102018220751A1 DE102018220751A1 DE102018220751.8A DE102018220751A DE102018220751A1 DE 102018220751 A1 DE102018220751 A1 DE 102018220751A1 DE 102018220751 A DE102018220751 A DE 102018220751A DE 102018220751 A1 DE102018220751 A1 DE 102018220751A1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
Die Erfindung betrifft im Allgemeinen Halbleiterstrukturen und insbesondere Middle-of-Line-Strukturen und -Herstellungsverfahren. Die Struktur umfasst: eine Mehrzahl von Gatestrukturen mit Source- und/oder Drain-Metallisierungsmerkmalen; Abstandshalter auf Seitenwänden der Gatestrukturen, die aus einem ersten Material und einem zweiten Material gebildet sind; und Kontakte in elektrischem Kontakt zu den Source- und/oder Drain-Metallisierungsmerkmalen, die von den Gatestrukturen durch die Abstandshalter getrennt sind.The invention generally relates to semiconductor structures, and more particularly to middle-of-line structures and fabrication methods. The structure comprises: a plurality of gate structures having source and / or drain metallization features; Spacers on sidewalls of the gate structures formed of a first material and a second material; and contacts in electrical contact with the source and / or drain metallization features separated from the gate structures by the spacers.
Description
GEBIET DER ERFINDUNGFIELD OF THE INVENTION
Die Erfindung betrifft im Allgemeinen Halbleiterstrukturen und insbesondere Middie-of-Line-Strukturen und Herstellungsverfahren.The invention generally relates to semiconductor structures, and more particularly to mid-of-line structures and fabrication methods.
HINTERGRUNDBACKGROUND
Mit der fortgesetzten Skalierung von Halbleiterprozessen zu kleineren Größen, zum Beispiel Schrumpfen, wird auch der gewünschte Abstand zwischen Merkmalen (insbesondere der Pitch) kleiner. Dazu wird es an kleineren Technologieknoten immer schwieriger, Back-End-of-Line (BEOL) und Middle-of-Line (MOL) -Metallisierungsmerkmale, z.B. Zwischenverbindungen, aufgrund von Prozesseigenschaften und der Skalierung der kritischen Dimension (CD), sowie der Materialien, die zur Herstellung dieser Strukturen verwendet werden, herzustellen.With the continued scaling of semiconductor processes to smaller sizes, such as shrinking, the desired spacing between features (especially the pitch) also becomes smaller. This is becoming increasingly difficult at smaller technology nodes, back-end-of-line (BEOL) and middle-of-line (MOL) metallization features, e.g. Interconnections, due to process properties and critical dimension (CD) scaling, as well as the materials used to make these structures.
Es ist zum Beispiel bei der Herstellung von Zwischenverbindungsstrukturen für Source- und Drain-Kontakte erforderlich, das dielektrische Material zu entfernen, das sich an den Gatestrukturen befindet. Die Entfernung des dielektrischen Materials wird durch einen Ätzprozess bereitgestellt, der das Abstandshaltermaterial der Gatestruktur tendenziell erodiert. Insbesondere kann das für die Abstandshalter oder Seitenwände der Gatestruktur verwendete dielektrische low-k-Material in nachfolgenden Ätzprozessen wegerodiert werden, die zur Bildung der Öffnungen für die Drain- und Source-Kontakte verwendet werden. Dieser Materialverlust legt das Metallmaterial der Gatestruktur frei, was zu einem Kurzschluss zwischen dem Metallmaterial der Gatestruktur und dem Metallmaterial führt, das zur Bildung des Kontaktes an sich verwendet wird.For example, in fabricating interconnect structures for source and drain contacts, it is necessary to remove the dielectric material located at the gate structures. The removal of the dielectric material is provided by an etching process that tends to erode the spacer material of the gate structure. In particular, the low-k dielectric material used for the spacers or sidewalls of the gate structure may be eroded away in subsequent etching processes used to form the openings for the drain and source contacts. This loss of material releases the metal material of the gate structure, resulting in a short circuit between the metal material of the gate structure and the metal material used to form the contact itself.
ZUSAMMENFASSUNGSUMMARY
In einem Aspekt der Erfindung umfasst eine Struktur: eine Mehrzahl von Gatestrukturen mit Source- und/oder Drain-Metallisierungsmerkmalen; Abstandshalter auf Seitenwänden der Gatestrukturen, wobei die Abstandshalter aus einem ersten Material und einem zweiten Material gebildet sind; und Kontakten in elektrischem Kontakt zu den Source- und/oder Drain-Metallisierungsmerkmalen, wobei die Kontakte von den Gatestrukturen durch Abstandshalter getrennt sind.In one aspect of the invention, a structure comprises: a plurality of gate structures having source and / or drain metallization features; Spacers on sidewalls of the gate structures, wherein the spacers are formed of a first material and a second material; and contacts in electrical contact with the source and / or drain metallization features, wherein the contacts are separated from the gate structures by spacers.
In einem Aspekt der Erfindung umfasst eine Struktur: eine Mehrzahl von Gatestrukturen mit Source/Drain-Bereichen, einem Gatematerial, Seitenwandabstandshaltern und einem Deckmaterial auf dem Gatematerial und den Seitenwandabstandshaltern; eine Mehrzahl von Source/Drain-Kontakten in elektrischem Kontakt zu den Source/Drain-Bereichen; eine Beschichtung, gebildet aus einem oberen Material und einem unteren Material entlang der Seitenwandabstandshalter; und Kontakte, die sich zu den Source/Drain-Kontakten erstrecken und die von dem Gatemetall durch die Beschichtung getrennt sind.In one aspect of the invention, a structure includes: a plurality of gate structures having source / drain regions, a gate material, sidewall spacers, and a cap material on the gate material and the sidewall spacers; a plurality of source / drain contacts in electrical contact with the source / drain regions; a coating formed of an upper material and a lower material along the sidewall spacers; and contacts extending to the source / drain contacts and separated from the gate metal by the coating.
In einem Aspekt der Erfindung umfasst ein Verfahren: ein Bilden einer Mehrzahl von Gatestrukturen mit Source- und/oder Drain-Metallisierungsmerkmalen; ein Bilden von Abstandshaltern auf Seitenwänden der Gatestrukturen, die ein erstes Material und ein zweites Material umfassen; und ein Bilden von Kontakten in elektrischem Kontakt zu den Source- und/oder Drain-Metallisierungsmerkmalen, wobei die Kontakte von den Gatestrukturen durch den Abstandshalter getrennt werden.In one aspect of the invention, a method comprises: forming a plurality of gate structures having source and / or drain metallization features; forming spacers on sidewalls of the gate structures comprising a first material and a second material; and forming contacts in electrical contact with the source and / or drain metallization features, wherein the contacts are separated from the gate structures by the spacer.
Figurenlistelist of figures
Die Erfindung wird in der detaillierten Beschreibung unten mit Bezug auf die Mehrzahl von Figuren anhand von nicht beschränkenden Beispielen beispielhafter Ausführungsformen der Erfindung beschrieben.
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1 zeigt unter anderen Merkmalen Gatestrukturen und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
2 zeigt unter anderen Merkmalen ein vertieftes Gatematerial der Gatestrukturen und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
3 zeigt unter anderen Merkmalen ein Deckmaterial auf den vertieften Gatematerialien und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
4 zeigt unter anderen Merkmalen Source und/oder Drain-Metallisierungsmerkmale (Kontakte) und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
5 zeigt unter anderen Merkmalen ein vertieftes Liner-Material und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
6 zeigt unter anderen Merkmalen ein Abstandshaltermaterial in den Vertiefungen des Liner-Materials und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
7 zeigt unter anderen Merkmalen eine Isolatorschicht, die in Vertiefungen der Source/Drain-Metallisierungsmerkmale gebildet ist, und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
8 zeigt unter anderen Merkmalen Kontakte, die mit den Source/Drain-Metallisierungsmerkmalen elektrisch verbunden sind, und entsprechende Fertigungsprozesse gemäß Aspekten der Erfindung. -
9 zeigt eine alternative Struktur und entsprechende Fertigungsprozesse gemäß zusätzlichen Aspekten der Erfindung.
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1 shows, among other features, gate structures and corresponding manufacturing processes according to aspects of the invention. -
2 shows, among other features, a recessed gate material of the gate structures and corresponding manufacturing processes in accordance with aspects of the invention. -
3 shows, among other features, a covering material on the recessed gate materials and corresponding manufacturing processes in accordance with aspects of the invention. -
4 shows, among other features, source and / or drain metallization features (contacts) and corresponding manufacturing processes in accordance with aspects of the invention. -
5 shows, among other features, a recessed liner material and corresponding manufacturing processes in accordance with aspects of the invention. -
6 shows, among other features, a spacer material in the recesses of the liner material and corresponding manufacturing processes in accordance with aspects of the invention. -
7 shows, among other features, an insulator layer formed in pits of the source / drain metallization features and corresponding fabrication processes in accordance with aspects of the invention. -
8th shows, among other features, contacts electrically connected to the source / drain metallization features and corresponding fabrication processes in accordance with aspects of the invention. -
9 shows an alternative structure and corresponding manufacturing processes according to additional aspects of the invention.
DETAILLIERTE BESCHREIBUNGDETAILED DESCRIPTION
Die Erfindung betrifft im Allgemeinen Halbleiterstrukturen und insbesondere Middie-of-Line-Strukturen und Herstellungsverfahren. Die hierin bereitgestellten Prozesse und Strukturen verwenden gemäß den Ausführungsformen hierin Abstandshalter auf den Seiten der Gatestrukturen, um einen Kurzschluss der Source/Drain (S/D) -Kontakte zu der Metallisierung der Gatestrukturen zu vermeiden. Vorteilhafterweise stellen die Abstandshalter ein zusätzliches Material bereit, um Kurzschlüsse in Fertigungsprozessen zu verhindern, insbesondere während Zwischenverbindungsstrukturen für die Source/Drain-Kontakte gebildet werden. Die hierin bereitgestellten Strukturen stellen Gatestrukturen mit einer verbesserten niedrigen parasitären Kapazität bereit.The invention generally relates to semiconductor structures, and more particularly to mid-of-line structures and fabrication methods. The processes and structures provided herein utilize spacers on the sides of the gate structures according to embodiments herein to avoid shorting the source / drain (S / D) contacts to the metallization of the gate structures. Advantageously, the spacers provide additional material to prevent short circuits in manufacturing processes, particularly during interconnect structures for the source / drain contacts. The structures provided herein provide gate structures with improved low parasitic capacitance.
Die Strukturen der Erfindung können in einer Vielzahl von Arten unter Verwendung einer Vielzahl von unterschiedlichen Werkzeugen hergestellt werden. Im Allgemeinen werden jedoch die Verfahren und Werkzeuge zur Bildung von Strukturen mit Dimensionen im Mikrometer-und Nanometerbereich verwendet. Die bei der Herstellung der Strukturen der Erfindung verwendeten Verfahren, insbesondere Technologien, wurden aus der Technik integrierter Schaltungen (ICs) übernommen. Die Strukturen werden z.B. auf Wafern gefertigt und in Materialfilmen realisiert, die durch fotolithografische Prozesse auf der Oberseite eines Wafers strukturiert werden. Insbesondere verwendet die Herstellung der Strukturen drei grundsätzliche Baublöcke: (i) Abscheidung von dünnen Materialfilmen auf einem Substrat, (ii) Aufbringen einer strukturierten Maske auf eine Oberseite der Filme mittels fotolithografischer Abbildung und (iii) selektives Ätzen der Filme bezüglich der Maske.The structures of the invention can be made in a variety of ways using a variety of different tools. In general, however, methods and tools are used to form structures with dimensions in the micrometer and nanometer range. The techniques used in fabricating the structures of the invention, particularly technologies, have been adopted from integrated circuit (IC) technology. The structures are e.g. manufactured on wafers and realized in film of material, which are structured by photolithographic processes on top of a wafer. In particular, the fabrication of the structures uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask to an upper surface of the films by photolithographic imaging, and (iii) selective etching of the films with respect to the mask.
In Ausführungsformern kann eine FIN-Struktur unter Verwendung einer Seitenwand-Bildübertragungs (side wall image transfer, SIT) -Technik gefertigt werden. Gemäß einem Beispiel einer SIT-Technik wird ein mandrel-Material, z.B. SiO2 auf dem Substrat
Mit weiterem Bezug auf
Mit weiterem Bezug auf
In
In
Mit weiterem Bezug auf
In
In
In Ausführungsformen dienen das Abstandshaltermaterial
In
Die Metallisierungsstrukturen
In Ausführungsformen kann der Lack durch einen bekannten Sauerstoffveraschungsprozess oder andere bekannte Entfernungsmittel gefolgt durch die Abscheidung des leitfähigen Materials mittels bekannter Abscheidungsprozesse, z.B. CVD-Prozesse, entfernt werden. Jedes verbleibende leitfähige Material auf der Oberfläche des Isolatormaterials
Die hierin beschriebenen Prozesse und sich ergebenen Strukturen dienen dazu, weiterhin das Gatemetall der Gatestruktur in MOL-Prozessen zu schützen. Die sich ergebenden Strukturen, insbesondere Seitenwandstrukturen, verhindern folglich Kurzschlüsse, die beim Auftreten mit Zwischenverbindungen oder anderen Verdrahtungsstrukturen der Source/Drain-Bereiche auftreten. Entsprechend erhöhen die hierin beschriebenen Prozesse und Strukturen die Ausbeute.The processes and resulting structures described herein serve to further protect the gate metal of the gate structure in MOL processes. The resulting structures, particularly sidewall structures, thus prevent short circuits that occur when occurring with interconnects or other wiring structures of the source / drain regions. Accordingly, the processes and structures described herein increase the yield.
Das/die Verfahren, das/die oben beschrieben wurde/wurden, wird/werden in der Herstellung von integrierten Schaltungschips verwendet. Die sich ergebenden integrierten Schaltungschips können durch den Hersteller in der Form von nackten Wafern (insbesondere als ein einzelner Wafer mit mehreren nicht gehausten Chips), als ein reines Die oder in gehauster Form vertrieben werden. In letzterem Fall wird der Chip in einem Einzelchipgehäuse (z.B. einem Plastikträger mit Leitungen, die in an einem Motherboard oder einem anderen Träger höherer Ordnung angebracht sind) oder in einem Mehrchipgehäuse (z.B. einem Keramikträger mit Oberflächenzwischenverbindungen und/oder vergrabenen Zwischenverbindungen) montiert. In jedem Fall wird der Chip dann mit anderen Chips, diskreten Schaltungselementen und/oder anderen signalverarbeitenden Vorrichtungen als Teil von (a) einem Zwischenprodukt, z.B. einem Motherboard, oder (b) einem Endprodukt integriert. Das Endprodukt kann ein beliebiges Produkt sein, das integrierte Schaltungschips umfasst, im Bereich von Spielzeug und anderen Low-end-Anwendungen bis zu fortschrittlichen Computerprodukten mit einer Anzeige, einer Tastatur oder anderen Eingabevorrichtungen und einem Zentralprozessor.The method (s) described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of bare wafers (especially as a single wafer with multiple non-die-cut chips), as a pure die or in a hulled form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier with leads attached to a motherboard or other higher order carrier) or in a multi-chip package (e.g., a ceramic carrier having surface interconnects and / or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate, e.g. a motherboard, or (b) an end product integrated. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with a display, keyboard or other input devices, and a central processor.
Die Beschreibung der verschiedenen Ausführungsformen der Erfindung erfolgte zur Veranschaulichung und soll nicht vollständig oder auf die hierin beschriebenen Ausführungsformen beschränkend sein. Viele Modifizierungen und Variationen sind ersichtlich und liegen im Wesen und Rahmen der beschriebenen Ausführungsformen. Die hierin verwendete Terminologie wurde ausgewählt, um die Prinzipien der Ausführungsformen, die praktische Anwendung oder technische Verbesserung gegenüber Technologien am besten zu erläutern, die auf dem Markt angefunden werden, oder um dem Laien ein Verständnis der hierin beschriebenen Ausführungsformen zu ermöglichen.The description of the various embodiments of the invention has been presented by way of illustration and is not intended to be exhaustive or limited to the embodiments described herein. Many modifications and variations are apparent and within the spirit and scope of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, the practical application or technical improvement over the technologies that have been discovered on the market, or to enable those of ordinary skill in the art to understand the embodiments described herein.
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US10811319B2 (en) * | 2018-11-29 | 2020-10-20 | Globalfoundries Inc. | Middle of line structures |
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US11107728B2 (en) * | 2019-05-22 | 2021-08-31 | International Business Machines Corporation | Interconnects with tight pitch and reduced resistance |
US11152486B2 (en) * | 2019-07-15 | 2021-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | FinFET semiconductor device having source/drain contact(s) separated by airgap spacer(s) from the gate stack(s) to reduce parasitic capacitance |
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