DE102018209052B4 - Comparator circuit - Google Patents

Abstract

Comparator circuit (1) which has an input stage for a first voltage and for a second voltage and which is configured to compare the first voltage and the second voltage and which is configured to apply a differential current based on the first voltage and the second voltage generate, the course of which follows a mathematical function, characterized in that the comparator circuit (1) is set up so that the differential current essentially has an exponential course when the differential input voltage rises, the input stage having one or more input stage transistors (M1-M4), each of which is preceded by a level shifter, which has one or more level shifter transistors (M5-M8), and the level shifter transistors (M5-M8) each have a larger area than the respectively assigned input stage transistors (M1-M4), with the comparator circuit (1) a current mirror is provided , which is set up to set a current flow in the one or more level shifters and the current mirror is set up to set a current flow for the input stage and preferably to implement a hysteresis for the input stage.

Description

The present invention relates to a comparator circuit which has an input stage for a first voltage and for a second voltage and which is configured to compare the first voltage and the second voltage, and which is configured to use one based on the first voltage and the second voltage Generate differential current, the course of which follows a mathematical function.

The present invention further relates to an application-specific integrated circuit having such a comparator circuit.

The present invention further relates to a method for comparing a first current and a second current by means of a comparator circuit, the method comprising a step of generating a differential current in the comparator circuit.

State of the art

Comparator circuits, application-specific integrated circuits and methods of the type mentioned at the beginning are known in principle from analog circuit technology in order to compare the first voltage and the second voltage with one another. A result of this voltage comparison is a digital signal at an output of the comparator circuit, which indicates which of the two voltages is higher or lower.

The comparator circuit can be used, for example, in an application-specific integrated circuit, also called ASIC, in order to compare internal operating voltages with a reference value.

Comparator circuits are known from the prior art, in which an input voltage signal each of the first voltage and the second voltage is fed to a differential amplifier of the comparator circuit. The differential amplifier is set up to convert a difference ΔU between the two input voltage signals, called differential input voltage, into a differential current ΔI. The known comparator circuit also has, for example, at least one current mirror and a Schmitt trigger. The differential current can be converted back into a voltage with the aid of the current mirror and converted by the Schmitt trigger into a digital output signal of the comparator circuit, which is provided at the output of the comparator circuit.

Conventional differential input stages generate a differential current that follows the course of the hyperbolic tangent function. The maximum differential current is thus limited by the current source that feeds it and that largely determines the total current consumption of the comparator circuit.

A characteristic of the comparator circuit is its switching time t _pd (propagation delay time), which is required to switch its output from a logical LOW or HIGH level to its complementary value when the polarity of the differential input voltage changes. This time depends on how quickly a parasitic capacitance Cpar can be recharged at a certain node of the comparator circuit and by what voltage value it has to be recharged so that the Schmitt trigger switches.

The greater the differential input voltage .DELTA.U, the faster the node can be recharged from the positive to the negative operating voltage (or vice versa) and the faster the switching process takes place. In classical architectures, in which the two input voltage signals, i.e. the first voltage and the second voltage, are fed to the differential amplifier, this effect saturates, depending on the temperature, at ΔU ≈ 3 × nkT / q ≈ 100 mV (at room temperature).

Due to component tolerances, the switching point of the comparator _{circuit is not exactly at U P} = U _N , so that in the real circuit there is a HIGH level at the output of the Schmitt trigger when U _P > U _N + U _offs and a LOW level U _P <U _N + U _offs results, where U _{offs is} the offset voltage. U _offs is typically in the micro or milli-volt range. The offset voltage of a comparator circuit is therefore another important characteristic variable. It is smaller, the better the matching of the components used (for example that of the differential input pair and that of the current mirror). In some known comparator circuits, the offset voltage U _offs is smaller, the better the matching of input stage transistors and that of current mirror transistors.

The matching of these components is better and the offset of the comparator circuit is smaller, the larger the input stage transistors and the current mirror transistors are. The larger these components are, however, the larger the parasitic transistor capacitances, in particular the parasitic capacitance Cpar at the certain node, and, associated therewith, also a longer switching time of the comparator circuit.

In classic analog circuit technology, there are various architectures for comparator circuits whose input stage is implemented with a differential input pair and whose maximum differential current for reloading the parasitic transistor capacitances is limited by the current strength of the current source feeding them.

If, instead of a symmetrical comparator circuit, an architecture analogous to a known Miller OTA (operational transconductance amplifier) is selected, the node only needs to reach the threshold voltage U _th of a certain transistor of the Miller-OTA are reloaded. The certain transistor charges the node and thus the input of the Schmitt trigger with a current _{when U P} > U _N. Correspondingly, with suitable dimensioning, this architecture can result in a shorter switchover time t _{pd, lh} from a LOW to a HIGH level compared to the symmetrical comparator circuit. When switching from HIGH to LOW level, a first power source of the Miller-OTA must remove the node from the positive operating voltage U _VDD discharged towards the negative operating voltage. It thus (together with a further current) essentially determines the switching time t _pd.hl from a HIGH to a LOW level and the current consumption of the comparator circuit.

The document US 2009/0 140 808 A1 describes a gain control loop.

The document US 6,710,654 B2 discloses an operational amplifier for high speed applications.

Disclosure of the invention

According to the invention, a comparator circuit is provided which has an input stage for a first voltage and for a second voltage and which is set up for comparing the first voltage and the second voltage, and which is set up for this based on the first voltage and the second voltage to generate a differential current, the profile of which follows a mathematical function, the comparator circuit being set up so that the differential current has an essentially exponential profile when the differential input voltage rises.

Advantages of the invention

The comparator circuit according to the invention has the advantage that, with the same offset and the same supply current, the comparator circuit has a switching time that is approximately an order of magnitude shorter than a symmetrical comparator circuit. The greater the input voltage difference between the first voltage and the second voltage, the shorter the switching time can be compared to known classical architectures whose input stage is implemented with a differential input stage. It is also advantageous that the comparator circuit according to the invention can have the same current consumption as classic architectures. The comparator circuit proposed here is superior to classical approaches in which fast switching times with low power consumption are required.

Advantageous developments of the invention are given in the subclaims and described in the description.

The comparator circuit is preferably set up so that the differential current follows a hyperbolic sine function when the differential input voltage increases. In this way, an essentially exponential profile of the differential current can be achieved in an advantageous manner with an increasing differential input voltage. Embodiments of the invention are designed to implement switching times of less than 100 ns, particularly preferably less than 70 ns, in particular with a total current consumption of approx. 1 μA. A particularly preferred switching time that can be achieved is approximately 60 ns.

It is preferred that the input stage has one or more input stage transistors, each of which is preceded by a level shifter, which has one or more level shifter transistors. The input stage preferably comprises four input stage transistors. Preferably, the Comparator circuit corresponding to four level shift transistors. The number of level shift transistors thus preferably corresponds exactly to the number of input stage transistors. Preferably, two level shift transistors are N-channel transistors. Preferably, two level shift transistors are P-channel transistors.

In some embodiments, the level shift transistors each have a larger area than the respectively assigned input stage transistors. Better matching and thus also a lower offset can be achieved in this way. A ratio of a width W to a length L of a level shifter transistor may preferably be different from a ratio of a width W to a length L of an input stage transistor.

It is preferred that a current mirror is provided in the comparator circuit. The current mirror is preferably set up to define a current flow in the one or more level shifters. The current mirror preferably comprises one or more current mirror transistors. The current mirror is preferably connected upstream of the level shifter.

The current mirror is preferably set up to define a current flow in the input stage. The current mirror is preferably connected upstream of the input stage. In some embodiments, the current mirror is set up to implement a hysteresis for the input stage. For this purpose, a coefficient δ> 1 is preferably provided in the comparator circuit, particularly preferably a coefficient δ between 1 and 1.5. Particularly preferred coefficients δ are 1.1 or 1.2. For this purpose, a current mirror transistor preferably has a larger width than a reference transistor of the comparator circuit. _{An output of the comparator circuit then preferably changes} from LOW to HIGH only when the input voltage is U _P > U _N + U _hys with U hys> 0 and / or from HIGH to LOW only when the input voltage is U _P <U _N - U _hys. Depending on the coefficient δ, the hysteresis _voltage U hys is preferably in the range between 1 and 100 mV, particularly preferably between 1 and 70 mV, again preferably between 1 and 30 mV, again preferably between 1 and 10 mV. In some embodiments, however, δ = 1, so that the current mirror does not implement any hysteresis.

Some embodiments provide that the input stage is followed by an amplifier stage which is set up to provide a recharging current for a recharging process that is greater than a current required by the amplifier stage after the recharging process. The amplifier stage preferably comprises one or more amplifier stage transistors. The amplifier stage preferably comprises a Schmitt trigger, the input of which is connected to a node that is to be reloaded in the reloading process. The comparator circuit is preferably set up to provide a very high current for a short time of the recharging process, but to require only a comparatively low current after the recharging process. This means that the node that is to be reloaded can be reloaded very quickly.

It is preferred that the comparator circuit is set up to reload the node of the comparator circuit essentially instantaneously to a negative operating voltage. It is particularly preferred that the comparator circuit, in particular the amplifier stage, is set up to discharge the node of the comparator circuit essentially instantaneously to the negative operating voltage as soon as a voltage at the node is less than a positive operating voltage by the threshold voltage of a transistor of the comparator circuit. One advantage of the embodiment proposed here is that the node can be completely and almost suddenly discharged to the negative operating voltage as soon as the node voltage at the node is less than the positive operating voltage by the threshold voltage of the transistor U _VDD is. _{This means that no static cross current} can advantageously flow near the switchover point U _P - U _N ≈ ± U hys in the Schmitt trigger, which is preferably connected downstream of the node to be discharged, as is the case with the symmetrical comparator circuit or the architecture analogous to the Miller OTA .

The comparator circuit is preferably set up to generate positive feedback that amplifies the charge reversal of the node as soon as a further voltage at a further node of the comparator circuit is greater than a further threshold voltage of a further transistor in the comparator circuit. In this way, the knot can be discharged in a very short time, like an avalanche, so to speak. The further node is preferably connected upstream of the node. A transistor is preferably interposed between the node and the further node.

It is preferred that the comparator circuit has one or more flip-flops which are set up to generate signals for controlling the input stage and / or to generate signals from which an output signal of the comparator circuit can be derived. A flip-flop (also known as flip-flop) can also be referred to as a bistable trigger stage or a bistable trigger element. The flip-flop is an electronic circuit and can assume two stable states. In this way, the flip-flop can store an amount of data of one bit for an unlimited time. It is preferred that two flip-flops are provided in the comparator circuit for this purpose. Preferred flip-flops are RS flip-flops. In this way, the input stage, in particular its input stage transistors, can be controlled and / or the output signal derived in a reliable manner. One of the flip-flops preferably has the output of the comparator circuit or is directly connected to the output of the comparator circuit. At least one of the flip-flops is preferably electrically connected on the input side to an output of the Schmitt trigger. One input of each flip-flop is particularly preferably connected to the output of the Schmitt trigger. The output of the Schmitt trigger is preferably electrically connected to a clock input of at least one of the flip-flops.

According to the invention, an application-specific integrated circuit is also made available which has the aforementioned comparator circuit.

With the same offset and the same current consumption, the ASIC can therefore be superior to known classical architectures with a differential input stage with regard to the switchover time. For the application-specific integrated circuit, there are also the possible embodiments described with regard to the comparator circuit and their advantages.

In a preferred application-specific integrated circuit, the comparator is set up as an undervoltage and / or overvoltage comparator in the standby mode of the application-specific integrated circuit. The comparator circuit proposed here is particularly suitable for low-power applications. The comparator circuit is therefore preferably provided as an undervoltage or overvoltage comparator in the standby mode of an ASIC. In embodiments, the comparator circuit can be used to compare the internal operating voltages of the ASIC with a reference value.

According to the invention, a method for comparing a first current and a second current by means of a comparator circuit is also provided, the method comprising a step of generating a differential current of the comparator circuit and the differential current essentially having an exponential profile when the differential input voltage rises.

With the same offset and the same current consumption, the method according to the invention can thus be superior to known methods that use classic architectures with a differential input stage with regard to the switchover time. Preferred method steps and their advantages result from the described possible embodiments of the comparator circuit.

Figure list

• 1 eine klassische symmetrische Komparatorschaltung nach dem Stand der Technik;
• 2 eine klassische Komparatorschaltung mit einer Architektur analog zu einem Miller-OTA nach dem Stand der Technik;
• 3 eine Ausführungsform der erfindungsgemäßen Komparatorschaltung;
• 4 ein Diagramm, dass in Abhängigkeit von der Differenzeingangsspannung einen Differenzstrom der Ausführungsform der Komparatorschaltung aus 3 gegenüber einem Differenzstrom gemäß dem Stand der Technik vergleichend darstellt;
• 5 ein Timing-Diagramm eines Umschaltvorgangs der Komparatorschaltung aus 3;
• 6 eine schematische Darstellung der Generation von digitalen Signalen in der Ausführungsform aus 3; und
• 7 einen Aufbau eines RS-Flip-Flops in der Ausführungsform aus 3.

Exemplary embodiments of the invention are explained in more detail with reference to the drawings and the following description. Show it:

• 1 a classic symmetrical comparator circuit according to the prior art;
• 2 a classic comparator circuit with an architecture analogous to a Miller OTA according to the prior art;
• 3 an embodiment of the comparator circuit according to the invention;
• 4th a diagram that, depending on the differential input voltage, a differential current of the embodiment of the comparator circuit 3 represents a comparison with a differential current according to the prior art;
• 5 a timing diagram of a switching operation of the comparator circuit 3 ;
• 6th Fig. 3 is a schematic representation of the generation of digital signals in the embodiment 3 ; and
• 7th shows a structure of an RS flip-flop in the embodiment 3 .

Embodiments of the invention

In the 1 is a classic symmetrical comparator circuit for explanation 1 shown according to the prior art. As well in 1 As well as in the following other circuit diagrams, currents I and voltages U are illustrated with arrows on the circuits in order to increase clarity in conjunction with the description.

In the classic comparator circuit shown 1 the end 1 two input voltage signals, i.e. a first voltage and a second voltage, are generated via corresponding inputs P. and N fed to a differential amplifier. The differential amplifier converts the input voltage difference into a differential current. The differential current is converted back into a voltage by means of current mirrors. A Schmitt trigger SMT1 then converts the voltage into a digital output signal for output A. In the classic comparator circuit 1 in 1 are the transistors used M ₁ - M ₈ MOS transistors. The comparator circuit 1 but can also be constructed with bipolar transistors.

The differential input voltage ΔU = U _P - U _N is, more precisely, in the circuit in 1 to the entrances P. and N applied and from the differential input pair, consisting of the two input transistors M ₁ and M ₂ , converted into a differential current ΔI = I _DS2 - I _DS1 . The current I _DS1 is via a first current mirror, which here consists of the current mirror transistors M ₃ and M ₄ consists, and a second current mirror, which here consists of the current mirror transistors M ₇ and M ₈ consists of a knot K1 dissipated to the negative operating voltage (ground). The current I _DS2 is via a third current mirror, which is made up of the current mirror transistors M ₅ and M ₆ insists on the knot K1 guided. Corresponding to the differential input voltage ΔU and the differential output resistances of the current mirror transistors M ₆ and M ₈ calls the differential current ΔI at the node K1 a voltage emerges that is all the closer to a positive operating voltage U _VDD lies, the larger U _P opposite to U _N is, or the closer it is to the negative operating voltage (ground), the smaller U _P opposite to U _N is. The tension at the knot K1 is from the Schmitt trigger SMT ₁ converted into a digital HIGH or LOW level and made available at output A if U _P > U _N or U _P <U _N.

wobei I_DS0 × (W/L) der Drain-Source-Strom ist, wenn die Gate- Source-Spannung U_GS1 beziehungsweise U_GS2 gleich der Schwellspannung U_th der Eingangstransistoren M₁ und M₂ ist (U_GS1,2 = U_th). W ist die Weite und L ist die Länge der Transistoren M₁ und M₂ . n (≈ 1,2 ... 1,5) ist eine Technologie-Konstante. $${\text{Mit U}}_{\text{P}}-{\text{U}}_{\text{N}}=\Delta \text{U}={\text{U}}_{\text{GS2}}-{\text{U}}_{\text{GS1}}$$

ergibt sich $${\text{I}}_{\text{DS2}}{\text{/I}}_{\text{DS1}}=\text{exp}\left[\Delta \text{U}/\left(\text{nkT/q}\right)\right]$$

und durch Auflösen nach I_DS1 beziehungsweise I_DS2 und Einsetzen in I_DS1 + I_DS2 = 2 × I_B erhält man $${\text{I}}_{\text{DS1}\text{,2}}=2\times {\text{I}}_{\text{B}}\times {\left\{1+\text{exp}\left[\pm \Delta \text{U}/\left(\text{nkT/q}\right)\right]\right\}}^{-1}.$$

The input transistors M ₁ and M ₂ of the differential input pair in 1 can work in weak inversion (sub-threshold region). Then there is the differential current (source and bulk of M ₁ and M ₂ connected to each other) to ΔI = I _DS2 - I _DS1 with $${\text{I.}}_{\text{SD1}\text{, 2}}={\text{I.}}_{\text{DS0}}\times \left(\text{W / L}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GS1}\text{, 2}}-{\text{U}}_{\text{th}}\right)/\left(\text{nkT / q}\right)\right],$$

where I _DS0 × (W / L) is the drain-source current when the gate-source voltage U _GS1 respectively U _GS2 equal to the threshold voltage U _th of the input transistors M ₁ and M ₂ is (U _GS1,2 = U _th ). W is the width and L is the length of the transistors M ₁ and M ₂ . n (≈ 1.2 ... 1.5) is a technology constant. $${\text{With U}}_{\text{P.}}-{\text{U}}_{\text{N}}=\Delta \text{U}={\text{U}}_{\text{GS2}}-{\text{U}}_{\text{GS1}}$$

surrendered $${\text{I.}}_{\text{DS2}}{\text{/ I}}_{\text{DS1}}=\text{exp}\left[\Delta \text{U}/\left(\text{nkT / q}\right)\right]$$

and by dissolving after I _DS1 respectively I _DS2 and inserting I _DS1 + I _DS2 = 2 × I _B is obtained $${\text{I.}}_{\text{DS1}\text{, 2}}=2\times {\text{I.}}_{\text{B.}}\times {\left\{1+\text{exp}\left[\pm \Delta \text{U}/\left(\text{nkT / q}\right)\right]\right\}}^{-1}.$$

From this one obtains with ΔI = I _DS2 - I _DS1 and with the aid of the simplifications 2 / [1 + exp (-x)] = 1 + tanh (x / 2) and tanh (-x / 2) = -tanh (x / 2 ) $$\Delta \text{I.}=2\times \text{IB}\times \text{tanh}\left[\Delta \text{U}/\left(\text{2nkT / q}\right)\right].$$

The differential current generated by the classic symmetrical comparator circuit 1 is generated, thus follows a hyperbolic tangent function according to equation (1).

As already explained at the beginning, comparator circuits are characterized by their respective switching times t _pd (propagation delay time), which are required to switch their output from a logical LOW or HIGH level to its complementary value when the polarity of the differential input voltage changes. This time depends on how fast the parasitic capacitance Cpar is at the node K1 that result from the transistor capacitances (in particular the drain-bulk and drain-gate Capacities of the current mirror transistors M ₆ and M ₈ ) and the input capacitance of the Schmitt trigger SMT ₁ results, can be reloaded and the voltage value by which it must be reloaded, so that the Schmitt trigger SMT ₁ switches.

According to equation (1), the node K1 with the parasitic capacitance Cpar with a maximum of the current 2 × I _B , which the current source, current mirror transistor M ₆ , deliver or the current sink, current mirror transistor M ₈ can be discharged, reloaded. Neglecting the switching time of the Schmitt trigger SMT ₁ and the assumption that the output A of the Schmitt trigger SMT ₁ switches from a LOW to a HIGH level when the input voltage exceeds 2/3 × U _VDD and switches from a HIGH to a LOW level _{when the input voltage falls below 1/3 × U VDD , resulting in switching times t pd for the comparator .lh} and t _pd.hl from LOW to HIGH level or from HIGH to LOW level from $${\text{t}}_{\text{pd}\text{.lh}}={\text{t}}_{\text{pd}\text{.hl}}\approx {\text{C.}}_{\text{par}}\times 2/3\times {\text{U}}_{\text{VDD}}/\left\{2\times {\text{I.}}_{\text{B.}}\times \text{tanh}\left[\Delta \text{U}/\left(\text{2nkT / q}\right)\right]\right\}.$$

The greater the differential input voltage ΔU, the faster the node can K1 from the positive to the negative operating voltage (or vice versa) and the faster the switching process takes place.

According to equation (2), this effect saturates in classical architectures such as that in 1 in which the two input voltage signals are fed to a differential amplifier, but temperature-dependent at ΔU ≈ 3 × nkT / q ≈ 100mV (at room temperature).

The switching point of the comparator circuit is due to component tolerances 1 in 1 not exactly at U _P = U _N , so that in the real circuit there is a HIGH level at the output of the Schmitt trigger at U _P > U _N + U _offs and a LOW level at U _P <U _N + U _offs , where U _{offs is} the offset voltage.

The offset voltage of a comparator circuit 1 is therefore, as already mentioned, another important characteristic variable. It is smaller, the better the matching of the components used (for example that of the differential input pair and that of the current mirror). In the case of the symmetrical comparator circuit 1 in 1 the offset voltage U _offs is the smaller, the better the matching of the input transistors M ₁ and M ₂ and that of the three current mirrors, correspondingly from the current mirror transistors M ₃ and M ₄ respectively M ₅ and M ₆ respectively M ₇ and M ₈ exist is. The matching of these components is better and the offset of the comparator circuit is smaller, the larger the transistors M ₁ until M ₈ are. However, the larger these components are, the larger the parasitic transistor capacitances, in particular the parasitic capacitance Cpar at the node K1 , and, associated with this, a longer switching time of the comparator circuit 1 according to the state of the art.

There are various architectures for comparator circuits in classic analog circuit technology 1 whose input stage is implemented with a differential input pair and whose maximum differential current for recharging the parasitic transistor capacitances _{is limited by the current intensity 2 × I B of} the current source feeding it.

Instead of the symmetrical comparator circuit 1 the end 1 According to the state of the art, an architecture analogous to a Miller OTA can be selected, which is described in 2 is illustrated.

In the in 2 comparator circuit shown 1 must be the knot K1 only up to the threshold voltage U _th of the transistor M ₅ be reloaded. The transistor M ₅ loads the node K1 in 2 and thus the input of the Schmitt trigger at U _P > U _N with the current I _DS5 = I _DSO × (W / L) × exp [(U _GS5 -Uth) / (nkT / q)] - I _B2 . Correspondingly, this in 2 Architecture shown with suitable dimensioning in comparison to the symmetrical comparator circuit 1 the end 1 result in a shorter switchover time t _pd.lh from a LOW to a HIGH level. When switching from HIGH to LOW level, the current source I _B2 must be the node K1 in 2 from the positive operating voltage U _VDD discharged towards the negative operating voltage. It determines with it (together with the power source I _B1 ) essentially the switching time t _pd.hl from a HIGH to a LOW level and the current consumption of the comparator circuit 1 .

3 now shows an embodiment according to the invention. The in 3 The circuit diagram shown serves as an exemplary guide for interconnecting components according to the embodiment of the invention.

In the 3 Comparator circuit according to the invention shown 1 has an input stage for a first voltage and for a second voltage. The comparator circuit 1 is further configured to compare the first voltage and the second voltage. The comparator circuit 1 is set up to generate a differential current based on the first voltage and the second voltage, the course of which follows a mathematical function. Ultimately is the comparator circuit 1 set up to use the differential current to determine which of the first voltage and the second voltage is greater or less and to output this result at an output. The comparator circuit according to the invention 1 is in this embodiment in an application-specific integrated circuit 2 , an ASIC. The comparator circuit 1 can, more precisely, as an undervoltage and overvoltage comparator in the standby mode of the application-specific integrated circuit 2 be set up.

In the comparator circuit 1 the end 3 the input stage comprises four input stage transistors M ₁ until M ₄ . A voltage input N is assigned to the first voltage. A voltage input P. is assigned to the second voltage. Each input stage transistor M ₁ until M ₄ is a corresponding level shift transistor M5 until M8 upstream.

In other words, as in 3 The input stage shown has a plurality of input stage transistors, each of which is preceded by a level shifter, which has a level shifter transistor. The level shifter transistor M ₅ is the input stage transistor M ₁ upstream. The level shifter transistor M ₇ is the input stage transistor M ₂ upstream. The level shifter transistor M ₆ is the input stage transistor M ₃ upstream. The level shifter transistor M ₈ is the input stage transistor M ₄ upstream. The comparator circuit 1 is designed so that the input stage transistor M ₁ and the input stage transistor M ₄ can be traversed by a current I _1. The comparator circuit 1 is designed so that the input stage transistor M ₂ and the input stage transistor M ₃ can be traversed by a current I _2.

The comparator circuit 1 has a current mirror. The current mirror has several current mirror transistors M ₉ until M ₁₃ which define both a current flow in the level shifter and a current flow in the input stage.

The level shift transistors can advantageously each have a larger area than the respectively assigned input stage transistors. More specifically, the level shift transistors M ₆ until M ₈ the level shifter have a larger area than the input stage transistors in favor of better matching and thus also in favor of a low offset M ₁ until M ₄ the entrance level. The ratio of the width W to the length L of the level shift transistors can be different from that of the input stage transistors. This is also taken into account in 3 using the coefficients α and β. The coefficients α and β scale the widths W and the lengths L of the transistors. For the input stage transistor M ₁ For example, the ratio α · W _n / L _n applies. For the input stage transistor M ₂ For example, the ratio α · W _n / L _n applies. For the input stage transistor M ₃ For example, the ratio α · W _p / L _p applies. For the input stage transistor M ₄ For example, the ratio α · W _p / L _p applies. For the level shifter transistor M ₅ For example, the ratio (β · W _n / β · L _n ) applies. For the level shifter transistor M ₆ For example, the ratio (β · W _p / β · L _p ) applies. For the level shifter transistor M ₇ For example, the ratio (ß · W _n / β · L _n ) applies. For the level shifter transistor M ₈ For example, the ratio (β · W _p / β · L _p ) applies.

und $$\Delta \text{U}={\text{U}}_{\text{P}}-{\text{U}}_{\text{N}}={\text{U}}_{\text{GS}7}+{\text{U}}_{\text{SG8}}-{\text{U}}_{\text{GS2}}-{\text{U}}_{\text{SG3}}.$$

Für ΔU = 0V gelten $${\text{U}}_{\text{GS1}}={\text{U}}_{\text{SG2}}={\text{U}}_{\text{GS5}}={\text{U}}_{\text{SG7}}={\text{U}}_{\text{GSn}}$$

beziehungsweise $${\text{U}}_{\text{GS3}}={\text{U}}_{\text{SG4}}={\text{U}}_{\text{GS6}}={\text{U}}_{\text{SG8}}={\text{U}}_{\text{SGp}}.$$

For the input stage transistors of the input stage, as in the circuit in FIG 3 illustrated with arrows, the mesh equations $$\Delta \text{U}={\text{U}}_{\text{P.}}-{\text{U}}_{\text{N}}={\text{U}}_{\text{GS1}}+{\text{U}}_{\text{SG4}}-{\text{U}}_{\text{GS5}}-{\text{U}}_{\text{SG6}}$$

and $$\Delta \text{U}={\text{U}}_{\text{P.}}-{\text{U}}_{\text{N}}={\text{U}}_{\text{GS}\mathrm{7th}}+{\text{U}}_{\text{SG8}}-{\text{U}}_{\text{GS2}}-{\text{U}}_{\text{SG3}}.$$

For ΔU = 0V apply $${\text{U}}_{\text{GS1}}={\text{U}}_{\text{SG2}}={\text{U}}_{\text{GS5}}={\text{U}}_{\text{SG7}}={\text{U}}_{\text{GSn}}$$

respectively $${\text{U}}_{\text{GS3}}={\text{U}}_{\text{SG4}}={\text{U}}_{\text{GS6}}={\text{U}}_{\text{SG8}}={\text{U}}_{\text{SGp}}.$$

beziehungsweise (3) $${\text{I}}_{\text{B}}={\text{I}}_{\text{SD0p}}\times \left({\text{W}}_{\text{p}}/{\text{L}}_{\text{p}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSp}}-{\text{U}}_{\text{thp}}\right)/\left(\text{nkT}/\text{q}\right)\right].$$

This results for the N-channel level shifter transistors through _{which the current I B flows} M ₅ and M ₇ or P-channel level shifter transistors M ₆ and M ₈ $${\text{I.}}_{\text{B.}}={\text{I.}}_{\text{DS0n}}\times \left({\text{W.}}_{\text{n}}/{\text{L.}}_{\text{n}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSn}}-{\text{U}}_{\text{thn}}\right)/\left(\text{nkT}/\text{q}\right)\right]$$

respectively (3) $${\text{I.}}_{\text{B.}}={\text{I.}}_{\text{SD0p}}\times \left({\text{W.}}_{\text{p}}/{\text{L.}}_{\text{p}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSp}}-{\text{U}}_{\text{thp}}\right)/\left(\text{nkT}/\text{q}\right)\right].$$

sodass sich die Gate-Source- beziehungsweise die Source-Gate-Spannung dieser Transistoren zu U_GS1 = U_GSN + ΔU_GSn beziehungsweise U_SG4 = U_SGp + Δ_USGp ergeben. Es gilt: $${\text{I}}_1={\text{I}}_{\text{DS0n}}\times \left(\mathrm{\alpha }{\text{W}}_{\text{n}}/{\text{L}}_{\text{n}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSn}}-{\text{U}}_{\text{thn}}+\Delta {\text{U}}_{\text{GSn}}\right)/\left(\text{nkT}/\text{q}\right)\right]$$

beziehungsweise (6) $${\text{I}}_1={\text{I}}_{\text{DS0p}}\times \left(\mathrm{\alpha }{\text{W}}_{\text{p}}/{\text{L}}_{\text{p}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSp}}-{\text{U}}_{\text{thp}}+\Delta {\text{U}}_{\text{SGp}}\right)/\left(\text{nkT}/\text{q}\right)\right].$$

For the input transistors through which _{current I 1 flows} M ₁ and M _{4 the differential input} voltage ΔU is divided into an additional gate-source voltage ΔU GSn and an additional source-gate voltage Δ _USGp $$\Delta \text{U}=\Delta {\text{U}}_{\text{GSn}}+\Delta {\text{U}}_{\text{SGp}},$$

so that the gate-source or source-gate voltage of these transistors results in U _GS1 = U _GSN + ΔU _GSn or U _SG4 = U _SGp + Δ _USGp . The following applies: $${\text{I.}}_1={\text{I.}}_{\text{DS0n}}\times \left(\mathrm{\alpha }{\text{W.}}_{\text{n}}/{\text{L.}}_{\text{n}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSn}}-{\text{U}}_{\text{thn}}+\Delta {\text{U}}_{\text{GSn}}\right)/\left(\text{nkT}/\text{q}\right)\right]$$

respectively (6) $${\text{I.}}_1={\text{I.}}_{\text{DS0p}}\times \left(\mathrm{\alpha }{\text{W.}}_{\text{p}}/{\text{L.}}_{\text{p}}\right)\times \text{exp}\left[\left({\text{U}}_{\text{GSp}}-{\text{U}}_{\text{thp}}+\Delta {\text{U}}_{\text{SGp}}\right)/\left(\text{nkT}/\text{q}\right)\right].$$

_Solving (6) and (7) for Δ UGSn or Δ _USGp and inserting into (5) gives $$\begin{array}{l}\Delta \text{U}=\left(\text{nkT / q}\right)\times \text{In}\left\{{\text{I.}}_{\text{1}}/\left[{\text{I.}}_{\text{DS0n}}\times \left(\mathrm{\alpha }{\text{W.}}_{\text{n}}{\text{/ L}}_{\text{n}}\right)\right]\right\}-\left({\text{U}}_{\text{GSn}}-{\text{U}}_{\text{thn}}\right)\\ +\left(\text{nkT / q}\right)\times \text{In}\left\{{\text{I.}}_{\text{1}}/\left[{\text{I.}}_{\text{SD0p}}\times \left(\mathrm{\alpha }{\text{W.}}_{\text{p}}{\text{/ L}}_{\text{p}}\right)\right]\right\}-\left({\text{U}}_{\text{GSp}}-{\text{U}}_{\text{thp}}\right)\end{array}$$

Solving (8) for I ₁ yields with the help of (3) and (4) $${\text{I.}}_{\text{1}}=\mathrm{\alpha }\times {\text{I.}}_{\text{B.}}\times \text{exp}\left[\Delta \text{U}/\left(\text{2nkT / q}\right)\right].$$

Analogously, one obtains for the input transistors through which _{current I 2 flows} M ₂ and M ₃ $${\text{I.}}_2=\mathrm{\alpha }\times {\text{I.}}_{\text{B.}}\times \text{exp}\left[-\Delta \text{U}/\left(\text{2nkT / q}\right)\right]$$

The currents I ₁ and I ₂ are in the embodiment of the invention 3 via the NMOS transistors working as switches M ₁₆ until M ₁₉ and the current mirror off M ₂₀ and M ₂₁ on the knot K1 guided. With the help of the coefficient δ (see also 3 ) with δ> 1 (for example δ = 1.1 or δ = 1.2) is used for the input stage of the comparator circuit 1 realized a hysteresis. For this purpose, in this exemplary embodiment, the current mirror transistor M ₂₁ the current mirror from the current mirror transistors M ₂₀ and M ₂₁ exists, a slightly larger width than the reference transistor M ₂₀ on. For the current mirror transistor M ₂₀ the ratio width to length Ws / Ls applies. For the current mirror transistor M ₂₁ the ratio width to length δ · W _S / L _S applies. This leads to the output A of the embodiment according to the invention of the comparator circuit 1 only with an input voltage of U _P > U _N + U _hys with U _hys > 0 from LOW to HIGH and only with an input voltage of U _P <U _N - U _{hys changes} from HIGH to LOW. The voltage U _hys is in the range of a few 1 to 10 mV, depending on the coefficient δ.

In the following, negated digital signals are marked with a preceding slash. In the figures, especially in 3 , on the other hand, the negated digital signals are marked by an overline.

For example, the negated digital signal of the digital signal Z described below is the digital signal / Z. If Z = HIGH or Z = LOW, / Z = LOW or / Z = HIGH. Mutatis mutandis, the same applies to the digital signals Q and S.

The gate of M ₁₄ is electrically connected to Q. The gate of M ₁₅ is electrically connected to / Q. The gates of M ₁₆ and M ₁₉ are each electrically connected with / Z. The gates of M ₁₇ and M ₁₈ are each electrically connected to Z. The gate of M ₃₀ is electrically connected to S. The gates of M ₂₃ , M ₂₆ , M ₂₉ and M ₃₁ are each electrically connected to / S. An output of a Schmitt trigger SMT ₁ is electrically connected to S and / S. The output of the Schmitt trigger SMT ₁ and S a non-gate I _{1 is} interposed.

If the digital signal Z = LOW (or / Z = HIGH), the switches are M ₁₆ and M ₁₉ closed. The switches M ₁₇ and M ₁₈ are open, the current I ₁ overflows M ₁₉ to the knot K1 and the current δ × I ₂ flows through the current mirror transistor M ₂₁ of the current mirror M ₂₀ and M ₂₁ from the knot K1 according to mass. This is caused by the current I ₂ , which over M ₁₆ through the reference transistor M ₂₀ the current mirror from the current mirror transistors M ₂₀ and M ₂₁ exists, flows. The knot K1 is then for ΔU = U _P - U _N > U _hys of the one at the node K1 resulting differential _{current I 1} - δ × I ₂ > 0 is pulled up within the time t pd.in, which is shown in 5 is illustrated.

If the digital signal Z = HIGH (or / Z = LOW), the switches are M ₁₇ and M ₁₈ closed. The switches M ₁₆ and M ₁₉ are open, the current I ₂ overflows M ₁₈ to the knot K1 and the current δ × I ₁ flows through the current mirror transistor M ₂₁ the current mirror from the current mirror transistors M ₂₀ and M ₂₁ exists, to the knot K1 according to mass. This is caused by the current I ₁ , which is over M ₁₇ through the reference transistor M ₂₀ the current mirror from the current mirror transistors M ₂₀ and M ₂₁ exists, flows. The knot K1 is then for ΔU = U _P - U _N <U _hys from the one at the node K1 resulting differential _{current I 2} - δ × I ₁ > 0 within the time t pd.in pulled up.

From (9) and (10) and δ = 1, which means that no hysteresis is caused, results for the differential current $$\Delta \text{I.}={\text{I.}}_{\text{1}}-{\text{I.}}_{\text{2}}=\mathrm{\alpha }\times {\text{I.}}_{\text{B.}}\times \left\{\text{exp}\left[\Delta \text{U /}\left(\text{2nkT / q}\right)\right]-\text{exp}\left[-\Delta \text{U}/\left(\text{2nkT / q}\right)\right]\right\}.$$

With (e ^x - e ^-x ) / 2 = sinh (x) it follows from (11) $$\Delta \text{I.}=\text{I1}-\text{I2}=2\mathrm{\alpha }\times \text{IB}\times \text{sinh}\left[\Delta \text{U /}\left(\text{2nkT / q}\right)\right].$$

The comparator circuit 1 is set up so that the differential current follows a hyperbolic sine function with increasing differential input voltage.

4th shows the course of the differential current ΔI normalized to 2 × IB for a classic input stage (dashed curve) with a differential input pair and the one proposed here and in the exemplary embodiment 3 realized input stage with α = 1 (solid curve) according to equations (1) or (12). The input stage proposed here according to the invention generates a large differential current ΔI even with a small input voltage difference ΔU. The comparator circuit 1 is like in 4th illustrated, set up so that the differential current with an increasing differential input voltage, that is to say the voltage difference between the first voltage and the second voltage, has an essentially exponential profile. A method for comparing a first current and a second current by means of a comparator circuit is thus disclosed 1 enables the method to include a step of generating a differential current in the comparator circuit 1 comprises, wherein the differential current has an exponential curve with an increasing differential input voltage essentially. The differential current ΔI of the comparator circuit according to the invention 1 follows, as already mentioned, the hyperbolic sine function. The differential current ΔI of the comparator circuit according to the invention follows in the in 3 shown embodiment more precisely the equation ΔI = 2α × IB × sinh [ΔU / (2nkT / q)], as in 4th illustrated, that is, according to equation (12) derived above.

Because the current I ₁ or I ₂ , which corresponds to equation (9) or (10), in contrast to a classic input stage, which is known from the prior art, can be a multiple of I _B , after the switching process from the current source M ₁₁ or M ₁₂ limited to the value α × γ × I _B. The PMOS transistor, which works as a switch, is used for this purpose M ₁₄ respectively M ₁₅ opened with Q = HIGH or / Q = HIGH. The current consumption of the input stage proposed here is comparable with the current consumption of a classic input stage, which is known from the prior art, _{with the same value for the current I B and α = 1.} The following must apply to the coefficients γ and δ: γ × δ> 1. In practice, values of γ × δ = 1.1 or γ × δ = 1.2 have proven effective. Larger values are possible, but without advantage, because it only has to be ensured that for ΔU> U _hys or ΔU <U hys the inequality δ × I ₁ > I ₂ or δ × I ₂ > I _{1 remains true} after the switching process and the charge transfer node from the current mirror transistor M ₂₁ of the current mirror M ₂₀ and M ₂₁ can be held down until the input conditions change to ΔU <U _hys or ΔU> U _hys .

The exemplary comparator circuit from 3 has an amplifier stage. The amplifier stage is connected downstream of the input stage. The amplifier stage is set up to provide a recharging current for a recharging process which is greater than a current required by the amplifier stage after the recharging process. For the consideration that now follows, let 3 also on the timing diagram in 5 referenced. In the timing diagram in 5 are the waveforms of the voltages U _P , U _N , U ₁ and U ₂ as well as the curves of digital signals S, Z and Q for a switching process from ΔU = U _P - U _N <0 to ΔU = U _P - U _N > 0 and back to ΔU = U _P - U _N <0, neglecting them of the offset and without hysteresis.

As in 3 shown is a knot K1 with a gate of an amplifier stage transistor M ₂₂ electrically connected to the subsequent amplifier stage. At the beginning of this consideration, a digital signal S = LOW (or / S = HIGH), so that the source connection of the transistor M ₂₂ via the transistor working as a switch M ₂₃ is connected to the negative operating voltage (ground). Is the tension U ₁ at the knot K1 greater than the threshold voltage U _th of the transistor M ₂₂ and is thereby the stream that M ₂₂ can dissipate greater than the current that the power source M ₂₄ can deliver, so pulls M ₂₂ the knot K2 downward.

As soon as the tension U ₂ at the knot K2 around the threshold voltage of M ₂₅ less than the positive operating voltage U _VDD is, begins M ₂₅ also to carry electricity. Because S = LOW (or / S = HIGH), the transistor working as a switch is also M ₂₆ closed and the source connection of the transistor M ₂₇ of the current mirror M ₂₇ and M ₂₈ is connected to ground and thus draws with the mirrored current in addition to the transistor M ₂₂ the knot K2 downward. The wider the knot K2 pulled down in this way, the greater the additional current with which M ₂₅ the knot K2 via the current mirror M ₂₇ and M ₂₈ pulls further down. There is a positive feedback that creates the knot K2 like an avalanche in a very short time, essentially instantaneously, (t _pd.amp , see 5 ) pulls down as soon as the tension U ₁ at the knot K1 greater than the threshold voltage U _th of the transistor M ₂₂ is.

The comparator circuit 1 , more precisely, its amplifier stage, is set up for the node K2 the comparator circuit 1 essentially instantaneously reloading to a negative operating voltage as soon as a voltage at the node K2 around the threshold voltage of the transistor M ₂₅ the comparator circuit 1 is less than a positive operating voltage. Also is the comparator circuit 1 set up to generate a positive feedback that reloads the node K2 amplified as soon as there is further tension on the further node K1 the comparator circuit 1 greater than the further threshold voltage of the further transistor M ₂₂ the comparator circuit 1 is.

The power source M ₂₄ is dimensioned in the exemplary embodiment so that it can deliver _{a maximum of the current I B.} In other embodiments that are not shown, the power source is M ₂₄ dimensioned so that it can only deliver _{a fraction of the current I B.} It can be interpreted very weakly because it is the knot K2 never has to reload to the positive operating voltage, but only required for this, the node K2 To hold up "gently".

The knot K2 is with the input of the Schmitt trigger SMT ₁ tied together. As soon as the tension U ₂ at the knot K2 the lower switching threshold of the Schmitt trigger U _SMT.L the output of the Schmitt trigger switches SMT ₁ with a small delay (t _pd.smt.hl) from a HIGH to a LOW level. Accordingly, the digital signal S = HIGH (or / S = LOW). The comparator circuit 1 is set up so that, as a result, the switches M ₂₃ and M ₂₆ be opened. So can M ₂₂ and M ₂₇ the knot K2 no longer pull on ground and the knot K2 is via the transistor working as a switch M ₂₉ very quickly to the positive operating voltage U _VDD drawn. In addition, the switch M ₃₀ the Input stage of the transhipment node pulled to ground. Also, the gate of the current mirror will turn off M ₂₀ and M ₂₁ over the switch M ₃₁ to the positive operating voltage U _VDD drawn. As soon as the tension U ₂ at the knot K2 now the upper switching threshold U _SMT.H of the Schmitt trigger exceeds (t _dc , see 5 ), its output switches back from a LOW to a HIGH level with a short delay (t _pd.smt.lh). Accordingly, the digital signal S = LOW (/ S = HIGH) and the amplifier stage is again at the starting point of the observation.

One advantage of the amplifier stage proposed here is that the node K1 in contrast to the amplifier stage of the comparator circuit 1 with an architecture analogous to a Miller OTA 2 both for a switchover process from a LOW to a HIGH level and for a switchover process from a HIGH to a LOW level of the comparator output A by only one threshold voltage U _th must be reloaded. The power source (in the exemplary embodiment from 3 transistor M ₂₄ ) can be designed very weakly without disadvantage, while the current source of the classical architecture (transistor M ₅ in 2 ) if the design is too weak, this is disadvantageous for the switching time and if the design is too strong, it is disadvantageous for the power consumption of the comparator circuit 1 as explained above.

Another advantage of the amplifier stage proposed here is that the amplifier stage is set up so that the node K2 due to the avalanche-like effect described above, it is essentially completely and essentially suddenly discharged to the negative operating voltage as soon as the voltage is reached U ₂ at the knot K2 once by the threshold voltage of M ₂₅ less than the positive operating voltage U _VDD is. Thus, near the switching point, which is defined as U _P - U _N ≈ ± U _hys , in the Schmitt trigger SMT ₁ that the knot K2 is connected downstream, no static cross current flow, as is the case with the symmetrical comparator 1 or the architecture analogous to a Miller OTA accordingly 2 the case is.

The switching time of the comparator circuit proposed here 1 The parasitic capacitance Cpar at the node therefore essentially results from the time that is required K1 , which is composed of the transistor capacitances, to the threshold voltage U _th from M ₂₂ reload: $${\text{t}}_{\text{pd}}\approx {\text{C.}}_{\text{par}}\times {\text{U}}_{\text{th}}/\left\{2\mathrm{\alpha }\times {\text{I.}}_{\text{B.}}\times \text{sinh}\left[\Delta \text{U /}\left(\text{2nkT / q}\right)\right]\right\}.$$

In particular, the drain-bulk and drain-gate capacitances of the transistors provide the parasitic capacitance Cpar M ₃ respectively M ₄ and M ₂₁ a contribution. The Miller capacity of M ₂₂ , the gate-source capacitance of M ₂₂ and the capacities of the switches M ₁₈ , M ₁₉ and M ₃₀ are comparatively small, since these transistors can have minimal dimensions.

Preferably by the exemplary comparator circuit 1 the end 3 Switching times of less than 100 ns, particularly preferably less than 70 ns, can be implemented. A switching time that can preferably be achieved is approximately 60 ns. For example, with a total current consumption of the comparator circuit according to the invention 1 of approx. 1 µA (IB = 250 nA), an offset voltage of approx. 3 mV (1-σ) and ΔU ≈ 3 × nkT / q ≈ 100 mV (at room temperature), switching times of approx. 60 ns can be achieved in the simulation. With a higher supply current, shorter switching times are possible. With the same supply current and the same offset, as described above, a switching time that is approximately one order of magnitude shorter is possible than with the symmetrical comparator.

Such a switching operation of the comparator circuit is described below 1 described in more detail. The comparator circuit 1 has several flip-flops which are set up to generate signals for controlling the input stage and to generate signals from which an output signal of the comparator circuit 1 can be derived. The embodiment from 3 sees two such flip-flops FF1 , FF2 before. The signals Z and / Z that the switches M ₁₆ - M ₁₉ control the input stage, as well as the signals Q and / Q, from which the output signal A of the comparator circuit 1 are derived in the embodiment according to 3 from a first flip-flop FF1 and a second flip-flop FF2 generated in 6th are shown schematically in order to generate the signals for controlling the input stage and in order to generate the signals from which an output signal of the comparator circuit can be derived. The first flip-flop FF1 and the second flip-flop FF2 are each designed as an RS flip-flop. In 6th is also a buffer B ₁ shown. The buffer B ₁ is the second flip-flop FF2 and the output A of the comparator circuit 1 interposed. In 6th A = Q always applies. Since A is the output of the comparator and the load capacity that loads output A is usually unknown, the buffer is disconnected B ₁ , also called buffer, the internal signal Q from the capacitively loaded output A, so that a load capacitance at the output A of the comparator circuit 1 cannot have any influence on the internal Q signal.

The structure of the RS flip-flop, which is shown in the comparator circuit according to 3 is provided by way of example, shows 7th .

A set input S of the first flip-flop FF1 is connected to the digital signal / Q. A reset input R of the first flip-flop FF1 is connected to the digital signal Q. A clock input C of the first flip-flop FF1 is connected to the digital signal S. An output Q of the first flip-flop FF1 generates the digital signal Z. An output / Q of the first flip-flop FF1 generates the digital signal / Z. While S = HIGH (or / S = LOW), Q = LOW or Q = HIGH leads to Z = HIGH or Z = LOW.

A set input S of the second flip-flop FF2 is connected to the digital signal Z. A reset input R of the second flip-flop FF2 is connected to the digital signal / Z. A clock input C of the second flip-flop FF2 is connected to the digital signal / S. An output Q of the second flip-flop FF2 generates the digital signal Q. An output / Q of the second flip-flop generates the digital signal / Q. While S = LOW (or / S = HIGH), Z = HIGH leads to Q = HIGH. While S = LOW (or / S = HIGH), Z = LOW leads to Q = LOW. The output Q of the second flip-flop FF2 and the output A of the comparator circuit 1 is the buffer B1 interposed, as in 6th is shown.

7th illustrates in detail the internal logic interconnection of the first flip-flop FF1 and the second flip-flop FF2 of the embodiment of the invention. There are for every flip-flop FF1 , FF2 four NAND gates are provided which are clock level controlled, namely a first NAND gate X _1, a second NAND gate X ₂ , a third NAND gate X ₃ and a fourth NAND gate X ₄ . Between the signal output / Q and the third NAND gate X ₃ is a first non-gate X ₅ switched. Between the signal output Q and the NAND gate X ₃ is the first non-gate X ₅ and a second non-gate X ₆ switched. More precisely, the set input S is connected to an A input of the first NAND gate X ₁ tied together. The reset input R is connected to a B input of the second NAND gate X ₂ tied together. The clock input C is connected to a B input of the first NAND gate X ₁ as well as with an A input of the second NAND gate X ₂ tied together. A Y output of the first NAND gate X ₁ is connected to an A input of the third NAND gate X ₃ tied together. A Y output of the second NAND gate X ₂ is connected to a B input of the fourth NAND gate X ₄ tied together. A Y output of the fourth NAND gate X ₄ is with a B input of the third NAND gate X ₃ tied together. A Y output of the third NAND gate X ₃ is both with an A input of the first non-gate X ₅ as well as with an A input of the fourth NAND gate X ₄ tied together. A Y output of the first non-gate X ₅ is both with an A input of the second non-gate X ₆ as well as connected to the output / Q. A Y output of the second non-gate X ₆ is connected to the Q output.

So it becomes a comparator circuit above 1 which has an input stage for a first voltage and for a second voltage and which is set up to compare the first voltage and the second voltage, and which is set up to generate a differential current based on the first voltage and the second voltage Course of a mathematical function follows, the comparator circuit 1 it is set up so that the differential current has an essentially exponential profile when the differential input voltage rises.

As described above, there is also an application-specific integrated circuit 2 proposed such a comparator circuit 1 having.

As described above, there is also a method for comparing a first current and a second current by means of a comparator circuit 1 proposed, the method comprising a step of generating a differential current in the comparator circuit 1 and the differential current essentially has an exponential profile when the differential input voltage rises.

Claims (8)

Comparator circuit (1) which has an input stage for a first voltage and for a second voltage and which is configured to compare the first voltage and the second voltage and which is configured to apply a differential current based on the first voltage and the second voltage generate, the course of which follows a mathematical function, characterized in that the comparator circuit (1) is set up so that the differential current with an increasing Differential input voltage essentially has an exponential curve, the input stage having one or more input stage transistors (M ₁ -M ₄ ), each of which is preceded by a level shifter, which has one or more level shifter transistors (M ₅ -M ₈ ), and the level shifter transistors (M ₅ -M ₈ ) each have a larger area than the respectively assigned input stage transistors (M ₁ -M ₄ ), a current mirror being provided in the comparator circuit (1) which is set up to define a current flow in the one or more level shifters and the current mirror is set up to define a current flow for the input stage and preferably to implement a hysteresis for the input stage. Comparator circuit (1) according to Claim 1 , wherein the comparator circuit (1) is set up so that the differential current follows a hyperbolic sine function when the differential input voltage increases. Comparator circuit (1) according to one of the preceding claims, wherein the input stage is followed by an amplifier stage which is set up to provide a recharge current for a recharging process that is greater than a current required by the amplifier stage after the recharging process. Comparator circuit (1) according to any one of the preceding claims, wherein the comparator circuit (1) is set up to reload a node (K2) of the comparator circuit (1) essentially instantaneously to a negative operating voltage as soon as a voltage at the node (K2) around the The threshold voltage of a transistor (M ₂₅ ) of the comparator circuit (1) is less than a positive operating voltage. Comparator circuit (1) according to Claim 4 , the comparator circuit (1) being set up to generate positive feedback that amplifies the charge reversal of the node (K2) as soon as a further voltage at a further node (K1) of the comparator circuit (1) is greater than a further threshold voltage of another transistor (M ₂₂ ) of the comparator circuit (1). Comparator circuit (1) according to one of the preceding claims, wherein the comparator circuit (1) has one or more flip-flops (FF1, FF2) which are set up to generate signals for controlling the input stage and / or to generate signals from which an output signal of the comparator circuit (1) can be derived. Application-specific integrated circuit (2) which has a comparator circuit (1) according to one of the Claims 1 until 6th having. Application-specific integrated circuit (2) according to Claim 7 , wherein the comparator circuit (1) is set up as an under- and / or over-voltage comparator in the standby mode of the application-specific integrated circuit (2).

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