DE102018202132A1 - Semiconductor structure with a substantially straight contact profile - Google Patents
Semiconductor structure with a substantially straight contact profile Download PDFInfo
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- DE102018202132A1 DE102018202132A1 DE102018202132.5A DE102018202132A DE102018202132A1 DE 102018202132 A1 DE102018202132 A1 DE 102018202132A1 DE 102018202132 A DE102018202132 A DE 102018202132A DE 102018202132 A1 DE102018202132 A1 DE 102018202132A1
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Abstract
Die vorliegende Erfindung betrifft Halbleiterstrukturen und insbesondere eine Halbleiterstruktur mit einem im Wesentlichen geraden Kontaktprofil und Verfahren zur Herstellung. Die Struktur umfasst ein Blockmaterial mit einer oberen oxidierten Schicht an einer Grenzfläche zu einem isolierenden Material; und eine Zwischenverbindungskontaktstruktur mit einem im Wesentlichen geraden Profil durch die oxidierte Schicht des Blockmaterials.The present invention relates to semiconductor structures, and more particularly to a semiconductor structure having a substantially straight contact profile and method of manufacture. The structure comprises a block material having an upper oxidized layer at an interface to an insulating material; and an interconnect contact structure having a substantially straight profile through the oxidized layer of the block material.
Description
GEBIET DER ERFINDUNGFIELD OF THE INVENTION
Die vorliegende Erfindung betrifft Halbleiterstrukturen und insbesondere eine Halbleiterstruktur mit einem im Wesentlichen geraden Kontaktprofil und Verfahren zur Herstellung.The present invention relates to semiconductor structures, and more particularly to a semiconductor structure having a substantially straight contact profile and method of manufacture.
HINTERGRUNDBACKGROUND
Halbleitervorrichtungen umfassen viele verschiedene Verdrahtungsschichten. Diese Verdrahtungsschichten sind in einem Zwischenebenen-Dielektrikumsmaterial gebildet und können Verdrahtungsstrukturen, Zwischenverbindungskontakte, passive Vorrichtungen und aktive Vorrichtungen umfassen. Die Zwischenverbindungskontakte werden in verschiedenen Verdrahtungsschichten von der Die bereitgestellt, um die unterschiedlichen Strukturen zu verbinden, beispielsweise unterschiedliche Verdrahtungsstrukturen usw.Semiconductor devices include many different wiring layers. These wiring layers are formed in an interlevel dielectric material and may include wiring structures, interconnect contacts, passive devices, and active devices. The interconnection contacts are provided in various wiring layers of the die to connect the different structures, for example, different wiring structures, etc.
In der Herstellung der Halbleitervorrichtungen wird typischerweise eine Haftschicht auf einer Bodenfläche des Zwischenebenen-Dielektrikumsmaterials, z.B. eines SiCOH-Vollsubstrat-Materials, über einer Verdrahtungsstruktur gebildet. Die Haftschicht weist jedoch eine von dem Zwischenebenen-Dielektrikumsmaterial verschiedene Ätzrate auf, was zu einem sich verengenden Durchkontaktierungsprofil führt. Mit anderen Worten, da sich die Ätzraten für das Zwischenebenen-Dielektrikumsmaterial und die Haftschicht unterscheiden, werden diese Materialien mit unterschiedlicher Ätzrate geätzt, was zu einem sich verengenden Profil innerhalb der Haftschicht führt. Das sich verengende Durchkontaktierungsprofil ergibt wiederrum Zwischenverbindungskontakte mit sich verengenden Profilen. Diese sich verengende Profile der Zwischenverbindungskontakte führen zu Problemen in dem elektrischen Leistungsvermögen, einschließlich einer Bildung von Poren in dem Metallmaterial, z.B. Kupfer, sowie einem Time Dependent Gate Oxide Breakdown (TDDB).In the manufacture of the semiconductor devices, an adhesive layer is typically deposited on a bottom surface of the interlevel dielectric material, e.g. SiCOH bulk substrate material formed over a wiring pattern. However, the adhesive layer has a different etch rate from the interlevel dielectric material, resulting in a narrowing via profile. In other words, as the etch rates for the interlevel dielectric material and the adhesion layer differ, these materials are etched at a different etch rate, resulting in a narrowing profile within the adhesion layer. The narrowing via profile results in turn interconnection contacts with narrowing profiles. These constricting profiles of interconnect contacts cause problems in electrical performance, including formation of pores in the metal material, e.g. Copper, as well as a Time Dependent Gate Oxide Breakdown (TDDB).
Wie auch bekannt ist, kann das Ätzen dieser verschiedenen Materialien schwer zu steuern sein, da es nicht möglich ist, die Dicke der Haftschicht beim Ätzen zu messen. Verschiedene Dicken der Haftschicht rufen unterschiedliche sich verengende Durchkontaktierungsprofile hervor.As is also known, the etching of these various materials can be difficult to control since it is not possible to measure the thickness of the adhesive layer during etching. Different thicknesses of the adhesive layer cause different narrowing via profiles.
ZUSAMMENFASSUNGSUMMARY
Eine Struktur umfasst in einem Aspekt der Erfindung: ein Blockmaterial mit einer oberen oxidierten Schicht an einer Grenzfläche zu einem isolierendem Material; und eine Zwischenverbindungskontaktstruktur mit einem im Wesentlichen geraden Profil durch die oxidierte Schicht des Blockmaterials.A structure in one aspect of the invention comprises: a block material having an upper oxidized layer at an interface to an insulating material; and an interconnect contact structure having a substantially straight profile through the oxidized layer of the block material.
Eine Struktur umfasst in einem Aspekt der Erfindung: eine Verdrahtungsschicht, die in einem Isolatormaterial gebildet ist; ein Blockmaterial mit einer oberen Oberfläche, die aus einem oxidierten Material gebildet ist; ein Zwischenebenen-Dielektrikumsmaterial direkt auf der oberen Oberfläche; und einen Kontakt, der sich zu der Verdrahtungsschicht durch das Blockmaterial, das oxidierte Material und das Zwischenebenen-Dielektrikumsmaterial erstreckt, wobei der Kontakt innerhalb des oxidierten Materials ein im Wesentlichen gerades Profil aufweist.A structure in one aspect of the invention comprises: a wiring layer formed in an insulator material; a block material having an upper surface formed of an oxidized material; an interlevel dielectric material directly on the top surface; and a contact extending to the wiring layer through the block material, the oxidized material and the interlevel dielectric material, wherein the contact within the oxidized material has a substantially straight profile.
Ein Verfahren umfasst in einem Aspekt der Erfindung: ein Bilden eines Blocklermaterials über einer Verdrahtungsstruktur; ein Oxidieren des Blockiermaterials zur Bildung einer oberen oxidierten Schicht; ein Bilden eines Zwischenebenen-Dielektrikumsmaterials über der oxidierten Schicht; ein Ätzen einer Durchkontaktierung in das Zwischenebenen-Dielektrikumsmaterial, die oxidierte Schicht und das Blockiermaterial, um die Verdrahtungsstruktur freizulegen, wobei die Durchkontaktierung durch die oxidierte Schicht ein im Wesentlichen gerades Durchkontaktierungsprofil aufweist; und ein Bilden eines Kontakts innerhalb der Durchkontaktierung, wobei der Kontakt durch die oxidierte Schicht ein im Wesentlichen gerades Profil aufweist.One method, in one aspect of the invention, comprises: forming a blocker material over a wiring structure; oxidizing the blocking material to form an upper oxidized layer; forming an interlevel dielectric material over the oxidized layer; etching a via into the interlevel dielectric material, the oxidized layer, and the blocking material to expose the wiring structure, the via through the oxidized layer having a substantially straight via profile; and forming a contact within the via, wherein the contact through the oxidized layer has a substantially straight profile.
Figurenlistelist of figures
Die vorliegende Erfindung wird in der folgenden detaillierten Beschreibung mit Bezug auf die Mehrzahl von Figuren anhand nicht beschränkender Beispiele der beispielhaften Ausführungsformen der vorliegenden Erfindung beschrieben.
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1 zeigt eine Struktur und entsprechende Herstellungsprozesse gemäß Aspekten der vorliegenden Erfindung. -
2 zeigt unter anderen Merkmalen eine Durchkontaktierung mit einem im Wesentlichen geraden Profil und entsprechende Herstellungsprozesse gemäß Aspekten der vorliegenden Erfindung. -
3 zeigt unter anderen Merkmalen einen Zwischenverbindungskontakt mit einem im Wesentlichen geraden Profil und entsprechende Herstellungsprozesse gemäß Aspekten der vorliegenden Erfindung.
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1 shows a structure and corresponding manufacturing processes in accordance with aspects of the present invention. -
2 shows, among other features, a via having a substantially straight profile and corresponding manufacturing processes in accordance with aspects of the present invention. -
3 shows, among other features, an interconnect contact having a substantially straight profile and corresponding manufacturing processes in accordance with aspects of the present invention.
DETAILLIERTE BESCHREIBUNGDETAILED DESCRIPTION
Die vorliegende Erfindung betrifft Halbleitervorrichtungen und insbesondere eine Halbleiterstruktur mit einem im Wesentlichen geraden Kontaktprofil und Verfahren zur Herstellung. Insbesondere stellt die vorliegende Erfindung ein im Wesentlichen gerades oder vertikales Zwischenverbindungskontaktprofil innerhalb eines oxidierten Films in einer Blockierschicht unterhalb eines Zwischenebenen-Dielektrikumsmaterials bereit. Unter Verwendung des oxidierten Films stellt die vorliegende Erfindung vorteilhafterweise einen besser steuerbaren Durchkontaktierungsätzprozess bereit, wobei bessere elektrische Parameterwerte des Zwischenverbindungskontakts resultieren, wie z.B. eine Verringerung von Poren und des Time Dependent Gate Oxide Breakdown (TDDB).The present invention relates to semiconductor devices, and more particularly to a semiconductor structure having a substantially straight contact profile and methods of manufacture. In particular, the present invention provides a substantially straight or vertical interconnect contact profile within an oxidized film in a blocking layer below an intermediate plane. Dielectric material ready. Advantageously, using the oxidized film, the present invention provides a more controllable via etch process, resulting in better electrical parameter values of interconnect contact, such as pore reduction and Time Dependent Gate Oxide Breakdown (TDDB).
In Ausführungsformen wird eine Sauerstoffbehandlung an einer oberen Oberfläche einer BLoK-Schicht, z.B. ein dielektrisches Isolatormaterial mit niedriger Dielektrizitätskonstante, bereitgestellt. Diese Sauerstoffbehandlung verbessert eine Steuerung der Verengung, z.B. Ätzung, an der Grenzfläche zwischen einem Zwischenebenen-Dielektrikumsmaterial und der BLoK-Schicht. Insbesondere weist eine oxidierte Schicht der BLoK-Schicht durch die Bereitstellung der Sauerstoffbehandlung eine zu der Zwischenebenen-Dielektrikumsschicht ähnliche Ätzrate auf. Das sich ergebende Durchkontaktierungsprofil wird wiederum an der Grenzfläche zwischen den zwei Materialien ein gerades oder im Wesentlichen gerades Profil aufweisen, z.B. 90° gemessen relativ zu der horizontalen Oberfläche des Dielektrikums, da die oxidierte Schicht und die Zwischenebenen-Dielektrikumsschicht ähnliche Ätzraten aufweisen. Durch die Umsetzung der hierin beschriebenen Prozesse ist es zusätzlich möglich, die Haftschicht, die auf dem Boden der Zwischenebenen-Dielektrikumsschicht gebildet wird, zu eliminieren, da diese typischerweise während des Ätzprozesses ein sich verengendes Durchkontaktierungsprofil hervorruft.In embodiments, an oxygen treatment is applied to an upper surface of a BLoK layer, e.g. a low dielectric constant dielectric insulator material. This oxygen treatment improves control of the constriction, e.g. Etching, at the interface between an interlevel dielectric material and the BLoK layer. In particular, by providing the oxygen treatment, an oxidized layer of the BLoK layer has an etch rate similar to the interlevel dielectric layer. The resulting via profile will in turn have a straight or substantially straight profile at the interface between the two materials, e.g. 90 ° measured relative to the horizontal surface of the dielectric, since the oxidized layer and the interlevel dielectric layer have similar etch rates. In addition, by implementing the processes described herein, it is possible to eliminate the adhesive layer formed on the bottom of the interlevel dielectric layer, as it typically causes a narrowing via profile during the etch process.
Die Struktur der vorliegenden Erfindung kann auf viele Arten unter Verwendung einer Vielzahl von unterschiedlichen Geräten hergestellt werden. Im Allgemeinen werden dennoch die Verfahren und Geräte eingesetzt, die zur Bildung von Strukturen mit Dimensionen im Mikrometer- und Nanometerbereich verwendet werden. Die Verfahren, insbesondere Technologien, die zur Herstellung der Struktur der vorliegenden Erfindung eingesetzt werden, wurden aus der Integrierten Schaltungs (IC) -Technologie angepasst. Beispielsweise kann die Struktur auf Wafern gebildet und in Materialfilmen realisiert werden, die durch fotolithografische Prozesse auf der Oberseite eines Wafer strukturiert werden. Insbesondere verwendet die Herstellung der Struktur drei grundsätzliche Baublöcke: (i) eine Abscheidung von dünnen Materialfilmen auf einem Substrat, (ii) ein Anwenden einer strukturierten Maske auf einer Oberseite der Filme mittels fotolithografischer Bildgebung, und (iii) ein bezüglich der Maske selektives Ätzen der Filme.The structure of the present invention can be manufactured in many ways using a variety of different devices. In general, however, the methods and devices used to form structures with dimensions in the micrometer and nanometer range are used. The methods, particularly technologies used to fabricate the structure of the present invention, have been adapted from integrated circuit (IC) technology. For example, the structure may be formed on wafers and realized in material films which are patterned by photolithographic processes on top of a wafer. In particular, fabrication of the structure utilizes three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask on top of the films by photolithographic imaging, and (iii) mask selective etching of the films Movies.
Beispielsweise wird ein Lack, der über dem Isolatormaterial
Mit weiterem Bezug auf
In Ausführungsformen wird das Blockmaterial
Die Sauerstoffbehandlung kann in einer Sauerstoffatmosphäre bereitgestellt werden. Die Sauerstoffatmosphäre kann z.B. durch O2, NO2 oder CO2 in einem Trägergas in einer CVD-Kammer bereitgestellt werden. Die Sauerstoffbehandlung kann z.B. nach Beginn des Abscheidungsprozesses unter Verwendung der gleichen CVD-Kammer bereitgestellt werden, die für den Abscheidungsprozess verwendet wird. Die Sauerstoffbehandlung kann nach Beginn oder am Ende von dem Abscheidungsprozess des Blockmaterials
Mit weiterem Bezug auf
Das/die oben beschriebene/-n Verfahren wird/werden in der Herstellung von integrierten Schaltungschips verwendet. Die sich ergebenen integrierten Schaltungschips können durch den Hersteller in der Form von unbearbeiteten Wafern (insbesondere als ein einzelner Wafer, der mehrere nicht verpackte Chips aufweist) als ein reiner Die oder in eingepackter Form vertrieben werden. In letzterem Fall ist der Chip in einem Einzelchipgehäuse (z.B. ein Plastikträger mit Leitungen, die an einem Motherboard oder einem anderen Träger höherer Ordnung befestigt sind) oder in einem Mehrchipgehäuse angebracht (z.B. ein Keramikträger mit Oberflächenzwischenverbindungen und/oder vergrabenen Zwischenverbindungen), In jedem Fall wird der Chip dann mit anderen Chips, diskreten Schaltungselementen und/oder anderen Signal-verarbeitenden Vorrichtungen als Teil eines (a) Zwischenprodukts, wie z.B. eines Motherboards, oder (b) als Teil eines Endprodukts integriert. Das Endprodukt kann ein beliebiges Produkt sein, das integrierte Schaltungschips umfasst, im Bereich von Spielzeuggeräten und anderen low-end-Geräten bis hin zu fortgeschrittenen Computerprodukten mit einer Anzeige, einer Tastatur oder anderen Eingabevorrichtung und einen Zentralprozessor.The method (s) described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in the form of raw wafers (especially as a single wafer having a plurality of unpackaged chips) as a pure die or in a packaged form. In the latter case, the chip is mounted in a single chip package (eg, a plastic carrier with leads attached to a motherboard or other higher order carrier) or in a multi-chip package (eg, a ceramic carrier having surface interconnects and / or buried interconnects), in any case For example, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an (a) intermediate, such as a motherboard, or (b) integrated as part of a final product. The final product can be any product that includes integrated circuit chips, ranging from toy and other low-end devices to advanced computer products with a display, keyboard or other input device, and a central processor.
Die Beschreibung in der verschiedenen Ausführungsform in der vorliegenden Erfindung erfolgt zu Darstellungszwecken und soll nicht vollständig oder auf die beschriebenen Ausführungsformen beschränkend sein. Es sind dem Fachmann viele Modifizierungen und Variationen ersichtlich, ohne vom Rahmen und Wesen der beschriebenen Ausführungsformen abzuweichen. Die hierin verwendete Terminologie wurde ausgewählt, um die Prinzipien der Ausführungsformen, der praktischen Anwendung oder der technischen Verbesserung gegenüber Technologien am besten zu erklären, die sich im Markt befinden, oder um anderen als dem Fachmann das Verständnis der hierin beschriebenen Ausführungsformen zu ermöglichen.The description in the various embodiments in the present invention is presented for purposes of illustration and is not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of embodiment, practice, or technical improvement over technologies that are in the marketplace, or to enable other than those skilled in the art to understand the embodiments described herein.
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US15/817,801 US20190157213A1 (en) | 2017-11-20 | 2017-11-20 | Semiconductor structure with substantially straight contact profile |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010000115A1 (en) * | 1999-09-29 | 2001-04-05 | Greco Stephen E. | Dual damascene flowable oxide insulation structure and metallic barrier |
DE10240176A1 (en) * | 2002-08-30 | 2004-04-29 | Advanced Micro Devices, Inc., Sunnyvale | A dielectric layer stack with a low dielectric constant including an etching indicator layer for use in dual damascene technology |
US20050233591A1 (en) * | 2004-03-31 | 2005-10-20 | Applied Materials, Inc. | Techniques promoting adhesion of porous low K film to underlying barrier layer |
US20110237085A1 (en) * | 2003-03-07 | 2011-09-29 | Francimar Campana Schmitt | Methods of modifying interlayer adhesion |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6593247B1 (en) | 1998-02-11 | 2003-07-15 | Applied Materials, Inc. | Method of depositing low k films using an oxidizing plasma |
US6251770B1 (en) * | 1999-06-30 | 2001-06-26 | Lam Research Corp. | Dual-damascene dielectric structures and methods for making the same |
DE10260619B4 (en) | 2002-12-23 | 2011-02-24 | Globalfoundries Inc. | Process for producing a cover layer with antireflective properties on a low-k dielectric |
US6893959B2 (en) | 2003-05-05 | 2005-05-17 | Infineon Technologies Ag | Method to form selective cap layers on metal features with narrow spaces |
JP4571785B2 (en) * | 2003-05-30 | 2010-10-27 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
US7030031B2 (en) | 2003-06-24 | 2006-04-18 | International Business Machines Corporation | Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material |
US7102232B2 (en) | 2004-04-19 | 2006-09-05 | International Business Machines Corporation | Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer |
US7223654B2 (en) * | 2005-04-15 | 2007-05-29 | International Business Machines Corporation | MIM capacitor and method of fabricating same |
US8017522B2 (en) | 2007-01-24 | 2011-09-13 | International Business Machines Corporation | Mechanically robust metal/low-κ interconnects |
JP5168273B2 (en) * | 2007-02-21 | 2013-03-21 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method thereof |
US7615482B2 (en) * | 2007-03-23 | 2009-11-10 | International Business Machines Corporation | Structure and method for porous SiCOH dielectric layers and adhesion promoting or etch stop layers having increased interfacial and mechanical strength |
US8357608B2 (en) * | 2010-08-09 | 2013-01-22 | International Business Machines Corporation | Multi component dielectric layer |
US8685867B1 (en) * | 2010-12-09 | 2014-04-01 | Novellus Systems, Inc. | Premetal dielectric integration process |
CN103187359B (en) * | 2011-12-29 | 2015-07-08 | 中芯国际集成电路制造(上海)有限公司 | Forming method of metal interconnecting wire |
TWI520351B (en) * | 2013-03-11 | 2016-02-01 | 華亞科技股份有限公司 | Stack capcaitor and manufacturing method thereof |
CN105226008B (en) * | 2014-06-27 | 2018-07-10 | 中芯国际集成电路制造(上海)有限公司 | The forming method of interconnection structure |
CN105336674B (en) * | 2014-07-28 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | Interconnection structure and forming method thereof |
US9777025B2 (en) * | 2015-03-30 | 2017-10-03 | L'Air Liquide, Société pour l'Etude et l'Exploitation des Procédés Georges Claude | Si-containing film forming precursors and methods of using the same |
US9985122B2 (en) | 2015-05-19 | 2018-05-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structures |
-
2017
- 2017-11-20 US US15/817,801 patent/US20190157213A1/en not_active Abandoned
-
2018
- 2018-01-22 TW TW107102215A patent/TW201924011A/en unknown
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- 2018-03-07 CN CN201810185273.6A patent/CN109817566A/en active Pending
-
2019
- 2019-04-04 US US16/374,969 patent/US11127683B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010000115A1 (en) * | 1999-09-29 | 2001-04-05 | Greco Stephen E. | Dual damascene flowable oxide insulation structure and metallic barrier |
DE10240176A1 (en) * | 2002-08-30 | 2004-04-29 | Advanced Micro Devices, Inc., Sunnyvale | A dielectric layer stack with a low dielectric constant including an etching indicator layer for use in dual damascene technology |
US20110237085A1 (en) * | 2003-03-07 | 2011-09-29 | Francimar Campana Schmitt | Methods of modifying interlayer adhesion |
US20050233591A1 (en) * | 2004-03-31 | 2005-10-20 | Applied Materials, Inc. | Techniques promoting adhesion of porous low K film to underlying barrier layer |
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