DE102018119804A1 - PAD ASYMMETRY COMPENSATION - Google Patents

Abstract

A modulator (100) comprising a delta-sigma modulation circuit (110) having an order greater than 1 and arranged to modulate an input signal into a pulse density modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit (120) configured to determine a relationship between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall To linearize drop transitions of the PDM signal and output a modified PDM signal, the linearized relationship being used to compensate for any offset in the PDM signal.

Description

Integrated Circuits (IC) have input / output (I / O) pads that can be physically asymmetric, resulting in an asymmetry between rise and fall times of passing signals.

7 illustrates that in a conventional delta-sigma modulator circuit, when a pulse density modulated (PDM) signal passes through an asymmetric I / O pad and is demodulated or averaged using a low pass filter (LPF), the asymmetry becomes a voltage offset of the direct current (DC) leads. E1 and E0 each represents the pulse widths of a logical 1 and a logical 0. If the PDM signal passes through a balanced I / O pad, the rise and fall times of the PDM signal are the same, and thus there is no DC voltage offset. On the other hand, if the PDM signal passes through an asymmetric I / O pad, there is a DC voltage offset that may be positive or negative depending on the type of asymmetry. More specifically, if the rise time is less than the fall time, the DC voltage offset is positive. And if the rise time is greater than the fall time, the DC voltage offset is negative. The DC voltage offset is not easily compensated.

• 1 veranschaulicht eine schematische Darstellung eines Modulators gemäß Aspekten der Offenbarung.
• 2 veranschaulicht eine Tabelle von Eingangssignalgrößen, Ausgangssignal-Bitströmen und Pulsdichten eines Delta-Sigma-Modulators (DSM) aus 1.
• 3 veranschaulicht ein Flussdiagramm eines Verfahrens, das von einer Pad-Asymmetriekompensations(PAC, Pad Asymmetric Compensation)-Schaltung gemäß Aspekten der Offenbarung durchgeführt wird.
• 4 veranschaulicht eine graphische Darstellung von Ausgangs-Bitströmen eines herkömmlichen DSM und eines DSM mit PAC-Logik gemäß Aspekten der Offenbarung.
• 5 veranschaulicht eine graphische Darstellung der Anzahl von Flanken/Übergängen im Vergleich zur Eingangsgröße für einen herkömmlichen DSM und einen DSM mit PAC-Logik gemäß Aspekten der Offenbarung.
• 6 veranschaulicht ein Flussdiagramm eines Modulationsverfahrens gemäß Aspekten der Offenbarung.
• 7 veranschaulicht einen Ausgangs-Bitstrom eines herkömmlichen DSM, der unter Verwendung eines Tiefpassfilters (LPF, Low Pass Filter) in eine analoge Spannung demoduliert wird.

Traditional approaches to achieving symmetry between rise and fall times have focused on improving the I / O pad design. Such approaches are disadvantageous in that they have longer design cycles, more complex pad designs, higher power consumption, larger area, and higher costs.

• 1 FIG. 12 illustrates a schematic of a modulator according to aspects of the disclosure. FIG.
• 2 FIG. 12 illustrates a table of input signal quantities, output signal bitstreams and pulse densities of a delta-sigma modulator (DSM) 1 ,
• 3 FIG. 12 illustrates a flowchart of a method performed by a Pad Asymmetric Compensation (PAC) circuit in accordance with aspects of the disclosure.
• 4 12 illustrates a graphical representation of output bitstreams of a conventional DSM and a DSM with PAC logic in accordance with aspects of the disclosure.
• 5 12 illustrates a plot of the number of edges versus transients for a conventional DSM and a DSM with PAC logic in accordance with aspects of the disclosure.
• 6 FIG. 12 illustrates a flowchart of a modulation method according to aspects of the disclosure. FIG.
• 7 FIG. 12 illustrates an output bitstream of a conventional DSM that is demodulated into an analog voltage using a low pass filter (LPF).

The present disclosure is directed to a modulator comprising a delta-sigma modulation circuit ( 110 ) with an order greater than 1 , and configured to modulate an input signal into a pulse density modulated (PDM) signal, and a Pad Asymmetric Compensation (PAC) circuit configured to determine a relationship between a magnitude of the input signal and a number of To linearize slope or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal and output a modified PDM signal, the linearized relationship serving to compensate for any offset in the PDM signal.

In a conventional DSM circuit having an order greater than one, there is a non-linear relationship between a size of an analog / digital input signal and a number of transitions or edges of a PDM output signal (ie, logic output) 0 to 1 and vice versa). The PAC circuit disclosed herein is designed to linearize this non-linear relationship. Using this linear relationship, the I / O pad asymmetry can be compensated by multiplying the input signal, the output PDM signal or its demodulated signal by a corresponding linear factor.

1 illustrates a schematic representation of a modulator 100 in accordance with aspects of the disclosure.

The modulator 100 includes a full-feedforward delta-sigma modulator (DSM) circuit 110 second order and pad asymmetry compensation (PAC, Pad Asymmetric Compensation) circuit 120 ,

The DSM circuit 110 may be any DSM having an order greater than one (ie, second order, third order, etc.) and designed to modulate an input signal into a pulse density modulated (PDM) signal. The order of the DSM circuit 110 is defined by their number of integrators. The DSM circuit 110 includes a subtractor 111 , an integration circuit 112 and 113 , a comparator 114 , a digital-to-digital converter (DDC, Digital-to-Digital Converter) 115 , a first multiplication factor 116 and a second multiplication factor 117 ,

The subtractor 111 is designed to receive a modified PDM signal from the DDC 115 is to subtract from the input signal and output a difference / error signal. The input signal in this example is a 16-bit input signal, although the disclosure is not limited in this regard.

The integration circuit comprises a plurality of integrators, in this case the integrator 112 the first stage and the integrator 113 the second stage. The integration circuit is adapted to receive the difference / error signal from the subtractor 111 on the integrator 112 the first stage and then on the integrator 113 to accumulate the second stage. The integrator circuit acts as LPF for the input signal. The integration circuit outputs an integration signal that is proportional to the difference / error signal for a predetermined period of time.

The comparator 114 is designed to be a summation of the integration signal and the intermediate / internal signals multiplied by the multiplication factors 116 and 117 with a certain threshold and output the PDM signal, which in this example is a one-bit signal comprising one or more logical 0s and / or 1s.

The DDC 115 is in the feedback path between an output of the PAC circuit 120 and the subtractor 111 coupled. The DDC 115 is adapted to convert the modified PDM signal from a one-bit signal back to a multi-bit signal, in this case a 16-bit signal.

The PAC circuit 120 is configured to linearize a relationship between a magnitude of the input signal and a number of rising or falling transitions / edges of the PDM signal by maximizing the number of rise or fall transitions. This linearized relationship is used to compensate for a voltage offset in the demodulated PDM signal due to I / O pad imbalance by multiplying the input signal, the PDM signal or its demodulated signal by a linear factor based on the linearized relationship. The PAC circuit 120 outputs this modified PDM signal.

The voltage offset generated after demodulation of the PDM signal is a function of the number of rising and falling edges in the PDM signal. If the output PDM signal is always a 1 is, the PDM signal will have no edges; the effect of asymmetry will be negligible in this case because there are no edges and thus no rise time and fall time asymmetries. The greater the number of edges, the greater the asymmetry effect and the greater the voltage offset.

Increasing the number of edges increases the total voltage offset after demodulation. The increase, however, makes it easier to compensate for the voltage offset. The voltage offset can be compensated for by multiplying the input signal, the PDM output signal or its demodulated signal by a linearity factor corresponding to the linear relationship.

2 illustrates a table 200 of input signal quantities, output signal bit streams, and DSM pulse densities 110 out 1 ,

The output bit streams of the DSM 110 have pulse densities based on the input signal quantities. For a full-scale input signal, the output is all logic 1s. For half a full-scale input signal, the number of logical 0's and logical 1's are the same.

Taking into account a scenario in which the full-scale value of the input signal of the DSM 110 216 (65,536), if there is an input signal of 0, there is a pulse density of 0%. If an input signal of 2 ^{14 is} present, there is a pulse density of 25%, that is 25% of the bits 1s and 75% of the bits are 0s. An input signal of 2 ¹⁴ does not mean an absolute input of 2 ^14, but 2 ¹⁴ divided by the full-scale value of 2 ¹⁶ (ie, 2 ^{14/2 16,} which ¼ or 25%). Similarly, an input signal from 2 ¹⁵ to a pulse density of 2 ^{15/2 16,} which is ½ or 50%.

3 illustrates a flowchart 300 a method that uses the Pad Asymmetry Compensation (PAC) circuit 120 according to aspects of the disclosure. 4 illustrates a graphical representation 400 of output bitstreams of a conventional DSM and the DSM 110 with the PAC circuit 120 ,

An overview is the PAC circuit 120 to establish a linear relationship between the input signal quantities and the number of rise and fall transitions / edges of the PDM output signal by maximizing the number of transitions / edges in the PDM output signal. This maximization is achieved by the PAC circuit 120 avoids two consecutive logical 1s as an output signal for an input signal that is less than a predetermined percentage of the full-scale (eg, 2 ¹⁵ , which is 50%) by replacing a current bit with a 0 (11 → 01) , Similarly, the PAC circuit avoids 120 two consecutive logical 0s as an output signal for an input signal that is greater than or equal to the predetermined percentage of the full-scale by replacing the current bit with a logical 1 (00 → 10). For example, the predetermined percentage of the full-scale may be 50%, although the disclosure is not limited in this regard.

When going through the flowchart 300 for a more detailed description, see the PAC circuit 120 at step 310 activated by setting a PAC enable bit (pac_en) to a logical 1 is set. Of course, the disclosure is not limited to this particular design; the PAC circuit 120 can be activated in any way.

If at step 320 For example, if the current value of the input signal is less than a predetermined percentage of the full-scale, the PAC flip bit (pfb), for example, becomes a logical one 1 set. On the other hand, if the current value of the input signal is greater than or equal to the predetermined percentage of the full-scale, the pfb is set to a logical 0, for example. The predetermined percentage may be 50%, although the disclosure is not limited in this respect.

At step 330 It is determined whether the PAC flip bit (pfb) is equal to both a previous bit (pb) and a current bit (cb) of the PDM signal from the DSM circuit 110 is. The current bit (cb) is stored as the previous bit (pb) for the next sample / bit generation.

If the PAC flip bit (pfb) is equal to both the previous bit (pb) and the current bit (cb) of the PDM signal from the DSM circuit 110 is (step 360 ), gives the PAC circuit 120 an inversion of the current bit ( ^cb ) (step 370 ).

On the other hand, if the PAC flip bit (pfb) is not equal to both the previous bit and the current bit of the PDM signal from the DSM circuit 110 is (step 340 ), gives the PAC circuit 120 the current bit (cb) off (step 350 ).

At step 380 can the process to step 310 to return.

The PAC circuit 120 is further configured to convert the modified PDM signal into the DSM circuit 110 so that the pulse density of the modified PDM signal does not differ from the pulse density of the unmodified PDM signal. As in 4 As shown, the conventional DSM has a PDM output having eight edges and a pulse density of 50%. The DSM circuit 110 with the PAC circuit 120 has a sixteen-edge PDM output and continues to maintain the pulse density of 50%. The pulse density is defined by a number of 1s relative to 0s. The pulse density does not vary, regardless of the order of the modulator. Only the distribution changes. For example, the bitstream could be 111000 or 101010, in each case the pulse density is the same.

5 illustrates a graphical representation 500 the number of edges / transitions compared to the input for a conventional DSM and for the DSM circuit 110 with the PAC circuit 120 in accordance with aspects of the disclosure.

Regarding the DSM circuit 110 with the PAC circuit 120 increases as the input signal size increases to half of the full-scale, the number of edges linear and then decreases linear off, like through the bend 520 displayed. This is because the PAC flip bit (pfb) controls the transition between an input signal size that is less than half the full-scale to more than or equal to half the full-scale. For a 16-bit signal, half of the full-scale is 2 ¹⁵ . For a 32-bit input signal, half of the full-scale is 2 ³¹ . The disclosure may be modified for each input signal bit width. Without the PAC circuit 120 and the PAC flip bit (pfb) there is a nonlinear voltage offset, as through the curve 510 displayed.

Again, there is a relationship between the size of the input signal and a number of transitions in the PDM signal. By establishing a linear relationship, it is possible to compensate for the I / O pad imbalances by multiplying the input signal, the PDM signal or its demodulated signal by a gain factor.

und $$\text{IM}=\left(1-\frac{\text{TS}}{\text{TP}}\text{*NFE}\right)\text{*FS}\text{, wenn IM}\ge \mathrm{0,5}*\text{FS}\text{,}$$

wobei IM die Eingangssignalgröße, NRE die Anzahl der steigenden Flanken, NFE die Anzahl der fallenden Flanken, TS die Taktperiode, TP die Beobachtungszeit und FS der Full-Scale-Wert ist.Without any I / O pad asymmetry, ie the rise and fall times of the signal are the same, the following applies: $$\text{IN THE}=\frac{\text{TS}}{\text{TP}}\text{* NRE * FS}\text{if IM}<0.5*\text{FS}.$$

and $$\text{IN THE}=\left(1-\frac{\text{TS}}{\text{TP}}\text{* NFE}\right)\text{* FS}\text{if IM}\ge 0.5*\text{FS}\text{.}$$

where IM is the input signal magnitude, NRE is the number of rising edges, NFE is the number of falling edges, TS is the clock period, TP is the observation time, and FS is the full-scale value.

und $$\text{IM}=\left(1-\frac{\text{TS}}{\text{TP}}\text{*NFE}\right)\text{*FS}\left(1+\mathrm{\Delta }\right)\text{, wenn IM}\ge \mathrm{0,5}*\text{FS}\text{, }$$

wobei Δ ein Asymmetriefaktor ist. Δ könnte positiv oder negativ sein. Falls die Beziehung zwischen IM und NRE/NFE linear gemacht wird, dann kann der Verstärkungsfaktor (1 + Δ) kompensiert werden, da Δ für die Prozessspannungstemperatur (PVT, Process Voltage Temperature) fast konstant ist.For I / O pad asymmetry, ie the rise and fall times of the signal are not equal, the following applies: $$\text{IN THE}=\frac{\text{TS}}{\text{TP}}\text{* NRE * FS}\left(1+\mathrm{\Delta }\right)\text{if IM}<0.5*\text{FS}\text{.}$$

and $$\text{IN THE}=\left(1-\frac{\text{TS}}{\text{TP}}\text{* NFE}\right)\text{* FS}\left(1+\mathrm{\Delta }\right)\text{if IM}\ge 0.5*\text{FS}\text{.}$$

where Δ is an asymmetry factor. Δ could be positive or negative. If the relationship between IM and NRE / NFE is made linear, then the gain factor (1 + Δ) can be compensated since Δ is almost constant for the process voltage temperature (PVT).

To further establish a linear relationship between the magnitudes of the input signal and the number of rising and falling edges in the PDM output signal: $$\text{Number of flaks}=\left(\text{Linear factor}\right)\left(\text{input}\right)$$

$$\text{Spannungsoffset}=\left(\text{Linearer Faktor}\right)\left(\text{Eingangssignal}\right)\left(\text{Asymmetriefaktor}\right)$$

The voltage offset produced after demodulation of the PDM output signal is a function of the number of rising and falling edges in the PDM output signal, as follows: $$\text{voltage offset}=\left(\text{Number of flanks}\right)\left(\text{asymmetry factor}\right).$$

$$\text{voltage offset}=\left(\text{Linear factor}\right)\left(\text{input}\right)\left(\text{asymmetry factor}\right)$$

The linear factor is constant. The asymmetry factor has a low dependence on the process voltage temperature (PVT, Process Voltage Temperature).

For example, if an input signal of 100 mV with a linear factor of 100 is multiplied, there are 10,000 flanks (10 ⁴ ) according to Equation 5. If the asymmetry factor is calculated as 1 nV (10 ^-9 ), according to Equation 6 there is a voltage offset of (10 ⁴ ) (10 ^-9 ) = 10 ^-5 V (10 μV). The voltage of the output signal is the expected output voltage plus the offset voltage. For an input signal from 100 It is thus assumed that the output voltage is ideally 100 mV, but there is an offset of 10 μV, so that the output voltage is 100 mV plus 10 μV. Since the linear factor is constant regardless of the input signal, the input signal can be predicted taking into account the offset voltage. If the desired output voltage is 100 mV, the input signal can then be set to approximately 99.99 mV, and with the offset voltage of 10 μV, the output voltage is 100 mV.

The training can be performed on a single IC to determine asymmetry. The IC designer can define the linear relationship and compensate for the asymmetry.

6 illustrates a flowchart 600 a modulation method according to aspects of the disclosure.

In step 610 modulates the delta-sigma modulation circuit 110 with an order greater than 1 an input to a pulse density modulated (PDM) signal.

In step 620 linearizes the Pad Asymmetry Compensation (PAC) circuit 120 a relationship between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal and outputs a modified PDM signal. The linearized relationship serves to compensate for any offset in the PDM signal.

For purposes of this discussion, the term "circuits" shall be understood to mean circuitry (s), processor (s), logic, or a combination thereof. For example, a circuit may include analog circuitry, digital circuitry, state machine logic, other structural electronic hardware, or a combination thereof.

Numerous other embodiments are also contemplated. These include embodiments that have fewer, additional and / or different components, steps, features, objects, benefits and benefits. This also includes embodiments in which the components and / or steps are arranged and / or sorted differently.

Although the foregoing has been described in connection with an exemplary embodiment, it will be understood that the term "exemplary" is meant to be exemplary only and not the best or optimal. Accordingly, the disclosure is intended to cover alternatives, modifications, and equivalents, which may be included within the scope of the disclosure.

While particular embodiments have been illustrated and described herein, those of ordinary skill in the art will understand that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. This disclosure is intended to cover any adaptations or variations of the specific embodiments discussed herein.

Claims (20)

A modulator (100) comprising: a delta sigma modulation circuit (110) having an order greater than 1 and adapted to modulate an input signal into a pulse density modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit (120) configured to determine a relationship between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions linearize the PDM signal and output a modified PDM signal, wherein the linearized relationship is for compensating for any offset in the PDM signal. Modulator (100) to Claim 1 wherein the PAC circuit (120) is adapted to return the modified PDM signal to the delta sigma modulation circuit (110) such that the pulse density of the modified PDM signal does not differ from the pulse density of the unmodified PDM signal , Modulator (100) according to one of Claims 1 or 2 wherein the PAC circuit (120) is adapted to maximize the number of rise or fall transitions of the PDM signal by: if the input signal is less than a predetermined percentage of the full-scale, replacing two consecutive 1 bits of the PDM Signal through a 0 and a 1; and if the input signal is greater than or equal to the predetermined percentage of the full-scale, replacing two consecutive 0 bits of the PDM signal with a 1 and a 0. Modulator (100) to Claim 3 , wherein the predetermined percentage is 50%. Modulator (100) according to one of Claims 1 to 4 wherein the PAC circuit (120) is adapted to maximize the number of rise or fall transitions of the PDM signal by: comparing previous and current bits of the PDM signal from the delta-sigma modulation circuit (110); if the input signal is less than a predetermined percentage of the full-scale and if the previous and current bits of the PDM signal are both 1, replacing the current bit with a 0; and if the input signal is greater than or equal to the predetermined percentage of the full-scale and if the previous and current bits of the PDM signal are both 0, replacing the current bit with a 1. Modulator (100) to Claim 5 , wherein the predetermined percentage is 50%. Modulator (100) according to one of Claims 1 to 6 wherein the PAC circuit (120) is adapted to maximize the number of rise or fall transitions of the PDM signal by: setting a PAC flip bit to 1 if the input signal is less than a predetermined percentage of the full-scale is and 0 if the input signal is greater than or equal to the predetermined percentage of the full-scale; Determining whether the PAC flip bit is equal to a previous bit and a current bit of the PDM signal from the delta sigma modulation circuit (110); if the PAC flip bit is equal to both the previous bit and the current bit of the PDM signal from the delta sigma modulation circuit (110), outputting an inversion of the current bit; and if the PAC flip bit is neither equal to the previous bit nor the current bit of the PDM signal from the delta sigma modulation circuit (110), outputting the current bit. Modulator (100) to Claim 7 , wherein the predetermined percentage is 50%. Modulator (100) according to one of Claims 1 to 8th wherein the delta-sigma modulation circuit (110) comprises: a subtractor (111) arranged to subtract the modified PDM signal from the input signal and output a difference or error signal; an integration circuit comprising a plurality of integrators (112, 113) and configured to output an integration signal proportional to the subtraction signal for a predetermined period of time; and a comparator (114) configured to compare the integration signal to a threshold and to output the PDM signal. Modulator (100) according to one of Claims 1 to 9 wherein the delta-sigma modulation circuit (110) further comprises: a digital-to-digital converter (115) coupled between the comparator (114) and the subtractor (111) and adapted to receive the PDM signal from an on To convert the bit signal into a multi-bit signal. Modulator (100) according to one of Claims 1 to 10 wherein each offset in the PDM signal is compensated by multiplying the input signal by a linearity factor based on the linearized relationship. Modulator (100) according to one of Claims 1 to 11 wherein each offset in the PDM signal is compensated by multiplying the PDM signal or its demodulated signal by a linearity factor based on the linearized relationship. A modulation method, comprising: modulating, by a delta-sigma modulation circuit (110) having an order greater than 1, an input signal into a pulse density modulated (PDM) signal; and linearizing, by a Pad Asymmetry Compensation (PAC) circuit (120), a relationship between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal PDM signal and outputting a modified PDM signal, wherein the linearized relationship for compensating for any offset in the PDM signal is used. Modulation method according to Claim 13 , further comprising: returning, from an output of the PAC circuit (120), the modified PDM signal to the delta-sigma modulation circuit (110) so that the pulse density of the modified PDM signal does not differ from the pulse density of the unmodified PDM Signal is different. Modulation method according to one of Claims 13 or 14 , further comprising: maximizing, by the PAC circuit (120), the number of rise or fall transitions of the PDM signal by: if the input signal is less than a predetermined percentage of the full-scale, replacing two consecutive 1 bits of the PDM Signal through a 0 and a 1; and if the input signal is greater than or equal to the predetermined percentage of the full-scale, replacing two consecutive 0 bits of the PDM signal with a 1 and a 0. Modulation method according to one of Claims 13 to 15 , further comprising: maximizing, by the PAC circuit (120), the number of rise or fall transitions of the PDM signal by: comparing previous and current bits of the PDM signal from the delta-sigma modulation circuit (110); if the input signal is less than a predetermined percentage of the full-scale and if the previous and current bits of the PDM signal are both 1, replacing the current bit with a 0; and if the input signal is greater than or equal to the predetermined percentage of the full-scale and if the previous and current bits of the PDM signal are both 0, replacing the current bit with a 1. Modulation method according to one of Claims 13 to 16 , further comprising: maximizing, by the PAC circuit (120), the number of rise or fall transitions of the PDM signal by: setting a PAC flip bit to 1 if the input signal is less than a predetermined percentage of the full-scale is and 0 if the input signal is greater than or equal to the predetermined percentage of the full-scale; Determining whether the PAC flip bit is equal to a previous bit and a current bit of the PDM signal from the delta sigma modulation circuit (110); if the PAC flip bit is equal to both the previous bit and the current bit of the PDM signal from the delta sigma modulation circuit (110), outputting an inversion of the current bit; and if the PAC flip bit is neither equal to the previous bit nor the current bit of the PDM signal from the delta sigma modulation circuit (110), outputting the current bit. Modulation method according to one of Claims 13 to 17 wherein the modulating comprises: subtracting, by a subtractor (111), the modified PDM signal from the input signal and outputting a difference or error signal; Generating, by an integrator circuit comprising a plurality of integrators (112, 113), an integration signal proportional to the subtraction signal over a predetermined period of time; and comparing, by a comparator (114), the integration signal with a threshold and outputting the PDM signal. Modulation method according to one of Claims 13 to 18 wherein the modulating comprises: converting, by a digital-to-digital converter (115) coupled between the comparator (114) and the subtractor (111), the PDM signal from a one-bit signal to a multi-bit signal. bit signal. Modulation method according to one of Claims 13 to 19 , further comprising: Compensating any offset in the PDM signal by multiplying the input signal or the PDM signal or its demodulated signal by a linearity factor based on the linearized relationship.

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