DE102018200229A1 - Integration circuit, current sensor and circuit breaker - Google Patents

Abstract

The invention discloses an integration circuit, a current sensor and a circuit breaker. In this case, the integration circuit comprises: a first circuit module, which is designed to obtain a first integration signal such that the signals of secondary voltage outputs of a Rogowski coil are integrated analogously; a second circuit module configured to obtain a second integration signal such that the first integration signals are analog-integrated; and a combination module configured to obtain a combined integration signal such that the first integration signal and the second integration signal are additively combined with each other. The technical solution in the embodiments of the present invention can not only exploit original metrological advantages of the circuit modules, but also their functions can complement each other to increase the accuracy of the restoration of integration in the entire integration component.

Description

Technical area

The invention relates to the field of circuits, in particular an integration circuit, a current sensor and a circuit breaker.

State of the art

Currently, Rogowski coils are typically used in current sensors for measuring a large current. The Rogowski coil has a wide frequency range, usually a designed range of 0.1 Hz to more than 100 MHz, and therefore can meet the general requirements for measurement at wide frequencies. However, the secondary signal of the voltage output of a Rogowski coil is the differential of the primary current signal, and the addition of a corresponding integration circuit is necessary to effect the faithful restoration of the signal proportional to the primary current. The primary current is the current in the main circuit of the system to be measured and the secondary output voltage signal is the voltage in the measuring circuit in which the Rogowski coil is located.

Usually, a passive integration circuit is used to recover the integration signal because it has excellent stability. However, there is a cutoff frequency f _L for the integration circuit. If the signal frequency through the integration circuit is lower than the cut-off frequency f _L , the amplitude of the signal is significantly weakened.

wobei M der Koeffizient der Gegeninduktion der Rogowski-Spule und I(t) der Wert des primären Stroms ist. R ist der Integrationswiderstand des passiven Integrationsschaltkreises und C die Integrationskapazität des passiven Integrationsschaltkreises.The output V _from a passive integration circuit can be simplified as in the following equation (1): $$V_{aus}\approx \frac{M}{R\cdot C}\cdot I\left(t\right)$$

where M is the mutual inductance coefficient of the Rogowski coil and I (t) is the value of the primary current. R is the integration resistance of the passive integration circuit and C is the integration capacity of the passive integration circuit.

wobei λ ein empirischer Koeffizient ist, bei dem sich die Genauigkeit der Integration im einem akzeptablen Umfang befindet. Wie z. B. λ=5, oder zur Vereinfachung der Gleichung (2) wird λ=6.28 eingestellt.In addition, in order to obtain a good integration result, the following equation (2) holds for the cut-off frequency f _{L of} a conventional passive integration circuit: $$R\cdot C>\frac{\mathrm{<figure-callout\; id="2"\; label="\lambda "\; filenames="DE102018200229A1\_0017.png"\; state="\{\{state\}\}">\lambda </figure-callout>}}{2\pi \cdot f_L}$$

where λ is an empirical coefficient in which the accuracy of the integration is within an acceptable level. Such as B. λ = 5, or to simplify the equation (2) λ = 6.28 is set.

It can be seen from equation (1) that the amount RC should not be too large, otherwise the output of the integration circuit will be reduced. It can also be seen from the equation (2) that due to the not too large amount RC, the amount f _L can not be too small. Normally, the amount f _{L is} about 30 Hz. Thus, the application scenarios of the passive integrator circuit are constrained because the frequency of the existing large current may be quite small in certain application scenarios, such as e.g. 10 Hz or even as low as a few Hz (eg, in a wind turbine), in which case the correct measurement of the primary current will be negative due to the necessarily strong attenuation of the secondary voltage signal output from the Rogowski coil via the existing passive integration circuit being affected.

Disclosure of the invention

In this regard, in one aspect, the present invention proposes an integration circuit that can increase the accuracy of integration. In another aspect, a current sensor and a circuit breaker are proposed to increase the sensing range of the current sensor and thereby achieve measurement of the current in a variety of application scenarios.

The present invention provides an integration circuit comprising: a first circuit module configured to receive a first integration signal such that the signals from secondary voltage outputs of a Rogowski coil are analogously integrated; a second circuit module configured to obtain a second integration signal such that the first integration signals are analog-integrated; and a combination module configured to obtain a combined integration signal such that the first integration signal and the second integration signal are additively combined with each other. Not only can the integration component exploit the original metrological benefits of the circuit modules, but its functions can complement each other to increase the accuracy of restoring integration throughout the integration component.

In one embodiment, the first circuit module is a passive analog integration circuit; a first cut-off frequency f _{L1 of} the first circuit module is greater than a set cut-off frequency f _{L of} the integration circuit; the second circuit module is an active analog integration circuit; and a second cutoff frequency f _{L2 of} the second circuit module is less than or equal to a set cutoff frequency f _{L of} the integration circuit. By setting a larger cut-off frequency for the passive analog-to-logic circuit and a smaller cut-off frequency for the active analog-to-logic integrated circuit, the characteristics of the passive and active analog-to-logic integrated circuits can be exploited. On the one hand, the stability of the passive analog-integrating circuit is used at the high frequencies, and on the other hand, the accuracy of the output of the active analog-integrating circuit at the low frequencies is used.

wobei f_L die Sollgrenzfrequenz des Integrationsschaltkreises, M der Koeffizient der Gegeninduktion der Rogowski-Spule, I_min das Minimum des primären Stroms, V1_erfassbar der geringste von dem passiven Analog-Integrationsschaltkreis erfassbare Spannungswert und λ ein eingestellter empirischer Koeffizient ist. In dieser Ausführungsform wird eine ausführliche Strategie für die Ausgestaltung eines passiven Analog-Integrationsschaltkreises bereitgestellt, welche einfach ausgeführt werden kann.In one embodiment, the amounts of an integration resistance R and an integration capacitor C of the analog-to-analogue passive circuit are determined by the following equation: $\frac{\mathrm{\lambda }}{2\pi \cdot f_L}>R\cdot C\ge \frac{M\cdot I_{\text{min}}}{V{1}_{erfassbar}};$

where f _{L is} the desired cut-off frequency of the integration circuit, M I is the coefficient of mutual induction of the Rogowski coil, _{min is} the minimum of the primary current, V1 _detected the least detectable by the passive analog integration circuit voltage value and λ a set of empirical coefficient. In this embodiment, a detailed strategy for the design of a passive analog-integrating circuit is provided which can be easily implemented.

In an embodiment, the passive analog integration circuit comprises: a first integration resistor, a second integration resistor, a first filter resistor, a second filter resistor, and a first integration capacitor; wherein the one end of the first integration resistor is connected to the one output of the Rogowski coil and the other end is connected to the one end of the first filter resistor and to the one end of the first integration capacitor; one end of the second integration resistor is connected to the other output of the Rogowski coil and the other end is connected to one end of the second filter resistor and to the other end of the first integration capacitor; the other end of the first filter resistor is grounded; the other end of the second filter resistor is grounded; and the two ends of the first integration capacitor are the outputs of the analog-to-analogue passive circuit. In this embodiment, a detailed measure is provided for the configuration of a passive analog-integrating circuit, which can be easily performed.

und wenn die Signalfrequenz f sich im Bereich [f_L2, f_L1] befindet, gilt für die Ausgabe V_aus2 des aktiven Analog-Integrationsschaltkreises die folgende Gleichung: $V_{aus2}\approx \frac{k\cdot V_{aus1}}{R_i\cdot C_i}\ge V{2}_{erfassbar};$

wobei V_{aus I} die Ausgabe des passiven Analog-Integrationsschaltkreises, k der Verstärkungskoeffizient, V2_erfassbar der geringste von dem aktiven Analog-Integrationsschaltkreis erfassbare Spannungswert und λ ein eingestellter empirischer Koeffizient ist. In dieser Ausführungsform wird eine ausführliche Strategie für die Ausgestaltung eines aktiven Analog-Integrationsschaltkreises bereitgestellt, welche einfach ausgeführt werden kann.In one embodiment, the amounts of the integration resistance R _i , the integration capacitor C _i, and the lossy integration resistance R _{0 of} the analog-to-analog integrated circuit connected in parallel with the integration capacitor C _{i are} determined by the following equation: ${\mathrm{<figure-callout\; id="0"\; label="R"\; filenames="DE102018200229A1\_0017.png,DE102018200229A1\_0018.png"\; state="\{\{state\}\}">R</figure-callout>}}_0\cdot C_i\ge \frac{\mathrm{<figure-callout\; id="2"\; label="\lambda "\; filenames="DE102018200229A1\_0017.png"\; state="\{\{state\}\}">\lambda </figure-callout>}}{2\pi \cdot f_L}.$

and when the signal frequency f is in the range [f _L2 , f _L1 ], the following equation applies to the output V _{aus2 of} the active analog-integration circuit: $V_{\mathrm{<figure-callout\; id="2"\; label="a\; u\; s"\; filenames="DE102018200229A1\_0017.png"\; state="\{\{state\}\}">a\; </figure-callout>}us2}\approx \frac{k\cdot V_{aus1}}{R_i\cdot C_i}\ge V{2}_{erfassbar};$

where V _{of I is} the output of the passive analog-to-logic circuit, k the gain coefficient, V2 _detectable, the lowest voltage value detectable by the active analog-to-logic circuit, and λ is a set empirical coefficient. In this embodiment, a detailed strategy for the design of an analog-to-analogue active circuit is provided which can be easily implemented.

In an embodiment, the active analog integration circuit comprises: a third integration resistor, a second integration capacitor, a lossy integration resistor, an operational amplifier, a third filter resistor, and a fourth filter resistor; with one end the third integration resistor serves as an input of the analog-to-analogue integrated circuit and the other end is connected to an opposite-phase input of the operational amplifier; one end of the second integration capacitor is connected to an opposite-phase input of the operational amplifier and the other end is connected to an output of the operational amplifier; the lossy integration resistor is connected in parallel with the second integration capacitor; one end of the third filter resistor is connected to an in-phase input of the operational amplifier, and the other end is grounded; the one end of the fourth filter resistor is connected to an output of the operational amplifier, and the other end is grounded. In this embodiment, a detailed measure is provided for the configuration of an active analog integration circuit which can be easily implemented.

In one embodiment, the integration circuit further comprises: a signal conditioning circuit configured to perform processings of the first integration signal output from the first circuit module, including amplification and / or filtering, and transmit the processed first integration signal to the second circuit module. In this embodiment, by adding the signal conditioning circuit, the accuracy of the signal input to the active analog integration circuit can be further increased, whereby the accuracy of the signal processing by the integration circuit can be improved.

In an embodiment, the signal conditioning circuit comprises: an operational amplifier chip, a gain resistor, and a power supply circuit; wherein two signal inputs of the operational amplification chip are respectively connected to the two outputs of the first circuit module; two voltage inputs of the operational amplification chip are respectively connected to the power supply of the power supply circuit; two amplification resistor terminals of the operational amplification chip are respectively connected to two ends of the amplification resistor; and a signal output of the operational amplification chip is connected to an input of the second circuit module. In this embodiment, a detailed measure is provided for the configuration of the signal conditioning circuit, which can be easily implemented.

wobei M der Koeffizient der Gegeninduktion der Rogowski-Spule, R der Integrationswiderstand des passiven Analog-Integrationsschaltkreises, C die Integrationskapazität des passiven Analog-Integrationsschaltkreises, V_{aus I}(t) die Ausgabe des passiven Analog-Integrationsschaltkreises, R_i der Integrationswiderstand des aktiven Analog-Integrationsschaltkreises, C_i die Integrationskapazität des aktiven Analog-Integrationsschaltkreises, V_{aus 2} (t) die Ausgabe des aktiven Analog-Integrationsschaltkreises, k ein Verstärkungskoeffizient, und I(t) das kombinierte Integrationssignal, d. h. das Stromsignal nach der Wiederherstellung der Integration mittels des Integrationsschaltkreises, ist. In dieser Ausführungsform wird eine ausführliche Strategie für die Ausgestaltung eines Kombinationsmoduls bereitgestellt, welche einfach ausgeführt werden kann.In one embodiment, the combination module in such a way combines the first integration signal and the second integration signal with each other additively: $I\left(t\right)\approx -\frac{1}{M}\left(R\cdot C\cdot V_{aus1}\left(t\right)-R_i\cdot C_i\cdot \frac{V_{aus2}\left(t\right)}{k}\right);$

where M is the coefficient of mutual induction of the Rogowski coil, R is the integration resistor of the passive analog integration circuit, C is the integration capacitance of the passive analog integration circuit V _{of I} (t) is the output of the passive analog integration circuit, R _i of the integration resistance of the active analog -Integrationsschaltkreises, C _i the integration capacity of the active analog integration circuit, V ₂ (t) the output of the active analog integration circuit, k is a gain coefficient, and I (t), the combined integration signal, that the current signal after the restoration of the integration by means of the Integration circuit is. In this embodiment, a detailed strategy for the design of a combination module is provided, which can be easily performed.

In one embodiment, the combination module is an op-amp based on the op-amp or a digital-sampled digital adder. Regardless of whether an addition circuit or a digital adder is used, the functions of the combination module can be implemented flexibly.

In the embodiments, a current sensor is proposed which comprises an integration circuit according to one of the aforementioned embodiments, and accordingly, the current sensor according to the invention can have a higher measurement accuracy and a larger measurement range.

In the exemplary embodiments, a circuit breaker is proposed which comprises an aforementioned current sensor, and accordingly the inventive protective sensor can have a higher measuring accuracy and a larger measuring range.

list of figures

• 1 zeigt eine schematische Strukturansicht des Integrationsschaltkreises in einem Ausführungsbeispiel der vorliegenden Erfindung.
• 2 zeigt eine schematische partielle Strukturansicht des Integrationsschaltkreises in einem Beispiel der vorliegenden Erfindung.
• 3 zeigt eine schematische Ansicht der Verbindung zwischen einem äquivalenten Schaltkreis zur Rogowski-Spule in einem Beispiel der Erfindung und dem passiven Analog-Integrationsmodul aus 2.
• 4A zeigt das Vergleichsergebnis der Integration mit einem Eingangssignal bei 50 Hz zwischen dem erfindungsgemäßen Integrationsschaltkreis und dem allein eingesetzten, passiven Analog-Integrationsschaltkreis im Stand der Technik.
• 4B zeigt das Vergleichsergebnis der Integration mit einem Eingangssignal bei 10 Hz zwischen dem erfindungsgemäßen Integrationsschaltkreis und dem allein eingesetzten, passiven Analog-Integrationsschaltkreis im Stand der Technik.
• 4C zeigt das Vergleichsergebnis der Integration mit einem Eingangssignal bei 1 Hz zwischen dem erfindungsgemäßen Integrationsschaltkreis und dem allein eingesetzten, passiven Analog-Integrationsschaltkreis im Stand der Technik.

In the following, the preferred embodiments of the present invention will be described in detail with reference to the figures, so that the above-described and other features and advantages of the invention will become more apparent to those skilled in the art.

• 1 shows a schematic structural view of the integration circuit in an embodiment of the present invention.
• 2 shows a schematic partial structural view of the integration circuit in an example of the present invention.
• 3 Figure 12 shows a schematic view of the connection between an equivalent circuit to the Rogowski coil in an example of the invention and the passive analog integration module 2 ,
• 4A shows the comparison result of integration with an input signal at 50 Hz between the inventive integration circuit and the stand alone passive analog-integrating circuit in the prior art.
• 4B shows the comparison result of integration with an input signal at 10 Hz between the inventive integration circuit and the stand alone passive analog-integrating circuit in the prior art.
• 4C shows the comparison result of the integration with an input signal at 1 Hz between the inventive integration circuit and the sole used, passive analog-integration circuit in the prior art.

LIST OF REFERENCE NUMBERS

reference numeral importance 11 first circuit module 12 second circuit module 13 Combo module 14 Signal conditioning circuit R1 - R9 resistors L1, L2 inductor C1 - C4 capacitors U2 Operational amplifying chip U3 operational amplifiers V _a input voltage V _off1 V _off2 output voltage

Detailed description of preferred embodiments

In order to make clear the objects, technical solutions and advantages of the invention, the invention will be described in more detail with reference to the embodiments.

In order to increase the accuracy of integration integration restoration in the integration circuit, in the embodiments of the invention, a novel integration circuit is proposed which measures the stability of the passive analog integration circuit in the measurement and the good characteristics of the analog active integration circuit at low frequencies of the input signal exploit in the art.

1 shows a schematic structural view of the integration circuit in an embodiment of the present invention. As 1 1, the integration circuit mainly comprises: a first circuit module 11 , a second circuit module 12 , and a combination module 13 ,

The first circuit module 11 is designed to obtain a first integration signal such that the signals of secondary voltage outputs of a Rogowski coil are integrated analogously.

The second circuit module 12 is designed to obtain a second integration signal such that the first integration signals are integrated analogously.

The combination module 13 is designed to obtain a combined integration signal such that the first integration signal and the second integration signal are combined with each other additively.

In the internship, the first circuit module 11 as a passive analog integration circuit and the second circuit module 12 be formed as an active analog-integration circuit; and vice versa, the first circuit module 11 as an active analog integration circuit and the second circuit module 12 be designed as a passive analog-integration circuit. The concrete design can be realized as needed.

Hereinafter, the integration circuit will be described in detail in this embodiment, in which the first circuit module 11 as a passive analog integration circuit and the second circuit module 12 is formed as an active analog-integration circuit.

wobei M der Koeffizient der Gegeninduktion der Rogowski-Spule, I_min das Minimum des primären Stroms, V1_erfassbar der geringste von dem passiven Analog-Integrationsschaltkreis erfassbare Spannungswert und λ ein eingestellter empirischer Koeffizient ist. In diesem Ausführungsbeispiel gilt z. B. λ = 6.28.Because the first circuit module 11 In this embodiment, it is designed as a passive analog-integration circuit, its limit frequency f _L1 may be greater than the desired limit frequency f _{L of} the integration circuit, so f _L1 > f _L. The amounts of the integration resistance R and the integration capacitor C of the first circuit module are determined by the following equation (3): $$\frac{\mathrm{<figure-callout\; id="2"\; label="\lambda "\; filenames="DE102018200229A1\_0017.png"\; state="\{\{state\}\}">\lambda </figure-callout>}}{2\pi \cdot f_L}>R\cdot C\ge \frac{M\cdot I_{\text{min}}}{V{1}_{erfassbar}}$$

where M is the mutual inductance coefficient of the Rogowski coil, I _{min is} the minimum of the primary current, V1 is _detectable, the lowest voltage value _detectable by the passive analog-to-logic circuit, and λ is an adjusted empirical coefficient. In this embodiment, for. B. λ = 6.28.

und wenn die Signalfrequenz f sich im Bereich [f_L2, f_L1] befindet, gilt für die Ausgabe V_{aus 2} des aktiven Analog-Integrationsschaltkreises die folgende Gleichung (5): $$V_{aus2}\approx \frac{k\cdot V_{aus1}}{R_i\cdot C_i}\ge V{2}_{erfassbar}$$

wobei V_{aus 1} die Ausgabe des passiven Analog-Integrationsschaltkreises, k der Verstärkungskoeffizient, und V2_erfassbar der geringste von dem aktiven Analog-Integrationsschaltkreis erfassbare Spannungswert ist. In der Gleichung (4) kann auch z. B. λ=6.28 gelten.Because the second circuit module 12 is formed as an active analog-integration circuit, its cut-off frequency f _L2 may be less than or equal to the desired limit frequency f _{L of} the integration circuit, so f _L2 ≤f _L , be. The amounts of the integration resistance R _i , the integration capacitor C _i , and the lossy integration resistance R _{0 of} the second circuit module connected in parallel with the integration capacitor C _i are determined by the following equation (4): $${\mathrm{<figure-callout\; id="0"\; label="R"\; filenames="DE102018200229A1\_0017.png,DE102018200229A1\_0018.png"\; state="\{\{state\}\}">R</figure-callout>}}_0\cdot C_i\ge \frac{\mathrm{<figure-callout\; id="2"\; label="\lambda "\; filenames="DE102018200229A1\_0017.png"\; state="\{\{state\}\}">\lambda </figure-callout>}}{2\pi \cdot f_L}$$

and when the signal frequency f is in the range [f _L2 , f _L1 ], the following equation (5) holds for the output V _{of FIG. 2 of} the analog-to-analogue active circuit: $$V_{a\mathrm{<figure-callout\; id="2"\; label="u\; s"\; filenames="DE102018200229A1\_0017.png"\; state="\{\{state\}\}">u\; </figure-callout>}s2}\approx \frac{k\cdot V_{aus1}}{R_i\cdot C_i}\ge V{2}_{erfassbar}$$

where V _{of FIG. 1 is} the output of the passive analog-integrating circuit, k is the gain coefficient, and V2 is _detectably the lowest voltage detectable by the active analog-to-logic circuit. In the equation (4) can also z. B. λ = 6.28 apply.

wobei M der Koeffizient der Gegeninduktion der Rogowski-Spule, R der Integrationswiderstand des passiven Analog-Integrationsschaltkreises, C die Integrationskapazität des passiven Analog-Integrationsschaltkreises, V_{aus 1}(t) die Ausgabe des passiven Analog-Integrationsschaltkreises, R_i der Integrationswiderstand des aktiven Analog-Integrationsschaltkreises, C_i die Integrationskapazität des aktiven Analog-Integrationsschaltkreises, V_aus1(t) die Ausgabe des aktiven Analog-Integrationsschaltkreises, k ein Verstärkungskoeffizient, und I(t) das kombinierte Integrationssignal, d. h. das Stromsignal nach der Wiederherstellung der Integration mittels des Integrationsschaltkreises, ist.The combination module 13 Combined with the following equation (6), the first integration signal and the second integration signal are additive with each other: $$I\left(t\right)\approx -\frac{1}{M}\left(R\cdot C\cdot V_{aus1}\left(t\right)-R_i\cdot C_i\cdot \frac{V_{aus2}\left(t\right)}{k}\right)$$

where M is the mutual inductance of the Rogowski coil, R is the integration resistance of the analog-to-analog passive circuit, C is the integration capacity of the passive analog-integrating circuit, V is ₁ (t) is the output of the passive analog-integrating circuit, R _{i is} the integration resistance of the active analog Integration circuit, C _i the integration _{capacity of} the active analog integration circuit, V out ₁ (t) the output of the active analog integration circuit, k a gain coefficient, and I (t) the combined integration signal, ie the current signal after the restoration of the integration by means of the integration circuit, is.

Equation (6) illustrates that when the frequency of the primary current is f≥f _L1 , the first part of the output in the equation V out _{Fig. 1} (t) represents the output that meets the accuracy requirements of the analog-to-analogue passive circuit while the second part of the output V out ₂ (t), ie the result of integration from the first part of the output V out ₁ (t), is negligible.

If the frequency of the primary current is f _L1 ≥f≥f _L2 , the second part of the output V out ₂ (t) in the equation, ie the result of the integration from the first part of the output V out ₁ (t), may be the requirements to the accuracy, and the result of adding the two parts is just approaching the ideal value of integration.

By setting the amount k, the second part of the output V out ₂ (t) in the equation can be accurately processed.

In the internship, it may be in the combination module 13 may be an op-amp based adder circuit or a digital-sampled digital adder. In a digital sample based digital adder, first and second integration signals are respectively analog-to-digital converted for digital sampling and then added together to obtain a combined integration result.

2 shows a schematic partial structural view of the integration circuit in an example of the present invention. As 2 illustrates is the first circuit module 11 in the integration circuit around a passive analog-integrating circuit, comprising: a first integration resistor R1, a second integration resistor R2, a first filter resistor R3, a second filter resistor R4, and a first integration capacitor C1.

One end of the first integration resistor R1 is connected to one output of the Rogowski coil, and the other end is connected to one end of the first filter resistor R3 and to one end of the first integration capacitor C1.

One end of the second integration resistor R2 is connected to the other output of the Rogowski coil, and the other end is connected to one end of the second filter resistor R4 and to the other end of the first integration capacitor C1.

The other end of the first filter resistor R3 is grounded.

The other end of the second filter resistor R4 is grounded.

The two ends of the first integration capacitor C1 are the outputs of the passive analog-integrating circuit.

The amounts of the first integration resistor R1, the second integration resistor R2 and the first integration capacitor C1 can be determined by the aforementioned equation (3).

As 2 illustrates is the second circuit module 12 in the integration circuit around an active analog integration circuit, comprising: a third integration resistor R _i , a second integration capacitor C _i , a lossy integration resistor R ₀ , an operational amplifier U3, a third filter resistor R5, and a fourth filter resistor R6.

The one end of the third integration resistor R _i serves as an input of the active analog integration circuit 12 , and the other end is connected to an antiphase input of the operational amplifier U3.

The one end of the second integration capacitor C _i is connected to an opposite-phase input of the operational amplifier U3, and the other end is connected to an output of the operational amplifier U3.

The lossy integration resistor R ₀ is connected in parallel with the second integration capacitor C _i .

One end of the third filter resistor R5 is connected to an in-phase input of the operational amplifier U3, and the other end is grounded.

One end of the fourth filter resistor R6 is connected to an output of the operational amplifier U3, and the other end is grounded.

In addition, the integration circuit comprises in 2 also a signal conditioning circuit 14 which in turn comprises: an operational amplification chip U2, a gain resistor R7, and a power supply circuit.

Two signal inputs IN + and IN- of the operational amplification chip U2 are respectively connected to the two outputs of the passive analog-integration circuit 11 connected.

Two voltage inputs VS + and VS- of the operational amplification chip U2 are respectively connected to the power supply of the power supply circuit.

Two amplifying resistor terminals RG + and RG- of the operational amplifying chip U2 are respectively connected to two ends of the amplifying resistor R7.

A signal output of the operational amplification chip U2 is connected to the input of the active analog integration circuit 12 connected.

In this embodiment, the operational amplification chip U2 may be powered by 1) symmetrical dual power sources or 2) a single power source.

When the symmetrical dual power sources are used, the positive terminal + E and the negative terminal -E are connected to the (VS +) and (VS-) poles of the operational amplifier, respectively, relative to a common terminal (ground). In this way, the signal source may be connected directly to the input poles of the operational amplification chip and the amplitude of the output voltage may reach the symmetrical positive and negative voltages.

If, however, a single energy source is used, as in the 2 is shown, the (-VEE) pole of the operational amplifier chip is grounded. In this case, it is necessary that a DC potential be added to the input of the operational amplification chip to ensure a suitable static operating point in the unitary circuit of the operational amplification chip. Here, the output of the operational amplification chip changes depending on the input signal based on a certain DC potential. In a static state, the output voltage of the operational amplification chip is approximately VCC / 2, and a capacitor can be inserted into the circuit for isolating the DC component in the output.

3 Figure 12 shows a schematic view of the connection between an equivalent circuit to the Rogowski coil in an example of the invention and the passive analog integration module 2 , As 3 illustrates, the equivalent circuit 10 to the Rogowski coil include: self-inductors L1 and L2, internal resistors R8 and R9 and a parasitic capacitance C2 of the coil. In addition, it may further include: filter capacitors C3 and C4.

The series circuit of the inductor L1 and the internal resistor R8 is connected to one end of the parasitic capacitance C2, and the series circuit of the inductor L2 and the internal resistor R9 is connected to the other end of the parasitic capacitance C2. At the same time, one end of the parasitic capacitance C2 is connected to the filter capacitor C3 and the other end to the filter capacitor C4. The respective other ends of the filter capacitors C3 and C4 are grounded.

The two ends of the parasitic capacitance C2 of the coil are referred to as the outputs of the equivalent circuit to the Rogowski coil with the input of the passive analog-integrating circuit 11 connected. Ie. one end of the parasitic capacitance C2 of the coil is connected to one end of the first integration resistor R1 in the passive analog-integrating circuit, and the other end to one end of the second integrating resistor R2 in the passive analog-integrating circuit.

4A to 4C show the comparison result of integration with an input signal at 50 Hz, 10 Hz and 1 Hz between the inventive integration circuit and the stand alone passive analog integration circuit in the prior art.

In order to compare the accuracy of the measurement in both cases, first, a reference current for representing an accurate sampled AC value, ie, the value of the primary current I _dl (n) can be set, and therefore, the sampled value of the current becomes alone used as I _rcl (n) and referred to in the inventive integration _circuit as I _rccl (n).

It can be seen that below a frequency of 50 Hz, as in 4A both the sampled value of the current in the inventive integration circuit and the sampled value of the current in the prior art passive analog-to-analogue integrated circuit approximate to the reference current, ie the measurement results of the two integration circuits in the conventional signals to be measured meet the requirements can meet the measurement. In the 4B and 4C on the other hand, the sampled value of the current in the integrating circuit according to the invention is closer to the reference current. Therefore, the technical solutions in the embodiments have greater accuracy in the low-frequency signals than in the prior art passive analog-to-analog circuit used alone.

Only the preferred embodiments of the present invention have been explained above, but the invention should not be limited thereto. All modifications, equivalent substitutions and extensions that fall within the scope of the idea and principle of the invention are intended to be included within the scope of the invention.

Claims (12)

An integration circuit, characterized by comprising: a first circuit module (11) adapted to receive a first integration signal such that the signals from secondary voltage outputs of a Rogowski coil are analogously integrated; a second circuit module (12) configured to obtain a second integration signal such that the first integration signals are analog-integrated; and a combination module (13) configured to obtain a combined integration signal such that the first integration signal and the second integration signal are additively combined with each other. Integration circuit after Claim 1 characterized in that the first circuit module (11) is a passive analog-integrating circuit, wherein a first cut-off frequency f _{L1 of} the first circuit module (11) is greater than a desired cut-off frequency f _{L of} the integration circuit; and the second circuit module (12) is an active analog integration circuit, wherein a second cutoff frequency f _{L2 of} the second circuit module (12) is less than or equal to a desired cutoff frequency f _{L of} the integration circuit. Integration circuit after Claim 2 characterized in that the amounts of an integration resistance R and an integration capacitor C of the analog-to-analogue passive circuit are determined by the following equation: $$\frac{\mathrm{\lambda }}{2\pi \cdot f_L}>R\cdot C\ge \frac{M\cdot I_{\text{min}}}{V{1}_{erfassbar}}$$

where f _{L is} the desired cut-off frequency of the integration circuit, M I is the coefficient of mutual induction of the Rogowski coil, _{min is} the minimum of the primary current, V1 _detected the least detectable by the passive analog integration circuit voltage value and λ a set of empirical coefficient. Integration circuit after Claim 2 characterized in that the passive analog-integrating circuit (11) comprises: a first integration resistor (R1), a second integration resistor (R2), a first filter circuit (R3, R4), and a first integration capacitor (C1); wherein the one end of the first integration resistor (R1) is connected to the one output of the Rogowski coil and the other end to the one end of the first integration capacitor (C1); one end of the second integration resistor (R2) is connected to the other output of the Rogowski coil and the other end is connected to the other end of the first integration capacitor (C1); one end of the first filter circuit (R3, R4) is connected to one end of the first integration capacitor (C1) and the other end is grounded; and the two ends of the first integration capacitor (C1) are the outputs of the analog-to-analogue passive circuit. Integration circuit after Claim 2 , characterized in that the amounts of the integration resistance R _i , the integration capacitor C _i and the lossy integration resistance R _{0 of} the active analog-integration circuit connected in parallel with the integration capacitor C _i are determined by the following equation: $R_0\cdot C_i\ge {\frac{\mathrm{\lambda }}{2\mathrm{\pi }\cdot f_L}}_{.}$

and when the signal frequency f is in the range [f _L2 , f _L1 ], the following equation applies to the output V _{aus2 of} the active analog-integration circuit: $$V_{aus2}\approx \frac{k\cdot V_{aus1}}{R_i\cdot C_i}\ge V{2}_{erfassbar};$$

where V _{out1 is} the output of the passive analog integration circuit, k is the gain coefficient, V2 is _detectable, the lowest voltage value detectable by the active analog-to-logic circuit, and λ is an adjusted empirical coefficient. Integration circuit after Claim 2 characterized in that the active analog integration circuit (12) comprises: a third integration resistor (R _i ), a second integration capacitor (C _i ), a lossy integration resistor (R ₀ ), an operational amplifier (U3) and a second filter circuit (R5 , R6); wherein one end of the third integration resistor (R _i ) serves as an input of the active analog integration circuit and the other end is connected to an opposite phase input of the operational amplifier (U3); one end of the second integration capacitor (C _i ) is connected to an opposite-phase input of the operational amplifier (U3) and the other end to an output of the operational amplifier (U3); the lossy integration resistor (R ₀ ) is connected in parallel with the second integration capacitor (C _i ); and one end of the second filter circuit (R5, R6) is connected to an in-phase input and an output of the operational amplifier (U3), and the other end is grounded. Integration circuit according to one of Claims 1 to 6 characterized in that it further comprises: a signal conditioning circuit (14) arranged to perform operations on the first integration signal output from the first circuit module (11), including amplification and / or filtering, and the processed first integration signal to second circuit module (12) is transmitted. Integration circuit after Claim 7 characterized in that the signal conditioning circuit (14) comprises: an operational amplification chip (U2), a gain resistor (R7), and a power supply circuit; wherein two signal inputs of the operational amplification chip (U2) are respectively connected to the two outputs of the first circuit module (11); two voltage inputs of the operational amplification chip (U2) are respectively connected to the power supply of the power supply circuit; two amplification resistor terminals of the operational amplification chip (U2) are respectively connected to two ends of the amplification resistor (R7); and a signal output of the operational amplification chip (U2) is connected to an input of the second circuit module (12). Integration circuit according to one of Claims 2 to 6 , characterized in that the combination module (13) additively combines the first integration signal and the second integration signal as follows: $$I\left(t\right)\approx -\frac{1}{M}\left(R\cdot C\cdot V_{aus1\left(t\right)}-R_i\cdot C_i\cdot \frac{V_{aus2\left(t\right)}}{k}\right).$$

where M is the mutual inductance of the Rogowski coil, R is the integration resistance of the analog-to-analog passive circuit, C is the integration capacity of the passive analog-integrating circuit, V is ₁ (t) is the output of the passive analog-integrating circuit, R _{i is} the integration resistance of the active analog Integral circuit, C _{i is} the integration _{capacity of} the active analog integration circuit, V out ₂ (t) is the output of the active analog integration circuit, k is a gain coefficient and I (t) is the combined integration signal, ie the current signal after restoration of integration by means of the integration circuit. is. Integration circuit after Claim 9 , characterized in that the combination module (13) is an op-amp based on the operational amplifier or a digital-sampled digital adder. Current sensor, characterized in that it comprises an integration circuit according to one of Claims 1 to 6 includes. Circuit breaker, characterized in that it the current sensor after Claim 11 includes.

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