DE102018104873A1 - Device for controlling electrical and / or electronic components of a motor vehicle module and such a motor vehicle module with automatic module addressing via powerline - Google Patents

Abstract

The invention relates to a car addressing method for assigning bus node addresses within a data bus system with a communication bus with bus nodes (BK ₁ ..... BK _n ) and a bus master (ECU). The bus nodes are supplied with electrical energy via a supply voltage line (V _bat ). The communication bus (DB) is connected to the bus master (ECU) and each bus node (BK ₁ ... BK _n ). Within the bus node (BK ₁ to BK _n ) a respectively assigned measuring resistor (Rm _j ) is inserted in the supply voltage line (V _bat ). Each bus node (BK _j) has an addressing current source (Iq _j) and means (D2, D3, Rm _j) to detect the current through the measuring resistor (Rm _j). The addressing current source (Iq _j) feeds an addressing current towards the power supply (SUP) to the supply voltage line (V _bat) in those terminal of the measuring resistor (Rm _j) a, the _(bat V) along the power supply line on entferntesten from the power supply (SUP ) lies. With signaling of an addressing state, the bus nodes assume this addressing state for carrying out an auto-addressing method, each bus node (BK _j ) detects the voltage drop across its measuring resistor (RM _j ). With an addressing current source (Iq _j ), it controls the voltage drop to a predetermined value. If it is not the last bus node in the chain of bus nodes without a valid bus node address, then the addressing current of its addressing power source (Iq _j ) is zero or very low. If it is the last bus node in the chain of bus nodes without a valid bus node address, then the addressing current of its addressing current source (Iq _j ) corresponds to the predetermined value. This allows the bus node to recognize that it is the last bus node in the chain of bus nodes without a valid bus node address. He then takes over the offered bus node address as a valid bus node address and does not participate in the further procedure. In this way, all bus nodes are addressed bit by bit.

Description

The invention relates to a device for controlling electrical and / or electronic components of a motor vehicle module, in particular an interior light and / or outdoor light such. a backlight module of a car. Furthermore, the invention relates to a motor vehicle module with a plurality of electrical and / or electronic components, in particular an interior light and / or outdoor light such. a backlight module of a car.

The electrical or electronic components of motor vehicle modules such as the various light modules are becoming increasingly complex. Particularly in the field of "light", in recent years there has been an increasing tendency to use dynamic functions, such as e.g. use the "wiping blinker" or the so-called "coming home" application. It is advantageous to exploit the fact that the individual exterior and interior light functions of a vehicle are realized by a plurality of LEDs or OLEDs. Dynamic effects can now be realized in a comparatively simple manner in terms of hardware in that the multiplicity of light sources which have such a motor vehicle light module are activated in different ways.

The plurality of components of a motor vehicle module, that is, for example, the plurality of LEDs assigned to the individual light functions or OLEDs of a backlight module, for example, are advantageously connected to a drive unit of the module via a communication bus or are in communication communication with the drive unit via the communication bus. As a rule, the drive unit also includes a voltage converter for supplying in particular LED drivers of a light module.

With regard to the transmission speed and robustness, differential two-wire communication bus systems have proven themselves. The information signals are transmitted between the drive unit and the participants as a voltage difference between the two bus lines, whereby a greater signal security and a higher transmission speed and a lower susceptibility to interference are achieved. Such two-wire bus lines are known in principle.

The problem is that the hardware complexity for such two-wire bus systems and their participants is not negligible. In particular, in terms of the cost of disadvantage is the fact that the participants must have relatively precisely working clock that work in sync with each other. Furthermore, the lighting modules must be able to determine their physical position during installation and connection in the vehicle plant and convert it into a logical address so that similar lighting modules can be used without preprogramming a bus node address for these lighting modules, which massively reduces the possibility of errors and logistics in production.

From NN: "High-Brightness LED Matrix Manager for Automotive Headlight Systems", February 1, 2016 (2016-02-01), pages 1-53, XP055348745, Dallas, Texas (found on the Internet: URL: http: // www .ti.com / lit / ds / symlink / tps92661-q1.pdf on 2017-02-23), a vehicle headlight driver is known whose bus has two lines to which no differential signals are applied.

In MONAL GIRADKAR ET AL: "Design and Implementation of Adaptive Front Light System of Vehicles Using FPGA Based LIN Controllers", EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET), 2011 4TH INTERNATIONAL CONFERENCE ON, IEEE, November 18, 2011 (2011-11- 18), pages 258-261 , XP032087461, DOI: 10.1109 / ICETET.2011.67; ISBN: 978-1-4577-1847-2 describes a bit timing logic for a CAN bus.

A device for driving an adaptive automotive font light with FPGA-based LlN controller is in GUO JINYAN ET AL: "The design and realization of CAN bit timing logic", MICROELECTRONICS AND ELECTRONIS (PRIMEASIA), 2010 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN, IEEE, PISCATAWAY, NJ, USA, September 22, 2010 (2010-09- 22), pages 333-337, XP031777603, ISBN: 978-1-4244-6735-8 ,

Finally there ZENG WEIYING ET AL: "In-Vehicle Networks Outlook: Achievements and Challenges", IEEE COMMUNICATIONS SURVEYS & TUTORIALS, Vol. 18, No. 3, 27 February 2016 (2016-02-27), pages 1552-1571, XP011620858, DOI: 10.1109 / COMST.2016.2521642; [found on 2016-08-19] an overview of car communication systems ,

The object of the invention is to provide a device for controlling electrical and / or electronic components of a motor vehicle module and such a motor vehicle module, which is reduced in terms of hardware complexity.

For the claimed scope, the claims exclude. The description specifies the claims and puts them in an overall context.

• • mit einem differentiellen Zweidraht-Kommunikationsbus,
• • mehreren an den Zweidraht-Kommunikationsbus angeschlossenen Komponenten und
• • einer Ansteuereinheit, die von extern Steuerbefehle für die Komponenten erhält und diese Steuerbefehle in über den Zweidraht-Kommunikationsbus an die Komponenten zu versendende Bitströme umsetzt sowie von den Komponenten erzeugte Bitströme empfängt,
• • wobei jede Komponente eine asynchrone, digitale, serielle Schnittstelle, einen Mikrocontroller und einen Taktgeber zum Erzeugen eines Abtastsignals zum Abtasten von über den Zweidraht-Kommunikationsbus versendete Bitströme aufweist und
• • wobei zumindest die von der Ansteuereinheit versendeten Bitströme Synchronisationsinformationen zur Synchronisation der Taktgeber der Komponenten auf den Takt aufweisen, mit denen die Ansteuereinheit die Bits der Bitströme über den Zweidraht-Kommunikationsbus sendet und
• • wobei jede Koponente dazu eingerichtet ist, mittels eines oder mehrerer Autoadressierungsverfahren eine mit ihrer physikalischen Position korrelierte logische Busknotenadresse zu ermitteln und dann zu nutzen.

To achieve this object, the invention provides a device for controlling electrical and / or electronic components of a motor vehicle module, in particular an interior light and / or or outdoor light such as a taillight module of a motor vehicle, proposed, wherein the device is provided

• With a differential two-wire communication bus,
• • several components connected to the two-wire communication bus and
• A control unit, which receives external control commands for the components and converts these control commands into bit streams to be sent to the components via the two-wire communication bus and receives bit streams generated by the components,
• Wherein each component comprises an asynchronous digital serial interface, a microcontroller and a clock generator for generating a sampling signal for sampling bitstreams sent over the two-wire communication bus, and
• Wherein at least the bit streams sent by the drive unit comprise synchronization information for synchronizing the clocks of the components to the clock with which the drive unit sends the bits of the bit streams via the two-wire communication bus and
• Where each component is adapted to determine and then use, by means of one or more auto-addressing methods, a logical bus node address correlated with its physical position.

• • einem differentiellen Zweidraht-Kommunikationsbus,
• • wobei die Komponenten an den Zweidraht-Kommunikationsbus angeschlossenen sind und
• • einer Ansteuereinheit, die von extern Steuerbefehle für die Komponenten erhält und diese Steuerbefehle in über den Zweidraht- Kommunikationsbus an die Komponenten zu versendende Bitströme umsetzt sowie von den Komponenten erzeugte Bitströme empfängt,
• • wobei jede Komponente eine asynchrone, digitale, serielle Schnittstelle, einen Mikrocontroller und einen Taktgeber zum Erzeugen eines Abtastsignals zum Abtasten von über den Zweidraht-Kommunikationsbus versendete Bitströme aufweist und
• • wobei zumindest die von der Ansteuereinheit versendeten Bitströme Synchronisationsinformationen zur Synchronisation der Taktgeber der Komponenten auf den Takt aufweisen, mit denen die Ansteuereinheit die Bits der Bitströme über den Zweidraht-Kommunikationsbus sendet und
• • wobei die Komponenten vor Aufnahme des Normalbetiebes aus einem Normalzustand in einen Adressierungszustand wechseln und ein Verfahren zur Ermittlung von Busknotenadressen, die von der physikalischen Position der Busknoten in der Kette der busknoten abhängen, durchführen und anschließend wieder den Adressierungszustand verlassen.

Furthermore, to achieve the object according to the invention a motor vehicle module with a plurality of electrical and / or electronic components, in particular an interior light and / or outdoor light such as a rear light module of a motor vehicle, wherein the motor vehicle module is provided with

• A differential two-wire communication bus,
• • where the components are connected to the two-wire communication bus and
• A control unit that receives control commands for the components from outside and converts these control commands into bit streams to be sent to the components via the two-wire communication bus and also receives bit streams generated by the components;
• Wherein each component comprises an asynchronous digital serial interface, a microcontroller and a clock generator for generating a sampling signal for sampling bitstreams sent over the two-wire communication bus, and
• Wherein at least the bit streams sent by the drive unit comprise synchronization information for synchronizing the clocks of the components to the clock with which the drive unit sends the bits of the bit streams via the two-wire communication bus and
• Wherein the components change from a normal state to an addressing state before the normal operation is started, and a method for determining bus node addresses that depend on the physical position of the bus nodes in the chain of the bus nodes, and then leave the addressing state again.

The proposed approach combines the advantages of a two-wire differential communication bus with auto-addressing capability with the advantages of using asynchronous digital serial interfaces over which the individual subscribers or components are connected to the two-wire communication bus. The use of so-called Universal Asynchronous Receiver Transmitters (UART) requires that the bit stream received via such a digital serial interface contain synchronization information for the clock of the bus user (of the respective bus node). However, such synchronization information (for example synchronization bits) can now also be easily integrated via a differential two-wire communication bus, for example in the header of a data frame representing the bit stream. Thus, the protocol of the differential two-wire communication bus used according to the invention comprises elements such as are known, for example, from single-wire buses whose subscribers have standardized and cost-effective UARTs.

The invention can be used in particular within the framework of digital interfaces for the robust and high-speed transmission of data over a two-wire cable connection between boards equipped with LEDs for, for example, tail light and interior light within a luminaire with a data rate of up to 500 kbit / s. In this case, the symmetrical transmission is used by means of a differential high-speed two-wire bus system for the purpose of transmitting a simple serial protocol and thus to reduce the hardware digital effort.

The 1 shows an example of a rear light module (BLM) of a motor vehicle. The rear light module (BLM) has a bus master ( ECU ) and a serial bidirectional differential two-wire communication bus ( DB ) on. The serial, bidirectional and differential two-wire communication bus ( DB ) consists of a first single-wire bus ( DB _a ) and one second single wire bus ( DB _b ). The TXD and RXD lines of the bus master ( ECU ) lead to a level converter (TR) to the signal level for the operation of the two-wire communication bus DB implement. The bus master ( ECU ) receives externally different control commands, for example for the functions taillight, turn signal, rear fog light, dynamic effects, etc., and / or information via a digital bus. The bus master ( ECU ) converts these instructions into bit streams, which inter alia include bits of a synchronization field of the corresponding data frames (bit stream packet ( BP )) respectively. Level converter and bus master ( ECU ) are also considered as a unit below and with bus master ( ECU ) together.

On the communication bus ( DB ) are various components or participants as bus nodes BK ₁ to BK ₆ connected. So the ertse and second bus node ( BK ₁ and BK ₂ ) as an example for the realization of the flashing light, the third bus node ( BK ₃ ) for the realization of the tail light, the fourth and sixth bus nodes ( BK ₄ ) and ( BK ₆ ) for the execution of the brake light function and the fifth bus node ( BK ₅ ) responsible for the realization of the return light. Each of these participants or each of these components has a multiplicity of LEDs ( LED ₁ to LED ₆ ), which are driven by respective LED drivers.

Each bus node is also equipped with a digital interface ( ₁ to ₆ ) in the form of a UART. Furthermore, each bus node, if necessary, has a microcontroller ( μC ₁ to μC ₆ ) and also a clock ( CLKG ₁ to CLKG ₆ ) on the differential two-wire communication bus ( DB ) to be able to read messages in synchronism with the transmission of the bits of the bit streams or to synchronize such bit streams synchronously for reading by other users or the bus master ( ECU ) on the two-wire communication bus ( DB ) to lay.

To simplify the hardware of the control of the components of a motor vehicle module according to the invention also contributes that is carried out at the level of the components or two-wire communication bus participants with fixed sampling points instead of a dynamic adjustment of the sampling points. The latter is much more expensive. Clock recovery per subscriber is accomplished by reading out the synchronization information of the bitstreams, which are advantageously sent at the beginning of a bitstream.

2 shows a two-wire communication bus ( DB ), as known for example from the prior art. The serial, bidirectional, differential two-wire communication bus ( DB ) consists of a first single-wire bus ( DB _a ) and a second single-wire bus ( DB _b ).

The serial, bidirectional, differential two-wire communication bus ( DB ) connects the bus master ( ECU ) with several bus nodes ( BK ₁ to BK _n ).

The bus master ( ECU ) has a first driver (TRa) with which the first one-wire bus ( DB _a ) into a first state ( Z1 ) or a second state ( Z2 ) or a third state ( Z3 ) can bring.

A first driver, as a CAN driver, preferably occupies two of three permitted states: in a first state, it sets a first logic level ( Z1 ) on the first single-wire bus ( DB _a ). In a second state, it sets a third logic level ( Z3 ) on the first single-wire bus ( DB _a ). The first driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as the first current sink for the first addressing currents of the first addressing current sources ( lq ₁ to lq _n ) the bus node ( BK ₁ to BK _n ) and their first quiescent currents. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or. of the bus master ( ECU ) the first state ( Z1 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the second state ( Z2 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the third state ( Z3 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the third state ( Z3 ). This will cause the signal to have a third differential level ( z3 ) impressed differentially.

The first driver may also occupy two of two permissible states as an RS485 driver: in a first state, it sets a first logic level ( Z1 ) on the first single-wire bus ( DB _a ). In a second state it sets a second logic level ( Z2 ) on the first single-wire bus ( DB _a ). The first driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as the first current sink for the first addressing currents of the first addressing current sources ( lq ₁ to lq _n ) the bus node ( BK ₁ to BK _n ) and their first quiescent currents. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the first state ( Z1 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the second state ( Z2 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the second state ( Z2 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the first state ( Z1 ). This will cause the signal to have a second differential level ( z2 ) impressed differentially. In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in case of simultaneous access to the first single-wire bus ( DB _a ) by a first driver of another bus node ( BK ₁ to BK _n ) or the bus master ( ECU ).

A second driver may preferably assume two of three permitted states as a CAN driver: in a first state, it sets a second logic level ( Z2 ) on the second single-wire bus ( DB _b ). In a second state, it sets a third logic level ( Z3 ) on the second single-wire bus ( DB _b ). The second driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as a second current sink for the second addressing currents of the second addressing current sources ( lq ' ₁ to lq _'n ) the bus node ( BK ₁ to BK _n ) and their second quiescent currents. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the second state ( Z2 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the first state ( Z1 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the third state ( Z3 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the third state ( Z3 ). This will cause the signal to have a third differential level ( z3 ) impressed differentially.

The second driver can also assume two of two permitted states as an RS485 driver: in a first state, it sets a second logic level ( Z2 ) on the first single-wire bus ( DB _a ). In a second state, it sets a first logic level ( Z1 ) on the second single-wire bus ( DB _b ). The second driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as a second current sink for the second addressing currents of the second addressing current sources (lq ' ₁ to lq' _n ) of the bus nodes ( BK ₁ to BK _n ) and their second quiescent currents. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the second state ( Z2 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the first state ( Z1 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the first state ( Z1 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the second state ( Z2 ). This will cause the signal to have a second differential level ( z2 ) impressed differentially.
In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in case of simultaneous access to the first single-wire bus ( DB _a ) by a first driver of another bus node ( BK ₁ to BK _n ) or the bus master ( ECU ).

Each of the bus nodes ( BK ₁ to BK _n ) and the bus master ( ECU ) preferably have a receiver ( Rec ). The respective recipient ( Rec ) extracts in the bit stream packets ( BP ) on the serial, bidirectional, differential two-wire communication bus ( DB ) ( DATA ) and preferably gives these together with error information about an output (out) of the receiver ( Rec ) out. The recipient ( Rec ) typically checks if the check information ( CHKD ) within the data information ( DATA ) of a bit stream packet ( BP ) to a faultless reception by the receiver ( Rec ) close. Was a bit-stream packet ( BP ) by the recipient ( Rec ) received incorrectly, the receiver signals ( Rec ) this is preferred. The actual payload circuits at the receiver output (out) are here in the 2 not shown for a better overview. These process the data through the receiver ( Rec ) received information (out) and control the drivers ( TR _a . TR _b ) for the respective transmission process of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ).

The data bus system has a common supply voltage line (V _bat ) and typically a common reference potential ( GND ), this in 2 is not shown.

Note that the 2 despite the serial arrangement of the bus nodes ( BK ₁ to BK _n ) has a star structure of the data bus. The presentation of the 2 breaks for a better overview at the third bus node ( BK ₃ ).

Thus, in one embodiment, a device for controlling electrical and / or electronic bus nodes ( BK ₁ to BK _n ), in particular within a motor vehicle module, an interior light and / or exterior lighting such as a rear light module of a motor vehicle proposed a serial, bidirectional, differential two-wire communication bus ( DB ) with n bus nodes ( BK ₁ to BK _n ) having. N is a whole positive number greater than 1. Furthermore, the proposed device has a bus master ( ECU ) on. The serial, bidirectional, differential communication bus ( DB ) consists of a first single-wire bus ( DB _a ) and one second single wire bus ( DB _b ). Each bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) has a differential, serial interface ( lf _j ) to match the serial, bidirectional, differential communication bus ( DB ). Each bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) preferably has a clock ( CLKG _j ), a scanning device ( AT _j ), an address recognition unit ( ADR _j ) and a bus node address register ( BKADR _j ) on. The serial, bidirectional, differential communication bus ( DB ) is designed so that it preferably at least in a first logical state (high, Z1 ) and in a second logical state (Low, Z2 ) and possibly in a third logical state (idle, Z3 ) can be located.

First, levels of high-speed CAN protocol (HS-CAN) can be used. This will be explained first.

For this purpose, the serial, bidirectional, differential communication bus ( DB ) in the transmitters ( TX _a . TX _b ) the respective bus node ( BK _j ) each preferably via in each case one high-impedance voltage divider per transmitter ( TX _a . TX _b ) preferably to a preferably vanishing differential voltage difference between the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b ) corresponding to the third logical state (idle, Z3 ) clamped. Each of the transmitters ( TX _a . TX _b ) preferably each comprise a switch with which the first single-wire bus ( DB _a ) of the serial, bidirectional, differential communication bus ( DB ) by the first driver ( TR _a ) to the first logical state (high, Z1 ) and the second single-wire bus ( DB _b ) of the serial, bidirectional, differential communication bus ( DB ) by the second driver ( TR _b ) into a second logical state (Low, Z2 ) can be brought. This is 3 shown below. Will the switches of the drivers ( TR _a . TR _b ) (IDLE), the serial, bidirectional, differential communication bus ( DB ) again the third logical state (idle, Z3 ) on.

Second, levels of the RS484 protocol can be used. This will be explained second.

For this purpose, the serial, bidirectional, differential communication bus ( DB ) in the transmitters ( TX _a . TX _b ) the respective bus node ( BK _j ) each preferably via in each case one high-impedance voltage divider per transmitter ( TX _a . TX _b ) preferably to a differential voltage difference corresponding to the third logic state (Idle, Z3 ) clamped. Each of the transmitters ( TX _a . TX _b ) preferably comprises a respective half-bridge, with which the serial, bidirectional, differential communication bus (by DB ) to the first logical state (high, Z1 ) and a second logical state (Low, Z2 ) can be brought. If the half bridges are switched off (IDLE), the serial, bidirectional, differential communication bus ( DB ) again the third logical state (idle, Z3 ) on.

The serial interface ( lf _j ) of the at least one bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) is connected to the serial, bidirectional, differential communication bus ( DB ) to receive data over this serial, bidirectional, differential communication bus ( DB ) to send and / or receive from this. It typically comprises per bus node ( BK _j ) the already mentioned transmitters ( TX _a . TX _b ) and a receiver ( Rec ). The clock and data extraction within the bus nodes ( BK ₁ to BK _n ) from the bit packets ( BP ) is not shown in the drawings for simplicity, since it can be taken from the prior art. The bus master ( ECU ) receives externally control commands for the n bus nodes ( BK ₁ to BK _n ) and sets these control commands in via the serial, bidirectional, differential communication bus ( DB ) to the bus nodes ( BK ₁ to BK _n ) to be sent bitstreams. The bus master ( ECU ) sends in response to a clock ( CLK ) within the bus master ( ECU ) the bits passed through the bus master ( ECU ) to be transmitted bit streams via the serial, bidirectional, differential communication bus ( DB ). The bus master ( ECU ) receives in the opposite direction from the bus node ( BK ₁ to BK _n ) generated bit streams via the serial, bidirectional, differential communication bus ( DB ). Clock ( CLKG _j ) within each bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) generate within each bus node ( BK _j ) this bus node ( BK ₁ to BK _n ) a respective scanning signal ( CLKA _j ). The scanning device ( AT _j ) of this respective bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) then samples in dependence on the sampling signal ( CLKA _j ) of this bus node ( BK _j ) via the serial, bidirectional, differential communication bus ( DB ) sent bitstreams. This can be both bit streams of the bus master ( ECU ) to the bus nodes ( BK ₁ to BK _n ) as well as bitstreams of the other bus nodes ( BK ₁ to BK _n ) to the bus master ( ECU ) or to other bus nodes ( BK ₁ to BK _n ) act. The relevant bus node ( BK _j ) extracts in this way from the signals on the serial, bidirectional, differential communication bus ( DB ) a local bit stream within this bus node ( BK _j ), from the output of the receiver ( Rec ) by sampling the output signal of the receiver ( Rec ) or a derived signal. The bus master ( ECU ) transmits the bitstreams to be sent as sequences of bitstream packets. BP ). The bus nodes also prefer to send their bitstreams to be transmitted as sequences of bitstream packets. BP ), which preferably have a structure similar to that of the bus master ( ECU ) correspond. to Simplification here only the bit-stream packets (English frames, BP ) of the bus master ( ECU ) discussed. For the bit stream packets ( BP ) the bus node ( BK ₁ to BK _n ) then applies accordingly.

As explained above, this structure means that the serial bidirectional differential two-wire communication bus ( DB ), if neither the bus master ( ECU ) nor one of the n bus nodes ( BK ₁ to BK _n ) Data via the serial, bidirectional, differential two-wire communication bus ( DB ) transmits the first logical state ( Z1 ) (dashed in 3 ) or the third logical state ( Z3 ) - which is preferred - assumes.

The proposed preferred structure of the bus master ( ECU ) sent bit stream packets ( BP ) is with the help of 3 explained. The signal labeled Vdiff is intended to represent the differential level on the serial, bidirectional, differential communication bus ( DB ), ie the voltage difference between the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b ).

The diagram labeled HS-CAN describes the corresponding levels when CAN drivers ( TR _a . TR _b ) be used.

The diagram labeled RS485 represents the corresponding levels when RS485 drivers ( TR _a . TR _b ) be used.

The drivers ( TR _a . TR _b ) provide three voltage levels in the HS-CAN scheme, but only two differential voltage levels.

The drivers ( TR _a . TR _b ) provide two voltage levels and only two differential voltage levels in the RS485 scheme.

1. 1. ein Startsignal (START) in Form von i Bits mit i als ganzer positiver Zahl mit i-1≤m/3 mit einem zweiten logischen differentiellen Zustand (z2) auf dem seriellen, bidirektionalen, differentiellen Zweidraht-Kommunikationsbus (DB),
2. 2. eine Synchronisationsinformation (SYNC), zur Synchronisation des Abtastsignals (CLKA_j ) der Taktgeber (CLKG_j ) der Busknoten (BK_j ) mit dem Takt (CLK) des Busmasters (ECU),
3. 3. Dateninformationen (DATA) aus den restlichen Bits der m-i-k Bits der m Bits des jeweiligen Bit-Strom-Paketes (BP), wobei die Dateninformationen (DATA) Adressinformationen (ADRD) und Nutzinformationen (INFO) umfassen.

It is proposed here that at least a part of the bus master ( ECU ) sent bit stream packets ( BP ) has the following contents:

1. 1. a start signal ( BEGIN ) in the form of i bits with i as a whole positive number with i-1≤m / 3 with a second logical differential state ( z2 ) on the serial, bidirectional, differential two-wire communication bus ( DB )
2. 2. a synchronization information ( SYNC ), for the synchronization of the scanning signal ( CLKA _j ) the clock ( CLKG _j ) the bus node ( BK _j ) with the clock ( CLK ) of the bus master ( ECU )
3. 3. Data information ( DATA ) from the remaining bits of the mik bits of the m bits of the respective bit stream packet ( BP ), where the data information ( DATA ) Address information ( ADRD ) and payload ( INFO ).

The address recognition units ( Adr ₁ to Adr _n ) the bus node ( BK ₁ to BK _n ) and possibly also the bus master ( ECU ) evaluate the address information ( ADRD ) of the bit stream packets ( BP ) out. The address recognition units ( Adr ₁ to Adr _n ) the bus node ( BK ₁ to BK _n ) only allow use of the included payload ( INFO ), if the content of the address information ( ADRD ) with the contents of the bus node address register ( BKADR _j ) of the bus node ( BK _j ) corresponds. Preferably, the bus nodes ( BK _j ) the n bus node ( BK ₁ to BK _n ) Means for performing a car addressing method for a two-wire data bus to provide the bus node address register ( BAKDR _j ) with a logical bus node address that corresponds to the physical position of this bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) within the serial, bidirectional, differential two-wire communication bus ( DB ) corresponds. This is an essential step that has not been solved in the prior art.

In a refinement of the method, each bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) a microcontroller ( μC _j ), which performs some of the above tasks, such as the address recognition ( ADR _j ) of the respective bus node ( BK _j ) and / or the scanning device ( AT _j ) of the respective bus node ( BK _j ) can take over by software program. It is now proposed that preferably additionally at least one bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) at least one lamp ( LED _j ) and at least one energy supply means ( EV _j ) having. The at least one energy supply means ( EV _j ) of the at least one bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) is then for the energy supply of at least one light source ( LED _j ) of the at least one bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) intended.

1. 1. Ein Startsignal (START) in Form von i Bits mit i als ganzer positiver Zahl mit i-1≤m/3 mit einem zweiten differentiellen logischen Zustand (z2) auf dem seriellen, bidirektionalen, differentiellen Zweidraht-Kommunikationsbus (DB);
2. 2. Eine Synchronisationsinformation (SYNC) aus k-Bits mit k als ganzer positiver Zahl, insbesondere mit k<i, zur Phasensynchronisation des Abtastsignals (CLKA_j ) der Taktgeber (CLKG_j ) der Busknoten (BK_j ) auf die Phase des Takts (CLK) des Busmasters (ECU) aufweisen und zur Frequenzsynchronisation des Abtastsignals (CLKA_j ) der Taktgeber (CLKG_j ) der Busknoten (BK_j ) auf die Frequenz des Takts (CLK) des Busmasters (ECU);
3. 3. Dateninformationen (DATA) aus den restlichen Bits der m-i-k Bits der m Bits des jeweiligen Bit-Strom-Paketes (BP), wobei die Dateninformationen (DATA) Adressinformationen (ADRD) und Nutzinformationen (INFO) und Prüfinformationen (CHKD) umfassen.

As before, the clock generates ( CLKG _j ) of each bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) a scanning signal ( CLKA _j ) within the respective bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ). The scanning device ( AT _j ) of a preferably each bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) again samples in dependence on the scanning signal ( CLKA _j ) of this bus node ( BK _j ) via the serial, bidirectional, differential two-wire communication bus ( DB ) sent bitstreams to a local bitstream within that bus node ( BK _j ) to win. The bit stream packets ( BP ) preferably consist of a time sequence of m individual bits of the same time length t _B with m as a whole positive number whose time length t _B by not more than a factor of +/- (0.4 / m) * t _B and / or better +/- (0.2 / m) * t _B and / or better +/- (0.1 / m ) * t _B and / or better +/- (0.05 / m) * t _B within a bit stream packet ( BP ) varies. At least part of the bus master ( ECU ) sent bit stream Packages ( BP ) preferably has the following contents (see 3 ):

1. 1. A start signal ( BEGIN ) in the form of i bits with i as a whole positive number with i-1≤m / 3 with a second differential logical state ( z2 ) on the serial, bidirectional, differential two-wire communication bus ( DB );
2. 2. Synchronization information ( SYNC ) of k-bits with k as a whole positive number, in particular with k <i, for the phase synchronization of the scanning signal ( CLKA _j ) the clock ( CLKG _j ) the bus node ( BK _j ) to the phase of the cycle ( CLK ) of the bus master ( ECU ) and for the frequency synchronization of the sampling signal ( CLKA _j ) the clock ( CLKG _j ) the bus node ( BK _j ) to the frequency of the clock ( CLK ) of the bus master ( ECU );
3. 3. Data information ( DATA ) from the remaining bits of the mik bits of the m bits of the respective bit stream packet ( BP ), where the data information ( DATA ) Address information ( ADRD ) and payload ( INFO ) and inspection information ( CHKD ).

At least part of the payload ( INFO ) includes illumination information ( ILD ) for controlling the power supply of the lamps ( LED _j ) of the bus node ( BK _j ) by the power supply means ( EV _j ) of the bus node ( BK _j ) in response to this lighting information. For this purpose, typically a lighting register within the power supply means ( EV _j ) with a value in Dependence on the received lighting information ( ILD ), which explains the radiation properties such as color, color temperature and brightness of the connected lamps ( LED _j ) certainly. In order for this data through the respective bus node ( BK _j ), the logical content of the address information ( ADRD ) with the contents of the bus node address register ( BKADR _j ) of the bus node ( BK _j ) to match. If this is not the case, the data information ( DATA ) ignored. The same is the case when verifying the integrity of the received data information ( DATA ) mittes the also received test data ( CHKD ) indicates that the reception was faulty. The respective address recognition unit ( ADR _j ) of the respective bus node ( BK _j ) evaluates the address information ( ADRD ) of a received bit stream packet ( BP ) and only then allows the use of the included payload ( INFO ) by the remainder of the bus node devices of the bus node ( BK _j ), if the contents of the received address information ( ADRD ) with the contents of the bus node address register ( BKADR _j ) of the bus node ( BK _j ) corresponds and is error-free. In contrast to the prior art, bus nodes ( BK ₁ to BK _n ) Means for implementing a car addressing method for a serial, bidirectional and differential communication bus ( DB ). As a result of such an auto-addressing method, the bus node address register ( BAKDR _j ) this bus node ( BK ₁ to BK _n ) is filled with a logical bus node address that corresponds to the physical position of this bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) within the serial, bidirectional, differential two-wire communication bus ( DB ) corresponds.

The tests described above can still be used. In a first variant of the device, the bus master ( ECU ) and / or bus nodes ( BK ₁ to BK _n ) are provided with means to evaluate the test information ( CHKD ) to an incorrectly running clock ( CLKG _j ) one or more bus nodes ( BK _j ) close.

In the following, various exemplary auto-addressing methods and other variants will be described, which may be used by way of example:

ASYMMETRIC AUTO ADDRESSING WITH BUS SHUNT WHEEL STANDS THAT ARE NOT FLUIDED BY THE ADDRESSING CURRENT

It is now typically desired that the bus nodes ( BK ₁ to BK _n ) their physical position within the data bus system in the serial, bidirectional, differential two-wire communication bus ( DB ) independently and obtain a bus node address based thereon so that the logical address corresponds to the physical address. This has the advantage that with similarly constructed bus nodes ( BK ₁ to BK _n ) only one type of bus node in production must be kept, which improves error possibilities and logistics. To carry out such a car addressing, one could now come up with the idea of incorporating a car addressing. This is in 4 shown. By way of example, the first single-wire bus ( DB _a ) a first bus shunt resistor ( R2 ) per bus node ( BK ₁ to BK _n ). A second differential amplifier ( D2 ) is used to measure the first current through the first single-wire bus ( DB _a ) by means of the first shunt resistor ( R2 ). The output of the second differential amplifier ( D2 ) used to measure the first current through the first single-wire bus ( DB _a ), is connected to a third comparator ( D3 ), the output value of the second differential amplifier ( D2 ) compares with a first reference value (Ref). This corresponds in its effect to a comparison of the first current in the first single-wire bus ( DB _a ) by the first bus shunt resistor ( R2 ) with a first reference current (L _ref ). The data bus system with its bundles ( BK ₁ to BK _n ) can now by the bus master ( ECU ) by means of a special bus signal in an addressing state and be put into a normal state. During the addressing state, a car addressing process is performed. If the data bus system is in the addressing state, then the bus nodes ( BK ₁ to BK _n ) that can perform the auto-addressing method in a corresponding addressing state of the bus nodes. The first addressing power source ( lq _j ) (with 1≤j≤n) of the respective bus node ( BK _j ) is switched off in the normal state or performs another function, such as, for example, the power supply of a light source ( LED _j ). The first addressing power source ( lq _j ) (with 1≤j≤n) of the respective bus node ( BK _j ) is switched off in the addressing state if the respective bus node ( BK _j ) by means of these first means ( R2 . D2 . D3 ) a first current through its first bus shunt resistor ( R2 ), which is above this threshold. In the example of 4 feeds the respective first addressing current source ( lq _j ) of a bus node ( BK _j ) receive its first addressing current from the bus master ( ECU ) seen in front of the respective first bus Shun resistor ( R2 ) of the respective bus node ( BK _j ) into the first single-wire bus ( DB _a ), if the bus node ( BK _j ) by means of the first means ( R2 . D2 . D3 ) determines that only a first current below this threshold value by its first bus shunt resistor ( R2 ) in the direction of the bus master ( ECU ) flows. This has the disadvantage that a self-test of the bus node ( BK _j ) is not possible at this feed-in point of the first addressing current. In addition, it can be overloaded during power-up of the first driver ( TR _a ) of the bus master ( ECU ) come. Therefore, the first addressing current of the first addressing current sources ( lq ₁ to lq _n ) are limited to an nth part of the maximum current value that the first driver ( TR _a ) can still record. This limits the resistance of the first bus shunt resistor ( R2 ), otherwise the level of the voltage drop across the first bus shunt resistor ( R2 ) of a bus node ( BK _j ) too small for detection by the first means ( R2 . D2 . D3 ) of this bus node ( BK _j ) would. This leads to an increased sensitivity to electromagnetic radiation, which should actually be avoided. In addition, the asymmetry between the first single-wire bus ( DB _a ) the 4 and the second single-wire bus ( DB _b ) the 4 for injecting common mode noise into the differential signal on the serial bidirectional differential two-wire communication bus ( DB ), which should also be avoided. Represents a bus node ( BK _j ) in the addressing state after a certain predetermined waiting time after taking the addressing state that its first addressing current source ( lq _j ) is not switched off, it is the last not yet provided with a valid bus node address bus node ( BK _j ). He then typically takes over from the bus master ( ECU ) to be given bus node address as its new valid bus node address. There he then has a valid bus node address, it then switches its addressing power source ( lq _j ) and then waits for the end of the addressing state of the data bus system without its addressing power source ( lq _j ) before this end of the addressing state of the data bus system. The bus node ( BK _j-1 ) which, as the next bus node in the next initialization run, then determines that its addressing power source ( lq _j ) is not switched off, then takes over the next from the bus master ( ECU ) to be given bus node address as its valid bus node address and so on. This is continued until all bus nodes ( BK ₁ to BK _n ) of the data bus system have thus obtained a valid bus node address. The bus master then typically relocates the data bus system and its bus node (FIG. BK ₁ to BK _n ) returns to normal, retaining the valid bus node addresses. This recommended maintenance of the valid bus node addresses during the transition from the addressing state into the normal state preferably applies to the entire document.

SYMMETRIC AUTO ADDRESSING WITH BUS SHUNT WHEEL STANDS THAT ARE NOT FLUSHED BY THE ADDRESSING CURRENT

A problem that arises in auto addressing is, as mentioned, that of symmetry. Since the serial, bidirectional, differential two-wire communication bus ( DB ) is a differential bus, the two single-wire buses ( DB _a and DB _b ) are constructed as symmetrically as possible in order to provide no point of attack for common mode noise. The data bus system should therefore be bus nodes ( BK _j ) for the serial, bidirectional, differential two-wire communication bus ( DB ), which consists of a first single-wire bus ( DB ₁ ) and a second single-wire bus ( DB ₂ ), a first bus shunt resistor ( R2 ) in the first single-wire bus ( DB ₁ ), and a second bus shunt resistor ( R2 ' ) inserted in the second single-wire bus ( DB ₂ ). An appropriate proposal based on 4 is in 5 shown. The two bus shunt resistors ( R2 . R2 ' ) per bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) are preferably monolithically integrated and matchend and with a relative resistance deviation within the respective bus node ( BK _j ) of less than 10% and / or better less than 5% and / or better less than 2% and / or better less than 1% and / or better less than 0.5%.

Each bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) is now in addition to the first means ( R2 . D2 . D3 ) for detecting the first current through the first bus shunt resistor ( R2 ) in the first single-wire bus ( DB _a ) with second means ( R2 ' . D2 ' . D3 ' ) for detecting the second current through the second bus shunt resistor ( R2 ' ) in the second single-wire bus ( DB _b ) fitted.

By way of example, the second single-wire bus ( DB _b ) a second bus shunt resistor ( R2 ' ) per bus node ( BK ₁ to BK _n ). Another second differential amplifier ( D2 ' ) is used to measure the second current through the second single-wire bus ( DB _b ) by means of the second shunt resistor ( R2 ' ) of the relevant bus node ( BK _j ). The output of the further second differential amplifier ( D2 ' ) for measuring the second current through the second single-wire bus ( DB _b ), is connected to another third comparator ( D3 ' ), the output value of the further second differential amplifier ( D2 ' ) with another reference value (Ref '), which is typically equal to the first reference value (Ref) mentioned. This corresponds in its effect to a comparison of the second current in the second single-wire bus ( DB _b ) by the second bus shunt resistor ( R2 ' ) with a second reference current (l ' _ref ), which is typically equal to the aforementioned first reference current ( I _ref ) is selected. The second addressing current source (lq ' _j ) (with 1≤j≤n) of the respective bus node ( BK _j ) is switched off if the respective bus node ( BK _j ) by means of these second means ( R2 ' . D2 ' . D3 ' ) a first current through its second bus shunt resistor ( R2 ' ), which is above this threshold. In the example of 5 feeds the respective second addressing current source (lq ' _j ) of a bus node ( BK _j ) the second addressing current from the bus master ( ECU ) seen also before the respective second bus shunt resistor ( R2 ' ) of the respective bus node ( BK _j ) into the second single-wire bus ( DB _b ), if the bus node ( BK _j ) by means of the second means described above ( R2 ' . D2 ' . D3 ' ) detects that only a second current below this threshold value is detected by its second bus shunt resistor ( R2 ' ) in the direction of the bus master ( ECU ) flows. As before, this has the disadvantage that a self-test of the bus node ( BK _j ) not possible. In addition, it can also be in the power-on to overload the second driver ( TR _b ) of the bus master ( ECU ) come. Therefore, the second addressing current of the second addressing current sources (lq ' ₁ to lq' _n ) must be limited to an nth part of the maximum current value that the second driver ( TR _b ) can still record. This limits the resistance of the second bus shunt resistor ( R2 ' ), otherwise the level of the voltage drop across the second bus shunt resistor ( R2 ' ) of a bus node ( BK _j ) too small for detection by the second means ( R2 ' . D2 ' . D3 ' ) would. This leads to an increased sensitivity to electromagnetic radiation, which should be avoided. The symmetry between the first single-wire bus ( DB _a ) the 5 and the second single-wire bus ( DB _b ) the 5 However, already leads to a reduced coupling of common mode noise in the differential signal on the serial, bi-directional, differential two-wire communication bus ( DB ), which is an advantage.

Both addressing current sources ( lq _j , lq ' _j ) of a bus node ( BK _j ) is switched off when the bus node ( BK _j ) by means of the first means ( R2 . D2 . D3 ) detects that a first current above the threshold is exceeded by its first bus shunt resistor ( R2 ) in the direction of the bus master ( ECU ) or by means of the second means described above ( R2 ' . D2 ' . D3 ' ) determines that only a second current above this threshold is exceeded by its second bus shunt resistor ( R2 ' ) in the direction of the bus master ( ECU ) flows.

SYMMETRIC AUTO ADDRESSING WITH BUS SHUNT WHEEL STAGES THROUGH THE ADDRESSING CURRENT

6 now shows another suggestion based on the 5 , Substantial difference to 5 is now that the respective first addressing current sources ( lq ₁ to lq _n ) from the bus master ( ECU ) seen the first addressing current behind the first bus shunt resistors ( R2 ) in the addressing phase in which the respective bus node ( BK _j ) in an addressing state, feed in if the respective bus node ( BK _j ) by means of the first means ( R2 . D2 . D3 ) a current value of the first current through the first bus shunt resistor ( R2 ), which is smaller than a predetermined first reference current value ( I _ref ). The third comparator ( D3 ), a third differential amplifier ( D3 ). In contrast to the proposal of 5 the first addressing current of the respective first addressing current source ( lq _j ) of the respective bus node ( BK _j ) but now readjusted until the first current through the first bus shunt resistor ( R2 ) the predetermined first reference current ( I _ref ) corresponds. Similarly dine in deviation from 5 the respective second addressing current sources (lq ' ₁ to lq' _n ) from the bus master ( ECU ) seen from the respective second addressing current also behind the corresponding second bus shunt resistors ( R2 ' ) in the addressing phase in which the respective bus node ( BK _j ) in an addressing state, if the respective bus node ( BK _j ) by the second means ( R2 ' . D2 ' . D3 ' ) a current value of the second current through the second bus shunt resistor ( R2 ) which is smaller than a predetermined second reference current value (I ' _ref ), preferably equal to the first reference current value ( I _ref ). The third third comparator ( D3 ' ), another third differential amplifier ( D3 ' ). In contrast to the proposal of 5 is the second addressing current of the respective second addressing current source (lq ' _j ) of the respective bus node ( BK _j ) but now also readjusted until the second current through the second bus shunt resistor ( R2 ' ) corresponds to the predetermined second reference current (l ' _ref ).

Of course it is possible in the configuration of 6 the addressing power sources ( lq ₁ to lq _n , lq ' ₁ to lq' _n ) instead of regulating.

The proposed bus node ( BK _j ) is thus connected to a first addressing current source ( lq _j ) for determining the bus position of the bus node ( BK _j ) in the serial, bidirectional, differential two-wire communication bus ( DB ) providing a first addressing current in the kind in the first single-wire bus ( DB _a ) of the serial, bidirectional, differential two-wire communication bus ( DB ) can additionally feed in such a way that the first total current ( i _j ) by the first bus shunt resistor ( R2 ) of the bus node ( BK _j ) a predetermined or calculated or otherwise determined first summation current ( I _ref ) corresponds. Preferably, the first addressing current flows through the first bus shunt resistor ( R2 ). Preferably, the respective bus node ( BK _j ) now with a second addressing current source (lq ' _j ) for determining the bus position of the bus node ( BK _j ) in the serial, bidirectional, differential two-wire communication bus ( DB ), which injects a second addressing current of the type into the second single-wire bus ( DB _b ) of the serial, bidirectional, differential two-wire communication bus ( DB ) regulated additionally can supply that the second total current ( i _j ) by the second bus shunt resistor ( R2 ' ) of the bus node ( BK _j ) corresponds to a predetermined or calculated or otherwise determined second summation current (l ' _ref ). The second addressing current now flows through the second bus shunt resistor ( R2 ' ). For the symmetry, it is helpful if the two addressing current sources ( lq _j , lq ' _j ) matchend are executed. Also, all measuring and controlling components of the control loop for these two addressing power sources ( lq _j , lq ' _j ) matchend to achieve full symmetry.

The 7 to 9 represent the proposed advantageous properties of the control. The control is based on the example of the regulation of the first addressing current sources ( lq ₁ to lq _n ), but also applies to the second addressing current sources (lq ' ₁ to lq' _n ) in an analogous manner. The control characteristic for the first addressing current source ( lq _j ) of a bus node ( Bk _j ) is preferably in each case by a first filter ( F ) generated from the output signal of the third differential amplifier ( D3 ) a first control signal ( rw _j ) of the relevant bus node ( BK _j ), with which the first addressing current source ( lq _j ) of the relevant bus node ( BK _j ) is controlled. The control characteristic for the second addressing current source (lq ' _j ) of a bus node ( Bk _j ) is in each case preferably generated by a second filter or a second controller (F '), which from the output signal of the further third differential amplifier ( D3 ' ) a second control signal (rw ' _j ) of the relevant bus node ( BK _j ), with which the second addressing current source (lq ' _j ) of the relevant bus node ( BK _j ) is controlled.

7 shows an example of the course of the output current ( i ₁ ) of the first bus node ( BK ₁ ), the output current ( i ₂ ) of the second bus node ( BK ₂ ) and the output current ( i ₃ ) of the third bus node ( BK ₃ ) in a particular data bus system with n = 3 bus nodes ( BK ₁ to BK ₃ ). It also shows the first addressing _current (l _{1_intern} ) of the first addressing _{current source} ( lq ₁ ) of the first bus node ( BK ₁ ), the first addressing current ( l _{2_intern} ) of the first addressing current source ( lq ₂ ) of the second bus node ( BK ₂ ) and the first addressing current ( l _{3_intern} ) of the first addressing current source ( lq ₃ ) of the third bus node ( BK ₃ ). Here are the time constants for the up-regulation of the first addressing current of the first addressing current sources and the down-regulation of the first addressing current of the first addressing current sources in about the same. It comes to an overshoot. It can be clearly seen that the first addressing current ( l _{1_intern} ) of the first addressing current source ( lq ₁ ) of the first bus node ( BK ₁ ) and the first addressing current ( l _{2_intern} ) of the first addressing current source ( lq ₂ ) of the second bus node ( BK ₂ ) are controlled down by the controllers of these first auto-addressing bus nodes, while the first addressing stream ( l _{3_intern} ) of the first addressing current source ( lq ₃ ) of the third bus node ( BK ₃ ) to the reference value ( I _ref ) is regulated. The settling time is determined by a first time constant ( τ ₁ ) for raising the first addressing current of the first addressing current sources ( lq ₁ to lq ₃ ) certainly.

8th shows the course of the output current ( i ₁ ) of the first bus node ( BK ₁ ), the output current ( i ₂ ) of the second bus node ( BK ₂ ) and the output current ( i ₃ ) of the third bus node ( BK ₃ ). In addition, she shows the stream ( l _{1_intern} ) of the first addressing current source ( lq ₁ ) of the first bus node ( BK ₁ ), the stream ( l _{2_intern} ) of the first addressing current source ( lq ₂ ) of the second bus node ( BK ₂ ) and the stream ( l _{3_intern} ) of the first addressing current source ( lq ₃ ) of the third bus node ( BL ₃ ). Here are the first time constants ( τ ₁ ) for the up-regulation of the first addressing current of the first Addressing power sources in about ten times as long as the second time constants ( τ ₂ ) for the down-regulation of the first addressing current of the first addressing current sources. It only comes to a minimum overshoot.

9 shows the course of the output current ( i ₁ ) of the first bus node ( BK ₁ ), the output current ( i ₂ ) of the second bus node ( BK ₂ ) and the output current ( i ₃ ) of the third bus node ( BK ₃ ). It also shows the first addressing stream ( l _{1_intern} ) of the first addressing current source ( lq ₁ ) of the first bus node ( BK ₁ ), the first addressing current ( l _{2_intern} ) of the first addressing current source ( lq ₂ ) of the second bus node ( BK ₂ ) and the first addressing current ( l _{3_intern} ) of the first addressing current source ( lq ₃ ) of the third bus node ( BK ₃ ). Here are the first time constants ( τ ₁ ) for the up-regulation of the first addressing current of the first addressing current sources in about a hundred times as long as the second time constants ( τ ₂ ) for the down-regulation of the first addressing current of the first addressing current sources. There is no overshoot.

Preferably, the bus node ( BK _j ) first means ( R2 . D2 ) to the current through the first bus shunt resistor ( R2 ) and / or second means ( R2 ' . D2 ' ) to the current through the second bus shunt resistor ( R2 ' ) to detect.

If the data bus system is constructed such that the first and second addressing current of the two addressing current sources ( lq _j , lq ' _j ) from the bus master ( ECU ) always seen behind the bus shunt resistors ( R2 . R2 ' ) can be fed in each case, then the respective detected current through the first bus shunt resistor ( R2 ) and / or by the second bus shunt resistor ( R2 ' ) are each used for a self-test. For example, with full symmetry, both voltage drops should be across both bus shunt resistors ( R2 . R2 ' ) preferably be the same. A cold solder joint, for example, can thus be easily detected in this way.

For error detection, it is advantageous to connect the bus node ( BK _j ) with a first detection device ( DET ), the internal signals ( ds1 . ds3 ) of the bus node ( BK _j ) checks for plausibility. The internal signals are preferably control signals within the bus node ( BK _j ). In the case of a bus symmetry, for example, the symmetry of these signals can be tested. But there are also tests per channel possible. For this purpose, see the not yet published German patent application EN 10 2017 122 365.7 which is fully part of this disclosure.

• • zum Ersten eine Vertauschung seiner Buseingänge mit seinem Busausgängen zu erkennen und
• • zum Zweiten in diesem Fall als beispielhafte Gegenmaßnahme
  • ○ den Einspeisepunkt für den ersten Adressierungsstrom seiner geregelten ersten Adressierungsstromquelle (lq_j ) so vor oder hinter seinem ersten Bus-Shunt Widerstand (R2) zu positionieren, dass die Autoadressierung je nach Beschaltung möglich ist und
  • ○ den Einspeisepunkt für den zweiten Adressierungsstrom seiner geregelten zweiten Adressierungsstromquelle (lq'_j ) so vor oder hinter seinem zweiten Bus-Shunt Widerstand (R2') zu positionieren, dass die Autoadressierung je nach Beschaltung möglich ist.

10 shows the principle of such detection. 10 shows the control loop of a bus node ( BK _j ). Here j stands for a position in the bus chain of the bus node ( BK ₁ to BK _n ) in the form of a positive, integer, natural number. It is a jth bus node ( BK _j ) who is able to

• • First, to detect an interchanging of its bus inputs with its bus outputs, and
• • second, in this case as an exemplary countermeasure
  • ○ the feed point for the first addressing current of its regulated first addressing power source ( lq _j ) so in front of or behind its first bus shunt resistor ( R2 ) to position that the auto addressing is possible depending on the wiring and
  • ○ the feed point for the second addressing current of its regulated second addressing current source ( lq ' _j ) so in front of or behind its second bus shunt resistor ( R2 ' ) to position that the auto-addressing is possible depending on the wiring.

In the 10 For example, only the repositioning of the feed point of the first addressing current of the first addressing current source ( lq _j ) of the considered bus node ( BK _j ). For the repositioning of the feed-in point of the second addressing current of the second addressing current source (lq ' _j ) of the considered bus node ( BK _j ) applies accordingly.

1. a. Signalisierung des Fehlers an einen Nutzer;
2. b. Signalisierung des Fehlers an den Busmaster (ECU) mittels Antwort auf eine Diagnoseanfrage (Broadcast-Message) oder mittels einer Interruptleitung;
3. c. Verwendung einer vorbestimmten Fehleradresse als gültige Busknotenadresse;
4. d. Umkonfiguration der internen Topologie zur Neutralisation des Fehlers;
5. e. Umparametrierung interner Teilvorrichtungen wie z.B. Stromquellen zur Neutralisation des Fehlers;

The in 10 exemplified jth auto addressing bus node ( BK _j ) for the repositioning of the feed point of the first addressing current of the first addressing current source ( lq _j ) of the considered bus node ( BK _j ) a first detection device ( DET ) which is capable of interchanging the bus input of the jth bus node ( BKj ) for the first single-wire bus ( DB _a ) with the bus output of the jth bus node ( BK _j ) for the first single-wire bus ( DB _a ). For this purpose, the exemplary first detection device ( DET ) internal signals of the jth bus node ( BK _j ) for plausibility. Leave the internal signals of the jth bus node ( BK _j ) to an exchange of the bus input of the jth bus node ( BK _j ) for the first single-wire bus ( DB _a ) with the bus output of the jth bus node ( BK _j ) for the first single-wire bus ( DB _a ), the first detection device ( DET ) potentially take various exemplary actions:

1. a. Signaling the error to a user;
2. b. Signaling the error to the bus master ( ECU ) by means of a response to a diagnostic request (broadcast message) or by means of an interrupt line;
3. c. Using a predetermined error address as a valid bus node address;
4. d. Reconfiguration of the internal topology to neutralize the fault;
5. e. Reparameterization of internal sub-devices such as power sources to neutralize the fault;

Further measures are conceivable.

In the example of 10 it is planned to reconfigure the internal topology to neutralize the error. In the 10 changes the first detection device by way of example ( DET ) the feed point for the first addressing current of the regulated first addressing current source ( lq _j ) of the jth bus node ( BK _j ), for example by means of a first analog multiplexer ( X3 ) and reverses the polarity of the inputs or the output of the second differential amplifier ( D2 ) by means of the polarity signal ( pole ).

1. a. Signalisierung des Fehlers an einen Nutzer;
2. b. Signalisierung des Fehlers an den Busmaster (ECU) mittels Antwort auf eine Diagnoseanfrage (Broadcast-Message) oder mittels einer Interruptleitung;
3. c. Verwendung einer Fehleradresse als Busknotenadresse;
4. d. Umkonfiguration der internen Topologie zur Neutralisation des Fehlers;
5. e. Umparametrierung interner Teilvorrichtungen wie z.B. Stromquellen zur Neutralisation des Fehlers;

For a better overview, the analog device for the second single-wire bus ( DB _b ) is not drawn, since it is constructed analogously. The in 11 illustrated by way of example jth Autoaddressierungsbusknoten ( BK _j ) for the repositioning of the feed point of the second addressing current of the second addressing current source (lq ' _j ) of the considered bus node ( BK _j ) a second detection device ( DET ' ) which is capable of interchanging the bus input of the jth bus node ( BK _j ) for the second single-wire bus ( DB _b ) with the bus output of the jth bus node ( BK _j ) for the second single-wire bus ( DB _b ). For this purpose, the exemplary second detection device ( DET ' ) further internal signals of the jth bus node ( BK _j ) for plausibility. Leave the internal signals of the jth bus node ( BK _j ) to an exchange of the bus input of the jth bus node ( BK _j ) for the second single-wire bus ( DB _b ) with the bus output of the jth bus node ( BK _j ) for the second single-wire bus ( DB _b ), the second detection device ( DET ' ) potentially take various exemplary actions:

1. a. Signaling the error to a user;
2. b. Signaling the error to the bus master ( ECU ) by means of a response to a diagnostic request (broadcast message) or by means of an interrupt line;
3. c. Using an error address as the bus node address;
4. d. Reconfiguration of the internal topology to neutralize the fault;
5. e. Reparameterization of internal sub-devices such as power sources to neutralize the fault;

Further measures are conceivable.

Again, a reconfiguration of the internal topology to neutralize the error can be provided. The second detection device ( DET ' ), the injection point for the second addressing current of the regulated second addressing current source ( lq ' _j ) of the jth bus node ( BK _j ), for example with the aid of a second multiplexer ( X3 ' ) and the polarity of the inputs or the output of the further second differential amplifier ( D2 ' ) by means of a second polarity signal ( pole' ) swap.

Alternatively to the previous example of 10 and 11 is a reparameterization of internal sub-devices such as power sources to neutralize the error possible if instead of a first addressing power source ( lq _j ) of the jth bus node ( BK _j ) and a first multiplexer ( X3 ) a first addressing power source ( lq _j1 ) of the jth bus node ( BK _j ) and, for example, another first addressing current source ( lq _j2 ) of the jth bus node ( BK _j ), of which the first addressing current source ( lq _j1 ) of the jth bus node ( BK _j ) its first addressing current before the first bus shunt resistor ( R2 ) and the further first addressing current source ( lq _j2 ) of the jth bus node ( BK _j ) its further first addressing current behind the first bus shunt resistor ( R2 ) feeds. In that case, the first detection device ( DET ) the first addressing current of one of the two first addressing current sources ( lq _j1 . lq _j2 ), so that the equivalent effect as with the combination of a first addressing power source ( lq _j ) of the jth Bus node ( BK _j ) with the switchover by a first multiplexer ( X3 ) is achieved.

For the second single-wire bus ( DB _b ) would then instead of a second addressing current source (lq ' _j ) of the jth bus node ( BK _j ) and another second multiplexer ( X3 ' ) a second addressing current source ( lq ' _j1 ) of the jth bus node ( BK _j ) and, for example, another second addressing current source ( lq ' _j2 ) of the jth bus node ( BK _j ), of which the second addressing current source ( lq ' _j1 ) of the jth bus node ( BK _j ) its second addressing current before the second bus shunt resistor ( R2 ' ) and the further second addressing current source ( lq ' _j2 ) of the jth bus node ( BK _j ) its further second addressing current behind the second bus shunt resistor ( R2 ' ) feeds. In that case, the second detection device ( DET ' ) the second addressing current of one of the two second addressing current sources ( lq ' _j1 . lq ' _j2 ), so that the equivalent effect as with the combination of a second addressing current source ( lq ' _j ) of the jth bus node ( BK _j ) with the switchover by a further second multiplexer ( X3 ' ) is achieved.

For example, the first detection device ( DET ) recognize that the first control value of the first control signal ( rw _j ) of the jth bus node ( BK _j ) the first addressing current of the first addressing current source ( lq _j ) maximizes. This may, for example, with a suitable construction by comparison of the first control value of the first control signal ( rw _j ) with a tenth threshold (Ref10). Is the derivative of the first addressing current of the first auto-addressing power source ( lq _j ) after the first control value of the first control signal ( rw _j ) positive, this means that the first control value of the first control signal ( rw _j ) above the tenth threshold ( Ref10 ) lies. Furthermore, the first detection device ( DET ) at the same time the output ( ds2 ) of the second differential amplifier ( D2 ) with an eleventh threshold ( Ref11 ) to compare. If the value of the output ( ds2 ) of the second differential amplifier ( D2 ) below the eleventh threshold ( Ref11 ), the first detection device ( DET ) to a negative voltage drop across the first bus shunt resistor ( R2 ) or a voltage drop across the first bus shunt resistor ( R2 close close to zero. This condition is illegal because the first auto-addressing power source ( lq _j ) yes provides a positive first addressing current which, when correctly mounted by the first bus shunt resistor ( R2 ), which obviously does not happen.

For example, in addition, the second detection device ( DET ' ) recognize that the second control value of the second control signal ( rw _'j ) of the jth bus node ( BK _j ) the second addressing current of the second addressing current source ( lq ' _j ) maximizes. By suitable construction, for example, this can be done by comparing the second control value of the second control signal ( rw _'j ) with another tenth threshold ( Ref10 ' ), preferably equal to the tenth threshold ( Ref10 ). Is the derivative of the second addressing current of the second auto-addressing power source ( lq ' _j ) after the second control value of the second control signal ( rw _'j ) positive, this means that the second control value of the second control signal ( rw _'j ) above the further tenth threshold ( Ref10 ' ), which is preferably equal to the tenth threshold ( Ref10 ). Furthermore, the second detection device ( DET ' ) simultaneously the further output ( ds2 ' ) of the further second differential amplifier ( D2 ' ) with another eleventh threshold ( Ref11 ') to compare. The further eleventh threshold ( Ref11 ' ) is preferably equal to the eleventh threshold ( Ref11 ). If the value of the further output ( ds2 ' ) of the further second differential amplifier ( D2 ' ) below the further eleventh threshold ( Ref11 ), the second detection device ( DET ' ) to a negative voltage drop across the second bus shunt resistor ( R2 ' ) or a voltage drop across the second bus shunt resistor ( R2 ' close close to zero. This condition is illegal because the second auto-addressing power source ( lq ' _j ) yes provides a positive second addressing current which, when correctly mounted by the second bus shunt resistor ( R2 ' ), which obviously does not happen.

Preferably, the first detection device ( DET ) and the second detection device ( DET ' ) one unity.

Switching the direction of the bus, as described above, preferably takes place only if both detection devices ( DET . DET ' ) recognize a permutation of the bus connections.

A detected error can be detected by the detection devices ( DET . DET ' ), for example via a respective error signal ( he . he' ) signal to a bus node internal computer or a suitable controller.

The test results can be determined by the bus node ( BK _j ) or a sub-device ( DET . DET ' ) of the bus node ( BK _j ) can be used to initiate and take predetermined actions when one or more of the detection devices ( DET . DET ' ) not plausible internal signals within the bus node ( BK _j ) determine. For example, the bus node ( BK _j ) assume an interchange of input and output. In order to be able to compensate for this, it is advantageous if the bus node ( BK _j ) a first sub-device ( X3 ) having the input point of the first addressing current of the first addressing current source ( lq _j ) and / or if the bus node ( BK _j ) a second sub-device ( X3 ' ) having the input point of the second addressing current of the second addressing current source ( lq ' _j ) can change. The changes for the activation of the first single-wire bus ( DB _a ) and the first bus shunt resistor ( R2 ) in synchronism with the analog changes for the control of the second single-wire bus ( DB _b ) and the second bus shunt resistor ( R2 ' ) carried out. Instead of switching the feed-in point of the addressing current sources ( iq _j and iq ' _j ) by means of said multiplexer ( X3 . X3 ' ) is also the use of two different first addressing current sources ( lq _j1 and lq _j2 ) instead of a single first addressing power source ( lq _j ) conceivable, what the switching by means of the multiplexer ( X3 ) in a reversing between these two first addressing current sources ( lq _j1 and lq _j2 ) transformed. Such a bus node ( BK _j ) thus has instead of a first addressing current source ( lq _j ) a first Addressing current source ( lq _j1 ) and another first addressing current source ( lq _j2 ), the first addressing current source ( lq _j1 ) its first addressing current in one with the first terminal of the first bus shunt resistor ( R2 ) feeds in connected node, and wherein the further first addressing current source ( lq _j1 ) its first addressing current in one with the second terminal of the first bus shunt resistor ( R2 ) feeds in connected nodes when feeding power. The first two addressing current sources ( lq _j1 . lq _j2 ) preferably feed their addressing currents so that the resulting total addressing current is the first bus shunt resistor ( R2 ), which ensures the self-testability. The bus node ( BK _j ), in contrast to the prior art, moreover, instead of a second addressing current source ( lq ' _j ) a second addressing current source ( lq ' _j1 ) and another second addressing current source ( lq ' _j2 ), the second addressing current source ( lq ' _j1 ) their addressing current in one with the first terminal of the second bus shunt resistor ( R2 ' ) feeds in connected node, and wherein the further second addressing current source ( lq ' _j1 ) their addressing current in one with the second terminal of the second bus shunt resistor ( R2 ' ) feeds in connected nodes when feeding power. These two second addressing current sources ( lq ' _j1 . lq ' _j2 ) preferentially feed their addressing currents such that the addressing current drives the second bus shunt resistor ( R2 ' ) to ensure the self-test capability.

If several bus nodes are now connected to one another on a data bus, it must be ensured that there are no dangerous overcurrent situations due to overshoots of the bus total current. Therefore, it has proved to be advantageous if the first addressing current source ( lq _j ) the first addressing current having a first time constant ( τ ₁ ) and with a second time constant ( τ ₂ ), which is smaller than the first time constant ( τ ₁ ) and / or if the second addressing current source ( lq ' _j ) the second addressing current with a third time constant ( τ ₃ ) and with a fourth time constant ( τ ₄ ) which is less than the third time constant ( τ ₃ ). Preferably, the third time constant ( τ ₃ ) and the first time constant ( τ ₁ ) is selected to be the same in order to ensure bus symmetry dynamically. For the same reason, the fourth time constant ( τ ₄ ) and the second time constant ( τ ₂ ) is selected to be equal in order to dynamically ensure the bus symmetry. It is here again on the 7 to 9 directed.

REDUCTION OF THE BUS RESISTANCE IN NORMAL OPERATION

It will be up here 12 directed. It has now been proven that the bus shunt resistors ( R2 . R2 ' ) the properties of the single-wire buses ( DB _a . DB _b ) and thus of the serial, bidirectional, differential two-wire communication bus ( DB ) deteriorate. Therefore, it was recognized that it makes sense with a first bus shunt bypass switch ( S4 ) per bus node ( BK _j ) the associated first bus shunt resistor ( R2 ) of the bus node ( BK _j ) in normal operation, ie in the normal state of the bus node ( BK _j ) and this first bus shunt bypass switch ( S4 ) only in the addressing state and thus only in the addressing state, the first bus shunt resistor ( R2 ) to take effect. In order not to disturb the bus symmetry, it therefore also makes sense to use a second bus shunt bypass switch ( S4 ' ) per bus node ( BK _j ) the associated second bus shunt resistor ( R2 ' ) of the bus node ( BK _j ) in normal operation, ie in the normal state of the bus node ( BK _j ) and this second bus shunt bypass switch ( S4 ' ) only in the addressing state and thus only in the addressing state, the second bus shunt resistor ( R2 ' ) to take effect.

In the previously described bus node ( BK _j ) is thus a bus node ( BK _j ) for carrying out a method for assigning bus addresses to bus nodes of a serial, bidirectional, differential two-wire communication bus ( DB ) be able to. The procedure for assigning bus addresses to bus nodes ( BK ₁ . BK ₂ . BK ₃ , ...... BK _n-1 . BK _n ) of a serial, bidirectional, differential two-wire communication bus ( DB ) by means of first bus shunt resistors ( R2 ) and with the aid of second bus shunt resistors ( R2 ' ) in the individual bus nodes ( BK ₁ . BK ₂ . BK ₃ , ...... BK _n-1 . BK _n ) in a grant period in which the bus nodes ( BK ₁ to BK _n ) are in an addressing state, which makes this method significantly different from the prior art. After carrying out the method for assigning bus addresses to the bus nodes ( BK ₁ . BK ₂ . BK ₃ , ...... BK _n-1 . BK _n ) of the serial, bidirectional, differential two-wire communication bus ( DB ) in the award period is followed by an operating period in which the bus nodes are operated normally, ie are in a normal state. The bus node ( BK _j ) is thus distinguished from the prior art by such a first bus shunt resistor ( R2 ) and such a second bus shunt resistor ( R2 ' ) out. The bus node ( BK _j ) each with a first bus shunt bypass switch ( S4 ), which prior to the assignment of a bus address to the bus node ( BK _j ) in the Award period is open and is closed after the assignment of a bus address to the bus node in the award period and which is closed in the operating period. Analog becomes for reasons of symmetry in the bus node ( BK _j ) a second bus shunt bypass switch ( S4 ' ) provided before assigning a bus address to the bus node ( BK _j ) is opened in the assignment period and after assigning a bus address to the bus node ( BK _j ) is closed during the awarding period and closed during the period of operation. These bus shunt bypass switches ( S4 . S4 ' ) massively reduce bus resistance and reduce sensitivity to electromagnetic radiation. So you improve the EMC behavior.

Differential symmetric common-mode and push-pull based auto-addressing Instead of a first addressing current of a first addressing current source ( lq _j ) of a bus node ( BK _j ) and a second addressing current of a second addressing current source ( lq ' _j ) of a bus node ( BK _j ) can also be a common mode source ( GLlq _j ) of a bus node ( BK _j ) with two outputs, both of which have the same common mode current in the first one-wire bus ( DB _a ) and the second single-wire bus ( DB _b ) of the serial bidirectional differential communication bus ( DB ) with the same sign. A first output of these two outputs thus corresponds to the first addressing current source ( lq _j ). The second output then corresponds to the second stress source ( lq ' _j ). The first addressing current of the first addressing current source ( lq _j ) is then equal in magnitude to the second addressing current of the second addressing current source ( lq ' _j ). The use of a single common mode addressing source ( GLlq _j ) has the advantage that only one controlled system is needed.

Instead of a first addressing current of a first addressing current source ( lq _j ) of a bus node ( BK _j ) and a second addressing current of a second addressing current source ( lq ' _j ) of a bus node ( BK _j ) but also a push-pull current source ( GGlq _j ) of a bus node ( BK _j ) with two outputs, both of which have the same differential current in the first one-wire bus ( DB _a ) and the second single-wire bus ( DB _b ) of the serial bidirectional differential communication bus ( DB ) with but different sign feed. A first output of these two outputs thus corresponds to the first addressing current source ( lq _j ). The second output then corresponds again to the second stress source ( lq ' _j ). The first addressing current of the first addressing current source ( lq _j ) is then the same amount but not exactly the same sign the second addressing current of the second Adresssierungsstromquelle ( lq ' _j ). The use of a single push-pull addressing power source (G Llq _j ) also has the advantage that only one controlled system is required.

Mixed solutions using common-mode and push-pull addressing power sources are conceivable.

Accordingly, here is also a bus node ( BK _j ) for a serial, bidirectional, differential two-wire communication bus ( DB ) with a bus master ( ECU ), in which the serial, bidirectional, differential two-wire communication bus ( DB ) a first one-wire bus ( DB ₁ ) and a second single-wire bus ( DB ₂ ). A first bus shunt resistor ( R2 ) in the first single-wire bus ( DB ₁ ), and a second bus shunt resistor ( R2 ' ) inserted in the second single-wire bus ( DB ₂ ) are part of the bus node ( BK _j ). The bus node further comprises a differential first common mode addressing power source ( GLlq _j ) for determining the bus position of the bus node ( BK _j ) in the serial, bidirectional, differential two-wire communication bus ( DB ). The differential first common mode addressing power source ( GLlq _j ) may be a first common mode addressing current component in the kind in the first single-wire bus ( DB _a ) of the serial, bidirectional, differential two-wire communication bus ( DB ) additionally feed in that the first total current ( i _j ) by the first bus shunt resistor ( R2 ) of the bus node ( BK _j ) a predetermined or calculated or otherwise determined first summation current ( I _ref ) corresponds. At the same time, the differential first common mode addressing power source ( GLlq _j ) a magnitude and sign same same common mode addressing current component in of the species in the second single-wire bus ( DB _b ) of the serial, bidirectional, differential two-wire communication bus ( DB ) are fed with the same sign as the sign of the first push-pull addressing current component, so that the second total current ( i ' _j ) by the second bus shunt resistor ( R2 ' ) of the bus node ( BK _j ) also corresponds to the predetermined or calculated or otherwise determined first summation current (Iref). The first common mode addressing current portion of the common mode addressing power source (FIG. GLlq _j ) of the bus node ( BK _j ) flows through the first bus shunt resistor ( R2 ) of the bus node ( BK _j ) in the direction of the bus master ( ECU ). The second common mode addressing current portion of the common mode addressing power source (FIG. GLlq _j ) of the bus node ( BK _j ) flows through the second bus shunt resistor ( R2 ' ) of the bus node ( BK _j ) in the direction of the bus master ( ECU ).

Complementary to the common mode control and push-pull control is possible. It is therefore a bus node ( BK _j ) for a serial, bidirectional, differential two-wire communication bus ( DB ) with a bus master ( ECU ), in which the serial, bidirectional, differential two-wire communication bus ( DB ) a first one-wire bus ( DB ₁ ) and a second single-wire bus ( DB ₂ ) and in which a first bus shunt resistor ( R2 ) into the first single-wire bus ( DB ₁ ) and a second bus shunt resistor ( R2 ' ) into the second single-wire bus ( DB ₂ ) is inserted. The bus node ( BK _j ) then has a differential first push-pull addressing power source ( GGlq _j ) for determining the bus position of the bus node ( BK _j ) in the serial, bidirectional, differential two-wire communication bus ( DB ), which is a first push-pull addressing current component in the kind in the first single-wire bus ( DB _a ) of the serial, bidirectional, differential two-wire communication bus ( DB ) can additionally feed in that the first total current ( i _j ) by the first bus shunt resistor ( R2 ) of the bus node ( BK _j ) a predetermined or calculated or otherwise determined first summation current ( I _ref ) corresponds. The push-pull addressing power source ( GGlq _j ) of the bus node ( BK _j ) feeds the amount of the same second counter-addressing current component in of the species in the second single-wire bus ( DB _b ) of the serial, bidirectional, differential two-wire communication bus ( DB ) is controlled with the opposite sign as the sign of the first push-pull addressing current component, so that the second total current ( i ' _j ) by the second bus shunt resistor ( R2 ' ) of the bus node ( BK _j ) the predetermined or calculated or otherwise determined first summation current ( I _ref ) also corresponds. The first push-pull addressing current component of the push-pull addressing power source ( GGlq _j ) of the bus node ( BK _j ) flows through the first bus shunt resistor ( R2 ) of the bus node ( BK _j ) in the direction of the bus master ( ECU ). The second push-pull addressing current component of the push-pull addressing power source ( GGlq _j ) of the bus node ( BK _j ) flows through the second bus shunt resistor ( R2 ' ) of the bus node ( BK _j ) in the direction of the bus master ( ECU ).

For the control, the bus node ( BK _j ) preferably via first means ( R2 . D2 ) to the current through the first bus shunt resistor ( R2 ) and / or via second means ( R2 ' . D2 ' ) to the current through the second bus shunt resistor ( R2 ' ) to detect.

As previously explained, the ability to reduce the voltage drop across the respective bus shunt resistor (FIG. R2 . R2 ' ) to be used for a self-test. It is therefore a bus node ( BK _j ), in which the detected current through the first bus shunt resistor ( R2 ) is used for a self-test and / or in which the detected current through the second bus shunt resistor ( R2 ' ) is used for a self-test. In this case, the detected voltage drop across the bus shunt resistor is compared with an expected value. If the detected voltage deviates from the expected value by more than a predetermined amount, then there is an error that can be signaled.

Preferably, the proposed bus node ( BK _j ) for this purpose at least one detection device ( DET ), the internal signals ( ds1 . ds3 ) of the bus node ( BK _j ) checks for plausibility. Preferably, the bus node ( BK _j ) or a sub-device ( DET ) of the bus node ( BK _j ) Measures when the detection device ( DET ) not plausible internal signals within the bus node ( BK _j ). One possible measure can be achieved by a first subdevice ( X3 ) of the bus node ( BK _j ) and / or a second second subdevice ( X3 ' ) of the bus node ( BK _j ) in such a way that the feed-in points of the first common-mode addressing currents of the common-mode addressing power source ( GLlq _j ) by the first sub-device ( X3 ) of the bus node ( BK _j ) and / or the second second sub-device ( X3 ' ) of the bus node ( BK _j ) is changed upon detection of a predetermined error.

Another possible measure can be achieved by a first subdevice ( X3 ) of the bus node ( BK _j ) and / or a second second subdevice ( X3 ' ) of the bus node ( BK _j ) are initiated in such a way that the feed-in points of the first push-pull addressing currents of the push-pull addressing power source ( GGlq _j ) by the first sub-device ( X3 ) of the bus node ( BK _j ) and / or the second second sub-device ( X3 ' ) of the bus node ( BK _j ) is changed upon detection of a predetermined error.

Again, a regulation of the addressing currents with certain time constants is desirable and recommended. It is therefore a bus node ( BK _j ) in which the common mode addressing power source ( GLlq _j ) the common mode addressing current with a first time constant ( τ ₁ ) and with a second time constant ( τ ₂ ), which is smaller than the first time constant ( τ ₁ ).

Analogously, therefore, a bus node ( BK _j ), in which the push-pull addressing current source ( GGlq _j ) the push-pull addressing current having a first time constant ( τ ₁ ) and with a second time constant ( τ ₂ ), which is smaller than the first time constant ( τ ₁ ).

AUTO ADDRESSING BY INTERRUPT CABLE

13 based on 2 , In addition to the addressing method described above, the bus node described above ( BK _j ) used for a data bus system with a serial, bidirectional, differential two-wire communication bus ( DB ) is provided for another auto-addressing method (see 13 ) to get prepared. The relevant bus node ( BK _j ) is then again provided to a method for assigning logical bus node addresses to the bus nodes ( BK ₁ to BK _n ) of the data bus system. The corresponding data bus system then has a bus master ( ECU ) with an address input ( Adr _i0 ) on. The data bus system should again be bus nodes ( BK ₁ to BK _n ) including this bus node ( BK _j ) even with n as a whole positive number. The bus node ( BK _j ) is transmitted via a data line section ( DB ₁ to DB _n ) or the serial bidirectional differential two-wire communication bus ( DB ) from data line sections ( DB ₁ to DB _n ) and further bus nodes ( BK ₂ to BK _n ) with the bus master ( ECU ) connected to the data transmission. Within the data bus system is a line ( L ₁ to L _n ) from an address input ( Adr _i0 ) of the bus master ( ECU ) of the data bus system, starting from all bus nodes ( BK ₁ to BK _n ) of the data bus system including this bus node ( BK _j ) itself looped through by the individual bus nodes ( BK ₁ to BK _n ) including this bus node ( BK _j ) even in n line sections ( L ₁ to L _n ) is divided. Each of the bus nodes ( BK _j ) includes an associated address input ( Adr _ij ) and a bus node ( BK _j ) associated address output ( Adr _oj ). Each of the bus nodes ( BK _j ) with 1≤j≤n-1 if it is not the nth bus node ( BK _n ), is provided in each case, with its address input ( Adr _ij ) with the address output ( Adr _{o (j + 1)} ) of a subsequent bus node ( BK _{j + 1} ) with 1≤j≤n-1 through a subsequent bus node ( BK _{j + 1} ) associated line section ( L _{j + 1} ) to be connected. Each of the bus nodes ( BK _j ), if it is not the first bus node ( BK ₁ ), with its address output ( Adr _oj ) with the address input ( Adr _{i (j-1)} ) of a preceding bus node ( BK _j-1 ) with 2≤j≤n through a bus node ( BK _j ) associated line section ( L _j ) connected. The first bus node ( BK ₁ ) is (j = 1), with its address output ( Adr _oj ) with the address input ( Adr _i0 ) of the bus master ( ECU ) by a bus node ( BK _j ) associated line section ( L ₁ ) connected. The bus node address of the bus node ( BK _j ) in its bus node address register ( BKADR _j ) may be valid or not valid as in this entire document. The proposed bus node now provides means and methods to set its bus node address and make its bus node address valid or invalid. This can eg special data content ( DATA ) of bit packets ( BP ) of the bus master ( ECU ), with which the bus master ( ECU ) single or multiple or all bus nodes ( BK ₁ to BK _n ) to invalidate the addresses in can force their bus node address registers. The proposed bus node ( BK _j ) can assume an addressing state and a second operating state (or normal state) different from the addressing state. The bus node ( BK _j ) preferably has means for switching between the addressing state and the second operating state in Dependence on commands of the bus master ( ECU ) switch. The bus node ( BK _j ) then has means for, when it is in the addressing state and if its bus node address is invalid, in this case the logic state at the address input ( Adr _{i (j-1)} ) of a preceding bus node ( BK _j-1 ) to a first logical value by overwriting or, if it is in the addressing state and if its bus node address is invalid, in this case the logic state at the address input ( Adr _i0 ) of a preceding bus master ( ECU ) to a first logical value by overwriting. The bus node ( BK _j ) further preferably has means for, in the addressing state, the logic state at its address input ( Adr _ij ) to a second logical value if this second logical value is not passed through a subsequent bus node ( BK _{j + 1} ) is overwritten with a first logical value, and means for switching on by the bus master ( ECU ) signaled bus node address as its valid future bus node address if its bus node address is invalid and if it is in the addressing state and if its address input ( Adr _ij ) has a second logical value, and this future bus node address in mark this case as "valid".

In a refinement of this proposal, the address input ( Adr _ij ) of the bus node ( BK _j ) in the second operating state as input of an interrupt signal of a subsequent bus node ( BK _j-1 ) be used. In this way, an interrupt line for the auto-addressing of bus nodes of a serial, bidirectional, differential two-wire communication bus ( DB ) be used. Preferably, the address output ( Adr _oj ) of the bus node ( BK _j ) in the second operating state as an output of an interrupt signal of a subsequent bus node ( BK _j-1 ) and / or the bus node ( BK _j ) yourself.

14 describes the basic procedure of the preferred address allocation method described here. After the start of the address allocation procedure ( BEGIN ) the bus master (BM) signals in a first step ( 1 ) by means of a preferred first broadcast command a bus node or preferably all or at least part of the set of bus nodes ( BK ₁ to BK _n ) that such a procedure for assigning bus node addresses for these bus nodes is started. On the one hand, this has the consequence that all these bus nodes ( BK ₁ to BK _n ) invalidate or delete any existing valid bus node addresses in this bus node. Should the addressing be carried out with the aid of an interrupt line looped through all bus nodes ( L ₁ to L _n ) as in 13 In this preferred version of the proposal, this interrupt line ( L ₁ to L _n ) for the duration of the addressing operation, and is placed in the said point-to-point connections between the bus nodes ( BK ₁ to BK _n ) and the point-to-point connection between the first LED bus node ( BK ₁ ) and the bus master ( BM ) split. In a second process step ( 2 ) the bus master ( ECU ) the bus node ( BK ₁ to BK _n ) that a bus node address is to be allocated and which logical bus node address this is. The one bus node, here by way of example for better clarity and arbitrarily the jth bus node ( BK _j ) whose address input ( Adr _ij ) has a second logical value, then takes over from the bus master ( BM ) offered Buskotenadresse in this step and sets its address output ( Adr _oj ) in the way that it receives the address input ( Adr _{i (j-1)} ) of a preceding bus node ( BK _j-1 ) no longer overrides the first logical value but a second logical value at which the address input ( Adr _{i (j-1)} ) of a preceding bus node ( BK _j-1 ) allows. This second logical value is then preferred by the preceding bus node ( BK _j-1 ) even at its address input ( Adr _{i (j-1)} ) imprinted. In a further third step ( 3 ) the bus master ( ECU ), whether the logical value at its address input ( Adr _i0 ) corresponds to a second logical value or not. Complies he not ( N ), the bus master repeats ( ECU ) the second process step ( 2 ). Complies he this logical value (J), the bus master ends ( ECU ) the method by performing a fourth method step ( 4 ). Possibly. He carries out a check on the correct assignment beforehand. Preferably, the bus master ( ECU ) upon successful assignment of all bus addresses, a message to all bus nodes ( BK ₁ to BK _n ) that the bus node addresses have been assigned. This causes the bus nodes ( BK ₁ to BK _n ) again from the addressing state associated with the first step ( 1 ) was in another operating state, preferably the normal operating state or normal state. In particular, the bus nodes ( BK ₁ to BK _n ) after performing this fourth method step, a looped interrupt line possibly used for the point-to-point connections again as an interrupt line. This completes the proposed procedure as such (END).

SYMMETRIC AUTOADRESSION PROCEDURE OVER BUS SHUNT RESISTORS

Here is a method for addressing the bus node ( BK ₁ to BK _n ) of a data bus system by means of a symmetric method.

It is a car addressing method for addressing the bus nodes ( BK ₁ to BK _n ) of a data bus system based on a serial, bidirectional, differential two-wire communication bus ( DB ). The data bus system includes a bus master ( ECU ), one from the bus master ( ECU ) outgoing serial, bidirectional, differential two-wire communication bus ( DB ) and a plurality of addressable bus nodes ( BK ₁ to BK _n ) connected to the serial bidirectional differential two-wire communication bus ( DB ) are connected. The serial, bidirectional, differential, two-wire communication bus ( DB ) consists of said first single-wire bus ( DB _a ) and the said second single-wire bus ( DB _b ). Each not yet addressed bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) does not have a valid bus node address and therefore feeds a first addressing current for identification in the first single-wire bus ( DB _a ) and a second addressing current in the second single-wire bus ( DB _b ) on. All of these addressing currents flow through the serial, bi-directional, differential two-wire communication bus ( DB ) in the direction of the bus master ( ECU ). Each not yet addressed bus node ( BK _j ) detects the signal transmitted through the first single-wire bus ( DB _a ) of the serial, bidirectional, differential two-wire communication bus ( DB ) flowing first current and by the second single-wire bus ( DB _b ) of the serial, bidirectional, differential two-wire communication bus ( DB ) flowing second stream. Only one, not yet addressed bus node ( BK _j ) that does not detect a first current or only a first current that is less than a predeterminable first threshold and that does not simultaneously detect a second current or only a second current that is less than a predeterminable other first threshold is considered to be unaddressed Bus node identified. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. The aforementioned steps are performed without the last addressed bus node until all not yet addressed bus nodes are addressed. Preferably, wherein the first threshold value is equal to the further first threshold value and the value of the first addressing current within a bus node is equal to the value of the second addressing current within this bus node.

To the serial, bidirectional, differential two-wire communication bus ( DB ) can be connected in addition to the addressed, ie provided with a valid bus node address bus node and non-addressed bus node without a valid bus node address. The non-addressed bus node feeds into the first single-wire bus ( DB _a ) a first quiescent current and in the second single-wire bus ( DB _b ) enter a second quiescent current. Each not yet addressed bus node detects before the feeding of the addressing currents through the first single-wire bus ( DB _a ) flowing first quiescent current and by the second single-wire bus ( DB _b ) flowing second quiescent current. Only the not yet addressed bus nodes with an invalid bus node address feed the first addressing currents in the first single-wire bus ( DB _a ) and the second addressing currents in the second single-wire bus ( DB _b ) on. Only the one not yet addressed bus node which detects no current difference of the first or second current or only a current difference of the first or second current when feeding the addressing currents through all not yet addressed bus node compared to the previous current detection, which is smaller than a predetermined second threshold identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. The aforementioned steps are carried out without the respectively last addressed bus node until all not yet addressed bus nodes are addressed. The second threshold value is preferably equal to the first threshold value or the further first threshold value.

In a further variant of the method, each addressable bus node feeds into the first single-wire bus (FIG. DB _a ) a first quiescent current, which may be zero, and in the second single-wire bus ( DB _b ) a second quiescent current, which can be zero. Each not yet addressed bus node without a valid bus node address feeds a first quiescent current in the first single-wire bus ( DB _a ) and a second quiescent current into the second single-wire bus ( DB _b ) on. Each not yet addressed bus node detects the signal through the first single-wire bus ( DB _a ) on the basis of the quiescent current supply flowing first current and by the second single-wire bus ( DB _b ) due to the quiescent current feed flowing second stream. In this case, it is determined which of the not yet addressed bus node detects a first current which is above a predefinable third threshold value, and which of the not yet addressed bus node detects a second current which is above a predefinable further third threshold value. Only those not yet addressed bus nodes, which detect a first current when feeding the quiescent currents, which is smaller than the third threshold value or equal to the third threshold value, feed first addressing currents into the first single-wire bus (FIG. DB _a ) and only those not yet addressed bus node, which detect a second current when feeding the quiescent currents, which is smaller than the further third threshold value or equal to the further third threshold, preferably feed second addressing currents into the second single-wire bus ( DB _b ) on. Preferably, at this point, if only those not yet addressed bus node, which detect a first current when feeding the quiescent currents, which is smaller than the third threshold or equal to the third threshold, and at the same time detect a second current when feeding the quiescent currents is smaller than the further third threshold value or equal to the further third threshold value, first addressing currents in the first single-wire bus ( DB _a ) and / or second addressing currents in the second single-wire bus ( DB _b ) feed.

From the group of these addressing currents feeding, not yet addressed bus node is only the one bus node that detects no first stream or only a first stream that is smaller than a predetermined fourth threshold, and detects no second stream or only a second stream that is smaller as a predeterminable further fourth threshold is identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing. The aforementioned steps are performed without the last addressed bus node until all not yet addressed bus nodes are addressed. Preferably, the third and / or fourth threshold value and / or the further third and / or further fourth threshold value and the first threshold value are the same.

In a variant of the method, the serial, bidirectional, differential two-wire communication bus ( DB ) in addition to the addressable bus node and non-addressable bus node connected. Such a non-addressable bus node feeds into the first single-wire bus ( DB _a ) a first quiescent current and in the second single-wire bus ( DB _b ) enter a second quiescent current. Each not yet addressed bus node determined before feeding the first addressing currents in the first single-wire bus ( DB _a ) in the first single-wire bus ( DB _a ) due to the quiescent current feed of all non-addressable bus node flowing first current through a first current detection. Each not yet addressed bus node determined before feeding the second addressing currents in the second single-wire bus ( DB _b ) in the second single-wire bus ( DB _b ) due to the quiescent current feed of all non-addressable bus node flowing second stream through a second current detection. Subsequently, each addressable bus node feeds in the first single-wire bus ( DB _a ) a first Quiescent current and into the second single-wire bus ( DB _b ) enter a second quiescent current. It is determined which of the not yet addressed bus node, a first stream in the first single-wire bus ( DB _a ), which is above a predefinable fifth threshold, and / or a second current in the second single-wire bus ( DB _b ), which is above a predefinable further fifth threshold. Only those not yet addressed bus node, when feeding the first quiescent currents in the first single-wire bus ( DB _a ) detect a first current that is less than the fifth threshold or equal to the fifth threshold, feed first addressing currents in the first single-wire bus ( DB _a ) on. Only those not yet addressed bus node, when feeding the second quiescent currents in the second single-wire bus ( DB _b ) detect a second current that is less than the further fifth threshold or equal to the further fifth threshold, feed second addressing currents in the second single-wire bus ( DB _b ) on. However, it is particularly preferred if only those not yet addressed bus node, when feeding the first quiescent currents in the first single-wire bus ( DB _a ) detect a first current that is less than the fifth threshold or equal to the fifth threshold, and at the same time when feeding the second quiescent currents in the second single-wire bus ( DB _b ) detect a second current that is less than the further fifth threshold or equal to the further fifth threshold, first addressing currents in the first single-wire bus ( DB _a ) and second addressing currents in the second single-wire bus ( DB _b ) feed.

From the group of these addressing currents feeding, not yet addressed bus node is only the one bus node, compared to the first current detection no current difference of the first current or only a current difference of the first current detected, which is smaller than a predetermined sixth threshold, and the opposite to the first current detection detects no current difference of the second current or only a current difference of the second current, which is smaller than a predeterminable further sixth threshold, identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing. The aforementioned steps are performed without the last addressed bus node until all not yet addressed bus nodes are addressed. The fifth threshold value and / or the sixth threshold value and / or the further fifth threshold value and / or the further sixth threshold value and / or the first threshold value are preferably the same.

The first current detection is preferably carried out in the bus node via the addressable bus node associated first bus shunt resistors ( R2 ) of the first single-wire bus ( DB _a ) and the second current detection is preferably carried out in the bus node via the addressable bus node associated second bus shunt resistors ( R2 ' ) of the second single-wire bus ( DB _b ). The first bus shunt resistors assigned to an addressable bus node ( R2 ) preferably correspond to the second bus shunt resistors assigned to the respective addressable bus node ( R2 ' ) at least in terms of value. All first bus shunt resistors ( R2 ) are preferred in the first single-wire bus ( DB _a ) along the first single-wire bus ( DB _a ) in series and all second bus shunt resistors ( R2 ' ) are preferred in the second single-wire bus ( DB _b ) along the second single-wire bus ( DB _b ) in series.

Instead of a current detection can also be a voltage detection in take the bus node.

The assignment of an address is then typically done by transmitting an address to the identified bus node in that all not yet addressed bus node before the identification of a bus node respectively the same address is transmitted and only the subsequently identified bus node accepts this address as its bus node address.

Preferably, the assignment of an address after the first identification of a bus node and / or a verification of the bus node address after the identification of a bus node.

The verification of the identification of a bus node can be done, for example, by re-identifying the bus node and / or by identifying the bus node by means of the other single-wire bus and comparing the second identification with the first identification.

The verification of the identification of a subscriber can also be done by re-identifying the subscriber by means of another auto-addressing method and comparing the second identification with the first identification. Any errors that occur are signaled.

ASYMMETRIC AUTOADRESSION PROCEDURE OVER BUS SHUNT RESISTORS

The data bus system has a bus master ( ECU ), one from the bus master ( ECU ) outgoing serial, bidirectional, differential two-wire communication bus ( DB ) and several addressable bus nodes ( BK ₁ to BK _n ) connected to the serial bidirectional differential two-wire communication bus ( DB ) are connected. The serial, bidirectional, differential, two-wire communication bus ( DB ) again consists of a first single-wire bus ( DB _a ) and a second one Single wire bus ( DB _b ). In the first auto-addressing method discussed here, each bus node not yet addressed feeds ( BK _j ) the bus node ( BK ₁ to BK _n ) for identifying an addressing current in at least ONE single-wire bus of the single-wire buses ( DB _a . DB _b ) on. Each not yet addressed bus node feeds the addressing current at least into a single-wire bus, hereinafter referred to as addressing single-wire bus. However, it is preferred if this addressing current in both single-wire buses ( DB _a . DB _b ) is fed. All other bus nodes not yet addressed also feed their respective addressing current into the addressing single-wire bus. In this case, all addressing currents flow through the serial, bidirectional, differential two-wire communication bus ( DB ) in the direction of the bus master ( ECU ). Each not yet addressed bus node ( BK _j ) detects the signal passing through the addressing single-wire bus of the serial bidirectional differential two-wire communication bus ( DB ) flowing electricity. This detection is preferably done via the already mentioned bus shunt resistors ( R2 . R2 ' ). Only the one not yet addressed bus node ( BK _j ) that detects no current or only a current that is less than a predeterminable first threshold is identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. This is preferred by the bus master ( ECU ) certainly. The aforementioned steps are carried out again without the respectively last addressed bus node, so a further Initialisierungsdurchlauf made until all not yet addressed bus nodes are addressed.

It may happen that the serial, bidirectional, differential two-wire communication bus ( DB ) in addition to the addressed bus node and one or more non-addressed bus nodes are connected, which feed a quiescent currents in the addressing single-wire. In this case, the method described above must be modified. This modification then requires that each not yet addressed bus node detect the quiescent current flowing through the addressing one-wire bus prior to feeding the addressing currents. Only the not yet addressed bus nodes feed the addressing currents in the addressing single wire bus. Only the one not yet addressed bus node, which detects no current difference or only a current difference that is smaller than a predefinable second threshold when feeding the addressing currents through all not yet addressed bus node compared to the previous current detection is identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. The aforementioned steps are performed without the last addressed bus node until all not yet addressed bus nodes are addressed. Incidentally, by the way, the second threshold value is equal to the first threshold value.

Incidentally, it can also happen that any addressable bus node in feeds a quiescent current to the addressing single-wire bus, and that each not yet addressed bus node has a quiescent current in feeds the addressing single-wire bus. The method is then modified in a manner similar to that described above: each not yet addressed bus node again detects the current flowing through the addressing single-wire bus due to the quiescent current feed. A circuit within the bus node ( BK _j ) then determines which of the not yet addressed bus node detects a current that is above a predefinable third threshold. Only those not yet addressed bus node, which detect a current that is less than the third threshold or equal to the third threshold when feeding the quiescent currents, feed addressing currents in the addressing single-wire bus. From the group of these addressing currents feeding, not yet addressed bus node only that bus node that detects no current or only a current that is smaller than a predetermined fourth threshold, identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. The aforementioned steps are carried out again without the respectively last addressed bus node until all not yet addressed bus nodes are addressed. Here too, the third and / or fourth threshold value is preferably equal to the first threshold value.

Again, it may happen that the serial, bidirectional, differential two-wire communication bus ( DB ) in addition to the addressable bus node and at least one non-addressable bus node is connected, which feeds a quiescent current in the addressing single-wire. Again, the method is suitably modified: Each bus node not yet addressed detects the current flowing in the addressing single-wire bus due to the quiescent current feed of all non-addressable bus nodes through a first current detection before feeding the addressing currents. Subsequently, each addressable bus node feeds a quiescent current into the addressing single-wire bus. It is then determined which of the not yet addressed bus node detects a current which is above a predefinable fifth threshold value. Only those not yet addressed bus node, which detect a current when feeding the quiescent currents, the is less than the fifth threshold or equal to the fifth threshold, feeds addressing currents into the addressing single-wire bus. From the group of these addressing currents feeding, not yet addressed bus node is only that bus node that detects no current difference or only a current difference compared to the first current detection, which is smaller than a predetermined sixth threshold, identified as a not yet addressed bus node. The bus node identified in this way is assigned an address for the purpose of addressing, whereby it receives a valid bus node address. The aforementioned steps are carried out again without the respectively last addressed bus node until all not yet addressed bus nodes are addressed. Again, the fifth threshold and / or sixth threshold is preferably equal to the first threshold.

The current detection in the bus node preferably takes place via the addressable bus node assigned shunt resistors of the addressing single-wire bus, wherein in the other single-wire bus, which is not the addressing single-wire, in the participants the addressable participants associated with further bus shunt resistors preferred, but are not necessarily arranged, which each preferably correspond in value to the shunt resistors in the addressing single-wire bus. Most preferably, the bus shunt resistors match ( R2 . R2 ' ) in the two single-wire buses ( DB _a . DB _b ) together. All shunt resistors in the addressing single-wire bus along the addressing single-wire bus are preferably connected in series. All shunt resistors in the other single-wire bus along this other single-wire bus are preferably also connected in series.

It is possible to make a voltage detection in the bus node instead of a current detection.

A variant of the method provides that the assignment of an address by transmitting an address to the identified bus node or takes place in that all not yet addressed bus node before the identification of a bus node in each case the same address is transmitted and that only the subsequently identified bus node this address as its bus node address.

A further variant of the proposed method provides that the assignment of an address takes place after the first identification of a bus node or that a verification of the bus node address takes place after the identification of a bus node.

A further variant of the proposed method provides that the verification of the identification of a bus node by re-identifying the bus node and / or by identifying the bus node by means of the other single-wire bus and comparison of the second identification with the first identification.

A further variant of the proposed method provides that the verification of the identification of a subscriber is carried out by again identifying the subscriber by means of another auto-addressing method and comparing the second identification with the first identification. Preferably, the bus node and / or the bus master then signal an error.

SYMMETRIC AUTOADRESSION PROCESS VIA BUS SHUNT RESISTORS WITH SELF-TESTING EFFICIENCY AND ADDRESSING POWER CONTROL

• • Signalisierung einer zu vergebenden Busadresse an alle Autoadressierungsbusknoten der n Busknoten (BK₁ , BK₂ , ..... BK_n-1 , BK_n );
• • Durchführung der folgenden Schritte für jeden Autoadressierungsbusknoten (BK_j ) der Autoadressierungsbusknoten der n Busknoten (BK₁ , BK₂ , ..... BK_n-1 , BK_n ), im Folgenden als betreffender Autoadressierungsbusknoten (BK_j ) bezeichnet:
  • ■ Empfang des besagten Autoadressierungskommandos vom Busmaster (ECU) durch den betreffenden Autoadressierungsbusknoten (BK_j );
  • ■ Empfang der zu vergebenden Busadresse vom Busmaster (ECU) durch den betreffenden Autoadressierungsbusknoten (BK_j );
  • ■ Empfang eines Startsignals für die Vergabe der zu vergebenden Busadresse vom Busmaster (ECU) durch den betreffenden Autoadressierungsbusknoten (BK_j ) und Start eines Zeitgebers durch den betreffenden Autoadressierungsbusknoten (BK_j );
  • ■ Einspeisen des von den nachfolgenden Busknoten (BK_j+1 , BK_j+2 ... BK_n-1 , BK_n ) empfangenen ersten Buseingangsstroms (i_(j+1) ) über den Abschnitt (DB₁ ) des ersten Eindrahtbusses (DB_a ), der Teil des Verbindungsabschnitts des seriellen, bidirektionalen, differentiellen Zweidraht-Kommunikationsbusses (DB) zwischen dem betreffenden Autoadressierungsbusknotens (BK_j ) und dem vorausgehenden (j-1)-ten Busknoten (BK_j-1 ) ist, als Teil des ersten Busausgangsstroms (i_j ) des betreffenden Autoadressierungsbusknotens (BK_j );
  • ■ Einspeisen des von den nachfolgenden Busknoten (BK_j+1 , BK_j+2 ...) empfangenen zweiten Buseingangsstroms (i'_(j+1) ) über den Abschnitt (DB₂ ) des zweiten Eindrahtbusses (DB_b ), der Teil des Verbindungsabschnitts des seriellen, bidirektionalen, differentiellen Zweidraht-Kommunikationsbusses (DB) zwischen dem betreffenden Autoadressierungsbusknotens (BK_j ) und dem vorausgehenden (j-1)-ten Busknoten (BK_j-1 ) ist, als Teil des zweiten Busausgangsstroms (i'_j ) des betreffenden Autoadressierungsbusknotens (BK_j );
  • ■ Erfassen des ersten Werts des ersten Busknotenausgangsstroms (i_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mittels erster Messmittel (R2, D2, D3);
  • ■ Erfassen des zweiten Werts des zweiten Busknotenausgangsstroms (i'_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mittels zweiter Messmittel (R2', D2', D3');
  • ■ Erzeugung eines ersten Regelsignals (rw_j ) aus dem erfassten ersten Wert des ersten Busknotenausgangsstroms (i_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mittels ersten Mitteln zum Regeln (F);
  • ■ Erzeugung eines zweiten Regelsignals (rw'_j ) aus dem erfassten zweiten Wert des zweiten Busknotenausgangsstroms (i'_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mittels zweiten Mitteln zum Regeln (F');
  • ■ Ausregeln des ersten Busknotenausgangsstroms (i_j ) durch den betreffenden Autoadressierungsbusknoten (BK_j ), mittels einer ersten geregelten Autoadressierungsstromquelle (Iq_j ), deren erster Adressierungsstrom einen Anteil des ersten Busausgangsstromes (i_j ) darstellt, auf einen ersten vorgegebenen Summenstromwert (I_ref ) in Abhängigkeit von dem erzeugten ersten Regelsignal (rw_j ), wobei eine Erhöhung des ersten Adressierungsstroms der ersten geregelten Autoadressierungsstromquelle (Iq_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mit einer ersten Zeitkonstante (τ₁ ) erfolgt und wobei eine Erniedrigung des ersten Adressierungsstroms der ersten geregelten Autoadressierungsstromquelle (Iq_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mit einer zweiten Zeitkonstante (τ₂ ) erfolgt und wobei die zweite Zeitkonstante (τ₂ ) kleiner ist als die erste Zeitkonstante (τ₁ );
  • ■ Ausregeln des zweiten Busknotenausgangsstroms (i'_j ) durch den betreffenden Autoadressierungsbusknoten (BK_j ), mittels einer zweiten geregelten Autoadressierungsstromquelle (Iq'_j ), deren zweiter Adressierungsstrom einen Anteil des zweiten Busausgangsstromes (i'_j ) darstellt, auf einen zweiten vorgegebenen Summenstromwert (I'_ref ) in Abhängigkeit von dem erzeugten zweiten Regelsignal (rw'_j ), wobei eine Erhöhung des zweiten Adressierungsstroms der zweiten geregelten Autoadressierungsstromquelle (Iq'_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mit einer dritten Zeitkonstante (τ₃ ) erfolgt und wobei eine Erniedrigung des zweiten Adressierungsstroms der zweiten geregelten Autoadressierungsstromquelle (Iq'_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mit einer vierten Zeitkonstante (τ₄ ) erfolgt und wobei die vierte Zeitkonstante (τ₄ ) kleiner ist als die dritte Zeitkonstante (τ₃ );
  • ■ Vergleichen des ersten Regelwerts (r_j ) des ersten Regelsignals (rw_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mit einem ersten Schwellwert (SW_j ) des betreffenden Autoadressierungsbusknotens (BK_j );
  • ■ Vergleichen des zweiten Regelwerts (r'_j ) des zweiten Regelsignals (rw'_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) mit einem zweiten Schwellwert (SW'_j) des betreffenden Autoadressierungsbusknotens (BK_j );
  • ■ Einfrieren der Regelung der ersten Adressierungsstromquelle (Iq_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) zu einem ersten Zeitpunkt t₁ nach dem Start des Zeitgebers;
  • ■ Einfrieren der Regelung der zweiten Adressierungsstromquelle (Iq'_j) des betreffenden Autoadressierungsbusknotens (BK_j ) zu einem zweiten Zeitpunkt t₂ nach dem Start des Zeitgebers;
  • ■ Übernahme der zu vergebenden Busknotenadresse vom Busmaster (ECU) als gültige Busknotenadresse des betreffenden Autoadressierungsbusknotens (BK_j ), wenn eine Mindestzeit seit dem Start des Zeitgebers vergangen ist und wenn der Vergleich des ersten Regelwerts (r_j ) mit dem ersten Schwellwert (SW_j ) ergibt, dass der erste Adressierungsstrom der ersten Adressierungsstromquelle (Iq_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) betragsmäßig oberhalb eines Stromschwellwertes liegt und/oder wenn der Vergleich des zweiten Regelwerts (r'_j ) mit dem zweiten Schwellwert (SW'_j ) ergibt, dass der zweite Adressierungsstrom der zweiten Adressierungsstromquelle (Iq_j ) des betreffenden Autoadressierungsbusknotens (BK_j ) betragsmäßig oberhalb eines Stromschwellwertes liegt und Konfiguration des betreffenden Autoadressierungsbusknotens (BK_j ) als Busknoten ohne Autoadressierungsfähigkeit mit der zu vergebenen Busknotenadresse als gültige Busknotenadresse des betreffenden Autoadressierungsbusknotens (BK_j ) zu einem dritten Zeitpunkt t₃ nach dem ersten Zeitpunkt t₁ und nach dem zweiten Zeitpunkt t₂ , wodurch dieser Autoadressierungsbusknoten (BK_j ) bis auf Weiteres nicht mehr an folgenden Initialisierungssequenzen teilnimmt.
• • Überprüfung der erfolgreichen Adressvergabe durch den Busmaster (ECU);
• • Ggf. Löschung der Gültigkeit der letzten vergebenen Busknotenadresse, wodurch die betreffenden Autoadressierungsbusknoten (BK_j ) sich wieder wie Autoadressierungsbusknoten (BK_j ) ohne gültige Busknotenadresse verhalten;
• • Überprüfung ob alle Autoadressierungsbusknoten eine gültige Busknotenadresse erhalten haben;
• • Durchführung einer weiteren Initialisierungssequenz, wenn nicht alle Autoadressierungsbusknoten eine gültige Busknotenadresse erhalten haben.

Furthermore, a self-testable auto addressing method for assigning bus node addresses within a data bus system is proposed. In this case, the data bus system comprises a serial, bidirectional, differential two-wire communication bus ( DB ) with a chain of n bus nodes ( BK ₁ . BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ), with n as the whole positive number greater than zero, and a bus master ( ECU ). The serial, bidirectional, differential two-wire communication bus ( DB ) is connected to the bus master ( ECU ) connected. Each bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) has a preceding bus node ( BK ₁ . BK ₂ . BK ₃ , ..... BK _n-1 ), if it is not the first bus node ( BK ₁ ) and each bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) is connected to its preceding bus node ( BK ₁ . BK ₂ . BK ₃ , ..... BK _n-1 ) through the serial, bidirectional, differential two-wire communication bus ( DB ) by means of a connection section of the serial bidirectional differential two-wire communication bus ( DB ), if it is not the first bus node ( BK ₁ ). The serial, bidirectional, differential two-wire communication bus ( DB ) consists of a first single-wire bus ( DB _a ) and a second single-wire bus ( DB _b ). The first bus node ( BK ₁ ) is connected to the bus master ( ECU ) through the serial, bidirectional, differential two-wire communication bus ( DB ) by means of a connection section of the serial bidirectional differential two-wire communication bus ( DB ) connected. Each bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) sends a first bus node output stream ( i ₂ . i ₃ , .. .i _(n-1) . i _n ) over the section ( DB ₁ ) of the first single-wire bus ( DB _a ), the part of the connection section between this bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) and its preceding bus node ( BK ₁ . BK ₃ , ..... BK _n-1 . BK _n-1 ), to its preceding bus node ( BK ₁ . BK ₂ . BK ₃ , ..... BK _n-1 ), if it is not the first bus node ( BK ₁ ). Each bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) sends a second bus node output stream ( i ' ₂ . i ' ₃ .. 'i' _(n-1) . i _'n ) over the section ( DB ₂ ) of the second single-wire bus ( DB _b ), the part of the connection section between this bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) and its preceding bus node ( BK ₁ . BK ₃ , ..... BK _n-1 . BK _n-1 ), to its preceding bus node ( BK ₁ . BK ₂ . BK ₃ , ..... BK _n-1 ), if it is not the first bus node ( BK ₁ ). The first bus node ( BK ₁ ) sends a first bus node output stream ( i ₁ ) over the section ( DB ₁ ) of the first single-wire bus ( DB _a ), the part of the connection section between the first bus node ( BK ₁ ) and the bus master ( ECU ), to the bus master ( ECU ). The first bus node ( BK ₁ ) sends a second bus node output stream ( i ₂ ) over the section ( DB ₂ ) of the second single-wire bus ( DB _b ), the part of the connection section between the first bus node ( BK ₁ ) and the bus master ( ECU ), to the bus master ( ECU ). The bus master ( ECU ) receives a first bus node input stream ( i ₁ ) over the section ( DB ₁ ) of the first single-wire bus ( DB _a ), the part of the connection section between the first bus node ( BK ₁ ) and the bus master ( ECU ), from its subsequent first bus nodes ( BK ₁ ). The bus master ( ECU ) receives a second bus node input stream ( i ' ₁ ) over the section ( DB ₂ ) of the second single-wire bus ( DB _b ), the part of the connection section between the first bus node ( BK ₁ ) and the bus master ( ECU ), from its subsequent first bus nodes ( BK ₁ ). Each bus node ( BK ₁ . BK ₂ , ..... BK _n-1 ) receives a first bus node input stream ( i ₂ . i ₃ , ... i _(ni) . i _n ) over the section ( DB ₁ ) of the first single-wire bus ( DB _a ), the part of the connection section between this bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) and its preceding bus node ( BK ₁ . BK ₃ , ..... BK _n-1 . BK _n-1 ), from its subsequent bus nodes ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ), if it is not the last bus node ( BK _n ). Each bus node ( BK ₁ . BK ₂ , ..... BK _n-1 ) receives a second bus node input stream ( i ₂ . i ₃ , ... i _(n-1) . i _n ) over the section of the second single-wire bus ( DB _b ), the part of the connection section between this bus node ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ) and its preceding bus node ( BK ₁ . BK ₃ , ..... BK _n-1 . BK _n-1 ), from its subsequent bus nodes ( BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ), if it is not the last bus node ( BK _n ). This method thus uses in contrast to the previously described both single-wire buses ( DB _a and DB _b ) for the transmission of the addressing currents. First, a maximum addressing current ( I _amax ) certainly. The following is the execution of an initialization sequence, which has the following steps, for each auto-addressing bus node of the n bus nodes ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ), which does not yet have a valid bus node address until all the auto-addressing bus nodes of the n bus nodes ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ) have a valid bus node address:

• Signaling of a bus address to be given to all auto-addressing bus nodes of the n bus nodes BK ₁ . BK ₂ , ..... BK _n-1 . BK _n );
• • Carry out the following steps for each auto-addressing bus node ( BK _j ) the auto-addressing bus node of the n bus nodes ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ), hereinafter referred to as the respective car addressing bus node ( BK _j ) designated:
  • ■ Receipt of said auto-addressing command from the bus master ( ECU ) by the relevant auto-addressing bus node ( BK _j );
  • ■ Receipt of the bus address to be issued by the bus master ( ECU ) by the relevant auto-addressing bus node ( BK _j );
  • ■ Receipt of a start signal for assigning the bus address to be assigned by the bus master ( ECU ) by the relevant auto-addressing bus node ( BK _j ) and start of a timer by the respective Autoaddressierungsbusknoten ( BK _j );
  • ■ feeding in of the following bus nodes ( BK _{j + 1} . BK _{j + 2} ... BK _n-1 . BK _n ) received first bus input current ( i _{(j + 1)} ) over the section ( DB ₁ ) of the first single-wire bus ( DB _a ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the relevant auto-addressing bus node ( BK _j ) and the preceding (j-1) th bus node ( BK _j-1 ), as part of the first bus output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j );
  • ■ feeding in of the following bus nodes ( BK _{j + 1} . BK _{j + 2} ...) received second bus input stream ( i ' _{(j + 1)} ) over the section ( DB ₂ ) of the second single-wire bus ( DB _b ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the relevant auto-addressing bus node ( BK _j ) and the preceding (j-1) th bus node ( BK _j-1 ), as part of the second bus output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j );
  • ■ detecting the first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D2 . D3 );
  • ■ detecting the second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D2 ' . D3 ' );
  • ■ Generation of a first control signal ( rw _j ) from the detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first means ( F );
  • ■ Generation of a second control signal ( rw _'j ) from the detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second means ( F ' );
  • ■ Balancing the first bus node output current ( i _j ) by the relevant auto-addressing bus node ( BK _j ), by means of a first regulated auto-addressing power source ( Iq _j ) whose first addressing current comprises a portion of the first bus output current ( i _j ), to a first predetermined total current value ( I _ref ) in dependence on the generated first control signal ( rw _j ), wherein an increase of the first addressing current of the first regulated auto-addressing power source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) with a first time constant ( τ ₁ ) and wherein a reduction of the first addressing current of the first regulated auto-addressing current source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) with a second time constant ( τ ₂ ) and wherein the second time constant ( τ ₂ ) is smaller than the first time constant ( τ ₁ );
  • ■ balancing the second bus node output stream ( i ' _j ) by the relevant auto-addressing bus node ( BK _j ) by means of a second regulated auto-addressing power source ( Iq ' _j ) whose second addressing current comprises a portion of the second bus output current ( i ' _j ), to a second predetermined total current value ( I ' _ref ) in dependence on the generated second control signal ( rw _'j ), wherein an increase of the second addressing current of the second regulated auto-addressing power source ( Iq ' _j ) of the relevant auto-addressing bus node ( BK _j ) with a third time constant ( τ ₃ ) and wherein a reduction of the second addressing current of the second regulated auto-addressing power source ( Iq ' _j ) of the relevant auto-addressing bus node ( BK _j ) with a fourth time constant ( τ ₄ ) and wherein the fourth time constant ( τ ₄ ) is smaller than the third time constant ( τ ₃ );
  • ■ Compare the first rule value ( r _j ) of the first control signal ( rw _j ) of the relevant auto-addressing bus node ( BK _j ) with a first threshold ( SW _j ) of the relevant auto-addressing bus node ( BK _j );
  • ■ Compare the second control value ( r ' _j ) of the second control signal ( rw _'j ) of the relevant auto-addressing bus node ( BK _j ) with a second threshold value (SW ' _j ) of the relevant auto-addressing bus node ( BK _j );
  • ■ Freezing the regulation of the first addressing current source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) at a first time t ₁ after starting the timer;
  • Freezing the control of the second addressing current source (Iq ' _j ) of the relevant auto-addressing bus node ( BK _j ) at a second time t ₂ after starting the timer;
  • ■ Transfer of the bus node address to be assigned by the bus master ( ECU ) as the valid bus node address of the relevant auto-addressing bus node ( BK _j ), if a minimum time has elapsed since the start of the timer and if the comparison of the first control value ( r _j ) with the first threshold ( SW _j ) indicates that the first addressing current of the first addressing current source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) amounts above a current threshold value and / or if the comparison of the second control value ( r ' _j ) with the second threshold ( SW ' _j ) indicates that the second addressing current of the second addressing current source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) is above a current threshold value and configuration of the relevant Autoaddressierungsbusknotens ( BK _j ) as a bus node without Autoaddressierungsfähigkeit with the bus node address to be assigned as a valid bus node address of the respective Autoaddressierungsbusknotens ( BK _j ) at a third time t ₃ after the first time t ₁ and after the second time t ₂ , whereby this auto-addressing bus node ( BK _j ) no longer participates in the following initialization sequences until further notice.
• • Verification of successful address assignment by the bus master ( ECU );
• • Possibly. Deletion of the validity of the last assigned bus node address, whereby the relevant auto-addressing bus nodes ( BK _j ) again like auto-addressing bus nodes ( BK _j ) with no valid bus node address;
• • check if all auto address bus nodes have received a valid bus node address;
• • Execution of a further initialization sequence if not all auto-addressing bus nodes have received a valid bus node address.

This basic method can be supplemented with an additional step after or together with the adoption of the bus node address to be assigned. It then includes bridging the first bus shunt resistor ( R2 ) by means of a first bus shunt bypass switch ( S4 ) and / or bridging the second bus shunt resistor ( R2 ' ) by means of a second bus shunt bypass switch ( S4 ' ) when changing from addressing state with invalid bus node address of the respective bus node ( BK _j ) in the addressing state with valid Busknotenadressse the jeweligen bus node ( BK _j ) or when changing in the normal state. This approach has the advantage that the bus resistance during operation (normal state after address assignment) is reduced.

At the transition in the auto addressing mode (addressing state) or normal state, the bridging of the bus shunt resistors ( R2 . R2 ' ) undone. The method then includes opening the first bus shunt bypass switch (FIG. S4 ), if the bus node address of the relevant auto-addressing bus node ( BK _j ) is not valid, and / or the opening of the second bus shunt bypass switch ( S4 ' ), if the bus node address of the relevant auto-addressing bus node ( BK _j ) is not valid.

The third time constant ( τ ₃ Incidentally, by way of a factor greater than 10, it is preferred that the latter be less than the first time constant (FIG. τ ₁ ) and as the second time constant ( τ ₂ ). The third time constant ( τ ₃ ) preferably hangs in a method variant within the relevant auto-addressing bus node ( BK _j ) of which by means of first measuring means ( R2 . D2 . D3 ) detected first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) and / or by means of second measuring means ( R2 ' . D2 ' . D3 ' ) detected second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ).

The first time constant ( τ ₁ ) within the relevant auto-addressing bus node ( BK _j ) of which by means of first measuring means ( R2 . D1 . D3 ) detected first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) and / or the second time constant ( τ ₂ ) within the relevant auto-addressing bus node ( BK _j ) of which by means of second measuring means ( R2 ' . D1 ' D3 ') detected second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ).

The first time constant ( τ ₁ ) within the relevant auto-addressing bus node (BKj) can be detected by the first measuring means (BKj). R2 . D2 . D3 ) detected value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) depend on the value of the first time constant ( τ ₁ ) has a first value below a threshold value and a second value above this threshold value, and / or by means of second measuring means ( R2 ' . D2 ' . D3 ' ) detected value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) depend on the value of the second time constant ( τ ₂ ) has a third value below a threshold value and a fourth value above this threshold value.

What is important now is that the technique disclosed here enables a self-test. It is therefore advantageous if, in addition, a check of the detected first value of the first bus node output current (FIG. i _j ) and / or the detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is carried out for plausibility and if necessary measures are initiated if the detected first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) and / or the detected second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) or their combination are not plausible.

It is preferable to redetermine the entry point of the first addressing stream ( i _j ) if the detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible. Likewise, a redetermination of the entry point of the first addressing stream ( i _j ) and the feed-in point of the second addressing current ( i ' _j ) if the detected first value of the first bus node output stream ( i _j ) and / or the detected second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) and / or their combination are not plausible.

In a variant, a signaling of an error preferably takes place via the serial bidirectional differential communication bus (FIG. DB ) at the request of a bus master ( ECU ) if the detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) and / or the detected second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) or their combination are not plausible.

In a variant of the method, the step of detecting the first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D1 . D3 ) as detecting the first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D1 . D3 ) with a first sign if the detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is plausible, and detecting the first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D1 . D3 ) with a second sign that is inverted to the first sign if the detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible.

In a further variant of the method, which relates to the other single-wire bus, the step of detecting the second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D1 ' D3 ') as follows: the step comprises detecting the second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D1 ' D3 ') with a first sign, if the detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is plausible, and detecting the second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D1 ' D3 ') having a second sign that is inverted to the first sign if the detected second value of the second bus node output current (' i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible.

A further method variant additionally comprises the detection of the second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D1 ' D3 ') in the following manner: This step comprises first detecting the second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D1 ' D3 ') with a first sign, if the previously detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is plausible and if the previously detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is plausible, and detecting the second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) by means of second measuring means ( R2 ' . D1 ' D3 ' ) with a second sign that is inverted to the first sign if the previously detected first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible or if the previously detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible.

Two values are plausible in the sense of this disclosure, if they are the result of two different tests, which, though not necessarily identical in their construction, should produce an identical result, and which are equal to one another. Equality here means a deviation of the amount of the norm of the results by less than a predetermined threshold value. In the sense of this disclosure, two values are not plausible, if they are the result of two different tests, which, though not necessarily identical in their construction, should yield an identical result, and which are not equal to one another.

Furthermore, this variant comprises performing the step of detecting the first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D1 . D3 ) in the following manner: the step comprises detecting the first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D1 . D3 ) with a first sign if the previously detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is plausible and if the previously detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is plausible, and detecting the first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) by means of first measuring means ( R2 . D1 . D3 ) with a second sign that is inverted to the first sign if the previously detected first value of the first bus node output current ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible or if the previously detected second value of the second bus node output stream ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible.

A variant of the method with plausibility checks comprises the use of an error address as the valid bus node address of the relevant auto-addressing bus node ( BK _j ) if the detected first value of the first bus node output stream ( i _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible or if the detected second value of the second bus node output current ( i ' _j ) of the relevant auto-addressing bus node ( BK _j ) is not plausible.

AUTOADRESSING PROCEDURE VIA INTERRUPT CABLE

• Hierbei handelt es sich um ein Verfahren zur Vergabe von logischen Busknotenadressen an die Busknoten (BK₁ bis BK_n ) eines Datenbussystems mit einem seriellen, bidirektionalen, differentiellen Zweidraht-Kommunikationsbus (DB), bei dem das Datenbussystem einen Busmaster (ECU) mit einem Adresseingang (Adr_i0 ) und n Busknoten (BK₁ bis BK_n ) (mit n als ganzer positiver Zahl) aufweist. Jeder der n Busknoten (BK₂ bis BK_n ) ist über einen Datenleitungsabschnitt (DB₁ bis DB_b ) oder einen seriellen, bidirektionalen, differentiellen Zweidraht-Kommunikationsbus (DB) mit dem Busmaster (ECU) zur Datenübertragung verbunden. Eine Leitung, die hier zur Signalisierung der Autoadressierungsinformation benutzt wird und die typischerweise eine Interruptleitung ist, ist nun von einem Adresseingang (Adr_i0 ) des Busmasters (ECU) ausgehend durch alle Busknoten (BK₁ bis BK_n ) so durchgeschleift, dass sie durch die einzelnen Busknoten (BK₁ bis BK_n ) in n Leitungsabschnitte (L₁ bis L_n ) unterteilt wird. Jeder der Busknoten, im Folgenden zur besseren Klarheit als j-ter Bus-Knoten (BK_j ) mit 1≤j≤9 n bezeichnet, weist nun einen diesem j-ten Bus-Knoten (BK_j ) zugehörigen Adresseingang (Adr_ij ) und einen diesem j-ten Bus-Knoten (BK_j ) zugehörigen Adressausgang (Adr_oj ) auf. Diese werden als Ein- und Ausgänge zur Stimulierung der Autoadressierungsinformation und zu deren Weitergabe verwendet. Jeder der Busknoten (BK_j ), wenn er nicht der n-te Busknoten (BK_n ) ist, ist mit seinem Adresseingang (Adr_ij ) (mit 1≤j≤ n-1) mit dem Adressausgang (Adr_o(j+1) ) eines nachfolgenden Busknotens (BK_j+1 ) mit 1≤j≤ n-1 durch einen dem nachfolgenden Busknoten (BK_j+1 ) zugehörigen Leitungsabschnitt (L_j+1 )verbunden. Jeder der Busknoten (BK_j ) mit 2≤j≤ n ist mit seinem Adressausgang (Adr_oj ) mit dem Adresseingang (Adr_i(j-1) ) eines vorausgehenden Busknotens (BK_j-1 ) mit 2≤j≤ n durch einen dem Busknoten (BK_j ) zugehörigen Leitungsabschnitt (L_j ) verbunden. Der erste Busknoten (BK₁ ) ist mit seinem Adressausgang (Adr_o1 mit dem Adresseingang (Adr_i0 ) des Busmasters (ECU) durch einen dem ersten Busknoten (BK₁ ) zugehörigen Leitungsabschnitt (L₁ ) verbunden. Die jeweilige Busknotenadresse jedes Busknotens (BK₁ bis BK_n ) kann gültig oder nicht gültig sein. Als erster Schritt dieses Verfahrens wird ein Ungültig machen aller oder zumindest eines Teils der jeweiligen Busknotenadressen der Busknoten (BK₁ bis BK_n ) und ein Versetzen zumindest dieses Teils der Busknoten (BK₁ bis BK_n ) z.B. von einem Normalzustand aus in einen Adressierungszustand vorgeschlagen. Das Erste hat den Zweck, einen definierten Anfangszustand herzustellen. Das Zweite hat den Zweck, die Adressvergabe in allen Busknoten (BK₁ bis BK_n ) zu starten. Solange der Busknoten sich im Adressierungszustand befindet, wird die besagte Leitung nicht für ihre normale Funktion, also beispielsweise als Interrupt-Request-Leitung, benutzt, sondern für den Transport der Autoadressierungsfunktion.

In addition to these bus shunt resistors ( R2 . R2 ' ) based methods for address assignment, it is proposed to carry out the following method for auto-addressing via an interrupt line:

• This is a method for assigning logical bus node addresses to the bus nodes ( BK ₁ to BK _n ) of a data bus system with a serial, bidirectional, differential two-wire communication bus ( DB ), in which the data bus system has a bus master ( ECU ) with an address input ( Adr _i0 ) and n bus nodes ( BK ₁ to BK _n ) (with n as the whole positive number). Each of the n bus nodes ( BK ₂ to BK _n ) is via a data line section ( DB ₁ to DB _b ) or a serial, bidirectional, differential two-wire communication bus ( DB ) with the bus master ( ECU ) connected to the data transmission. A line which is used here for signaling the auto address information and which is typically an interrupt line is now from an address input ( Adr _i0 ) of the bus master ( ECU ) starting from all bus nodes ( BK ₁ to BK _n ) are looped through so that they pass through the individual bus nodes ( BK ₁ to BK _n ) in n line sections ( L ₁ to L _n ) is divided. Each of the bus nodes, in the following for better clarity as a j-th bus node ( BK _j ) with 1≤j≤9 n, now has a j th bus node ( BK _j ) associated address input ( Adr _ij ) and a jth bus node ( BK _j ) associated address output ( Adr _oj ) on. These are used as inputs and outputs to stimulate the auto-addressing information and to pass it on. Each of the bus nodes ( BK _j ), if it is not the nth bus node ( BK _n ) is, with its address input ( Adr _ij ) (with 1≤j≤n-1) with the address output ( Adr _{o (j + 1)} ) of a subsequent bus node ( BK _{j + 1} ) with 1≤j≤n-1 through a subsequent bus node ( BK _{j + 1} ) associated line section ( L _{j + 1} )connected. Each of the bus nodes ( BK _j ) with 2≤j≤n is with its address output ( Adr _oj ) with the address input ( Adr _{i (j-1)} ) of a preceding bus node ( BK _j-1 ) with 2≤j≤n through a bus node ( BK _j ) associated line section ( L _j ) connected. The first bus node ( BK ₁ ) with its address output ( Adr _o1 with the address input ( Adr _i0 ) of the bus master ( ECU ) by a first bus node ( BK ₁ ) associated line section ( L ₁ ) connected. The respective bus node address of each bus node ( BK ₁ to BK _n ) can be valid or not valid. As a first step of this method, invalidating all or at least part of the respective bus node addresses of the bus nodes ( BK ₁ to BK _n ) and displacing at least this part of the bus nodes ( BK ₁ to BK _n ), for example, from a normal state into an addressing state. The first purpose is to create a defined initial state. The second has the purpose of addressing in all bus nodes ( BK ₁ to BK _n ) to start. As long as the bus node is in the addressing state, the said line is not used for its normal function, that is, for example, as an interrupt request line, but for the transport of the Autoadressierungsfunktion.

During this existence of the addressing state, a setting of the level of the address input ( Adr _i0 ) of the bus master ( ECU ) to a second logical value when the level of this address input ( Adr _i0 ) this bus master ( ECU ) not through the address output ( Adr _o1 of the first bus node ( BK ₁ ) the bus node ( BK ₁ to BK _n ) is overwritten. It is a characteristic that both bus masters ( ECU ) with its address input ( Adr _i0 ), as well as the bus nodes ( BK ₁ to BK _n-1 ) with their address inputs ( Adr _i1 to Adr _in ) through the address outputs ( Adr _o1 to Adr _on ) of the following bus nodes ( BK ₁ to BK _n ) can be overwritten, since they are designed lower resistance than the corresponding driver stages in the address inputs ( Adr _i1 to Adr _in ) the bus node ( BK ₁ to BK _n ). Only the last bus node ( BK _n ) is with its address input ( Adr _in ) is not connected to any other subsequent bus node. Therefore determined in this last bus node ( BK _n ) the driver stage within the address input ( Adr _in ) of the last bus node ( BK _n ) the logical state at the address input ( Adr _in ). This allows the last bus node to recognize that it is the last in the row of bus nodes that does not yet have a valid bus node address, and therefore can accept the address offered by the bus master as a new valid bus node address if it does not have a valid bus node address, if it does Also has a valid bus node address. There he has received a valid bus node address in this way and now has it, this bus node ( BK _j ) then its address output ( Adr _oj ), whereby the driver stage of the preceding address input ( Adr _{i (j-1)} ) of the previous bus node ( BK _j-1 ) no longer through the address output ( Adr _oj ) of the bus node ( BK _j ) and the preceding bus node ( BK _j-1 ) then as the last bus node without a valid bus node address in the row of not yet addressed bus node can detect and thus at the next initialization of the previous bus node ( BK _j-1 ) then the new from the bus master ( ECU ) can take over newly offered bus node address in the same way as its valid bus node address.

Since the previous bus node ( BK _j-1 )in this way in the following inintialisierungslauf receives a valid bus node address and then has these, this switches outgoing bus node ( BK _j-1 ) then its address output ( Adr _{o (j-1)} whereby the driver stage of the next but one preceding address input ( Adr _{i (j-2)} ) of the next but one preceding bus node ( BK _j-2 ) no longer through the address output ( Adr _{o (j-1)} ) of the previous bus node ( BK _j-1 ) is overwritten and the next but one preceding bus node ( BK _j-2 ) then as the last bus node without a valid bus node address in can recognize the row of not yet addressed bus node and thus at the next next next initialization of the next but one preceding bus node ( BK _j-2 ) then the new from the bus master ( ECU ) can take over newly offered bus node address in the same way as its valid bus node address.

This will continue bus nodes for bus nodes. During the existence of the addressing state, therefore, takes place in each bus node ( BK _j ) the bus node ( BK ₂ to BK _n ) excluding the first bus node ( BK ₁ ) an override of the level at the address input ( Adr _{i (j-1)} ) of the respective bus node ( BK _j ) preceding bus node ( BK _j-1 ) through this respective bus node ( BK _j ) at a first logic level when the bus node address of that respective bus node ( BK _j ) is invalid and the level at the address input ( Adr _ij ) of this respective bus node ( BK _j ) has a first logical value and setting the level of the address input ( Adr _ij ) of this bus node ( BK _j ) to a second logical value when the level of this address input ( Adr _ij ) of this bus node ( BK _j ) not through the address output ( Adr _{o (j + 1)} ) of the respective bus node ( BK _j ) optionally following bus node ( BK _{j + 1} ) the bus node ( BK ₃ to BK _n ) is overwritten. Likewise takes place during the existence of the addressing state in the first bus node ( BK ₁ ) an override of the level at the address input ( Adr _i0 ) of the bus master ( ECU ) by the first bus node ( BK ₁ ) with a first logic level when the bus node address of the first bus node ( BK ₁ ) is invalid and the level at the address input ( Adr _o1 ) of this first bus node ( BK ₁ ) has a first logical value and setting the level of the address input ( Adr _i1 ) of this first bus node ( BK ₁ ) to a second logical value when the level of this address input ( Adr _i1 ) of this first bus node ( BK ₁ ) not through the address output ( Adr _o2 ) of the first bus node ( BK ₁ ) subsequent bus node ( BK ₂ ) the bus node ( BK ₂ to BK _n ) is overwritten. Furthermore, during the existence of the addressing state, the signaling of a bus node address to all bus nodes takes place ( BK ₁ to BK _n ) by the bus master ( ECU ) and the assumption of the signaled bus node address as a valid bus node address by that bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) whose bus node address is invalid and whose address input ( Adr _ij ) has a second logical value and repeating this signaling by the bus master ( ECU ) until the address input ( Adr _i0 ) of the bus master ( ECU ) has a second logical value, that is not overwritten. This addressing is thus repeated until the bus master ( ECU ) is the last in the chain of unaddressed bus nodes. There is therefore a displacement of the bus nodes ( BK ₁ to BK _n ) in a different from the addressing state second operating state - which is typically the normal state when the address input ( Adr _i0 ) of the bus master ( ECU ) has a second logical value.

As already mentioned, in some cases it is beneficial if the line ( L ₁ to L _n ) is used in the second operating state as an interrupt line.

AUTOADRESSION PROCEDURE ABOUT BUS SHUNT RESISTORS IN SUPPLY VOLTAGE

Finally, an auto-addressing method for assigning bus node addresses within a data bus system to a communication bus, in particular a serial, bi-directional, differential two-wire communication bus ( DB ), with n bus nodes ( BK ₁ . BK ₂ . BK ₃ , ..... BK _n-1 . BK _n ), with n as the whole positive number greater than zero, and a bus master ( ECU ), in which the bus nodes are connected via a supply voltage line ( V _asked ) are supplied with electrical energy, the communication bus ( DB ) with the bus master ( ECU ), each bus node ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ) with the communication bus ( DB ) and in which within the bus node ( BK ₁ to BK _n ) each one the respective bus node ( BK _j ) the n bus node ( BK ₁ to BK _n ) associated measuring resistor ( Rm _j ) in the supply voltage line ( V _asked ) is inserted. This case corresponds to the 15 , Thus, the data bus system proposed here has n measuring resistances ( Rm ₁ to Rm _n ). The measuring resistors ( Rm ₁ to Rm _n ) the bus node ( BK ₁ to BK _n ) thus divide the supply voltage line ( V _asked ) in n supply voltage line sections. In particular, in the case of data bus systems for controlling a plurality of light source groups ( LED ₁ to LED _n ) (see also 16 ) considerable currents via the supply voltage line ( V _asked ), the measuring resistors ( Rm ₁ to Rm _n ) are preferably selected as low impedance as possible in order to minimize the losses. It is therefore conceivable, instead of dedicated measuring resistors ( Rm ₁ to Rm _n ) only Leiterbahneinschnürungen or even line pieces predefined and for all bus nodes of the same length, width and Thickness with the same material and with a specific sheet resistance deviating from 0 Ω / m as measuring resistors ( Rm ₁ to Rm _n ) to use. These are just examples of the realization of the measuring resistors ( Rm ₁ to Rm _n ). Other implementations, such as in thick film technology, etc., are conceivable. Each bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) has an addressing power source ( Iq _j ). As such addressing power sources ( Iq _j ) can also be used power sources that in the normal state of the bus node, for example, as a power source for a light-emitting diode or a different light source ( LED _j ) to be used. Each bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) preferably has resources ( D2 . D3 . Rm _j ) to measure the current through the measuring resistor ( Rm _j ) of this bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) capture. The second differential amplifier ( D2 ) of a bus node ( BK _j ) detects the voltage drop across the respective measuring resistor ( Rm _j ) of the relevant bus node ( BK _j ). A third differential amplifier ( D3 ) compares by subtraction the value of the output signal of the second differential amplifier ( D2 ) with a reference value ( Ref ). The third differential amplifier ( D3 ) of the bus node ( BK _j ) generates, depending on the result of this comparison, together with a regulator or filter ( F ) of the bus node ( BK _j ) a control signal ( rw _j ) specific to this bus node ( BK _j ). From the value of this control signal ( rw _j ) depends on which value the addressing current of the addressing current source ( Iq _j ) of the relevant bus node ( BK _j ), if the bus node ( BK _j ) by the bus master ( ECU ) previously from the normal state in the addressing state has been brought. If the bus node is in the normal state, then typically the addressing power source ( Iq _j ) is switched off if it has no other task in this normal state. For example, it is also possible to use a current source which, in normal operation, for example, for supplying energy to consumers, that is to say, for example, illuminants and / or LEDs ( LED _j ), in the addressing state of the bus node ( BK _j ) as addressing current source ( Iq _j ) of the bus node ( BK _j ) to use. This is in 16 represented, except for the bulbs ( LED ₁ to LED _n ) not from the 15 different. By a command of the bus master ( ECU ) the relevant bus node ( BK _j ) in the addressing state, whereby its addressing current source ( Iq _j ) is turned on. This switching on its addressing current source ( Iq _j ) preferably a bus node ( BK _j ) only if it does not have a valid bus node address, which is typically stored in a bus node address register (BKADR) and marked as "valid" or "invalid" with a corresponding flag. This flag is then typically used for marking as "invalid". If its bus node address is invalid, a bus node ( BK _j ) thus preferably participates in a car addressing sequence, if these are provided by the bus master ( ECU ) is started. Incidentally, this also applies to the other car addressing methods. The addressing current source ( Iq _j ) of each bus node ( BK _j ) the bus node ( BK ₁ to BK _n ) then feeds an addressing current in this case in Direction to the power supply ( SUP ) in the supply voltage line ( V _asked ) into the connection of the measuring resistor ( Rm _j ) of this bus node ( BK _j ), along the supply voltage line ( V _asked ) farthest from the power supply ( SUP ) lies. The bus nodes ( BK ₁ to BK _j-1 ), which are located less far from the power supply (Sup), detect with their respective measuring means ( Rm ₁ to Rm _j-1 . D2 . D3 ) each of the additional voltage drop across their respective measuring resistors ( Rm ₁ to Rm _j-1 ) and regulate their addressing power sources ( Iq ₁ to Iq _j-1 ) or switch these, depending on the implementation of the method, in this addressing state of the bus node ( BK ₁ to BK _n ). This shutdown can be achieved by a threshold comparison, eg of the respective control signal ( rw _j ) of a bus node ( BK _j ) be recognized. Thus, the respective bus node ( BK _j ) then realize again that he is not the last bus node in the bus node row is without a valid bus node address or that it is the last bus node in the bus node row is without a valid bus node address. In this last case, the bus node takes over the bus node address to be assigned by the bus master, as its valid bus node address. Thus, this bus node has - assuming the jth bus node ( BK _j ) - now a valid bus node address and switches its addressing power source ( Iq _j ) for the duration of the addressing process. The addressing method, as always in this disclosure, is typically performed by a bus master ( ECU ), which preferably all bus nodes ( BK ₁ to BK _n ) are typically caused to terminate the addressing state and, for example, to assume the normal state.

• • Signalisierung eines Adressierungszustands, im Folgenden Power-Line-Adressierungszustand genannt, an alle Busknoten (BK₁ bis BK_n ), wodurch diese einen Adressierungszustand für die Durchführung eines Autoadressierungsverfahrens mittels der Versorgungsspannungsleitung (V_bat ) annehmen;
• • Ggf. Signalisierung an zumindest einen Busknoten oder einen Teil, besser an alle der Busknoten (BK₁ bis BK_n ) deren Busknotenadressen ungültig zu machen;
• • Durchführen einer Intitialisierungssequenz, die folgende Schritte aufweist, für jeden Busknoten (BK_j ) der n Busknoten (BK₁ , BK₂ , ..... BK_n-1 , BK_n ), der noch keine gültige Busknotenadresse besitzt bis alle Busknoten der n Busknoten (BK₁ , BK₂ , ..... BK_n-1 , BK_n ) über eine gültige Busknotenadresse verfügen:
  • o Signalisierung einer zu vergebenden Busadresse an alle Busknoten der n Busknoten (BK₁ , BK₂ , ..... BK_n-1 , BK_n ) (Typischerweise erfolgt mit dieser Signalisierung auch der Befehl des Busmasters (ECU) an die Busknoten, den Adressierungszustand einzunehmen oder ggf. beizubehalten.);
  • o Durchführung der folgenden Schritte parallel für jeden Busknoten (BK_j ) der Busknoten der n Busknoten (BK₁ , BK₂ , ..... BK_n-1 , BK_n ), im Folgenden als betreffender Busknoten (BK_j ) bezeichnet, der über keine gültige Busknotenadresse verfügt:
    • ■ Empfang des besagten Autoadressierungskommandos vom Busmaster (ECU) durch den betreffenden Busknoten (BK_j );
    • ■ Empfang der zu vergebenden Busadresse vom Busmaster (ECU) durch den betreffenden Busknoten (BK_j );
    • ■ Empfang eines Startsignals für die Vergabe der zu vergebenden Busadresse vom Busmaster (ECU) durch den betreffenden Busknoten (BK_j ) und Start eines Zeitgebers zu einem Startzeitpunkt (t₀=0s) durch den betreffenden Busknoten (BK_j );
    • ■ Erfassen des Spannungsabfalls über den Messwiderstand (Rm_j ) des betreffenden Busknotens (BK_j ) als Basisspannungswert (V_m0 ) mittels Messmitteln (Rm_j , D2, D3);
    • ■ Zu einem vierten Zeitpunkt (t₄ ) nach dem Startzeitpunkt (t₀ ): Einschalten der Adressierungsstromquelle (Iq_j ) des betreffenden Busknotens (BK_j ) und Ausregelung des Spannungsabfalls über den Messwiderstand (Rm_j ) des betreffenden Busknotens (BK_j ) mit Hilfe der Adressierungsstromquelle (Iq_j ) in Abhängigkeit von dem Spannungsabfall über den Messwiderstand (Rm_j ) mittels eines Regelsignals (rw_j ), das durch Messmittel (D2, D3, Rm_j ) und/oder Regelmittel (F) des Busknotens (BK_j ) erzeugt wird, auf einen Gesamtzielspannungswert der einem Zielspannungswert als plus dem zuvor gemessenen Basisspannungswert (V_m0 ) entspricht, wobei eine Erhöhung des Adressierungsstroms der Autoadressierungsstromquelle (Iq_j ) des betreffenden Busknotens (BK_j ) mit einer ersten Zeitkonstante (τ₁ ) erfolgt und wobei eine Erniedrigung des Adressierungsstroms der Autoadressierungsstromquelle (Iq_j ) des betreffenden Busknotens (BK_j ) mit einer zweiten Zeitkonstante (τ₂ ) erfolgt (Man beachte, dass hier noch keine Aussage über das wertemäßige Verhältnis der ersten Zeitkonstante (τ₁ ) im Vergleich zur zweiten Zeitkonstante (τ₂ ) erfolgt.);
    • ■ Zu einem fünften Zeitpunkt (t₅ ) nach dem Startzeitpunkt (t₀ ) und nach dem vierten Zeitpunkt (t₄ ): Erfassen des Werts des Regelsignals (rw_j ) oder eines daraus abgeleiteten Signals und Vergleich dieses Werts mit einem Schwellwert und
    • ■ Verwendung der zu vergebenden Busknotenadresse als gültige Busknotenadresse des Busknotens (BK_j ), wenn der Betrag dieses Wertes über dem Schwellwert liegt und Ausschalten der Adressierungsstromquelle (Iq_j ) zumindest bis zum Verlassen des Adressierungszustands durch den Busknoten (BK_j );

The proposed method for addressing over voltage drops along the supply voltage line ( V _asked ) now provides the following steps:

• Signaling of an addressing state, referred to below as the power-line addressing state, to all bus nodes ( BK ₁ to BK _n ), whereby this one addressing state for the implementation of a car addressing method by means of the supply voltage line ( V _asked ) accept;
• • Possibly. Signaling to at least one bus node or part, better to all of the bus nodes ( BK ₁ to BK _n ) invalidate their bus node addresses;
• • Performing an initialization sequence, which has the following steps, for each bus node ( BK _j ) the n bus node ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ), which does not yet have a valid bus node address until all the bus nodes of the n bus nodes ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ) have a valid bus node address:
  • o signaling a bus address to be given to all bus nodes of the n bus nodes ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ) (Typically, with this signaling, the command of the bus master ( ECU ) to the bus nodes, to assume the addressing state or if necessary to maintain it.);
  • o Perform the following steps in parallel for each bus node ( BK _j ) the bus node of the n bus nodes ( BK ₁ . BK ₂ , ..... BK _n-1 . BK _n ), hereinafter referred to as the relevant bus node ( BK _j ), which does not have a valid bus node address:
    • ■ Receipt of said auto-addressing command from the bus master ( ECU ) by the relevant bus node ( BK _j );
    • ■ Receipt of the bus address to be issued by the bus master ( ECU ) by the relevant bus node ( BK _j );
    • ■ Receipt of a start signal for assigning the bus address to be assigned by the bus master ( ECU ) by the relevant bus node ( BK _j ) and start of a timer at a start time (t ₀ = 0s) by the relevant bus node ( BK _j );
    • ■ Detecting the voltage drop across the Measuring resistor ( Rm _j ) of the relevant bus node ( BK _j ) as the base voltage value ( V _m0 ) by means of measuring means ( Rm _j . D2 . D3 );
    • ■ At a fourth time ( t ₄ ) after the start time ( t ₀ ): Switching on the addressing current source ( Iq _j ) of the relevant bus node ( BK _j ) and compensation of the voltage drop across the measuring resistor ( Rm _j ) of the relevant bus node ( BK _j ) with the aid of the addressing current source ( Iq _j ) as a function of the voltage drop across the measuring resistor ( Rm _j ) by means of a control signal ( rw _j ) generated by measuring means ( D2 . D3 . Rm _j ) and / or control means ( F ) of the bus node ( BK _j ) to a total target voltage value of a target voltage value as plus the previously measured base voltage value (Fig. V _m0 ), wherein an increase of the addressing current of the auto-addressing power source ( Iq _j ) of the relevant bus node ( BK _j ) with a first time constant ( τ ₁ ) and wherein a reduction of the addressing current of the auto-addressing power source ( Iq _j ) of the relevant bus node ( BK _j ) with a second time constant ( τ ₂ (Note that here is no statement about the value-wise ratio of the first time constant ( τ ₁ ) compared to the second time constant ( τ ₂ ) he follows.);
    • ■ At a fifth point in time ( t ₅ ) after the start time ( t ₀ ) and after the fourth date ( t ₄ ): Detecting the value of the control signal ( rw _j ) or a signal derived therefrom and comparing this value with a threshold value and
    • ■ Use of the bus node address to be assigned as a valid bus node address of the bus node ( BK _j ), if the value of this value is above the threshold value and switching off the addressing current source ( Iq _j ) at least until it leaves the addressing state by the bus node ( BK _j );

It is useful to check the successful assignment of addresses by the bus master ( ECU ) after assigning a bus node address to a bus node ( BK _j ). If this results in an error, for example, several bus nodes report a bus collision, it is advisable to delete the validity of the last assigned bus node address, whereby the relevant bus nodes ( BK _j ) again like bus nodes ( BK _j ) without a valid bus node address. After assigning all bus node addresses to all bus nodes ( BK ₁ to BK _n ), which should receive a bus node address, it should be checked whether all bus nodes ( BK ₁ to BK _n ), which should receive a bus node address, have received a valid bus node address. If all bus nodes have received a valid bus node address, the bus master signals ( ECU ) preferably to all bus nodes ( BK ₁ to BK _n ) that they should leave the addressing state and another state, preferably to take the normal state. In the normal state, the bus nodes ( BK ₁ to BK _n ) their addressing power sources ( Iq ₁ to I _n ) or operate them in the function required for these addressing power sources ( Iq ₁ to Iq _n ) is provided in this operating state, here the normal state. The execution of a further initialization sequence is expedient, if not all bus nodes ( BK ₁ to BK _n ), which should receive a bus node address, have received a valid bus node address. In principle, it is expedient if the second time constant ( τ ₂ ) is smaller than the first time constant by a factor greater than 10 ( τ ₁ ). But at least the first time constant ( τ ₁ ) greater than the second time constant ( τ ₂ ) his. It is favorable if the first time constant ( τ ₁ ) within the relevant auto-addressing bus node ( BK _j ) of which by means of measuring means ( Rm _j . D2 . D3 ) detected value of the voltage drop across the measuring resistor ( Rm _j ) of the relevant auto-addressing bus node ( BK _j ) and / or the second time constant ( τ ₂ ) within the relevant auto-addressing bus node ( BK _j ) of which by means of measuring means ( Rm _j . D2 . D3 ) detected value of the voltage drop across the measuring resistor ( Rm _j ) of the relevant auto-addressing bus node ( BK _j ) depends. This allows a faster control of the voltage drop across the measuring resistance ( Rm _j ) of the relevant bus node ( BK _j ).

In the 17 Now also second addressing current sources ( Iq ' _j ) of the relevant bus node ( BK _j ) for auto-addressing via the power supply line ( V _asked ) used. Also, second measuring means ( D2 ' . D3 ' ) in addition to the first measuring means ( Rm ₁ to Rm _n . D2 . D3 ) used. This redundancy can be used for checking and monitoring purposes, as each auto-addressing pass should result in a similar result for both branches. If this is not the case, then the offered bus node address is preferably not accepted, but for example, a specially reserved and predetermined error address adopted. Does the bus master ( ECU ), this error address via its data bus protocol, the bus node, where the error occurred, the bus master ( ECU ), what he should not, if not a mistake in the bus node would have occurred. Specifically, for example, the test may be such that the difference between the value of the first control signal ( rw _j ) of a bus node ( BK _j ) and the value of the second control signal ( rw _'j ) of this bus node ( BK _j ) is formed. If the amount of this difference is above a predetermined limit, at least one of the circuits will not work properly. This can thus be recognized and used to prevent the bus master ( ECU ) is given to be given bus node address as a valid bus node address. Instead, the predetermined error address is then accepted as a valid bus node address, which then by addressing this address by the bus master ( ECU ) can be checked by the same.

Simultaneous use of various auto-addressing methods

It is now advantageous to be able to use various of the auto-addressing methods described herein, as each method can confirm the success of the correct identification by redundancy. In addition, when using more than two auto-addressing methods, a fail-operational property can be achieved. This means that auto-addressing is usually carried out successfully, but an error is detected, which can then be signaled. This is potentially of particular importance for safety applications. eighteen shows such a proposed device that allows the implementation of several Autoadressierungsverfahren and thus has increased security. The eighteen is a combination of 17 . 13 . 6 and 5 , In the bus node ( BK ₁ to BK _n ), a first multiplexer ( X1 ) of the respective bus node ( BK _j ) and a second multiplexer ( X2 ) of this bus node ( BK _j ) are used around the inputs of the second differential amplifier ( D2 ) of this bus node ( BK _j ) to the first bus shunt resistor ( R2 ) of this bus node ( BK _j ) or to the measuring resistor ( Rm _j ) of this bus node ( BK _j ) to switch. In the bus node ( BK ₁ to BK _n ), a further first multiplexer ( X1 ' ) of the respective bus node ( BK _j ) and another second multiplexer ( X2 ' ) of this bus node ( BK _j ) are used to connect the inputs of the further second differential amplifier ( D2 ' ) of this bus node ( BK _j ) to the second bus shunt resistor ( R2 ' ) of this bus node ( BK _j ) or to the measuring resistor ( Rm _j ) of this bus node ( BK _j ) to switch. Accordingly, the first addressing current source ( Iq _j ) of this bus node ( BK _j ) either with a reference potential ( GND ) or with the first single-wire bus ( DB _a ) by a third multiplexer ( X3 ) of this bus node ( BK _j ) connected. The third multiplexer ( X3 ) of this bus node ( BK _j ) also determines whether the first addressing current of the first addressing current source ( Iq _j ) of this bus node ( BK _j ) in front of or behind the first bus shunt resistor ( R2 ) of this bus node ( BK _j ) into the first single-wire bus ( DB _a ) is fed. Analogously, the second addressing current source ( Iq ' _j ) of this bus node ( BK _j ) either with a reference potential ( GND ) or with the second single-wire bus ( DB _b ) by another third multiplexer ( X3 ' ) of this bus node ( BK _j ) connected. The further third multiplexer ( X3 ' ) of this bus node ( BK _j ) also determines whether the second addressing current of the second addressing current source ( Iq ' _j ) of this bus node ( BK _j ) in front of or behind the second bus shunt resistor ( R2 ' ) of this bus node ( BK _j ) into the second single-wire bus ( DB _b ) is fed.

Low impedance normal operation

It now makes sense if only in the addressing state of the bus node ( BK ₁ to BK _n ) the bus shunt resistors ( R2 . R2 ' ) in the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b ) are effective. Therefore, it makes sense, as soon as the addressing state is exited, to be preferred in all bus nodes ( BK ₁ to BK _n ) by a first bypass switch ( S4 ) in preferably each bus node ( BK _j ) the first bus shunt resistor ( R2 ) of this bus node ( BK _j ) and a second bypass switch ( S4 ' ) in this bus node ( BK _j ) the second bus shunt resistor ( R2 ' ) of this bus node ( BK _j ) short circuit. This is in 19 shown.

Of course, this procedure would also be for the measuring resistor ( Rm _j ) of a bus node ( BK _j ) conceivable. The corresponding switches would, however, usually take up too much chip area. In addition, the voltage drop across the normal supply voltage line usually suffices, so that in these cases no dedicated measuring resistor ( Rm _j ) in the supply voltage line ( V _asked ) is inserted, but a line section of the supply voltage line ( V _asked ) as a measuring resistor ( Rm _j ) of this bus node ( BK _j ) can be used.

Vertauschungserkennung

20 now additionally shows in the exemplary bus node ( BK ₁ to BK _n ) each have a fourth multiplexer ( X4 ) per bus node ( BK _j ), with which a controller within this bus node ( BK _j ) the two inputs of the second differential amplifier ( D2 ) of this bus node ( BK _j ) can swap. Furthermore, the shows 20 additionally in the exemplary bus node ( BK ₁ to BK _n ) each have a further fourth multiplexer ( X4 ' ) per bus node ( BK _j ), with which the controller within this bus node ( BK _j ) the two inputs of the further second differential amplifier ( D2 ' ) of this bus node ( BK _j ) can swap.

This can be on 21 be explained for the error case shown there: the second bus node ( BK ₂ ) is installed reversed. This can now be done very easily by controlling the second bus node ( BK ₂ ) in a self-test, which is preferably performed at the beginning of the initialization procedure. For example, the bus master ( ECU ) to the bus nodes ( BK ₁ to BK _n ) that they should perform such a self-test. Other start scenarios, eg in a switch-on phase are conceivable. For example, the bus node ( BK _j ) by means of its measuring means ( R2 . R2 ' . D2 . D2 ' . D3 . D3 ' . Iq _j . Iq ' _j . X1 . X1 ' X2 . X2 ' X3 . X3 ') determine whether the first addressing current of its first addressing current source ( Iq _j ) by its first bus shunt resistor ( R2 ) flows when it passes through its first bus shunt resistor ( R2 ), and whether the second addressing current of its second addressing current source ( Iq ' _j ) by its second bus shunt resistor ( R2 ' ) flows when it passes through the second bus shunt resistor ( R2 ' ) should flow. If this is the other way around, the control of the bus node can determine this on the basis of the corresponding measurement results and by means of a fourth multiplexer ( X4 ) of this bus node ( BK _j ) and the third multiplexer ( X3 ) of this bus node ( BK _j ) on the one hand, the inputs of the second differential amplifier ( D2 ) of this bus node ( BK _j ) and on the other hand, the feed-in point for the first addressing current of the first addressing current source ( Iq _j ) of this bus node ( BK _j ) to the other side of the first bus shunt resistor ( R2 ) of this bus node ( BK _j ) lay. In this case, the control of the bus node by means of another fourth multiplexer ( X4 ' ) of this bus node ( BK _j ) and the further third multiplexer ( X3 ' ) of this bus node ( BK _j ) on the one hand the inputs of the further second differential amplifier ( D2 ' ) of this bus node ( BK _j ) and, on the other hand, the feed-in point for the second addressing current of the second addressing current source ( Iq ' _j ) of this bus node ( BK _j ) to the other side of the second bus shunt resistor ( R2 ' ) of this bus node ( BK _j ) lay. Then the implementation of the auto-addressing method using the bus shunt resistors ( R2 . R2 ' ) again possible. Also possible, but not shown here for clarity, is a flipping of the feed-in point of the first addressing current source ( Iq _j ) of this bus node ( BK _j ) in the supply voltage line ( V _asked ) to the other side of the measuring resistor ( Rm _j ) by means of a not shown fifth multiplexer ( X5 ). However, this only makes sense if the first addressing current source ( Iq _j ) in the normal state does not have to deliver too much power. But this is exactly the case when the first auto-addressing power source ( Iq _j ) in the normal state of the bus node ( BK _j ), for example, the energy source of bulbs ( LED _j ) represents the bus node. In that case, the transistors of the fifth multiplexer (not shown) would be X5 ) too big and therefore too expensive. Likewise, a flipping of the feed-in point of the second addressing current source ( Iq ' _j ) of this bus node ( BK _j ) in the supply voltage line ( V _asked ) to the other side of the measuring resistor ( Rm _j ) by means of a not further marked fifth multiplexer ( X5 ') no longer drawn. The same considerations apply here.

Likewise, it was not shown that the input of the address input ( Adr _ij ) of the relevant bus node ( BK _j ) (here by way of example the second bus node ( BK ₂ )) with the output of the address output ( Adr _oj ) of the relevant bus node ( BK _j ) by means of two multiplexers ( X6 . X7 ) can be reversed if such a permutation as in 21 through the control of the bus node ( BK _j ) was determined, for example, in the manner described above.

These are exemplary measures for compensating an insertion of a bus node with plug replacement.

LIST OF REFERENCE NUMBERS

ADRD

Address information within the data information ( DATA ) of a bit stream packet ( BP );

ADR ₁

Address recognition unit of the first bus node ( BK ₁ );

ADR ₂

Address recognition unit of the second bus node ( BK ₂ );

ADR ₃

Address recognition unit of the third bus node ( BK ₃ );

ADR ₄

Address recognition unit of the fourth bus node ( BK ₄ );

ADR ₅

Address recognition unit of the fifth bus node ( BK ₅ );

ADR ₆

Address recognition unit of the sixth bus node ( BK ₆ );

ADR _j

Address recognition unit of the jth bus node ( BK _j );

ADR _n

Address recognition unit of the nth bus node ( BK _n );

Adr _io

Address input of the bus master ( ECU );

Adr _i1

Address input of the first bus node ( BK ₁ );

Adr _i2

Address input of the second bus node ( BK ₂ );

Adr _i3

Address input of the third bus node ( BK ₃ );

Adr _{i (j-1)}

Address input of the (j-1) -th bus node ( BK _(j-1) );

Adr _ij

Address input of the jth bus node ( BK _j );

Adr _{i (j + 1)}

Address input of the (j + 1) -th bus node ( BK _{(j + 1)} );

Adr _in

Address input of the nth bus node ( BK _n );

Adr _o1

Address output of the first bus node ( BK ₁ );

Adr _o2

Address output of the second bus node ( BK ₂ );

Adr _o3

Address output of the third bus node ( BK ₃ );

Adr _{o (j-1)}

Address output of the (j-1) -th bus node ( BK _(j-1) );

Adr _oj

Address output of the jth bus node ( BK _j );

Adr _{o (j + 1)}

Address output of the (j + 1) -th bus node ( BK _{(j + 1)} );

Adr _on

Address output of the nth bus node ( BK _n );

AT ₁

Scanning device of the first bus node ( BK ₁ );

AT ₂

Scanning device of the second bus node ( BK ₂ );

AT ₃

Scanning device of the third bus node ( BK ₃ );

AT ₄

Scanning device of the fourth bus node ( BK ₄ );

AT ₅

Scanning device of the fifth bus node ( BK ₅ );

AT ₆

Scanning device of the sixth bus node ( BK ₆ );

AT _j

Scanning device of the jth bus node ( BK _j );

AT _n

Sampling device of the nth bus node ( BK _n );

BK ₁

first bus node;

BK ₂

second bus node;

BK ₃

third bus node;

BK ₄

fourth bus node;

BK ₅

fifth bus node;

BK ₆

sixth bus node;

BK _j-2

(j-2) -ter bus node;

BK _j-1

(j-1) -th bus node;

BK _j

j-th bus node, also referred to as the relevant bus node in this disclosure, if statements about a single bus node of the bus node ( BK ₁ . BK ₂ , ...... BK _n-1 . BK _n ) are made;

BK _{j + 1}

(j + 1) -th bus node;

BK _{j + 2}

(j + 2) -th bus node;

BK _n-2

(n-2) -th bus node;

BK _n-1

(n-1) -th bus node;

BK _n

nth bus node;

BKADR ₁

Bus node address register of the first bus node ( BK ₁ );

BKADR ₂

Bus node address register of the second bus node ( BK ₂ );

BKADR ₃

Bus node address register of the second bus node ( BK ₃ );

BKADR ₄

Bus node address register of the second bus node ( BK ₄ );

BKADR ₅

Bus node address register of the second bus node ( BK ₅ );

BKADR ₆

Bus node address register of the second bus node ( BK ₆ );

BKADR _j

Bus node address register of the jth bus node ( BK _j );

BKADR _n

Bus node address register of the nth bus node ( BK _n );

BP

Bit stream packet (English frame), also called data packet;

CHKD

Check information within the data information ( DATA ) of a bit stream packet ( BP ). It is preferably a CRC checksum and / or parity bits, etc .;

CLK

Clock within the bus master ( ECU );

CLKA ₁

Sampling signal within the first bus node ( BK ₁ );

CLKA ₂

Sampling signal within the second bus node ( BK ₂ );

CLKA ₃

Sampling signal within the third bus node ( BK ₃ );

CLKA ₄

Sampling signal within the fourth bus node ( BK ₄ );

CLKA ₅

Sampling signal within the fifth bus node ( BK ₅ );

CLKA ₆

Sampling signal within the sixth bus node ( BK ₆ );

CLKA _j

Sampling signal within the jth bus node ( BK _j );

CLKA _n

Sampling signal within the nth bus node ( BK _n );

CLKG ₁

Clock of the first bus node ( BK ₁ );

CLKG ₂

Clock of the second bus node ( BK ₂ );

CLKG ₃

Clock of the third bus node ( BK ₃ );

CLKG ₄

Clock of the fourth bus node ( BK ₄ );

CLKG ₅

Clock of the fifth bus node ( BK ₅ );

CLKG ₆

Clock of the sixth bus node ( BK ₆ );

CLKG _j

Clock of the jth bus node ( BK _j );

CLKG _n

Clock of the nth bus node ( BK _n );

D2

second differential amplifier for measuring the first current through the first single-wire bus ( DB _a ) by means of the first shunt resistor ( R2 ) or to measure the current through the supply voltage line ( V _asked ) by means of the measuring resistor ( RM _j ) within the concerned Bus node ( BK _j ). The second differential amplifiers are not provided with indices for the respective bus nodes for a better overview.

D2 '

second differential amplifier for measuring the second current through the second single-wire bus ( DB _b ) by means of the second shunt resistor ( R2 ' ) or to measure the current through the supply voltage line ( V _asked ) by means of the measuring resistor ( RM _j ) within the relevant bus node ( BK _j ). The second differential amplifiers are not provided with indices for the respective bus nodes for a better overview.

D3 '

third comparator or third differential amplifier for comparing the output of the second differential amplifier ( D2 ), which is used to measure the current through the first single-wire bus ( DB _a ) by means of the first shunt resistor ( R2 ) or by the supply voltage line by means of the measuring resistor ( RM _j ), with a threshold (Ref) within the relevant bus node ( BK _j ). The third comparators and differential amplifiers are not provided with indices for the respective bus nodes ( BK _j ) Provided.

D3 '

third comparator or third differential amplifier for comparing the output of the second differential amplifier ( D2 ' ) used to measure the current through the second single-wire bus ( DB _b ) by means of the second shunt resistor ( R2 ' ) or by the supply voltage line by means of the measuring resistor ( RM _j ), with another threshold ( Ref ' ) within the relevant bus node ( BK _j ). The third comparators and differential amplifiers are not provided with indices for the respective bus nodes ( BK _j ) Provided.

DATA

Data information within a bit stream packet;

DB

serial, bidirectional, differential two-wire communication bus;

DB _a

first single-wire bus of the serial, bidirectional, differential two-wire communication bus ( DB );

DB _a

second single-wire bus of the serial, bidirectional, differential two-wire communication bus ( DB );

DB ₁

first, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the first bus node

DB ₂

( BK ₁ ) and the bus master ( ECU ). It comprises in each case a corresponding section of the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b ); second, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the second bus node ( BK ₂ ) and the first bus node ( BK ₁ ). It comprises in each case a corresponding section of the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b );

DB ₃

third, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the third bus node ( BK ₃ ) and the second bus node ( BK ₂ ). It comprises in each case a corresponding section of the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b );

DB _j

third, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the jth bus node ( BK _j ) and the (j-1) -th bus node ( BK _j-1 ). It comprises in each case a corresponding section of the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b );

DB _n

nth, bidirectional, differential data line section of the bidirectional differential two-wire communication bus between the nth bus node ( BK _n ) and the (n-1) th bus node ( BK _n-1 ). It comprises in each case a corresponding section of the first single-wire bus ( DB _a ) and the second single-wire bus ( DB _b );

DET

first detection device within a bus node ( BK _j );

DET '

second detection device within a bus node ( BK _j );

ds2

Output of the second differential amplifier ( D2 ). It is an internal signal within a bus node ( BK _j );

ds2 '

Output of the further second differential amplifier ( D2 ' ). It is an internal signal within a bus node ( BK _j );

ds3

internal signal within a bus node ( BK _j );

ECU

Bus master, also referred to here as drive unit;

he

first error signal of the first detection device ( DET );

he'

second error signal of the second detection device ( DET ' );

EV ₁

Power supply means of the first bus node ( BK ₁ ), which for the energy supply of the first light source ( LED ₁ ) of the first bus node ( BK ₁ ) is provided.

EV ₂

Power supply means of the second bus node ( BK ₂ ), which for the energy supply of the second light source ( LED ₂ ) of the second bus node ( BK ₂ ) is provided.

EV ₃

Power supply means of the third bus node ( BK ₃ ), which is responsible for the energy supply of the third illuminant ( LED ₃ ) of the third bus node ( BK ₃ ) is provided.

EV ₄

Power supply means of the fourth bus node ( BK ₄ ), which for the power supply of the fourth light source ( LED ₄ ) of the fourth bus node ( BK ₄ ) is provided.

EV ₅

Power supply means of the fifth bus node ( BK ₅ ), which for the power supply of the fifth light source ( LED ₅ ) of the fifth bus node ( BK ₅ ) is provided.

EV ₆

Power supply means of the sixth bus node ( BK ₆ ), which for the energy supply of the sixth illuminant ( LED ₆ ) of the sixth bus node ( BK ₆ ) is provided.

EV _j

Power supply means of the jth bus node ( BK _j ), which is responsible for the energy supply of the jth illuminant ( LED _j ) of the jth bus node ( BK _j ) is provided.

EV _n

Power supply means of the nth bus node ( BK _n ), which is used for the power supply of the nth illuminant ( LED _n ) of the nth bus node ( BK _n ) is provided.

F

first filter;

F '

second filter;

GND

second supply voltage line (complementary to Vbat ) also referred to as reference potential;

i ₁

first bus node output stream which the first bus node ( BK ₁ ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the first bus node ( BK ₁ ) and the bus master ( ECU ), to the bus master ( ECU ) and which the bus master receives as the first bus master input stream;

i ' ₁

second bus node output stream which the first bus node ( BK ₁ ) over the section of the second single-wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the first bus node ( BK ₁ ) and the bus master ( ECU ), to the bus master ( ECU ) and which the bus master receives as the second bus master input stream;

i ₂

first bus node output stream which the second bus node ( BK ₂ ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the second bus node ( BK ₂ ) and the first bus node ( BK ₁ ), to the first bus node ( BK ₁ ) and the first bus node ( BK ₁ ) as the first bus node input stream;

i ' ₂

second bus node output stream which the second bus node ( BK ₂ ) over the section of the second single-wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the second bus node ( BK ₂ ) and the first bus node ( BK ₁ ), to the first bus node ( BK ₁ ) and the first bus node ( BK ₁ ) as the second bus node input stream;

i ₃

first bus node output stream which the third bus node ( BK ₃ ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial,

i ' ₃

bidirectional, differential two-wire communication bus ( DB ) between the third bus node ( BK ₃ ) and the second bus node ( BK ₂ ), to the second bus node ( BK ₂ ) and the second bus node ( BK ₂ ) as the first bus node input stream; second bus node output stream which the third bus node ( BK ₃ ) over the section of the second Single wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the third bus node ( BK ₃ ) and the second bus node ( BK ₂ ), to the second bus node ( BK ₂ ) and the second bus node ( BK ₂ ) as the second bus node input stream;

i _j

first bus node output stream which the jth bus node ( BK _j ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the jth bus node ( BK _j ) and the (j-1) -th bus node ( BK _j-1 ) is at the (j-1) th bus node ( BK _j-1 ) and the (j-1) th bus node ( BK _(j-1) ) as the first bus node input stream;

i ' _j

second bus node output stream which the jth bus node ( BK _j ) over the section of the second single-wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the jth bus node ( BK _j ) and the (j-1) -th bus node ( BK _j-1 ) is at the (j-1) th bus node ( BK _j-1 ) and the (j-1) th bus node ( BK _(j-1) ) as the second bus node input stream;

i _{j + 1}

first bus node output stream which the (j + 1) th bus node ( BK _{j + 1} ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the (j + 1) -th bus node ( BK _{j + 1} ) and the jth bus node ( BK _j ), to the jth bus node ( BK _j ) and that the jth bus node ( BK _j ) as the first bus node input stream;

i ' _{j + 1}

second bus node output stream which the (j + 1) th bus node ( BK _{j + 1} ) over the section of the second single-wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) wipe the (j + 1) th bus node ( BK _{j + 1} ) and the jth bus node ( BK _j ), to the jth bus node ( BK _j ) and that the jth bus node ( BK _j ) as the second bus node input stream;

i _n-1

first bus node output stream which the (n-1) th bus node ( BK _n-1 ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the (n-1) -th bus node ( BK _n-1 ) and the (n-2) th bus node ( BK _n-2 ) is at the (n-2) th bus node ( BK _n-2 ) and the (n-2) th bus node ( BK _n-2 ) as the first bus node input stream;

i'n _-1

second bus node output stream which the (n-1) th bus node ( BK _n-1 ) over the section of the second single-wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the (n-1) -th bus node ( BK _n-1 ) and the (n-2) th bus node ( BK _n-2 ) is at the (n-2) th bus node ( BK _n-2 ) and the (n-2) th bus node ( BK _n-2 ) as the second bus node input stream;

in

first bus node output stream which the nth bus node ( BK _n ) over the section of the first single-wire bus ( DB ₁ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the nth bus node ( BK _n ) and the (n-1) th bus node ( BK _n-1 ) is at the (n-1) th bus node ( BK _n-1 ) and the (n-1) th bus node ( BK _n-1 ) as the first bus node input stream;

i _'n

second bus node output stream which the nth bus node ( BK _n ) over the section of the second single-wire bus ( DB ₂ ), the part of the connection section of the serial bidirectional differential two-wire communication bus ( DB ) between the nth bus node ( BK _n ) and the (n-1) th bus node ( BK _n-1 ) is at the (n-1) th bus node ( BK _n-1 ) and the (n-1) th bus node ( BK _n-1 ) as the second bus node input stream;

IF ₁

differential serial interface of the first bus node ( BK ₁ );

IF ₂

differential serial interface of the second bus node ( BK ₂ );

IF ₃

differential serial interface of the third bus node ( BK ₃ );

IF ₄

differential serial interface of the fourth bus node ( BK ₄ );

IF ₃

differential serial interface of the fifth bus node ( BK ₅ );

IF ₆

differential serial interface of the sixth bus node ( BK ₆ );

IF _(j-1)

differential serial interface of the (j-1) -th bus node ( BK _j-1 );

IF _j

differential serial interface of the jth bus node ( BK _j );

IF _{(j + 1)}

differential serial interface of the (j + 1) -th bus node ( BK _{j + 1} );

IF _(n-1)

differential serial interface of the (n-1) -th bus node ( BK _n-1 );

IF _n

differential serial interface of the nth bus node ( BK _n );

ILD

Lighting information for controlling the power supply of the lamps ( LED _j ) of the bus node ( BK _j ) by the power supply means ( EV _j ) of the bus node ( BK _j ) in response to this illumination information;

INFO

Payload within the data information ( DATA ) of a bit stream packet ( BP ). Preferably, it is illumination data for the respective bus node ( BK _j );

Iq ₁

first addressing power source of the first bus node ( BK ₁ );

Iq ₂

first addressing power source of the second bus node ( BK ₂ );

Iq ₃

first addressing power source of the third bus node ( BK ₃ );

Iq _j

first addressing current source of the jth bus node ( BK _j );

Iq _j1

first addressing current source of the jth bus node ( BK _j ) when dividing the first addressing current source ( Iq _j1 ) of the jth bus node ( BK _j ) in a first addressing current source, which before the first bus shunt resistor ( R2 ) and another first addressing current source behind the first bus shunt resistor (FIG. R2 ) feeds;

Iq _j2

further first addressing current source of the jth bus node ( BK _j ) when dividing the first addressing current source ( Iq _j1 ) of the jth bus node ( BK _j ) in a first addressing current source, which before the first bus shunt resistor ( R2 ) and a first addressing power source located behind the first bus shunt resistor ( R2 ) feeds;

Iq ' _j1

second addressing current source of the jth bus node ( BK _j ) when splitting the second addressing current source ( Iq _j1 ) of the jth bus node ( BK _j ) in a second addressing current source, before the second bus shunt resistor ( R2 ' ) and another second addressing current source behind the second bus shunt resistor (FIG. R2 ' ) feeds;

Iq ' _j2

further second addressing current source of the jth bus node ( BK _j ) when splitting the second addressing current source ( Iq _j1 ) of the jth bus node ( BK _j ) in a second addressing current source, before the second bus shunt resistor ( R2 ' ) and another second addressing current source behind the second bus shunt resistor (FIG. R2 ' ) feeds;

Iq _j

first addressing current source of the jth bus node ( BK _j );

Iq _n

first addressing current source of the nth bus node ( BK _n );

I _ref

first predetermined total current value within a bus node ( BK _j ) for the first bus node output stream ( i _j ). The first summation current value should be for all

I ' _ref

Although bus nodes may be the same size. But it can also vary from bus node to bus node. second predetermined summation current value within a bus node ( BK _j ) for the second bus node output stream ( i ' _j ). Although the second summation current value should preferably be the same for all bus nodes. But it can also vary from bus node to bus node.

L ₁

first line section from the first bus node ( BK ₁ ) to the bus master ( ECU );

L ₂

second line section from the second bus node ( BK ₂ ) to the first bus node ( BK ₁ );

L ₃

third line section from the third bus node ( BK ₃ ) to the second bus node ( BK ₂ );

L ₄

fourth line section from the fourth bus node ( BK ₄ ) to the third bus node ( BK ₃ );

L _j-1

(j-1) -th line section from (j-1) -th bus node ( BK _j-1 ) to the (j-2) th bus node ( BK _j-2 );

L _j

j-th line section from the jth bus node ( BK _j ) to the (j-1) -th bus node ( BK _j-1 );

L _{j + 1}

(j + 1) -th line section from the (j + 1) -th bus node ( BK _{j + 1} ) to the jth bus node ( BK _j );

Ln _-1

(n-1) -th line section from the (n-1) th bus node ( BK _n-1 ) to the (n-2) -th bus node ( BK _n-2 );

L _n

nth line section from the nth bus node ( BK _n ) to the (n-1) th bus node ( BK _n-1 );

μC ₁

Microcontroller of the first bus node ( BK ₁ );

μC ₂

Microcontroller of the second bus node ( BK ₂ );

μC ₃

Microcontroller of the third bus node ( BK ₃ );

μC ₄

Microcontroller of the fourth bus node ( BK ₄ );

μC ₅

Microcontroller of the fifth bus node ( BK ₅ );

μC ₆

Microcontroller of the sixth bus node ( BK ₆ );

μC _j

Microcontroller of the jth bus node ( BK _j );

μC _n

Microcontroller of the nth bus node ( BK _n );

LED ₁

Illuminant of the first bus node ( BK ₁ ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

LED ₂

Illuminant of the second bus node ( BK ₂ ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

LED ₃

Illuminant of the third bus node ( BK ₃ ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

LED ₄

Illuminant of the fourth bus node ( BK ₄ ). Illuminant groups and interconnections are included here. (These can be, for example, sera and parallel circuits of several light-emitting diodes.)

LED ₅

Illuminant of the fifth bus node ( BK ₅ ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

LED ₆

Illuminant of the sixth bus node ( BK ₆ ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

LED _j

Illuminant of the jth bus node ( BK _j ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

LED _n

Illuminant of the nth bus node ( BK _n ). Illuminant groups and interconnections are included here. (These may be, for example, serial and parallel connections of several light-emitting diodes.)

pole

first polarity signal, which preferably the multiplexer ( X4 ) controls;

pole

second polarity signal, which preferably the further multiplexer ( X4 ' ) controls;

R2

first shunt resistor for measuring the current through the first single-wire bus ( DB _a ) within the relevant bus node ( BK _j ). The first shunt resistor is shown here as part of the bus node ( BK _j ). It is in each of the auto addressing bus nodes ( BK ₁ to BK _n ) preferably present in each case. The first shunt resistors were not provided with indices for the respective bus nodes for a better overview.

R2 '

second shunt resistor for measuring the current through the second single-wire bus ( DB _b ) within the relevant bus node ( BK _j ). The second shunt resistor is shown here as part of the bus node ( BK _j ). It is in each of the auto addressing bus nodes ( BK ₁ to BK _n ) preferably present in each case. The second shunt resistors were not provided with indices for the respective bus nodes for a better overview.

Rec

Receiver. Each bus node ( BK ₁ to BK _n ) and the bus master ( ECU ) preferably have a receiver. A receiver extracts the information in the bit stream packets ( BP ) ( DATA ) and preferably outputs these together with error information about an output (out). The receiver typically checks that the check information ( CHKD ) within the data information ( DATA ) of a bit stream packet ( BP ) can be concluded to a faultless reception. Was a bit-stream packet ( BP ) received incorrectly, the receiver signals this.

r ₁

first control value of the first control signal ( rw ₁ ) of the first bus node ( BK ₁ );

r ' ₁

second control value of the second control signal ( rw ₁ ) of the first bus node ( BK ₁ );

r ₂

first control value of the first control signal ( rw ₂ ) of the second bus node ( BK ₁ );

r ' ₂

second control value of the second control signal ( rw ' ₁ ) of the second bus node ( BK ₁ );

r ₃

first control value of the first control signal ( rw ₃ ) of the third bus node ( BK ₁ );

r ' ₃

second control value of the second control signal (rw ' ₁ ) of the third bus node ( BK ₁ );

r _j

first control value of the first control signal ( rw _j ) of the jth bus node ( BK ₁ );

r ' _j

second control value of the second control signal ( rw ' ₁ ) of the jth bus node ( BK ₁ );

r _n

first control value of the first control signal ( rw _n ) of the nth bus node ( BK ₁ );

r ' _n

second control value of the second control signal ( rw ' ₁ ) of the nth bus node ( BK ₁ );

Rm ₁

measuring resistor in the supply voltage line for the first bus node ( BK ₁ );

Rm ₂

measuring resistor in the supply voltage line for the second bus node ( BK ₂ );

Rm ₃

measuring resistor in the supply voltage line for the third bus node ( BK ₃ );

Rm _j

measuring resistor in the supply voltage line for the jth bus node ( BK _j );

Rm _n

measuring resistor in the supply voltage line for the nth bus node ( BK _n );

rw ₁

first control signal of the first bus node ( BK ₁ ). The first control signal of the first bus node ( BK ₁ ) is by means, preferably a first filter ( F ) of the first bus node ( BK ₁ ), with the third comparator ( D3 ) of the first bus node ( BK ₁ ) can also form a unit, from the output signal of the third comparator ( D3 ) of the first bus node ( BK ₁ ) and is used to control the first auto-addressing power source ( Iq ₁ ) of the first bus node ( BK ₁ );

rw ' ₁

second control signal of the first bus node ( BK ₁ ). The second control signal of the first bus node ( BK ₁ ) is by means, preferably a second filter ( F ) of the first bus node ( BK ₁ ), which is connected to the corresponding third comparator ( D3 ' ) of the first bus node ( BK ₁ ) can also form a unit, from the output signal of the corresponding third comparator ( D3 ' ) of the first bus node ( BK ₁ ) and is used to control the second auto-addressing power source ( Iq ' ₁ ) of the first bus node ( BK ₁ );

rw ₂

first control signal of the second bus node ( BK ₂ ). The first control signal of the second bus node ( BK ₂ ) is by means, preferably a first filter ( F ) of the second bus node ( BK ₂ ), with the third comparator ( D3 ) of the second bus node ( BK ₂ ) can also form a unit, from the output signal of the second comparator ( D3 ) of the second bus node ( BK ₂ ) and serves to control the first auto-addressing power source ( Iq ₂ ) of the second bus node ( BK ₂ );

rw ' ₂

second control signal of the second bus node ( BK ₂ ). The second control signal of the second bus node ( BK ₂ ) is by means, preferably a second filter ( F ) of the second bus node ( BK ₂ ), who with the corresponding third comparator ( D3 ' ) of the second bus node ( BK ₂ ) can also form a unit, from the output signal of the corresponding third comparator ( D3 ' ) of the second bus node ( BK ₂ ) and is used to control the second auto-addressing power source ( Iq ' ₂ ) of the second bus node ( BK ₂ );

rw ₃

first control signal of the third bus node ( BK ₃ ). The first control signal of the third bus node ( BK ₃ ) is by means, preferably a first filter ( F ) of the third bus node ( BK ₃ ), with the third comparator ( D3 ) of the third bus node ( BK ₃ ) can also form a unit, from the output signal of the third comparator ( D3 ) of the third bus node ( BK ₃ ) and is used to control the first auto-addressing power source ( Iq ₃ ) of the third bus node ( BK ₃ );

rw _'3

second control signal of the third bus node ( BK ₃ ). The second control signal of the third bus node ( BK ₃ ) is by means, preferably a second filter ( F ) of the third bus node ( BK ₃ ), which is connected to the corresponding third comparator ( D3 ' ) of the third bus node ( BK ₃ ) can also form a unit, from the output signal of the corresponding third comparator ( D3 ' ) of the third bus node ( BK ₃ ) and is used to control the second auto-addressing power source ( Iq ' ₃ ) of the third bus node ( BK ₃ );

rw _j

first control signal of the jth bus node ( BK _j ). The first control signal of the jth bus node ( BK _j ) is by means, preferably a first filter ( F ) of the jth bus node ( BK _j ), with the third comparator ( D3 ) of the jth bus node ( BK _j ) can also form a unit, from the output signal of the third comparator ( D3 ) of the jth bus node ( BK _j ) and is used to control the first auto-addressing power source ( Iq _j ) of the jth bus node ( BK _j );

rw _'j

second control signal of the jth bus node ( BK _j ). The second control signal of the jth bus node ( BK _j ) is by means, preferably a second filter ( F ) of the jth bus node ( BK _j ), which is connected to the corresponding third comparator ( D3 ' ) of the jth bus node ( BK _j ) can also form a unit, from the output signal of the corresponding third comparator ( D3 ' ) of the jth bus node ( BK _j ) and is used to control the second auto-addressing power source ( Iq ' _j ) of the jth bus node ( BK _j );

rw _n

first control signal of the nth bus node ( BK _n ). The first control signal of the nth bus node ( BK _n ) is by means, preferably a first filter ( F ) of the nth bus node ( BK _n ), with the third comparator ( D3 ) of the nth bus node ( BK _n ) can also form a unit, from the output signal of the third comparator ( D3 ) of the nth bus node ( BK _n ) and is used to control the first auto-addressing power source ( Iq _n ) of the nth bus node ( BK _n );

rw _'n

second control signal of the nth bus node ( BK _n ). The second control signal of the nth bus node ( BK _n ) is by means, preferably a second filter ( F ) of the nth bus node ( BK _n ), which is connected to the corresponding third comparator ( D3 ' ) of the nth bus node ( BK _n ) can also form a unit, from the output signal of the

S4

corresponding third comparator ( D3 ' ) of the nth bus node ( BK _n ) and is used to control the second auto-addressing power source ( Iq _'n ) of the nth bus node ( BK _n ); first bypass switch - also called first bus shunt bypass switch - for bridging the first shunt resistor ( R2 ) within a bus node ( BK _j ). The first bypass switch may also be implemented as a transistor and / or as a more complex circuit of various electronic and other components, if the functionality of a switch results in the working area;

S4 '

second bypass switch - also called second bus shunt bypass switch - to bypass the second shunt resistor ( R2 ' ) within a bus node ( BK _j ). The second bypass switch can also be implemented as a transistor and / or as a more complex circuit of various electronic and other components, if the functionality of a switch results in the work area;

BEGIN

Start signal;

SUP

Voltage supply;

SW ₁

first threshold value for comparison with the first control value ( r ₁ ) of the first bus node ( BK ₁ ) for deciding whether the address data should be accepted as a valid bus node address;

SW ' ₁

second threshold value for comparison with the second control value ( r ' ₁ ) of the first bus node ( BK ₁ ) for deciding whether the address data should be accepted as a valid bus node address;

SW ₂

first threshold value for comparison with the first control value ( r ₂ ) of the second bus node ( BK ₂ ) for deciding whether the address data should be accepted as a valid bus node address;

SW ' ₂

second threshold value for comparison with the second control value ( r ' ₂ ) of the second bus node ( BK ₂ ) for deciding whether the address data should be accepted as a valid bus node address;

SW ₃

first threshold value for comparison with the first control value ( r ₃ ) of the third bus node ( BK ₃ ) for deciding whether the address data should be accepted as a valid bus node address;

SW ' ₃

second threshold value for comparison with the second control value ( r ' ₃ ) of the third bus node ( BK ₃ ) for deciding whether the address data should be accepted as a valid bus node address;

SW _j

first threshold value for comparison with the first control value ( r _j ) of the jth bus node ( BK _j ) for deciding whether the address data should be accepted as a valid bus node address;

SW ' _j

second threshold value for comparison with the second control value ( r ' _j ) of the jth bus node ( BK _j ) for deciding whether the address data should be accepted as a valid bus node address;

SW _n

first threshold value for comparison with the first control value ( r _n ) of the nth bus node ( BK _n ) for deciding whether the address data should be accepted as a valid bus node address;

SW ' _n

second threshold value for comparison with the second control value ( r ' _n ) of the nth bus node ( BK _n ) for the decision whether the address data as valid bus node address to be adopted;

SYNC

Synchronization information;

τ ₁

first time constant with which the increase of the first addressing current of the first regulated auto-addressing current source ( Iq _j ) of the relevant bus node ( BK _j ) he follows;

τ ₂

second time constant with which the lowering of the first addressing current of the first regulated auto-addressing current source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) he follows

τ ₃

third time constant with which the increase of the second addressing current of the second regulated auto-addressing power source ( Iq ' _j ) of the relevant bus node ( BK _j ) he follows;

τ ₄

fourth time constant with which the reduction of the second addressing current of the second regulated auto-addressing current source ( Iq ' _j ) of the relevant auto-addressing bus node ( BK _j ) he follows;

t ₁

first time after the start of the timer, to which a freeze of the control of the first addressing current source ( Iq _j ) of the relevant auto-addressing bus node ( BK _j ) he follows;

t ₂

second time after the start of the timer, to which a freeze of the control of the second addressing current source ( Iq ' _j ) of the relevant auto-addressing bus node ( BK _j ) he follows;

t ₃

third time at which, under certain conditions, the transfer of the bus node address to be assigned by the bus master ( ECU ) as the valid bus node address of the relevant auto-addressing bus node ( BK _j ) he follows;

t _B

Length of a single bit within a bit stream packet ( BP );

TR _a

first driver in the bus master ( ECU ) or in a bus node ( BK ₁ to BK _n ). Preferably, the driver is implemented as a CAN driver or RS485 driver. A first driver, as a CAN driver, preferably occupies two of three permitted states: in a first state, it sets a first logic level ( Z1 ) at first Single wire bus ( DB _a ). In a second state, it sets a third logic level ( Z3 ) on the first single-wire bus ( DB _a ). I The first driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as the first current sink for the first addressing currents of the first addressing current sources ( Iq ₁ to Iq _n ) the bus node ( BK ₁ to BK _n ) and their first quiescent currents. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the first state ( Z1 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the second state ( Z2 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the third state ( Z3 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the third state ( Z3 ). This will cause the signal to have a third differential level ( z3 ) impressed differentially. The first driver may also occupy two of two permissible states as an RS485 driver: in a first state, it sets a first logic level ( Z1 ) on the first single-wire bus ( DB _a ). In a second state it sets a second logic level ( Z2 ) on the first single-wire bus ( DB _a ). The first driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as the first current sink for the first addressing currents of the first addressing current sources ( Iq ₁ to Iq _n ) the bus node ( BK ₁ to BK _n ) and their first quiescent currents. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the first state ( Z1 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the second state ( Z2 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the first driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the second state ( Z2 ), if the second driver ( TR _b ) of the relevant bus node ( BK ₁ to BK _n ) the first state ( Z1 ). This will cause the signal to have a second differential level ( z2 ) impressed differentially. In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in case of simultaneous access to the first single-wire bus ( DB _a ) by a first driver of another bus node ( BK ₁ to BK _n ) or the bus master ( ECU ).

TR _b

second driver in the bus master ( ECU ) or in a bus node ( BK ₁ to BK _n ). Preferably, the second driver is implemented as a CAN driver or RS485 driver. A second driver may preferably assume two of three permitted states as a CAN driver: in a first state, it sets a second logic level ( Z2 ) on the second single-wire bus ( DB _b ). In a second state, it sets a third logic level ( Z3 ) on the second single-wire bus ( DB _b ). The second driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as the second current sink for the second addressing currents of second addressing current sources ( Iq ' ₁ to Iq _'n ) the bus node ( BK ₁ to BK _n ) and their second quiescent currents. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the second state ( Z2 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the first state ( Z1 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the third state ( Z3 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the third state ( Z3 ). This will cause the signal to have a third differential level ( z3 ) impressed differentially. The second driver can also assume two of two permitted states as an RS485 driver: in a first state, it sets a second logic level ( Z2 ) on the first single-wire bus ( DB _a ). In a second state, it sets a first logic level ( Z1 ) on the second single-wire bus ( DB _b ). The second driver of the bus master ( ECU ) also operates in the addressing state of the data bus system and the bus node ( BK ₁ to BK _n ) as a second current sink for the second addressing currents of the second addressing current sources ( Iq ' ₁ to Iq _'n ) the bus node ( BK ₁ to BK _n ) and their second quiescent currents. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the second state ( Z2 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the first state ( Z1 ). This will cause the signal to be at a first differential level ( z1 ) impressed differentially. Preferably, the second driver of a bus node ( BK ₁ to BK _n ) or the bus master ( ECU ) the first state ( Z1 ) when the first driver ( TR _a ) of the relevant bus node ( BK ₁ to BK _n ) the second state ( Z2 ). This will cause the signal to have a second differential level ( z2 ) impressed differentially. In addition, the first driver typically has a sub-device for detecting and avoiding a bus collision in case of simultaneous access to the first single-wire bus ( DB _a ) by a first driver of another bus node ( BK ₁ to BK _n ) or the bus master ( ECU ).

Vbat

Supply voltage line;

X1

first multiplexer for connecting a first input of the second differential amplifier ( D2 ) for measuring the current through the first single-wire bus ( DB _a ) with a first terminal of the first shunt resistor ( R2 ) on the side of the bus master ( ECU ) or optionally with a second connection of the measuring resistor ( Rm _j ) in the supply voltage line within the relevant bus node ( BK _j );

X1 '

second multiplexer for connecting a first input of the second comparator ( D2 ' ) for measuring the current through the second single-wire bus ( DB _b ) with a first terminal of the second shunt resistor ( R2 ' ) on the side of the bus master ( ECU ) or optionally with a second connection of the measuring resistor ( Rm _j ) in the supply voltage line within the relevant bus node ( BK _j );

X2

first multiplexer for connecting a second input of the second differential amplifier ( D2 ) for measuring the current through the first single-wire bus ( DB _a ) with a second terminal of the first shunt resistor ( R2 ) on the opposite side of the bus master ( ECU ) or with a first connection of the measuring resistor ( Rm _j ) in the supply voltage line within the relevant bus node ( BK _j );

X2 '

second multiplexer for connecting a second input of the second comparator ( D2 ' ) for measuring the current through the second single-wire bus ( DB _b ) with a second terminal of the second shunt resistor ( R2 ' ) on the opposite side of the bus master ( ECU ) or with a first connection of the measuring resistor ( Rm _j ) in the supply voltage line within the relevant bus node ( BK _j );

X3

first multiplexer for connecting a terminal of the first addressing current source ( Iq _j ) of Bus node ( BK _j ) with a first terminal of the first shunt resistor ( R2 ) or with a second connection of the first shunt resistor ( R2 ) or with a reference potential within the relevant bus node ( BK _j );

X3 '

second multiplexer for connecting a terminal of the second addressing current source ( Iq ' _j ) of the bus node ( BK _j ) with a first terminal of the second shunt resistor ( R2 ' ) or with a second connection of the second shunt resistor ( R2 ' ) or with a reference potential within the relevant bus node ( BK _j );

X4

first multiplexer for interchanging the inputs of the second differential amplifier ( D2 ) of the bus node ( BK _j );

X4 '

second multiplexer for interchanging the inputs of the further second differential amplifier ( D2 ' ) of the bus node ( BK _j );

X5

Multiplexer for interchanging the connections of the measuring resistor ( Rm _j ) of a bus node ( BK _j );

X6

first multiplexer for interchanging the terminals of the address input ( Adr _ij ) and the Astrest output ( Adr _oj ) of a bus node ( BK _j );

X7

second multiplexer for interchanging the terminals of the address input ( Adr _ij ) and the Astrest output ( Adr _oj ) of a bus node ( BK _j );

Z1

first logical state in which the first single-wire bus ( DB _a ) or the second single-wire bus ( DB _b ) can be located. This is also referred to as high in this disclosure.

z1

first differential state in The serial, bidirectional, differential two-wire communication bus ( DB ) can be located. This is also referred to as high in this disclosure.

Z2

second logical state in which the first single-wire bus ( DB _a ) or the second single-wire bus ( DB _b ) can be located. This is also referred to as Low in this disclosure.

z2

second differential state in The serial, bidirectional, differential two-wire communication bus ( DB ) can be located. This is also referred to as Low in this disclosure.

Z3

third logical state in which the first single-wire bus ( DB _a ) or the second single-wire bus ( DB _b ) can be located. This is also called idle in this disclosure. Preferably, but not necessarily, the corresponding physical level of the first single-wire bus ( DB _a ) or the second single-wire bus ( DB _b ) a value around a common mean.

z3

third differential state in The serial, bidirectional, differential two-wire communication bus ( DB ) can be located. This is also called idle in this disclosure. Preferably but not necessarily, the corresponding differential physical level has a value around zero

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 102017122365 [0063]

Cited non-patent literature

• MONAL GIRADKAR ET AL: "Design and Implementation of Adaptive Front Light System of Vehicles Using FPGA Based LIN Controllers", EMERGING TRENDS IN ENGINEERING AND TECHNOLOGY (ICETET), 2011 4TH INTERNATIONAL CONFERENCE ON, IEEE, November 18, 2011 (2011-11- 18), pages 258-261 [0007]
• GUO JINYAN ET AL: "The design and realization of CAN bit timing logic", MICROELECTRONICS AND ELECTRONIS (PRIMEASIA), 2010 ASIA PACIFIC CONFERENCE ON POSTGRADUATE RESEARCH IN, IEEE, PISCATAWAY, NJ, USA, September 22, 2010 (2010-09- 22), pages 333-337, XP031777603, ISBN: 978-1-4244-6735-8. [0008]
• ZENG WEIYING ET AL: "In-Vehicle Networks Outlook: Achievements and Challenges", IEEE COMMUNICATIONS SURVEYS & TUTORIALS, Vol. 18, No. 3, 27 February 2016 (2016-02-27), pages 1552-1571, XP011620858, DOI: 10.1109 / COMST.2016.2521642; [found on 2016-08-19] overview of automotive communications systems [0009]

Claims (3)

Bus node (BK _j ) for a data bus system with a communication bus, in particular a serial, bidirectional, differential two-wire communication bus (DB), with n bus nodes (BK ₁ , BK ₂ , BK ₃ , ..... BK _n-1 , BK _n ), where n is the whole positive number greater than zero, - wherein the bus node (BK _j ) comprises a supply voltage line section of a supply voltage line (V _bat ), via which it is supplied with electrical energy and - wherein the bus node (BK _j ) is provided to be connected to the communication bus (DB), and - wherein within the bus node (BK _j), a bus node (BK _j) associated measuring resistor (Rm _{j) (bat} V) in the power supply line in the region of the supply voltage line section inserted and - wherein the bus node (BK _j ) has an addressing current source (Iq _j ), and - the bus node (BK _j ) has means (D2, D3, Rm _j ) for passing the current through the measuring resistor (Rm _j ) of that bus node (BK _j ) to detect the bus node (BK ₁ to BK _n ) and - wherein the addressing current source (Iq _j ) of the bus node (BK _j ) is provided, an addressing current towards the power supply (SUP) of the data bus system in the supply voltage line (V _bat ) in the terminal of the measuring resistor (Rm _j ) this bus node (BK _j ) feed along the supply voltage line (V _bat ) farthest from the power supply (SUP), and - wherein the bus node (BK _j ) at least one Addressing state and can assume a normal state and - wherein the bus node has a bus node address register (BKADR), which may include a bus node address, which may be valid or invalid, and - wherein the bus node is provided to receive an indication of an addressing state, whereby its addressing state for the implementation of a car addressing method by means of the supply voltage line ( V _bat ), and - wherein the bus node is intended, when in the addressing state and has no valid bus node address, to receive signaling of a bus address to be assigned, and - the bus node being provided when it is in the addressing state is located and has no valid bus node address to receive a Autoaddressierungskommando over the communication bus, and - wherein the bus node is provided, if it is in the addressing state and has no valid bus node address to receive a start signal for the assignment of the bus address v zugeben and then stripping a timer at a start time (t ₀ = 0s), and - the bus node being provided, when in the addressing state and having no valid bus node address, the voltage drop across the measuring resistor (Rm _j ) d as the base voltage value ( V _m0 ) by means of measuring means ( Rm _j , D2, D3), and - wherein the bus node is provided, when it is in the addressing state and has no valid bus node address, at a fourth time (t ₄ ) after the start time (t ₀ ) the addressing current source ( Iq _j ) and the voltage drop across the measuring resistor (Rm _j ) of the relevant bus node (BK _j ) using this addressing current source (Iq _j ) in response to the voltage drop across the measuring resistor (Rm _j ) by means of a control signal (rw _j ), the is generated by measuring means (D2, D3, Rm _j ) and / or control means (F) of the bus node (BK _j ), to a total target voltage value corresponding to a target voltage value plus the previously measured base voltage value (V _m0 ), and wherein Bus node is provided, if it is in the addressing state and has no valid bus node address, an increase of the addressing current of Autoadressierungsstromque lle (Iq _j) carried out with a first time constant (τ ₁₎ and a lowering of the addressing current of the auto addressing current source (Iq _j) carried out with a second time constant (τ _2), and - wherein the bus node is provided, when it is in Adressierungsszustand and has no valid bus node address, at a fifth time (t ₅ ) after the start time (t ₀ ) and after the fourth time (t ₄ ) to detect the value of the control signal (rw _j ) or a signal derived therefrom and this value a threshold, and wherein the bus node is intended, when in the addressing state and does not have a valid bus node address, to use the bus node address to be granted as a valid bus node address of that bus node (BK _j ) if the magnitude of the detected value exceeds the threshold value, and - wherein the bus node is provided when it has a valid bus node address has the address current source (Iq _j ) at least in the addressing state until the address state by the bus node (BK _j ) to turn off. Bus node after Claim 1 - Where the second time constant (τ ₂ ) by a factor greater than 10 is smaller than the first time constant (τ ₁ ). Bus node after Claim 1 or 2 - wherein the second time constant (τ ₂ ) is smaller than the first time constant (τ ₁ ).

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