DE102017219674A1 - Semiconductor power module with integrated capacitor - Google Patents

Abstract

The invention relates to power electronic circuits, in particular power electronic circuits in a vehicle, the semiconductor power modules and DC link capacitors, for example, the so-called commutation of an inverter.

Description

The invention relates to power electronic circuits, in particular power electronic circuits in a vehicle, the semiconductor power modules and DC link capacitors, for example, the so-called commutation of an inverter. An inverter powers the electric motor in a hybrid or electric vehicle.

According to the current state of the art, half-bridge modules or three-phase modules are used in so-called hard-switching inverters. These are often connected via bus bars directly to a DC link capacitor, as shown in 1 is shown. The distance between the busbars is kept as low as possible due to the parasitic inductances and the leadership of the rails is carried out as parallel or stacked as possible. The parasitic inductances for the total loop are then in the range of 50-100 nH.

The relatively large inductance in the commutation path causes large voltage peaks ("voltage overshoot") during switch-off, especially in the case of fast-switching power semiconductors with di / dt> 3,000 A / μs. For this reason, the switching speed (di / dt) must be limited so that the blocking voltage of the power semiconductors is not reached or exceeded. Since the switching losses from the product of current and voltage in the switching process are calculated, such voltage overshoots make a significant contribution to the switching losses. In addition, the parasitic inductance limits the switching speeds, as a larger inductance leads to a greater tendency to oscillate.

Using conventional silicon-based IGBTs used in standard traction converters, the phenomena previously described can be mastered. With SiC power semiconductors much higher switching speeds are achieved. Values in the range from 12,000 A / μs to 40,000 A / μs are achieved for di / dt. Therefore, the voltage overshoots at turn-off and the so-called ringing result in massive limitations, so that the SiC power semiconductor material can not be fully utilized.

An object of the present invention was to provide arrangements and methods by means of which the sum of the parasitic inductances or the total leakage inductance in power electronic circuits can be reduced.

According to the invention the object is achieved by a device having the features of claim 1 and a method having the features of claim 9. Embodiments of the device and the method emerge from the dependent claims.

One aspect of the solution according to the invention is to divide a capacitor provided in the power electronic circuit into several components and to place a smaller capacitance directly in the power module in the vicinity of the power semiconductors or directly on the power semiconductors in order to reduce the parasitic inductances.

The application of capacitors to semiconductor devices is known in principle.

So revealed the DE 199 40 200 A1 a pyrotechnic ignition system with integrated ignition circuit, wherein a semiconductor device is connected in flip-chip technology with a starting capacitor. The semiconductor device is applied to a capacitor to realize a more compact overall circuit.

From the DE 11 2005 002 373 T5 For example, a shared thin-film capacitor for multiple voltages is known. The thin-film capacitor is connected to the substrate of a further semiconductor component by means of flip-chip technology.

From the DE 10 2005 009 508 A1 shows the production of a mountable on a surface of a component flip-chip capacitor out. The flip-chip capacitor is connected by conductive tracks with a conductive powder.

The invention relates to a power electronic circuit, the at least one power semiconductor and at least two capacitors connected in parallel C _big and C _small includes, where C _big is arranged outside of the at least one power semiconductor comprehensive power module and C _small is arranged within the power module comprising the at least one power semiconductor. In an embodiment C _big a larger capacity than C _small , In another embodiment, the capacitors C _big and C _small Ceramic capacitors. The advantage of the solution according to the invention lies in the minimization of the parasitic inductances or the leakage inductance.

In one embodiment of the invention, the at least one power semiconductor is an IGBT. In another embodiment, the at least one power semiconductor is a MOSFET. In one embodiment of the invention, the power module comprises at least one silicon power semiconductor. In a further embodiment, the power module comprises at least one silicon carbide power semiconductor.

In one embodiment of the invention, the power module is a half-bridge circuit comprising two power semiconductors and a capacitor C _small includes. In a further embodiment, the power electronic circuit is a commutation cell of an inverter and comprises at least one half-bridge circuit and an intermediate circuit capacitor C _big , In a further embodiment, the power electronic circuit comprises a plurality, in particular three, half-bridge circuits and an intermediate circuit capacitor C _big to which the half-bridge circuits are connected. In another embodiment, the power electronic circuit comprises an intermediate circuit capacitor C _big and a three-phase inverter module.

In one embodiment of the invention, at least one ceramic capacitor C _small arranged in the power module between HV + and HV, eg clamped. The outer capacitor C _big is connected to the power module. The capacity of the capacitor C _big but can be reduced due to the module's internal capacity.

In a further embodiment of the invention, the capacitor C _small mounted directly on two power semiconductors, which are components of a half-bridge circuit. One of the two power semiconductors must then be placed flipped on the substrate.

In a variant of the invention, the current loops of the capacitors are coupled in such a way that their magnetic fluxes compensate and thereby reduce the effective leakage inductance. In one embodiment, the current loops for C _small and C _big is crossed and the coupling between the parasitic inductances is exploited to compensate for the magnetic fluxes and further reduce the effective inductance.

The invention also provides a method for reducing stray inductance in power electronic circuits, which comprises at least one power module and at least one capacitor C include. The power module comprises at least one power semiconductor.

In the method according to the invention, the at least one capacity C by two parallel connected capacitors C _big and C _small formed, the sum of the capacitances of the capacitors C _big and C _small the capacity C corresponds. In one embodiment, the capacitor becomes C _big located outside the power module and the capacitor C _small within the power module. In a further embodiment, the current loops of the capacitors C _big and C _small guided in parallel and through one of the two loops, the current is conducted in the opposite direction to the current direction through the other loop.

It is one of the advantages of the present invention that the stray inductance in a power electronic circuit, for example a commutation loop, can be significantly reduced. This results in lower power losses. If the power electronic circuit is, for example, an inverter in an electrically driven vehicle, the result is a lower cycle consumption.

Another advantage of the present invention is that the space requirement and the weight of a power electronic circuit can be reduced.

The present invention also allows maximum utilization of power semiconductors and advantages in EMC performance. The power electronic circuits according to the invention can be operated with a smaller safety margin to the blocking voltage of the power semiconductors, which entails advantages in terms of cost and power losses.

It is understood that the features mentioned above and those yet to be explained below can be used not only in the particular combination indicated, but also in other combinations or in isolation, without departing from the scope of the present invention.

• 1 drei mit einem Zwischenkreiskondensator verbundene Halbbrückenmodule in perspektivischer Darstellung;
• 2 ein elektrisches Ersatzschaltbild einer Halbbrücke inklusive Kondensator;
• 3 den Strom- und Spannungsverlauf bei einem Ausschaltvorgang in einem Halbbrückenmodul des Standes der Technik;
• 4 ein elektrisches Ersatzschaltbild einer erfindungsgemäßen Halbbrücke inklusive Kondensatoren ;
• 5 ein elektrisches Ersatzschaltbild einer anderen erfindungsgemäßen Halbbrücke inklusive Kondensatoren ;
• 6 eine perspektivische Darstellung einer Anordnung eines Keramikkondensators auf zwei MOSFETs in Flip-Chip-Technik mit gekreuzten Stromflüssen;
• 7 a) eine schematische Draufsicht einer Ausführungsform eines erfindungsgemäßen Leistungsmoduls; 7 b) den DC-Leitungspfad in dem Leistungsmodul; 7 c) den Leitungspfad zu dem Kondensator des Leistungsmoduls;
• 8 a) eine schematische Seitenansicht einer anderen Ausführungsform eines erfindungsgemäßen Leistungsmoduls; 8 b) eine perspektivische Darstellung des Leistungsmoduls; 8 c) den DC-Leitungspfad in dem Leistungsmodul; 8 d) den Leitungspfad zu dem Kondensator des Leistungsmoduls;
• 9 a) eine schematische Draufsicht einer weiteren Ausführungsform eines erfindungsgemäßen Leistungsmoduls; 9 b) den DC-Leitungspfad in dem Leistungsmodul; 9 c) den Leitungspfad zu dem Kondensator des Leistungsmoduls.

The invention is illustrated by means of embodiments in the figures and will be further described with reference to the figures. It shows:

• 1 three connected to a link capacitor half bridge modules in perspective view;
• 2 an electrical equivalent circuit of a half-bridge including capacitor;
• 3 the current and voltage during a turn-off in a half-bridge module of the prior art;
• 4 an electrical equivalent circuit diagram of a half-bridge according to the invention including capacitors;
• 5 an electrical equivalent circuit diagram of another half-bridge according to the invention including capacitors;
• 6 a perspective view of an arrangement of a ceramic capacitor on two MOSFETs in flip-chip technology with crossed current flows;
• 7 a) a schematic plan view of an embodiment of a power module according to the invention; 7 b) the DC line path in the power module; 7c) the conduction path to the capacitor of the power module;
• 8 a) a schematic side view of another embodiment of a power module according to the invention; 8 b) a perspective view of the power module; 8c) the DC line path in the power module; 8 d) the conduction path to the capacitor of the power module;
• 9 a) a schematic plan view of another embodiment of a power module according to the invention; 9 b) the DC line path in the power module; 9 c) the conduction path to the capacitor of the power module.

1 shows schematically three with a DC link capacitor 12 connected half-bridge modules 11 in perspective view. The half-bridge modules 11 are over power rails 13 with the DC link capacitor 12 connected.

2 shows an electrical equivalent circuit of a half-bridge including capacitor C _big as known in the art. The half-bridge comprises two MOSFETs, MOSFET1 (high side) and MOSFET2 (low side). Also marked are the leakage inductances occurring in the module L ₁ . L ₂ . L ₃ ,

3 shows the current and voltage curve in a turn-off in a half-bridge module of the prior art. The curves show the course of current and voltage measured over an exemplary switch-off process over time. As can be seen from the diagram, the maximum change in the current intensity is di / dt = -3000 A / μs. The result is a voltage peak with an overvoltage ΔU of about 160 V.

In 4 an electrical equivalent circuit diagram of an embodiment of a half-bridge according to the invention is shown. Instead of a single capacitor C _big are two parallel capacitors C _big and C _small available. The capacitor C _small is attached directly to the power semiconductors and has a much lower capacity than C _big , Also in the conduction path of the capacitor C _small occurring stray inductances L ₃ and L ₄ are much smaller than those in the conduction path of the capacitor C _big occurring stray inductances L ₁ and L ₅ , (L ₁ >> L ₃ and L ₅ >> L ₄ ).

5 shows an electrical equivalent circuit diagram of another embodiment of a half-bridge according to the invention. In this embodiment, the loops intersect with the two capacitors connected in parallel C _big and C _small , As a result, the current directions in the two capacitors in opposite directions, the coupling between the parasitic inductances L ₁ and L ₃ such as L ₅ and L ₄ leads to a compensation of the generated magnetic flux and a further reduction of the effective leakage inductance. Also in this embodiment, the capacitor C _small attached directly to the power semiconductors.

6 is a perspective schematic representation of an arrangement of a ceramic capacitor 61 on two MOSFETs in flip-chip technology with crossed current flows. The ceramic capacitor 61 , the C _small is equivalent, is about the connections 62 and 63 connected to the power semiconductors. The DC link capacitor C _big is about the connections 64 and 65 connected to the module and is not shown in the drawing.

Hereinafter, three design variants for power electronic modules according to the invention are described and compared with each other. Each module comprises two MOSFETs forming a half-bridge. A snubber circuit is used to attenuate the rapid increase in voltage across a transistor. A capacitor is placed directly in the module. The simulation of the modules was done with the software ANSYS Q3D. The total inductance for DC and the total resistance for DC of each module were calculated.

A first module design is in 7 shown. In this variant, the power semiconductors (MOSFET1, MOSFET2) are arranged coplanar. The DC + and DC- terminals of the module are located close together so that the generated magnetic fields overlap and cancel out. A capacitor (not shown) is above the terminals 71 connected to the module. The MOSFETs are over thin films 74 with the copper plates 76 . 77 connected. connection films 74 connect MOSFET1 (high side) to one terminal 75 on the copper plate 78 and MOSFET2 (low side) with one terminal 75 on the copper plate 77 , The design does not use bonding wires to prevent the magnetic field generated by the wires and reduce electromagnetic interference.

• • Kupferplatte 76: 10 mm x 20 mm x 0,2 mm;
• • Kupferplatte 78: 10 mm x 9 mm x 0,2 mm;
• • Kupferplatte 77: 14 mm x 10 mm x 0,2 mm + 3 mm x 10 mm x 0,2 mm;
• • MOSFET1: 7 mm x 7 mm x 0,3 mm;
• • MOSFET2: 7 mm x 7 mm x 0,3 mm;
• • DC+ / DC- Anschlüsse (Kupfer): 2 mm x 1 mm x 4,6 mm;
• • Anschlussfolien 74: 4 mm x 7 mm x 0,5 mm.

The dimensions of the individual components are summarized below:

• • copper plate 76 : 10mm x 20mm x 0.2mm;
• • copper plate 78 : 10mm x 9mm x 0.2mm;
• • copper plate 77 : 14mm x 10mm x 0.2mm + 3mm x 10mm x 0.2mm;
• • MOSFET1: 7mm x 7mm x 0.3mm;
• • MOSFET2: 7mm x 7mm x 0.3mm;
• • DC + / DC terminals (copper): 2 mm x 1 mm x 4.6 mm;
• • Connection foils 74 : 4mm x 7mm x 0.5mm.

In 7 b) is the current flow in the module from the source 72 to the valley 73 symbolized by arrows. The total inductance of the device is calculated to be 15.332 nH, the total resistance to 0.507 mΩ. In 7c) is the conduction path to the capacitor not shown in the picture, via the connections 71 connected to the module, symbolized by arrows. The ANSYS Q3D software also calculates AC inductors and AC resistors at different frequencies for the module, respectively for the current path and the conduction path to the internal capacitor. The following results were obtained: current path conduction path frequency inductance resistance inductance resistance 10 kHz 14,480 nH 0.567 mΩ 3.028 nH 0.159mΩ 100 kHz 12.709 nH 1.067 mΩ 2,704 nH 0.254 mΩ 1 MHz 11,837 nH 2,872 mΩ 2,512 nH 0.685 mΩ

A second module design is in 8th shown. In this variant, the power semiconductors (MOSFET1, MOSFET2) are arranged on top of each other. The dimensions of the module are significantly smaller, the entire module is very compact. The module can be cooled from both sides. The current flows through the parallel copper plates 86 . 87 in opposite directions, causing the generated magnetic fields to overlap and cancel. A capacitor (not shown) is above the terminals 81 connected to the module. The MOSFETs are above the copper plates 88 connected with each other.

• • a 16 mm;
• • b 12 mm;
• • c 6,7 mm;
• • d 10 mm;
• • e 5,6 mm.

8 b) shows a perspective view of the module with drawn dimensions ae. The dimensions are:

• • a 16 mm;
• • b 12 mm;
• • c 6.7 mm;
• • d 10 mm;
• • 5.6 mm.

In 8c) is the current flow in the module from the source 82 to the valley 83 symbolized by arrows. The total inductance of the module was calculated to be 10.489 nH, the total resistance to 0.315 mΩ. In 8 d) is the conduction path to the capacitor not shown in the picture, via the connections 81 connected to the module, symbolized by arrows. The ANSYS Q3D software also calculates AC inductors and AC resistors at different frequencies for the module, respectively for the current path and the conduction path to the internal capacitor. The following results were obtained: current path conduction path frequency inductance resistance inductance resistance 10 kHz 10,054 nH 0.345 mΩ 1,818 nH 0.105 mΩ 100 kHz 9.218 n 0.605 mΩ 1,667 nH 0.161 mΩ 1 MHz 8.708 nH 1.734 mΩ 1.536 nH 0.492 mΩ

A third module design is in 9 shown. In this variant, the power semiconductors (MOSFET1, MOSFET2) are arranged side by side and MOSFET1 is turned on the back ("flipped"). The current flows through the copper plates 96 . 97 and the parallel copper plate 98 in opposite directions, causing the generated magnetic fields to be superimposed and canceled, thereby reducing electromagnetic interference. A capacitor (not shown) is above the terminals 91 connected to the module. The gates 94 . 95 The MOSFETs are led out of the module at the side. The module can be cooled from both sides.

• • Kupferplatte 96: 8 mm × 8,5 mm × 0,2 mm;
• • Kupferplatte 98: 10 mm × 17 mm × 0,2 mm;
• • Kupferplatte 97: 8 mm × 8 mm × 0,2 mm;
• • MOSFET1: 7 mm × 7 mm × 0,3 mm;
• • MOSFET2: 7 mm × 7 mm × 0,3 mm;
• • DC+ / DC- Anschlüsse (Kupfer): 1 mm × 1 mm × 1,8 mm.

The dimensions of the individual components are summarized below:

• • copper plate 96 : 8 mm × 8.5 mm × 0.2 mm;
• • copper plate 98 : 10 mm × 17 mm × 0.2 mm;
• • copper plate 97 : 8 mm × 8 mm × 0.2 mm;
• • MOSFET1: 7 mm × 7 mm × 0.3 mm;
• • MOSFET2: 7 mm × 7 mm × 0.3 mm;
• • DC + / DC terminals (copper): 1 mm × 1 mm × 1.8 mm.

In 9 b) is the current flow in the module from the source 92 to the valley 93 symbolized by arrows. The total inductance of the module was calculated to be 3.799 nH, the total resistance to 0.519 mΩ. In 9 c) is the conduction path to the capacitor not shown in the picture, via the connections 91 connected to the module, symbolized by arrows. The ANSYS Q3D software also calculated AC inductances and AC resistances at different frequencies for the module, respectively for the current path and the conduction path to the internal capacitor. The following results were obtained: current path conduction path frequency inductance resistance inductance resistance 10 kHz 3,599 nH 0.53 mΩ 1,686 nH 0.219 mΩ 100 kHz 3,133 nH 0.71mΩ 1.577 nH 0.273 mΩ 1 MHz 2.775 nH 1.52 mΩ 1,431 nH 0.653mΩ

The following table shows a comparison of the parasitic inductances used in the 7 to 9 shown power modules calculated for different line paths in each module: path Inductance [nH] 7 8th 9 DC + to DC 15.332 10.489 3,779 Gate-source loop 1.524 1.95 3,336 DC + to drain 6,185 5,036 1,862 DC to Source 9.103 5,443 1,862

LIST OF REFERENCE NUMBERS

11

power module

12

Link capacitor

13

conductor rail

61

ceramic capacitor

62

HV + C _small

63

HV-C _small

64

Connection HV + C _big

65

Connection HV- C _big

71

Connection capacitor

72

source

73

depression

74

conductive foil

75

Connection MOSFET

76

copperplate

77

copperplate

78

copperplate

81

Connection capacitor

82

source

83

depression

86

copperplate

87

copperplate

88

copperplate

91

Connection capacitor

92

source

93

depression

94

Gate MOSFET1

95

Gate MOSFET2

96

copperplate

97

copperplate

98

copperplate

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• DE 19940200 A1 [0009]
• DE 112005002373 T5 [0010]
• DE 102005009508 A1 [0011]

Claims (10)

Power electronic circuit comprising at least one power semiconductor and at least two capacitors C _big and C _small connected in parallel, wherein C _{big is arranged} outside a power module comprising the at least one power semiconductor and C _small is arranged inside the power module comprising the at least one power semiconductor. Power electronic circuit according to Claim 1 wherein the power module comprises at least one half-bridge circuit having two power semiconductors and a capacitor C _small . Power electronic circuit according to Claim 1 or 2 which forms a commutation cell of an inverter and comprises at least a half-bridge circuit and a DC link capacitor Cbig. Power electronic circuit according to one of Claims 1 to 3 in which the capacitors Cbig and Csmall are ceramic capacitors. Power electronic circuit according to one of Claims 1 to 4 wherein the at least one power semiconductor is an IGBT. Power electronic circuit according to one of Claims 1 to 4 wherein the at least one power semiconductor is a MOSFET. Power electronic circuit according to one of Claims 1 to 6 in which the capacitor Csmall is mounted directly on two power semiconductors which are components of a half-bridge circuit. Power electronic circuit according to one of Claims 1 to 7 in which the current loops of the capacitors Cbig and Csmall are coupled such that the stray inductances of the current loops at least partially cancel each other out. Method for reducing the leakage inductance in a power electronic circuit, which comprises at least one power module comprising at least one power semiconductor and at least one capacitor C, wherein the at least one capacitor C is formed by two capacitors Cbig and Csmall connected in parallel, the sum of the capacitances of the capacitors Cbig and Csmall corresponds to the capacitance C, and wherein the capacitor Cbig is placed outside the power module and the capacitor Csmall is placed inside the power module. Method according to Claim 9 in which the current loops of the capacitors Cbig and Csmall are led in parallel and in which the current through the other loop is passed through one of the two loops in the opposite direction to the current direction.

Images