DE102017216991B4 - Communication module and device for data transmission - Google Patents

Abstract

Communication module (21) which is designed to be operated as a slave and to be connected to a second communication module (22) which is designed to be operated as a master, the first communication module (21) having a first line (CLK) for receiving a clock signal from the second communication module (22), a second line (MOSI) for receiving data, a third line (MISO) for sending data and a fourth line (CS), via which the first communication module (21) through the second communication module (22) can be activated. The communication module (21) further has at least one of a fifth line (BUSY) for outputting a first signal which contains information about whether the first communication module (21) is ready to receive data, and a sixth line (IRQ) for outputting a second signal which contains information about whether the first communication module (21) wants to send data.

Description

The invention relates to a communication module and a device for data transmission, in particular a communication module for a serial peripheral interface (SPI interface).

The Serial Peripheral Interface (SPI) is a bus system with a standard for a synchronous serial data bus (Synchronous Serial Port) with which digital circuits can be connected to one another according to the master-slave principle. An SPI allows data to be exchanged serially (one bit at a time) between two devices, one called a master and the other a slave. An SPI can operate in full duplex mode, meaning that data can be transmitted in both directions at the same time. For example, control units can be connected to peripheral devices or to microcontrollers using SPI.

SPI communication blocks support various functions, such as the configuration of communication parameters, writing and reading outgoing and incoming data, etc. An SPI slave should generally have a high level of time accuracy with the highest possible availability and the lowest possible software overhead. However, it is particularly problematic in software that the times at which communication should take place are determined by the master. The slave must therefore provide the data to be sent at the desired time and collect the data to be received from the master at the desired time. Providing the data in the slave at precisely the right time is relatively complex with conventional software-driven SPI communication blocks. Most building blocks are a compromise between availability, complexity, interrupt load and resource consumption (e.g. CPU runtime, behavior in phases of low performance, etc.).

The publication US 2006/0143348 A1 discloses a method for interchip communication between an extended serial peripheral interface (EPSI) master chip with clocking capability and an EPSI slave chip. The method includes selecting a slave chip by the master chip, clocking the master data from the master chip into the slave chip and simultaneously clocking data from the slave chip into the master chip, and the Processing the clocked data to negotiate further data transfer between the master chip and the slave chip. Selection of a slave chip by the master chip may also occur in response to an interrupt received by the master chip from the slave chip, with the master then clocking data in both directions to enable further data transfer between the master chip and to negotiate with the slave chip.

The object of the invention is to provide an improved communication module, in particular a slave, and an improved device for data communication, which have high performance as well as low complexity and short runtimes of a required software driver, so that the master can be used as a conventional (SPI) Master can be implemented.

This task is solved by a communication module according to claim 1, a communication module according to claim 13 or a device for data transmission according to claim 14.

The communication module according to the invention is designed to be operated as a slave and to be connected to a second communication module. The second communication module is designed to be operated as a master. The first communication module has a first line for receiving a clock signal from the second communication module, a second line for receiving data, a third line for sending data and a fourth line via which the first communication module can be activated by the second communication module. The first communication module also has either a fifth line for outputting a first signal which contains information about whether the first communication module is ready to receive data, or a sixth line for outputting a second signal which contains information about whether the first communication module is ready to receive data want to send, or both.

Data flow control can be carried out via the fifth and sixth lines. The second communication module is informed at all times whether the first communication module can receive data and/or wants to send data. If the first communication module cannot receive data at a time, the second communication module can, for example, refrain from sending data and instead wait until the first communication module is ready to receive data again. This allows unwanted error situations to be avoided.

The first communication module can be designed to be connected to the second communication module via an SPI bus. The first, second, third and fourth lines are typically already present in an SPI bus. The fifth and sixth lines are an addition to these lines.

The first communication module can further have at least one input buffer, which is designed to store messages that are received from the second communication module. Received messages are therefore not processed further directly, but are first cached. The data can be read from the input buffer and processed at any later time.

The first communication module also has at least one output buffer, which is designed to store messages that are to be transmitted to the second communication module. Messages can be placed in the output buffer at any time. If communication is then initiated by the second communication module, it can then read the data from the output buffer.

The first communication module can be designed to be connected to a microcontroller, whereby the microcontroller can be designed to read and process messages from the input buffer and to store messages in the output buffer for transmission to the second communication module. The first communication block therefore only serves as an interface. The data is processed and provided in the microcontroller.

The first signal of the fifth line can assume a first state if the first communication module cannot receive new messages and can assume a second state if the first communication module can receive new messages. The state of the signal thus simply reflects the state of the first communication module.

The second signal of the sixth line can assume a first state if the first communication module wants to send new messages and can assume a second state if the first communication module does not have to send any new messages. The state of the signal thus easily reflects the state of the first communication module.

The first communication module can be designed to send messages to the second communication module, which have a checksum in addition to user data, and to receive messages from the second communication module, which also have a checksum in addition to user data. This makes it easy to check the integrity of a message using the checksum.

The first communication module can further have at least one of at least a first shift register, which is arranged in front of the input buffer in such a way that messages received from the second communication module are first stored in the first shift register and from there are transferred to the input buffer, and at least one second shift register , which is arranged behind the output buffer in such a way that messages that are to be sent to the second communication module are transferred from the output buffer to the second shift register and are transmitted from there to the second communication device. This means that another buffer is provided before or after the respective input or output buffer.

The communication module can alternatively or additionally have at least one shift register, with at least one of the shift registers being designed to initially store both messages that are received from the second communication module before they are transferred from there to the input buffer, as well as messages that are sent to the second communication module are to be sent, from the output buffer before they are transmitted from there to the second communication device.

The shift registers can be driven by the clock signal or by a clock generated from the clock signal.

A message that is to be transmitted to the second communication module can be stored in the output buffer at a first time. A first timestamp is stored together with the message in the output buffer, the first timestamp containing information about the first point in time. The message can then be transmitted to the second communication module 6 at a second time. The first communication module is designed to replace the first time stamp with first data when the message is transmitted to the second communication module, the first data having information about a time period (delta) that has passed between the first time and the second time .

A second communication module is designed to be operated as a master and to be connected to at least a first communication module. The first communication module is designed to act as a slave to be operated. The second communication module has a first line for outputting a clock signal to the at least one first communication module, a second line for sending data, a third line for receiving data and a fourth line via which the second communication module can activate the at least one first communication module. The second communication module has either a fifth line for receiving a first signal from the at least one first communication module, the first signal containing information about whether the at least one first communication module is ready to receive data, or a sixth line for receiving a second signal from the at least one first communication module, the second signal containing information about whether the at least one first communication module wants to send data, or both.

A device for data transmission has at least a first communication module and a second communication module, the at least one first communication module being designed to be operated as a slave and the second communication module being designed to be operated as a master. The at least one first communication module and the second communication module are connected to one another via a data bus. The data bus has a first line for transmitting a clock signal from the second communication module to the first communication module, a second line for transmitting data from the second communication module to the at least one first communication module, a third line for transmitting data from the at least one first communication module the second communication module and a fourth line via which the at least one first communication module can be activated by the second communication module. The device further has either a fifth line for transmitting a first signal to the second communication module which contains information about whether the at least one first communication module is ready to receive data, or a sixth line for transmitting a second signal to the second communication module which contains information whether the at least one first communication module wants to send data, or both. The first communication module also has at least one output buffer, which is designed to store messages that are to be transmitted to the second communication module. A message that is to be transmitted to the second communication module can be stored in the output buffer at a first time. A first timestamp is stored together with the message in the output buffer, the first timestamp containing information about the first point in time. The message can then be transmitted to the second communication module at a second time. The first communication module is designed to replace the first time stamp with first data when the message is transmitted to the second communication module, the first data having information about a time period (delta) that has passed between the first time and the second time .

The device can be arranged in a vehicle.

• 1 in einer schematischen Darstellung beispielhaft das Prinzip eines Serial Peripheral Interface,
• 2 beispielhaft in einem Blockdiagramm einen Kommunikationsbaustein,
• 3 beispielhaft in zeitlichen Diagrammen Signale in einer Datenkommunikation,
• 4 beispielhaft in zeitlichen Diagrammen Signale in einer Datenkommunikation unter Verwendung von Puffern,
• 5 beispielhaft in einem Blockdiagramm eine Schnittstelle zwischen einem Mikrocontroller und einem Kommunikationsbaustein,
• 6 , aufweisend die 6A und 6B, eingehende und ausgehende SPI-Daten,
• 7 beispielhaft in einem Blockdiagramm einen Kommunikationsbaustein mit Puffern und Schieberegistern,
• 8 beispielhaft in zeitlichen Diagrammen eine zeitliche Zuordnung eines Übertragungszeitpunkts und eines Verarbeitungszeitpunkts,
• 9 beispielhaft ausgehende SPI-Daten mit einem Zeitstempel, und
• 10 beispielhaft in zeitlichen Diagrammen eine zeitliche Zuordnung eines Beauftragungszeitpunktes und eines Übertragungszeitpunktes.

The invention is explained in more detail below with reference to the exemplary embodiments shown in the figures of the drawing. It shows:

• 1 in a schematic representation, the principle of a serial peripheral interface is exemplified,
• 2 For example, a communication block in a block diagram,
• 3 For example, in time diagrams, signals in data communication,
• 4 for example in time diagrams signals in a data communication using buffers,
• 5 For example, in a block diagram, an interface between a microcontroller and a communication module,
• 6 , having the 6A and 6B , incoming and outgoing SPI data,
• 7 For example, in a block diagram, a communication block with buffers and shift registers,
• 8th For example, in temporal diagrams, a temporal assignment of a transmission time and a processing time,
• 9 for example, outgoing SPI data with a timestamp, and
• 10 For example, in time diagrams, a time allocation of a commissioning time and a transfer time.

1 shows a schematic representation of a serial peripheral interface. A Serial Peripheral Interface (SPI) is a bus system with a standard for a synchronous serial data bus (Synchronous Serial Port) with which digital circuits can be connected to one another according to the master-slave principle. An SPI enables the serial (one bit at a time) exchange of data between two modules 11, 12, one of which is referred to as master 12 and the other as slave 11. An SPI can operate in full duplex mode, which means that data can be transferred in both directions (master to slave and slave to master) simultaneously. For example, control units can be connected to peripheral devices or to microcontrollers using SPI.

An SPI communication module, regardless of whether it functions as a master or a slave, has three lines to which each participant (master and one or more slaves) is connected. These are a clock line CLK, also known as clock or serial clock, where the clock is output by the master, and two lines for transmitting data. A so-called MOSI line (Master Output, Slave Input), for transferring data from master 12 to slave 11, and a so-called MISO line (Master Input, Slave Output), for transferring data from slave 11 to master 12 The data lines can, for example, also be referred to as Serial Data Out (SDO) and Serial Data In (SDI), whereby the naming usually occurs from the perspective of the respective bus participant, so that in this case the lines have to be connected crosswise in contrast to that illustrated case in which MISO is connected to MISO and MOSI is connected to MOSI.

An SPI communication module also has one or more logic-0 active chip select lines (CS line) (often also referred to as Slave Select SS or Slave Transmit Enable STE). As a rule, each slave only has one CS line. A master can have one or more CS lines. For example, the master can have its own CS line for each slave to which it is connected. These lines CS are controlled by the master 12.

Theoretically, any number of participants can be connected to an SPI bus. However, exactly one master 12 is always required to generate the clock signal CLK. Using the Chip-Select CS line, the master 12 determines which slave 11 it wants to communicate with. If the corresponding CS line is pulled to ground (logical 0) by the master 12, the associated slave 11 is active and “listens” on the MOSI line whether data is being transmitted from the master 12. At the same time, it applies its data that is to be transmitted to the master 12 to the MISO line in time with the clock signal. In a subsequent data communication, a word is transmitted from the master 12 to the slave 11 and another word from the slave 11 to the master 12.

There is no set data transfer protocol for SPI, but four different modes have generally been adopted. These are determined by the Clock Polarity (CPOL) and Clock Phase (CPHA) parameters. With CPOL = 0 the clock idle is low, with CPOL = 1 the clock idle is high. CPHA specifies at which edge of the clock signal the data should be accepted. If CPHA = 0 they are applied on the first edge after CS is pulled low, and if CPHA = 1 on the second edge. Thus, with CPOL = 0 and CPHA = 0, the data is accepted with the first edge, which can only be a rising edge. If CPHA = 1 it would be the second edge, i.e. a falling edge. With CPOL = 1 this is exactly the other way around, i.e. with CPHA = 0 a falling edge and with CPHA = 1 a rising edge.

With CPHA = 0, slave 11 usually applies its data to MISO when CS goes low so that master 12 can accept it at the first edge change. With CPHA = 1, the data from slave 11 is only sent to MISO at the first edge change so that it can be accepted by master 12 at the second edge change. The master 12, on the other hand, always creates its data at the same time, usually shortly after the falling edge of CLK.

One bit is transmitted with each clock period. With the usual byte transfer, eight clock periods are necessary for a complete transfer. Several words can also be transmitted one after the other. It is not specified whether the CS line must be briefly pulled to high after each word or not. A transmission is ended when the CS line is finally set to high again.

2 shows an example of a communication module 21 in a block diagram. The communication module 21 (hereinafter referred to as a slave) is designed to be operated as a slave and has several lines (or pins). These are a first line CLK for receiving a clock signal. The slave 21 receives the clock signal from a second communication module 22, which is designed to be operated as a master (hereinafter referred to as master). Furthermore, the slave 21 has a second line MOSI (Master Output Slave Input) for receiving data from the master 22. The slave 21 can send data to the master 22 via a third line MISO (Master Input Slave Output). The slave 21 can be activated by the master 22 via a fourth line CS.

The slave 21 is activated by the master 22, for example, when data is transmitted should be. This is independent of whether data is to be transferred from master 22 to slave 21, from slave 21 to master 22 or in both directions. A signal that is present on the chip select (CS) line can assume two states, a high state (logic-1) or a low state (logic-0). Slave 21 is typically activated when the signal on the CS line goes low. This means that slave 21 is active at logic 0.

However, this is just an example; in principle there is also the possibility that the slave 21 is active at logic 1, that is, that it is active when the signal on the CS line assumes a high state.

The clock signal has a high state as long as the slave 21 is inactive (CS = High). When the signal on the CS line goes low and the slave 21 is activated, the signal on the CLK line sets a corresponding clock, that is, it changes at regular intervals between a low state and a high state. This is exemplified in 3 shown.

While slave 21 is active, data can be transferred from master 22 to slave 21 or from slave 21 to master 22 or both. The data is transmitted as messages with a length of X bytes. This length can be constant. For example, all messages can be 20 bytes long (X = 20). However, this is just an example. The length of the messages can basically be chosen arbitrarily. In principle, it is also possible for the length of the messages to vary. That is, every time the slave 21 is active, messages of a different length with X ≥ 1 can be transmitted.

If the length of the messages is limited (e.g. If the amount of data to be transmitted is smaller than the length of the messages, the unneeded part of the data transmitted in a message can simply be ignored. The size of the individual data transfers usually varies greatly from application to application. The denomination of the data transfers, i.e. the size of the individual messages and thus the number of messages required for a data transfer, can be selected depending on the requirements of the application.

As explained above, it is possible, for example, to set a fixed size for messages, which can then no longer be changed. However, it is also possible for the size of the messages to be redefined before each data transfer, for example.

The slave 21 can be connected to a microcontroller 30, for example. The microcontroller 30 can control the slave 21, for example. The message length is usually set by the master 22. This means that the master 22 can specify to the slave 21 what length the messages should have with each data transmission. According to one example, the microcontroller 30 sets the amount of data to be transmitted (message length). If a different length is specified by the master, for example longer messages, the slave 21, in particular the slave hardware, can automatically fill up the messages specified by the microcontroller 30, so that the messages are ultimately transmitted with the length specified by the master 22.

The slave 21 can, for example, have at least one input buffer 41 (N ≥ 1) and at least one output buffer 42 (M ≥ 1). In 4 Two input buffers 41 (N = 2) and two output buffers 42 (M = 2) are shown as examples. However, the communication module 21 can also have more or fewer input buffers 41 and output buffers 42. The number of input buffers 41 does not have to correspond to the number of output buffers 42, that is, it does not necessarily have to be N = M. Received messages are first stored in one of the input buffers 41 before they are read out and processed from there. Messages to be sent can be stored by the slave 21 in one of the output buffers 42. From there the messages can be picked up by Master 22. This is in 4 shown as an example by the arrows.

As in 5 Shown schematically, the input buffers 41 and the output buffers 42 can represent an interface between the slave 21 and the microcontroller 30. The microcontroller 30 can be designed to read out the input buffers 41. The microcontroller 30 can further be designed to describe the output buffers 42. The microcontroller 30 can also check and monitor the fill levels of the input buffers 41 and the output buffers 42. However, it is also possible for the slave 21 to monitor and check the fill levels and to send the microcontroller 30 information about the fill levels. In any case, the microcontroller 30 has, for example, information 43 about whether the buffers 41, 42 are filled. The microcontroller 30 can also have information 44 about whether the buffers 41, 42 are at least partially empty and can still store messages. This is independent of whether the slave 21 receives this information 43, 44 to the microcontroller 30 or whether the microcontroller 30 determines the information itself.

The slave 21 can, for example, also be designed to send information 45 to the microcontroller 30 when communication between the slave 21 and the master 22 is started (“SPI Transmission started” event). Likewise, the slave 21 can send the microcontroller 30 information 46 that the communication between the slave 21 and the master 22 has ended (“SPI Transmission completed” event). Communication can involve sending data from the master 22 to the slave 21, from the slave 21 to the master 22, or both.

If a data transfer is carried out by the master 22, the data that is transmitted on the MOSI line is written into an input buffer 41 and can be picked up from there by the microcontroller 30. The other way around, the microcontroller 30 can write messages into the output buffers 42. This can take place before a data transmission has been initiated by the master 22. As soon as the next data transfer has been initiated by the master 22, the data from the at least one output buffer 42 can then be transferred to the master 22 via the MISO line.

It can happen that at the beginning of data communication there are no messages in the output buffer 42, i.e. the output buffers 42 are empty. In this case, for example, a predetermined dummy message could be transmitted to the master 22. Such a dummy message can, for example, have predetermined content, so that the master 22 clearly recognizes the message as a dummy message and can, for example, ignore it.

The slave 21 can also have a fifth line BUSY, which is designed to output a signal which contains information about whether the slave 21 is ready to receive data. Furthermore, the slave 21 can also have a sixth line IRQ, which is designed to output a signal which contains information about whether the slave 21 currently wants to send data. This means that flow control of the data to be transmitted takes place via these two additional lines. The slave 21 can have either only the fifth line BUSY or only the sixth line IRQ or both the fifth line BUSY and the sixth line IRQ.

The fifth line BUSY and the sixth line IRQ can both assume two states. A first state is an active state “active” and a second state is an inactive state “not active”. If the fifth line BUSY is in the “active” state, this means that the slave 21 cannot currently receive any new messages. This means that all input buffers 41 are full. If the fifth line BUSY is “not active”, this means that new messages can be received. This means that there is space in the input buffers 41.

If the sixth line IRQ is “active”, this means that there are messages that should be sent to the master 22. This means that the output buffers 42 are at least partially filled. However, if the sixth line IRQ is “not active”, this means that there are no messages to send to the master 22 and the output buffers 42 are empty.

Intervention by the microcontroller 30 is not required to manage the fifth and sixth lines BUSY, IRQ. The BUSY and IRQ lines can be managed autonomously by the hardware, so to speak. This allows the microcontroller 30 to process the data with very low real-time requirements, since the hardware itself buffers the data autonomously until the microcontroller 30 is ready to process it. This means that the processing of the two events “SPI Transmission started” and “SPI Transmission completed” can take place in the microcontroller 30 without hard real-time requirements and is completely decoupled from the scheduling requirements (timing requirements) of the SPI interface itself.

The state of the fifth line BUSY can only change from “not active” to “active” during an ongoing data transfer, since the master 22 only sends data to the slave 21 during an ongoing data transfer and the input buffers 41 therefore only sends data during an ongoing data transfer can be filled. As described above, the slave 21 does not fill the input buffer 41 itself at any time. These are always filled by the master 22. The master 22 can therefore check the state of the fifth line BUSY before the start of a data transmission to ensure that a transmission can take place. If the status of the BUSY line is recognized as “active”, the slave 21 cannot receive any further data. The slave 21 is therefore not ready for a new data transmission.

If the state of the BUSY line is recognized as “not active”, data transmission can take place regardless of the current state of the microcontroller 30, since the data transmitted by the master 22 can be stored in the input buffers 41 until the microcontroller 30 is ready to process them. This procedure, that is Displaying the current status via the BUSY and IRQ lines can avoid so-called “race conditions”. A “race condition”, also known as a race situation, is a constellation in which the result of an operation depends on the temporal behavior of certain individual operations. This means that two signals are in a race to be the first to influence an output. The above-described integration of the flow control directly into the hardware of the slave 21 ensures that the flow control remains consistent at all times so that “race conditions” can be avoided.

In principle, it is possible that the master 22 overrides flow control and sends messages to the slave 21 even though the BUSY line is set to “active”. The slave 21 recognizes this because it knows its own state and can inform the microcontroller 30 accordingly, for example by sending an error message to the microcontroller 30. If possible, the master 22 should therefore avoid sending messages despite the BUSY line being set (“active”).

The slave 21 can also be designed to carry out an error check. Error checking can detect disruptions in communication, both in terms of data transmission and flow control. The error check can, for example, include checking the expected message length X for each data transmission and comparing the expected length with the actual length used by the master 22. If the slave 21 detects a deviation of the actual message length from the expected message length, the slave 21 can send an error message to the microcontroller 30.

The error check can, for example, also include checking a checksum PS (checksum) of the data received from the master 22. A checksum is a value that can be used to verify the integrity of data. A checksum is basically a value that is calculated from the data to be transferred. By checking the checksum PS, at least one bit error in the data can be detected. Depending on how complex the calculation rule for the checksum is, several errors can be detected or even corrected.

A message to be transmitted from the master 22 to the slave 21 can, for example, have a total length 6A shown. For example, if However, this is just an example. The same applies, as exemplified in 6B shown, for messages that are transmitted on the MISO line from slave 21 to master 22.

If the checksum PS of a message is recognized as incorrect, the message can be discarded, for example. This means that the message cannot be accepted into the input buffer 41, for example. In addition, an error message can also be output to the microcontroller 30, for example. Likewise, the slave 21 can also transmit a checksum PS together with a message to the master 22. The master 22 can also check the checksum PS and discard the message if the checksum is not correct. However, using checksums is optional. However, by adding checksums, the communication between slave 21 and master 22 can generally be well protected against interference.

The slave 21 can also have one or more shift registers 50, 51 (shift registers). This is in 7 shown schematically. A first shift register 50 (Rx shift register) can, for example, be preceded by the at least one input buffer 41. Messages transmitted from the master 22 to the slave 21 can first be stored in the first shift register 50. The first shift register 50 has a first number of memory locations (flip-flops). The shift register 50 is clock-driven. This means that the memory contents are shifted one memory location further with each cycle of the clock signal from master 22 (clock of the SPI transmission). The number of memory locations in shift register 50 is constant.

A second shift register 51 (Tx shift register) can be downstream of the at least one output buffer 42. Messages that are to be sent to the master 22 can then be transferred from the output buffer 42 to the second shift register 51. In the second shift register 51, the memory content is shifted one memory location further in a clock-driven manner, as described with respect to the first shift register 50, with each cycle of the clock signal from the master 22 (clock of the SPI transmission).

In 7 the first shift register 50 and the second shift register 51 are each shown as a shift register. However, each of the shift registers 50, 51 can also have more than one register. Alternatively, the slave 21 can only have a shift register that is designed for this purpose is to first store messages that are received from the master 22 before they are transferred from there to the input buffer 41, as well as to accept messages that are to be sent to the master 22 from the output buffer 42 before they are transferred from there to the master 22 become. In this case, the shift register functions both as an input shift register and as an output shift register. It is also conceivable that the slave has several shift registers, each of which functions as both an input shift register and an output shift register. Any combination of pure input shift registers, pure output shift registers and combined input and output shift registers is also possible.

However, in order to transfer the data from the first shift register 50 to the input buffer 41 or from the output buffer 42 to the second shift register 51, an external clock is required. These processes require an external clock, i.e. a clock that is provided by external components. However, such an external clock may not always be available. For example, the microcontroller 30 can provide the external clock. The clock is then, for example, not available when the microcontroller 30 is switched off. The same problem can also arise if the external clock is not provided by the microcontroller 30 but by another external unit (not shown).

For example, it can be provided that the system switches to a low-power mode or idle state in which no external clock is available. In low-power mode, the slave 21 can first store the data in the shift register 50. As described above, this can be done without an external clock. The first shift register 50 thus forms a further buffer in front of the input buffer 41. As soon as the slave 21 receives data from the master 22, it can send a wake-up signal to the microcontroller 30 and possibly also to other components. As soon as the microcontroller 30 has woken up, it can provide an external clock and transfer the data from the first shift register 50 into the input buffer 41 and further process it accordingly. The slave 21 can signal to the master 22 at any time via the fifth line BUSY whether it is still ready to receive further data (SPI transmissions) or not.

The microcontroller 30 and/or other components do not necessarily have to switch to an idle state if there is no communication with the master 22. In order to save electricity, however, it usually makes sense to switch at least some components to a standby state, in which the power consumption is usually significantly lower than the power consumption in normal operation.

By placing the messages in an input buffer 41 before they are processed by the microcontroller 30, delays may arise between the time a message is received and the time it is processed. The microcontroller 30 can in principle read the messages from the input buffer 41 at any time. In order to be able to assign the data that is read out of the input buffer 41 by the microcontroller 30 to a previous data transmission, the messages can, for example, be provided with a timestamp. This is exemplified in 9 shown. This means that in addition to the user data (payload) and an (optional) checksum PS, timestamps associated with the data can also be stored in the slave 21. The timestamp contains information about the time at which the respective message was stored in the input buffer.

The possible resulting time delay is exemplified in 8th shown. In 8th A timer is shown schematically. The timer can be, for example, a continuous timer. At a first point in time, the data transfer from the master 22 to the slave 21 takes place. This first timer value, which relates to the transmission time, can be saved parallel to the message. The microcontroller 30 can also read the current timer value at the time at which it reads the data from the input buffer 41. He can compare this current time with the first timer value associated with the message and thus knows how much time has passed since the transmission (delta). This allows the microcontroller 30 to clearly determine the actual time of transmission of the data.

Similarly, when transmitting data from the slave 21 to the master 22, there may be a time delay between the data being stored in the output buffer 42 and the actual transmission. For example, the data can be stored in the output register 42 by the microcontroller 30 at a first point in time. The microcontroller 30 can read out the timer value at this point in time and store a first time stamp together with the data in the output buffer 42, the first time stamp containing information about the first point in time. Again referring to 9 , for example, the last data bytes W of the user data can be interpreted as the first timestamp information. The actual transfer takes place to a second one Time. This is in 10 shown as an example. However, according to an example, the first timestamp is not transmitted to the master 22. Instead, different data is linked to the user data and transmitted, which, however, is related to the timer value at the time the data is stored (first parameter). For example, the first time stamp stored by the microcontroller 30 at the time of transmission from the slave 21 can be replaced by such data. The data can, for example, contain information about how much time has passed between the first time and the second time (delta between the first timer value and the current timer value at the time of transmission).

Not only a communication module 21, which functions as a slave, can have the six lines described above. A communication module 22, which acts as a master, can also have the corresponding six lines so that it can also receive the information that the communication module 21 provides on the fifth and sixth lines.

A device for transmitting data has a first communication module 21, which is designed to be operated as a slave. The device for transmitting data also has a second communication module 22, which is designed to be operated as a master. The first communication module 21 and the second communication module 22 are connected to one another via a data bus. The data bus has six lines. These are a first line CLK for transmitting a clock signal from the second communication module 22 to the first communication module 21, a second line MOSI for transmitting data from the second communication module 22 to the first communication module 21, a third line MISO for transmitting data from the first communication module 21 to the second communication module 22, a fourth line CS via which the first communication module 21 can be activated by the second communication module 22, a fifth line BUSY for transmitting a first signal from the first communication module 21 to the second communication module 22, which contains information about it, whether the first communication module 21 is ready to receive data, and a sixth line IRQ for transmitting a second signal from the first communication module 21 to the second communication module 22, which contains information about whether the first communication module 21 wants to send data. The device can have a first communication module 21 and a second communication module 22, or a plurality of first communication modules 21 and a second communication module 22, each of the first communication modules 21 being connected to the second communication module 22 via the six lines described. The device can be arranged in a vehicle, for example.

Reference symbol list

11

Slave

12

master

21

first communication device/slave

22

second communication device/master

30

Microcontroller

41

Input buffer

42

Output buffer

43

Information whether buffer is full

44

Information whether buffer is empty

45

Information about the start of a transfer

46

Information about the end of a transmission

50, 51

Shift register

Claims (12)

Communication module (21) which is designed to be operated as a slave and to be connected to a second communication module (22) which is designed to be operated as a master, the first communication module (21) having: a first line (CLK) for receiving a clock signal from the second communication module (22); a second line (MOSI) for receiving data; a third line (MISO) for sending data; a fourth line (CS) via which the first communication module (21) can be activated by the second communication module (22); and at least one of a fifth line (BUSY) for outputting a first signal which contains information about whether the first communication module (21) is ready to receive data; and a sixth line (IRQ) for outputting a second signal which contains information about whether the first communication module (21) wants to send data, the first communication module (21) further having an output buffer (42) which is designed for this purpose is to store messages that are to be transmitted to the second communication module (22); a message that is to be transmitted to the second communication module (22) is stored in the output buffer (42) at a first time; a first time stamp is stored together with the message in the output buffer (42), the first time stamp containing information about the first time; the message is transmitted to the second communication module (22) at a second time; the first communication module (21) is designed to replace the first time stamp with first data when the message is transmitted to the second communication module (22), the first data having information about a time period (delta) between the first time and passed the second point in time. Communication module (21). Claim 1 , which is designed to be connected to the second communication module (22) via an SPI bus. Communication module (21). Claim 1 or 2 , which further has at least one input buffer (41) which is designed to store messages which are received from the second communication module (22). Communication module (21) according to one of the Claims 1 until 3 , which is designed to be connected to a microcontroller (30), the microcontroller (30) being designed to read and process messages from the input buffer (41) and messages into the output buffer (42) for transmission to the second communication module (22). Communication module (21) according to one of the preceding claims, wherein the first signal of the fifth line (BUSY) assumes a first state (active) when the first communication module (21) cannot receive any new messages; and assumes a second state (not active) when the first communication module (21) can receive new messages. Communication module (21) according to one of the preceding claims, wherein the second signal of the sixth line (IRQ) assumes a first state (active) when the first communication module (21) wants to send new messages; and assumes a second state (not active) when the first communication module (21) does not have to send any new messages. Communication module (21) according to one of the preceding claims, which is designed for this purpose to send messages to the second communication module (22), which, in addition to user data, also have a checksum (PS); and Receive messages from the second communication module (22) which, in addition to user data, also have a checksum (PS), The integrity of a message can be checked using the checksum. Communication module (21) according to one of the preceding claims, which further comprises at least one of: at least one first shift register (50), which is arranged in front of the input buffer (41) in such a way that messages received from the second communication module (22) are first stored in the first shift register (50) and from there are transferred to the input buffer (41). ; and at least one second shift register (51), which is arranged behind the output buffer (42) in such a way that messages that are to be sent to the second communication module (22) are transferred from the output buffer (42) to the second shift register (51) and from there be transmitted to the second communication device (22). Communication module (21) according to one of the preceding claims, which has at least one shift register, at least one of the shift registers being designed to Messages that are received from the second communication module (22) must first be saved before they are transferred from there to the input buffer (41), and Messages that are to be sent to the second communication module (22) are taken over from the output buffer (42) before they are transmitted from there to the second communication device (22). Communication module (21). Claim 8 or 9 , whereby the shift registers are driven by the clock signal or by a clock generated from the clock signal. Device for data transmission with at least one first communication module (21) and a second communication module (22), the at least one first communication module being designed to be operated as a slave and the second communication module (22) being designed to be operated as a master, wherein the at least one first communication module (21) and the second communication module (22) communicate with one another via a data bus which are connected, and wherein the data bus comprises: a first line (CLK) for transmitting a clock signal from the second communication module (22) to the first communication module (21); a second line (MOSI) for transmitting data from the second communication module (22) to the at least one first communication module (21); a third line (MISO) for transmitting data from the at least one first communication module (21) to the second communication module (22); a fourth line (CS) via which the at least one first communication module (21) can be activated by the second communication module (22); and at least one of a fifth line (BUSY) for transmitting a first signal to the second communication module (22) which contains information about whether the at least one first communication module (21) is ready to receive data; and a sixth line (IRQ) for transmitting a second signal to the second communication module (22), which contains information about whether the at least one first communication module (21) wants to send data, and wherein the first communication module (21) further has an output buffer (42 ) which is designed to store messages that are to be transmitted to the second communication module (22); a message that is to be transmitted to the second communication module (22) is stored in the output buffer (42) at a first time; a first time stamp is stored together with the message in the output buffer (42), the first time stamp containing information about the first time; the message is transmitted to the second communication module (22) at a second time; the first communication module (21) is designed to replace the first time stamp with first data when the message is transmitted to the second communication module (22), the first data having information about a time period (delta) between the first time and passed the second point in time. Device according to Claim 11 , wherein the device is arranged in a vehicle.

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