DE102017216991A1 - Communication module and device for data transmission - Google Patents

Abstract

Communication module (21) which is designed to be operated as a slave and to be connected to a second communication module (22), which is designed to be operated as a master, wherein the first communication module (21) a first line (CLK) for receiving a clock signal from the second communication module (22), a second line (MOSI) for receiving data, a third line (MISO) for transmitting data and a fourth line (CS) via which the first communication module (21) through the second communication block (22) can be activated. The communication module (21) further comprises at least one of a fifth line (BUSY) for outputting a first signal containing information on whether the first communication device (21) is ready to receive data and a sixth line (IRQ) for outputting a second signal containing information about whether the first communication module (21) wants to send data.

Description

The invention relates to a communication module and a device for data transmission, in particular a communication module for a serial peripheral interface interface (SPI interface).

The Serial Peripheral Interface (SPI) is a standard synchronous serial port bus system that allows master-slave digital circuits to be interconnected. An SPI enables serial (one bit at a time) exchange of data between two devices, one of which is called a master and the other a slave. An SPI can operate in full-duplex mode, meaning that data can be transmitted simultaneously in both directions. For example, controllers can be interconnected with peripherals or with microcontrollers using SPI.

SPI communication blocks support various functions, such as the configuration of communication parameters, the writing and reading of incoming and outgoing data, etc. An SPI slave should generally have a high time accuracy with the highest possible availability and the lowest possible software overhead. In this case, however, it is particularly problematic for software in particular that the times at which a communication should take place are determined by the master. The slave must thus provide the data to be sent at the desired time and pick up data to be received at the desired time at the master. The timely provision of data in the slave is relatively expensive in conventional software-driven SPI communication modules. Most devices are a compromise between availability, complexity, interrupt load, and resource consumption (e.g., CPU runtime, low-power behavior, etc.).

The object of the invention is to provide an improved communication module, in particular a slave, and an improved device for data communication, which have a high performance as well as a low complexity and short run times of a required software driver, so that the master as a conventional (SPI) Master can be implemented.

This object is achieved by a communication module according to claim 1, a communication module according to claim 13 or a device for data transmission according to claim 14.

The communication module according to the invention is designed to be operated as a slave and to be connected to a second communication module. The second communication module is designed to be operated as a master. The first communication module has a first line for receiving a clock signal from the second communication block, a second line for receiving data, a third line for transmitting data and a fourth line via which the first communication block can be activated by the second communication block. The first communication device further comprises either a fifth line for outputting a first signal containing information as to whether the first communication device is ready to receive data or a sixth line for outputting a second signal containing information as to whether the first communication device is data want to send, or both.

Via the fifth and sixth line, a flow control of the data can take place. The second communication module is informed at any time whether the first communication module can receive data and / or send data. If the first communication module can not receive any data at a time, the second communication module may, for example, refrain from sending data and instead wait until the first communication module is again ready to receive data. As a result, unwanted error situations can be avoided.

The first communication module can be designed to be connected to the second communication module via an SPI bus. The first, second, third and fourth lines are typically already present in an SPI bus. The fifth and sixth lines are a supplement to these lines.

The first communication module may further comprise at least one input buffer, which is configured to store messages which are received by the second communication module. Received messages are thus not further processed directly, but initially cached. The data can be read out of the input buffer at any later time and processed.

The first communication module may further comprise at least one output buffer, which is configured to store messages that are to be transmitted to the second communication module. Messages can be stored in the output buffer at any time. Will then be a communication through the triggered second communication block, this can then read the data from the output buffer.

The first communication module may be configured to be connected to a microcontroller, wherein the microcontroller may be configured to read messages from the input buffer and to process and store messages in the output buffer for transmission to the second communication module. The first communication module thus serves only as an interface. The processing and provision of the data takes place in the microcontroller.

The first signal of the fifth line may assume a first state if the first communication block can not receive new messages and may assume a second state if the first communication block can receive new messages. The state of the signal thus simply reflects the state of the first communication module.

The second signal of the sixth line may assume a first state if the first communication block wants to send new messages and may assume a second state if the first communication block does not have to send new messages. The state of the signal thus simply reflects the state of the first communication module.

The first communication module may be configured to send messages to the second communication module, which in addition to user data also have a checksum, and to receive messages from the second communication module, which in addition to payload data also have a checksum. As a result, the integrity of a message can be checked in a simple manner on the basis of the checksum.

The first communication module may further comprise at least one of at least a first shift register, which is arranged in front of the input buffer such that messages received by the second communication module are first stored in the first shift register and transferred from there to the input buffer, and at least one second shift register , which is arranged behind the output buffer so that messages to be sent to the second communication module are taken from the output buffer in the second shift register and are transmitted from there to the second communication device. As a result, a further buffer is provided before or after the respective input or output buffer.

The communication module may alternatively or additionally also have at least one shift register, wherein at least one of the shift registers is configured to store both messages received by the second communication module before they are transferred from there into the input buffer, as well as messages to the second communication module should be sent from the output buffer before they are transferred from there to the second communication device.

The shift registers may be driven by the clock signal or by a clock generated from the clock signal.

A message that is to be transmitted to the second communication module can be stored in the output buffer at a first time. In this case, a first time stamp can be stored together with the message in the output buffer, the first time stamp containing information for the first time. The message can then be transmitted to the second communication module at a second time. The first communication module can be designed to replace the first time stamp with first data if the message is transmitted to the second communication module, the first data having information on a time duration (delta) which has elapsed between the first time and the second time is.

A second communication module is designed to be operated as a master and to be connected to at least one first communication module. The first communication module is designed to be operated as a slave. The second communication module has a first line for outputting a clock signal to the at least one first communication module, a second line for transmitting data, a third line for receiving data and a fourth line via which the second communication module can activate the at least one first communication module. The second communication device either has a fifth line for receiving a first signal from the at least one first communication device, the first signal containing information as to whether the at least one first communication device is ready to receive data, or a sixth line for receiving a second signal from the at least one first communication device, wherein the second signal contains information about whether the at least one first communication device wants to send data, or both.

A device for data transmission has at least a first communication module and a second communication module, wherein the at least one first communication module is designed to be operated as a slave and the second communication module is designed to be operated as a master. The at least one first communication module and the second communication module are connected to each other via a data bus. The data bus has a first line for transmitting a clock signal from the second communication module to the first communication module, a second line for transmitting data from the second communication module to the at least one first communication module, a third line for transmitting data from the at least one first communication module the second communication module and a fourth line over which the at least one first communication module can be activated by the second communication module. The device further comprises either a fifth line for transmitting a first signal to the second communication module containing information on whether the at least one first communication block is ready to receive data, or a sixth line for transmitting a second signal to the second communication block which information about whether the at least one first communication module wants to send data, or both.

The device may be arranged in a vehicle.

• 1 in einer schematischen Darstellung beispielhaft das Prinzip eines Serial Peripheral Interface,
• 2 beispielhaft in einem Blockdiagramm einen Kommunikationsbaustein,
• 3 beispielhaft in zeitlichen Diagrammen Signale in einer Datenkommunikation,
• 4 beispielhaft in zeitlichen Diagrammen Signale in einer Datenkommunikation unter Verwendung von Puffern,
• 5 beispielhaft in einem Blockdiagramm eine Schnittstelle zwischen einem Mikrocontroller und einem Kommunikationsbaustein,
• 6 , aufweisend die 6A und 6B, eingehende und ausgehende SPI-Daten,
• 7 beispielhaft in einem Blockdiagramm einen Kommunikationsbaustein mit Puffern und Schieberegistern,
• 8 beispielhaft in zeitlichen Diagrammen eine zeitliche Zuordnung eines Übertragungszeitpunkts und eines Verarbeitungszeitpunkts,
• 9 beispielhaft ausgehende SPI-Daten mit einem Zeitstempel, und
• 10 beispielhaft in zeitlichen Diagrammen eine zeitliche Zuordnung eines Beauftragungszeitpunktes und eines Übertragungszeitpunktes.

The invention will be explained in more detail with reference to the embodiments illustrated in the figures of the drawing. It shows:

• 1 in a schematic representation by way of example the principle of a serial peripheral interface,
• 2 by way of example in a block diagram a communication module,
• 3 exemplary in time diagrams signals in a data communication,
• 4 by way of example in chronological diagrams signals in a data communication using buffers,
• 5 exemplified in a block diagram an interface between a microcontroller and a communication module,
• 6 Having the 6A and 6B , incoming and outgoing SPI data,
• 7 by way of example in a block diagram a communication module with buffers and shift registers,
• 8th by way of example in time diagrams a temporal assignment of a transmission time and a processing time,
• 9 exemplary outgoing SPI data with a timestamp, and
• 10 For example, in temporal diagrams a temporal assignment of a commissioning time and a transmission time.

1 shows a schematic representation of a Serial Peripheral Interface. A Serial Peripheral Interface (SPI) is a standard synchronous serial port bus system that can be used to connect master-slave digital circuits. An SPI allows serial (one bit at a time) exchange of data between two blocks 11 . 12 , one of them being a master 12 and the other as a slave 11 referred to as. An SPI can operate in full-duplex mode, meaning that data can be transmitted simultaneously in both directions (master to slave and slave to master). For example, controllers can be interconnected with peripherals or with microcontrollers using SPI.

An SPI communication block, regardless of whether it acts as a master or as a slave, has three lines to which each participant (master and one or more slaves) are connected. These are a clock line CLK, also referred to as clock or serial clock, the clock being output from the master, and two lines for transferring data. A so-called MOSI line (Master Output, Slave Input), for transferring data from the master 12 to the slave 11 , and a so-called MISO line (Master Input, Slave Output), for transmitting data from the slave 11 to the master 12 , The data lines may, for example, also be referred to as Serial Data Out (SDO) and Serial Data In (SDI), the designation generally taking place from the point of view of the respective bus user, so that in this case the lines must be connected crosswise in contrast to the one shown Case where MISO is connected to MISO and MOSI is connected to MOSI.

An SPI communication module furthermore has one or more logically-active chip select lines (CS line) (often also referred to as slave select SS or slave transmit enable STE). As a rule, each slave has only one CS line. A master may have one or more CS lines. For example, the master may have its own CS line for each slave to which it is connected. These lines CS are from the master 12 controlled.

In theory, any number of participants can be connected to an SPI bus. However, it is always exactly one master 12 required, which generates the clock signal CLK. With the line Chip-Select CS puts the master 12 firmly, with which slave 11 he wants to communicate. Is the corresponding CS line through the master 12 pulled to ground (logical-0), is the associated slave 11 active and "listens" on the MOSI line whether data from the master 12 be transmitted. At the same time he puts his data to the master 12 to be transmitted in time with the clock signal to the MISO line. In a following data communication, a word is taken from the master 12 to the slave 11 and another word from the slave 11 to the master 12 transfer.

There is no established protocol for data transmission for SPI, but generally four different modes have prevailed. These are defined by the parameters Clock Polarity (CPOL) and Clock Phase (CPHA). At CPOL = 0 the clock idle is low, at CPOL = 1 the clock idle is high. CPHA indicates at which time edge of the clock signal the data should be taken over. At CPHA = 0, they are taken on the first edge after CS has been pulled low, and at CPHA = 1 on the second edge. Thus, the data at CPOL = 0 and CPHA = 0 are taken over with the first edge, which can only be a rising edge. With CPHA = 1, it would be the second edge, ie a falling edge. With CPOL = 1, this is exactly the other way around, ie with CPHA = 0 a falling edge and with CPHA = 1 a rising edge.

The slave 11 As a rule, if CPHA = 0, it will already put its data on MISO if CS goes low, so that the master 12 you can take on the first edge change. With CPHA = 1, the data is from the slave 11 placed on MISO only at the first edge change, so that at the second edge change from the master 12 can be taken over. The master 12 however, its data always arrives at the same time, usually shortly after the falling edge of CLK.

With each clock period, one bit is transmitted. In the usual byte transfer so eight clock periods are required for a complete transfer. You can also transfer several words in succession. It is not determined whether after each word the CS line must be briefly pulled high or not. A transfer is complete when the CS line is finally reset to high.

2 shows by way of example in a block diagram a communication block 21 , The communication module 21 (hereinafter referred to as slave) is designed to be operated as a slave and has a plurality of lines (or pins). These are a first line CLK for receiving a clock signal. The clock signal is received by the slave 21 from a second communication module 22 which is designed to be operated as a master (hereinafter referred to as master). Furthermore, the slave points 21 a second line MOSI (Master Output Slave Input) to receive data from the master 22 , The slave can be connected via a third line MISO (Master Input Slave Output) 21 Data to the master 22 send. Via a fourth line CS, the slave 21 through the master 22 to be activated.

The slave 21 is by the master 22 for example, activated when data is to be transferred. This is regardless of whether data is from the master 22 to the slave 21 , from the slave 21 to the master 22 or to be transmitted in both directions. A signal applied to the chip select (CS) line can assume two states, a high state (logic 1) or a low state (logic 0). The slave 21 is usually enabled when the signal on the CS line goes low. That is, the slave 21 is logical-0 active.

However, this is only an example, in principle there is also the possibility that the slave 21 logical-1 is active, that is to say that it is active when the signal on the CS line assumes a high state.

The clock signal has a high state as long as the slave 21 is inactive (CS = High). When the signal on the CS line goes low and the slave goes off 21 is activated, the signal on the CLK line before a corresponding clock, that is, it changes at regular intervals between a low state and a high state. This is exemplary in 3 shown.

While the slave 21 Active is data from the master 22 to the slave 21 or from the slave 21 to the master 22 be transferred or both. The data is transmitted as messages with a length of X bytes. This length can be consistent. For example, all messages may have a length of 20 bytes (X = 20). This is just an example. The length of the messages can basically be chosen arbitrarily. In principle, it is also possible that the length of the messages varies. That is, every time the slave 21 is active, messages of a different length can be transmitted with X ≥ 1.

If the length of the messages is limited (eg X = 20), but data should be transmitted in an amount which is the length of a message exceed, the total amount of data can be split across multiple messages. If the amount of data to be transmitted is smaller than the length of the messages, the unneeded portion of the data transmitted in a message can simply be ignored. The size of the individual data transfers varies from application to application. The denomination of the data transfers, ie the size of the individual messages and thus the number of messages required for a data transfer can be selected according to the requirements of the application.

It is, as already explained above, for example, set a fixed size for messages, which then can not be changed. However, it is also possible that the size of the messages, for example, before each data transfer is redefined.

The slave 21 for example, with a microcontroller 30 be connected. The microcontroller 30 for example, the slave 21 Taxes. The message messages are usually set by the master 22 , That is, the master 22 can the slave 21 redefine the length of the messages for each data transfer. According to one example, the microcontroller represents 30 the amount of data to be transmitted (message length). If a different length is specified by the master, eg longer messages, the slave can 21 , especially the slave hardware, by the microcontroller 30 automatically populate given messages so that the messages ultimately match those from the master 22 be transmitted predetermined length.

The slave 21 For example, at least one input buffer 41 (N ≥ 1) and at least one output buffer 42 (M ≥ 1). In 4 are exemplified by two input buffers 41 (N = 2) and two output buffers 42 (M = 2). The communication module 21 however, it can also have more or fewer input buffers 41 and output buffer 42 exhibit. The number of input buffers 41 it does not have to be the number of output buffers 42 This means that it is not absolutely necessary to apply N = M. Received messages are initially stored in one of the input buffers 41 filed before they are read from there and processed. Messages to be sent can be sent by the slave 21 in one of the output buffers 42 be filed. From there you can read the messages from the master 22 be collected. This is in 4 represented by the arrows by way of example.

As in 5 shown schematically, the input buffer 41 and the output buffers 42 an interface between the slave 21 and the microcontroller 30 represent. The microcontroller 30 may be adapted to the input buffers 41 read. The microcontroller 30 may be further configured to the output buffer 42 to describe. The microcontroller 30 can also change the levels of the input buffer 41 and the output buffer 42 check and monitor. However, it is equally possible that the slave 21 monitors and checks the levels and the microcontroller 30 Send information about the fill levels. In any case, lies the microcontroller 30 eg an information 43 about whether the buffers 41 . 42 are filled. The microcontroller 30 can continue to provide information 44 about whether the buffers 41 . 42 at least partially empty and still can save messages. This is regardless of whether the slave 21 this information 43 . 44 to the microcontroller 30 sends or whether the microcontroller 30 the information itself determined.

The slave 21 For example, it may also be designed to provide information 45 to the microcontroller 30 to send if communication between the slave 21 and the master 22 is started (Event "SPI Transmission started"). Likewise, the slave can 21 the microcontroller 30 an information 46 Send over that communication between the slave 21 and the master 22 finished (Event "SPI Transmission completed"). A communication can be the sending of data from the master 22 to the slave 21 , from the slave 21 to the master 22 or both.

So it is through the master 22 When a data transfer is performed, the data transmitted on the MOSI line is transferred to an input buffer 41 written and can from there through the microcontroller 30 be collected. The other way around is the microcontroller 30 Messages in the output buffer 42 write. This can already be done before a data transfer by the master 22 was initiated. As soon as the next data transfer through the master 22 was initiated, the data from the at least one output buffer 42 then via the MISO line to the master 22 be transmitted.

It may happen that at the beginning of a data communication no messages in the output buffer 42 are present, the output buffers 42 so are empty. In this case, for example, a predetermined dummy message to the master 22 be transmitted. Such a dummy message may have predetermined contents, for example, so that the master 22 uniquely identifies the message as a dummy message and can ignore it, for example.

The slave 21 may further comprise a fifth line BUSY, which is adapted to output a signal which information about it contains, whether the slave 21 ready to receive data. Furthermore, the slave can 21 also have a sixth line IRQ, which is designed to output a signal which contains information about whether the slave 21 currently want to send data. That is, via these two additional lines, a flow control of the data to be transmitted takes place. The slave 21 may have either only the fifth line BUSY or only the sixth line IRQ or both the fifth line BUSY and the sixth line IRQ.

Both the fifth line BUSY and the sixth line IRQ can each assume two states. A first state is an active state "active" and a second state is an inactive state "not active". If the fifth line BUSY is in the "active" state, this means that the slave 21 currently can not receive any new messages. That is, all input buffers 41 are full. If the fifth line BUSY is "not active", this means that new messages can be received. That means there is room in the entrance buffers 41 available.

If the sixth line IRQ is "active", this means that there are messages which are sent to the master 22 to be sent. That is, the output buffers 42 are at least partially filled. On the other hand, if the sixth line IRQ is "not active", this means that there are no messages to send to the master 22 present and the output buffer 42 are empty.

To manage the fifth and sixth line BUSY, IRQ is an intervention of the microcontroller 30 not mandatory. The BUSY, IRQ lines can be autonomously managed by the hardware as it were. This allows the microcontroller 30 a processing of the data with very low real-time requirements, since the hardware itself autonomously buffers the data to the microcontroller 30 ready to edit this. This also allows the processing of the two events "SPI Transmission started" and "SPI Transmission completed" in the microcontroller 30 without hard real-time requirements and is completely decoupled from the timing requirements of the SPI interface itself.

In this case, the state of the fifth line BUSY only during a data transfer from "not active" to "active" change, as the master 22 only during a data transfer data to the slave 21 sends and the input buffers 41 thus can only be filled during an ongoing data transfer. The slave 21 fills the input buffers as described above 41 at no time itself. These are always by the master 22 filled. The master 22 can thus check the state of the fifth line BUSY before beginning a data transmission in order to ensure that a transmission can take place. If the status of the BUSY line is detected as "active", the slave can 21 no further data received. The slave 21 is therefore not ready for a new data transfer.

If the state of the BUSY line is detected as "not active", it may be independent of the current state of the microcontroller 30 a data transfer takes place, as that of the master 22 transmitted data in the input buffers 41 can be stored until the microcontroller 30 ready to process this. This procedure, ie displaying the current status via the BUSY and IRQ lines, can avoid so-called "race conditions". A "race condition", also referred to as a race situation, is a constellation in which the result of an operation depends on the temporal behavior of certain individual operations. That is, two signals are in a race, so to speak, to influence an output first. The above-described integration of the flow control directly into the hardware of the slave 21 ensures that the flow control remains consistent at all times, so that race conditions can be avoided.

Basically, it is possible that the master 22 the flow control passes and messages to the slave 21 sends, even though the BUSY line is set to "active". The slave 21 recognizes this because he knows his own state, and can use the microcontroller 30 inform accordingly, for example by sending an error message to the microcontroller 30 sends. By the master 22 It should therefore be avoided, if possible, to send messages in spite of the BUSY line being set ("active").

The slave 21 may also be configured to perform an error check. An error check can detect communication disruptions both in terms of data transmission and in terms of flow control. For example, the error check may include checking the expected message length X for each data transfer and comparing the expected length with the actual one from the master 22 used length. Represents the slave 21 a deviation of the actual message length of the expected message length fixed, the slave 21 an error message to the microcontroller 30 send.

The error check can for example also check a checksum PS (Checksum) of the master 22 have received data. A checksum is a value that can be used to verify the integrity of data. A checksum is basically a value which is calculated from the data to be transmitted. By checking the checksum PS at least one bit error in the Data to be recognized. Depending on how complex the calculation rule for the checksum is, several errors can be detected or even corrected.

One from the master 22 to the slave 21 The message to be transmitted may have, for example, an overall length X, the total length being composed of payload data of a length Y and a check sum PS of length Z, that is to say X = Y + Z 6A shown. For example, if X = 20 (total message length) 20 Byte), the length Y of the user data can be, for example, 18 bytes (Y = 18) and the length Z of the checksum 2 Byte (Z = 2). This is just an example. The same applies as exemplified in 6B shown for messages on the MISO line from the slave 21 to the master 22 be transmitted.

If the checksum PS of a message is recognized as incorrect, the message can be discarded, for example. That is, the message may not be in the input buffer, for example 41 be taken over. In addition, for example, an error message to the microcontroller 30 be issued. Likewise, the slave can 21 a checksum PS along with a message to the master 22 transfer. The master 22 can also check the checksum PS and discard the message if the check sum is not correct. However, using checksums is optional. By adding checksums, the communication between slave 21 and master 22 However, in principle, be well protected against interference.

The slave 21 can still have one or more shift registers 50 . 51 (Shift Register). This is in 7 shown schematically. A first shift register 50 (Rx Shift Register), for example, the at least one input buffer 41 be upstream. From the master 22 to the slave 21 transmitted messages can first in the first shift register 50 be filed. The first shift register 50 has a first number of memory locations (flip-flops). The shift register 50 is clock-driven. That is, the memory contents at each clock of the clock signal from the master 22 (Clock of SPI transmission) shifted by one space. The number in the shift register 50 available memory spaces is constant.

A second shift register 51 (Tx Shift Register) can the at least one output buffer 42 be downstream. Messages to the master 22 can then be sent out of the output buffer 42 to the second shift register 51 be handed over. In the second shift register 51 the memory contents become as in relation to the first shift register 50 described clock-driven at each clock of the clock signal from the master 22 (Clock of SPI transmission) shifted by one space.

In 7 are the first shift register 50 and the second shift register 51 each represented as a shift register. Each of the shift registers 50 . 51 however, it may also have more than one register. The slave 21 may alternatively have only one shift register, which is designed to both messages from the master 22 to be received first before storing them from there into the input buffer 41 as well as messages to the master 22 to be sent from the output buffer 42 to take over before this from there to the master 22 be transmitted. The shift register thus acts simultaneously as an input shift register and as an output shift register in this case. It is also conceivable that the slave has a plurality of shift registers, each of which acts both as an input shift register and as an output shift register. Any combination of pure input shift registers, pure output shift registers, and combined input and output shift registers is also possible.

To the data from the first shift register 50 to the input buffer 41 or from the output buffer 42 to the second shift register 51 however, an external clock is required to transmit. These operations require an external clock, that is, a clock provided by external components. However, such an external clock may not always be available. For example, the microcontroller 30 provide the external clock. The clock is then not available, for example, if the microcontroller 30 is switched off. The same problem may arise even if the external clock is not controlled by the microcontroller 30 but provided by another external unit (not shown).

It can be provided, for example, that the system switches to a low-power mode or idle state in which no external clock is available. In low-power mode, the slave can 21 the data first in the shift register 50 lay down. This can be done without an external clock as described above. The first shift register 50 thus forms another buffer before the input buffer 41 , As soon as the slave 21 Data from the master 22 It can send a wake-up signal to the microcontroller 30 and possibly also send to other components. Once the microcontroller 30 has woken up, it can provide an external clock and the data from the first shift register 50 in the input buffer 41 take over and process accordingly. Here, the slave 21 the master 22 at any time via the fifth line BUSY signal whether he is ready to receive more data (SPI transmissions) or not.

The microcontroller 30 and / or other components do not necessarily have to go to a sleep state if there is no communication with the master 22 takes place. In order to save power, however, it is usually useful to switch at least some components into a state of rest, in which the power consumption is usually well below the power consumption in normal operation.

By putting the messages in an input buffer 41 be filed before going through the microcontroller 30 can be processed, there may be delays between the time a message is received and the time it is processed. The microcontroller 30 In principle, the messages can be retrieved from the input buffer at any time 41 read. To the data, by the microcontroller 30 from the input buffer 41 can be read to be able to assign a previous data transmission, the messages can be provided for example with a timestamp. This is exemplary in 9 shown. That is, in addition to the payload and an (optional) checksum PS can in the slave 21 still time stamps associated with the data are stored. The timestamp contains information about the time at which the respective message was stored in the input buffer.

The possibly resulting time delay is exemplary in 8th shown. In 8th schematically a timer is shown. The timer may be, for example, a continuous timer. At a first time, data transfer takes place from the master 22 to the slave 21 instead of. This first timer value, which relates to the transmission time, can be stored parallel to the message. The microcontroller 30 can at the time when it receives the data from the input buffer 41 also reads the current timer value read. He can compare this current time with the first timer value associated with the message and thus knows how much time has passed since the transmission (delta). This allows the microcontroller 30 then determine the actual transmission time of the data uniquely.

Similarly, during data transfer from the slave 21 to the master 22 a time delay between storing the data in the output buffer 42 and the actual transmission result. For example, the data may be transmitted through the microcontroller 30 at a first time in the output register 42 be filed. The microcontroller 30 At this time, the timer value can be read out and a first time stamp together with the data in the output buffer 42 store, wherein the first timestamp has information about the first time. Again referring to 9 For example, the last data bytes W of the payload data may be interpreted as the first timestamp information. The actual transfer takes place at a second time. This is in 10 exemplified. However, according to one example, the first timestamp is not sent to the master 22 transfer. Instead, different data is linked to the payload and transmitted, but related to the timer value at the time the data is stored (first parameter). For example, the one from the microcontroller 30 filed first timestamp at the time of transmission from the slave 21 be replaced by such data. For example, the data may include information about how much time has elapsed between the first time and the second time (delta between the first timer value and the current timer value at the time of transmission).

Not just a communication module 21 , which acts as a slave, may have the six lines described above. Also a communication module 22 , which acts as a master, can have the corresponding six lines so that this information, which the communication module 21 at the fifth and sixth line provides, can also receive.

A device for transmitting data has a first communication module 21 which is designed to be operated as a slave. The device for transmitting data further has a second communication module 22 who is trained to be a master. The first communication module 21 and the second communication module 22 are interconnected via a data bus. The data bus has six lines. These are a first line CLK for transmitting a clock signal from the second communication module 22 to the first communication block 21 , a second line MOSI for transmitting data from the second communication module 22 to the first communication block 21 , a third line MISO for transmitting data from the first communication block 21 to the second communication module 22 , a fourth line CS via which the first communication block 21 through the second communication module 22 can be activated, a fifth line BUSY for transmitting a first signal from the first communication module 21 to the second communication module 22 which contains information about whether the first communication module 21 is ready to receive data, and a sixth line IRQ for transmitting a second signal from the first communication device 21 to the second communication module 22 which contains information about whether the first communication module 21 Want to send data. The device can be a first communication module 21 and a second communication module 22 have, or more first communication blocks 21 and a second communication module 22 , wherein each of the first communication blocks 21 with the second communication block 22 connected via the described six lines. The device may for example be arranged in a vehicle.

LIST OF REFERENCE NUMBERS

11

slave

12

master

21

first communication device / slave

22

second communication device / master

30

microcontroller

41

input buffer

42

output buffer

43

Information on whether buffer is filled

44

Information if buffer is empty

45

Information about the beginning of a transmission

46

Information about the end of a transmission

50, 51

shift register

Claims (15)

Communication module (21) which is designed to be operated as a slave and to be connected to a second communication module (22), which is designed to be operated as a master, wherein the first communication module (21) comprises: a first line (CLK) for receiving a clock signal from the second communication device (22); a second line (MOSI) for receiving data; a third line (MISO) for transmitting data; a fourth line (CS) via which the first communication module (21) can be activated by the second communication module (22); and at least one of a fifth line (BUSY) for outputting a first signal containing information as to whether the first communication device (21) is ready to receive data; and a sixth line (IRQ) for outputting a second signal containing information as to whether the first communication device (21) wishes to transmit data. Communication module (21) after Claim 1 which is adapted to be connected to the second communication module (22) via an SPI bus. Communication module (21) after Claim 1 or 2 further comprising at least one input buffer (41) adapted to store messages received from the second communication module (22). Communication module (21) according to one of Claims 1 to 3 further comprising at least one output buffer (42) adapted to store messages to be transmitted to the second communication module (22). Communication module (21) after Claim 4 adapted to be connected to a microcontroller (30), the microcontroller (30) being adapted to read and process messages from the input buffer (41) and messages to the output buffer (42) for transmission to the second communication device (22). Communication module (21) according to one of the preceding claims, wherein the first signal of the fifth line (BUSY) assumes a first state (active) when the first communication device (21) can not receive new messages; and assumes a second state (not active) when the first communication device (21) can receive new messages. Communication module (21) according to one of the preceding claims, wherein the second signal of the sixth line (IRQ) assumes a first state (active) when the first communication device (21) wishes to send new messages; and assumes a second state (not active) when the first communication device (21) has no new messages to send. Communication module (21) according to one of the preceding claims, which is adapted to send messages to the second communication module (22), which in addition to payload data also have a checksum (PS); and Receive messages from the second communication module (22), which in addition to payload also a checksum (PS), wherein the integrity of a message can be checked based on the checksum. Communication module (21) according to one of the preceding claims, further comprising at least one of: at least one first shift register (50) arranged in front of the input buffer (41) such that messages received by the second communication module (22) are first stored in the first shift register (50) and transferred from there to the input buffer (41) ; and at least one second shift register (51) located behind the output buffer (42) such that messages to be sent to the second communication device (22) are taken from the output buffer (42) to the second shift register (51) and from there be transmitted to the second communication device (22). Communication module (21) according to one of the preceding claims, comprising at least one shift register, wherein at least one of the shift registers is designed to Messages received by the second communication module (22) are first to be stored before they are transferred from there into the input buffer (41), and Messages to be sent to the second communication module (22) to take over from the output buffer (42) before they are transferred from there to the second communication device (22). Communication module (21) after Claim 9 or 10 wherein the shift registers are driven by the clock signal or by a clock generated from the clock signal. Communication module (21) according to one of Claims 4 to 11 wherein a message to be transmitted to the second communication device (22) is stored at a first time in the output buffer (42); a first timestamp is stored along with the message in the output buffer (42), the first timestamp containing information about the first time; the message is transmitted to the second communication module (22) at a second time; the first communication module (21) is designed, when the message is transmitted to the second communication module (22), to replace the first time stamp with first data, the first data having information about a time duration (delta) between the first time and the second time has passed. Communication module (22) which is designed to be operated as a master and to be connected to at least one first communication module (21), which is designed to be operated as a slave, wherein the second communication module (22) comprises: a first line (CLK) for outputting a clock signal to the at least one first communication module (21); a second line (MOSI) for transmitting data; a third line (MISO) for receiving data; a fourth line (CS) via which the second communication module (22) can activate the at least one communication module (21); and at least one of a fifth line (BUSY) for receiving a first signal from the at least one first communication device (21), the first signal containing information as to whether the at least one first communication device (21) is ready to receive data; and a sixth line (IRQ) for receiving a second signal from the at least one first communication device (21), the second signal containing information about whether the at least one first communication device (21) wishes to transmit data. Device for data transmission with at least a first communication module (21) and a second communication module (22), wherein the at least one first communication module is configured to be operated as a slave and the second communication module (22) is designed to be operated as a master, wherein the at least one first communication component (21) and the second communication component (22) are interconnected via a data bus, and wherein the data bus comprises: a first line (CLK) for transmitting a clock signal from the second communication component (22) to the first communication component ( 21); a second line (MOSI) for transmitting data from the second communication module (22) to the at least one first communication module (21); a third line (MISO) for transmitting data from the at least one first communication device (21) to the second communication device (22); a fourth line (CS) via which the at least one first communication module (21) can be activated by the second communication module (22); and at least one of a fifth line (BUSY) for transmitting a first signal to the second communication device (22) containing information as to whether the at least one first communication device (21) is ready to receive data; and a sixth line (IRQ) for transmitting a second signal to the second communication device (22) containing information as to whether the at least one first communication device (21) wishes to transmit data. Device after Claim 14 , wherein the device is arranged in a vehicle.

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