DE102017215856B4 - information management device - Google Patents

Abstract

Information management device comprising:
a non-volatile memory (6) having a memory area in which data is writable and from which data is erasable; and
a writer (2, S32, S36, S92, S94) configured to write data to an empty area in the storage area of the non-volatile memory, wherein
deleting data from the memory area switches the memory area from a second state to a first state, the first state being a pre-write state of the memory area,
writing data to the memory area switches the memory area from the first state to the second state, the second state being an after-write state of the memory area, and wherein
the writer is configured to divide the memory area by means of the empty area to write a plurality of data pieces of data in the memory area in sequence.

Description

The present invention generally relates to an information management device.

Generally holds, i. H. Flash memory stores data in a writable and erasable manner. While the data is written in the flash memory in units of 2 bytes or 4 bytes, data is erased from the flash memory in a unit of blocks, that is, a unit of tens of bytes to kilobytes. Flash memory is limited to a certain number of data erases, i.e. flash memory has a finite number of program/erase (P/E) cycles. Based on the characteristics of a flash memory mentioned above, a flash memory uses a method of storing data by writing the data in blocks.

When such a method of storing data is used, an identifier at a header of each piece of data must be determined in order to find a desired piece of data in a plurality of pieces of data.

However, with an identifier represented by a bit value, i. H. using a value of "1" or "0", it can sometimes be difficult to distinguish the identifier from a data bit value, which is also represented by a "1" or "0" bit value. That is, identification using such an identification measure can be difficult and prone to error.

Therefore uses the JP H05 - 119 777 A a different measure in which a memory area is pre-divided into a plurality of sections and the header of each of the respective sections has a fixed address value to write the data in each of the pre-divided sections.

However, the data writing method described above may waste memory when, for example, the data length of the data to be written in a certain pre-divided memory section is shorter than the capacity or the length of the pre-divided memory section. That is, the shorter the length of the written data is relative to the capacity of the pre-divided memory area, the less efficient is the use of the memory area.

It will also refer to the U.S. 2014/0 136 765 A1 referenced, which has been identified as prior art. the US 2014/0 136 765 A1 Fig. 11 shows an information management device comprising: a non-volatile memory having a storage area in which data is writable and from which data is erasable; and a writer configured to write data to an empty area in the memory area of the non-volatile memory, wherein erasing data from the memory area switches the memory area from a second state to a first state, the first state being a pre-write - state of the memory area, writing data to the memory area switches the memory area from the first state to the second state, the second state being a post-write state of the memory area. It is an object of the present invention to provide an information management device which limits inefficient use of storage areas in a storage medium such as a flash memory or the like.

According to an aspect of the present invention, the information management device includes: a non-volatile memory and a writer.

The non-volatile memory (6) has a memory area to which data is writable and from which data is erasable, and the writer (2, S32, S36, S92, S94) is designed to write data to an empty area in the memory area of the non-volatile memory to write.

Deleting data from the memory area switches the memory area from a second state to a first state, i.e. a pre-write state of the memory area, and writing data to the memory area switches the memory area from the first state to the second state, that is, an after-write state of the memory area, and the writer divides the memory area by means of the empty area to write a plurality of pieces of data in sequence (i.e., in an ordered manner/one after another) in the memory area.

According to the information management device of the present invention, data is written in the storage area using the empty area as a “data divider”. Therefore, the loss of storage capacity, i. H. to unused areas. That is, inefficient use of memory space is limited.

The numbers in parentheses in the above paragraph and in the claims only serve to indicate relationships between the claim features and the components in the later described to show embodiments and are not intended to limit the technical scope of the present invention in any way.

• 1 ein Blockdiagramm einer Informationsmanagementvorrichtung gemäß einem ersten Ausführungsbeispiel der vorliegenden Erfindung darstellt;
• 2 Speicherbereiche in einem Flash-Speicher darstellt;
• 3 Prozesse darstellt, wie ein Zustand einer Zelle detektiert wird;
• 4 eine Darstellung eines Datenformats zum Speichern von Daten in dem Speicherbereich darstellt;
• 5 eine Vielzahl von in einer ersten Region gespeicherten Datenstücken darstellt;
• 6 ein Flussdiagramm eines Schreibprozesses gemäß dem ersten Ausführungsbeispiel der vorliegenden Erfindung darstellt;
• 7 ein Flussdiagramm eines Datenschreibprozesses gemäß dem ersten Ausführungsbeispiel der vorliegenden Erfindung darstellt;
• 8 Schreibzieldaten, die in den Speicherbereich geschrieben sind, darstellt;
• 9 das Sichern von Daten basierend auf den hier beschriebenen Prozessen darstellt;
• 10 Datenungültigerklärung basierend auf den hier beschriebenen Prozessen darstellt;
• 11 ein Flussdiagramm eines Leseprozesses gemäß dem ersten Ausführungsbeispiel der vorliegenden Erfindung darstellt;
• 12 ein Flussdiagramm des Schreibprozesses gemäß dem zweiten Ausführungsbeispiel der vorliegenden Erfindung darstellt;
• 13 ein Flussdiagramm des Datenschreibprozesses gemäß dem zweiten Ausführungsbeispiel der vorliegenden Erfindung darstellt; und
• 14 das Bewegen von Daten basierend auf den hier beschriebenen Prozessen darstellt.

Objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings, in which:

• 1 Fig. 14 is a block diagram of an information management device according to a first embodiment of the present invention;
• 2 represents storage areas in a flash memory;
• 3 processes depicts how a state of a cell is detected;
• 4 Figure 12 illustrates a data format for storing data in the storage area;
• 5 represents a plurality of pieces of data stored in a first region;
• 6 Fig. 14 is a flow chart of a writing process according to the first embodiment of the present invention;
• 7 Fig. 14 is a flowchart of a data writing process according to the first embodiment of the present invention;
• 8th represents write target data written in the storage area;
• 9 depicts backing up data based on the processes described herein;
• 10 represents data invalidation based on the processes described herein;
• 11 Fig. 12 is a flow chart of a reading process according to the first embodiment of the present invention;
• 12 Fig. 14 is a flow chart of the writing process according to the second embodiment of the present invention;
• 13 Fig. 14 is a flowchart of the data writing process according to the second embodiment of the present invention; and
• 14 depicts moving data based on the processes described herein.

Embodiments of the present invention will be described below with reference to the drawings.

[1. First embodiment]

[1-1. Configuration]

An information management device 1 is described with reference to FIG 1 described. The information management device 1 is a device that can write data in a flash memory 6 acting as a memory or storage medium and also delete data written in the memory 6 .

The information management device 1 is provided with a CPU 2, a ROM 3, a RAM 4, a flash controller 5, the flash memory 6, and an input/output (I/O) 7. FIG. Electric power is supplied to each part of the information management device 1 from a power source 11 . The I/O 7 serves as an input/output interface functioning as an input-output section with an external device.

The CPU 2 performs overall control of the information management device 1 by executing flash driver software 8 and application software 9 which may be programs stored in the ROM 3 .

Specifically, the CPU 2 controls reading and writing of data from and to the flash memory 6 via the flash controller 5 by executing the flash driver software 8 based on an access request to the flash memory 6 from the application software 9.

The RAM 4 is a volatile memory that provides a work area used by the CPU 2 . The RAM 4 provides a function of temporarily holding the data read from the flash memory 6 and the data to be written into the flash memory 6 .

The flash controller 5 performs a writing process, a reading process, an erasing process, and the like to write, read, and erase the data in and/or from the flash memory 6 based on an instruction from the CPU 2 .

The flash memory 6 is a non-volatile memory that has a storage area used by the CPU 2 . The storage area of the flash memory 6 includes a plurality of blocks 10, and each of the blocks 10 serves as a unit for erasing.

The flash memory 6 stores data by writing a bit value of "0" or "1" into a cell. As in 2 shown, the data in memory 6 is in a unit of "words" written, which are multiple bytes of memory area.

On the other hand, the data from the flash memory 6, i. H. deleted from the memory area in a unit of blocks 10 larger units than words. That is, the block 10 can have a size ranging from several tens of bytes to several kilobytes.

That is, data writing is performed in units of words (i.e., word by word), and data erasing is performed in units of blocks (i.e., block by block).

A state of the memory area after deleting data is referred to as “empty”, and a memory area in an empty state is referred to as an “empty area”.

Since the data is not writable in a memory area already written (i.e. overwriting the data already written in the memory area is not allowed), the data is written in the empty area. In other words, the empty area is a storage area in a first state, or in a pre-write state, before the data is written therein. Thus, when a process of writing data to an empty area (i.e., to the memory area in the first state) is performed, the memory area is converted to a second state, or switched to an after-write state, after the data there have been written in.

In particular, after erasing the data, the flash memory 6 remains in the first state, ie remains in a non-determinable state (ie "NON-DET" in 3 ) in which the bit value of the memory is fixed as neither "0" nor "1", and, after writing data to the flash memory 6 remaining in the first state, the flash memory 6 switches to the second state , or a particular state in which the bit value is fixed as either "0" or "1".

As in 3 shown, a command called “empty check” can be used to detect whether a specific memory area is an empty area. The empty check is performed for one cell.

If a cell is determined by the empty check to be in the first state (i.e. if a memory area is determined to be an empty area), any of the bit values "0" or "1" can be read, but an actually read one from the two bit values "0" or "1" cannot be determined.

If a cell is determined by the empty check to be in the second state (i.e. if a memory area is determined not to be an empty area: "NOT EMPTY" in 3 ), a bit value of either "0" or "1" can be read from it.

[1-2. writing process]

The format of the data stored in the storage area of the flash memory 6 will be described with reference to FIG 4 described. The data stored in the storage area is organized in an ordered combination of a header 12, a management part 13 and a data part 14, a combination of which (ie the three parts 12 to 14) serves as a unit for data storage. The unit of such a combination of the parts described above can also be referred to as a combination unit 15. That is, the combination unit 15 serves as a unit for storing data, and a plurality of pieces of data are stored in the storage area as consecutive combination units 15 written in the storage area starting from the head of the storage area.

As in 5 1, for example, a first region 200, which is a specific block 10 among the storage areas of the flash memory 6, stores a plurality of pieces of data as a plurality of combination units 15. Note that, in the drawings, the header 12 is denoted as "S". can be, a flag described below can be referred to as “F” and an identifier also described below can be referred to as “ID”.

The data stored by the data portion 14 may include (i) the identifier for identifying one of the plurality of data types, and (ii) a data value representing a value of the data of the specified identifier.

The identifier may be stored/written at a head of the data part 14 and may specify a name of a variable.

The data value can be a value of the variable.

Each of the data length of the identifier and the data length of the data value can be an arbitrary length. That is, both the identifier and the data value can have any data length.

The header 12 is a header of the unit combination 15, which serves as a "header" and a is one word in length. This area is always in the first state, ie an empty area.

Since two or more pieces of data are stored by using two or more combination units 15 consecutively, i. H. in series, a location of the stored data is identified by each of the headers 12 .

The management part 13 is an area for storing a flag showing whether the data stored by the data part 14 is valid or invalid, and the management part 13 has a one-word length.

If the management part 13 is an empty area, i. H. is in the first state, the flag in the management part 13 shows that the data is valid. When the management part 13 is in the second state, the flag in the management part 13 shows that the data is invalid. In the following description, data that is valid may be simply referred to as “valid data”, and data that is invalid may be simply referred to as “invalid data”.

If the data is valid, the data value of the valid data is the newest among the data values having the same identifier. When the data is invalid, the data value of the invalid data is not the newest value among the data values having the same identifier.

That is, even if there are many data values having the same identifier, basically only one data value has the flag showing that the data value is valid. Furthermore, by toggling the data to have either a valid/invalid state, i. H. by changing/switching the flag to either the first state or the second state, updating data having a specific identifier.

Next, the writing process that writes data in the first region 200 of the storage area of the flash memory 6 will be described with reference to FIG 6 described.

The writing process is started when the CPU 2 receives a write request for writing write target data (i.e., data to be written).

In step S21 (i.e., S21), the CPU 2 executes a process, i.e., H. performs an empty check starting from the head of the first region 200 and detects an empty area. If an empty area having a one-word length is detected, the process proceeds to step 22.

In step 22, the CPU 2 performs a process that determines whether the area detected in step 21 has the data. That is, specifically, determines whether the area detected in step 21 serves as the header 12 of a combination unit 15 having any data in the data part 14 . In other words, the CPU 2 regards the detected one-word area as a first area of a combination unit 15, and regards the next (i.e., the second) one-word area as the management part 13, and considers the next (i.e., the third) one-word area word area as the head of the data part 14 to determine whether there is any data in this combination unit 15.

Specifically, the CPU 2 performs an empty check for the third one-word area. Since the data is already written in the head of the data part 14 when the third one-word area is in the second state, the CPU 2 determines that a combination unit 15 having the area detected in step 21 as the head part 12 , which has data.

Since the writing to the head of the data part 14 has not yet been performed when the third one-word area is in the first state, i. H. is an empty area, the CPU 2 determines that a combining unit 15 having the area detected in step 21 as the header 12 does not have any data in such a case, that is, when the third one-word area is in the first state.

A combination unit 15 having the blank area detected in step 21 as the header 12 has no data, which means that a "writable" blank area has been found. In other words, the combining unit 15 is the last combining unit 15 at an end of consecutive storing of combining units 15 (i.e., at an end of a series of combining units 15) written from the head of the first region 200.

If an affirmative determination is made in step 22, the process proceeds to step 23.

In step 23, the CPU 2 performs a process of determining whether the data determined to exist in step 22 is valid data.

Specifically, the CPU 2 performs a process that determines whether the data detected in step 22 is valid data by performing an empty check for the second one-word area before the third one-word area identified in step 22 has been processed.

When the second one-word area, ie, the flag, is determined to be in the first state, the CPU 2 determines that the data determined to exist in step 22 is valid data.

On the other hand, if the second one-word area, i. H. the flag is determined to be in the second state, the CPU 2 determines that the data determined to exist in step 22 is invalid data.

If a negative determination is made in step 23, the process returns to step 21.

In step 21, the CPU 2 performs a process that detects an empty area serving as the header 12 of the next combining unit 15 next following the combining unit 15 having the header 12 detected in the previous step 21.

If an affirmative determination is made in step 23, the process proceeds to step 24.

In step 24, the CPU 2 performs a process that determines whether the identifier of the combining unit 15 determined in step 23 to have the valid data is the same identifier as the identifier of the write target data.

Specifically, the CPU 2 performs a process that obtains the identifier based on the bit value written in the area after the third one-word area next to the second one-word area processed in step 23 .

If a negative determination is made in step 24, the process returns to step 21.

In step 21, just like the negative determination process in step 23, the CPU 2 performs a process that detects a vacant area serving as the header 12 of the next combination unit 15 which follows the combination unit 15 detected in the previous step 21 next follows.

If an affirmative determination is made in step 24, the process proceeds to step 25.

In step 25, the CPU 2 performs a data writing process.

The concrete content of the data writing process will be described with reference to 7 described.

In step S31 (i.e., S31), the CPU 2 performs a process that determines whether there is any writable area, i.e., H. the vacant area, into which the write target data from the combination unit 15 is writable.

If an affirmative determination is made in step 31, the process proceeds to step 32.

In step 32, the CPU 2 performs the data writing process which writes the write target data, i. H. writes the identifier and the data value into the empty areas starting at the third one-word area of the empty area. That is, by keeping the two blank areas left unwritten after the last combination unit 15 at one end of a series of consecutive combination unit 15 stores starting from the head of the first region 200, writing of the write target data begins in the third one-word -area, towards the following blank areas.

The situation can be clearer with reference to 8th be understood, which shows a state of the first region 200 after the process of step 32 for the in 5 shown first region 200 has been performed.

As in 8th shown, the CPU 2 writes the write target data by writing the header part 12 and the management part 13 in empty areas 51 and 52, that is, in a two-word-length area, and by writing the data part 14 in an area 53 that is in the third one-word area and extends thereafter, all of which constitute a combination unit 15 of data writing.

Since the management part 13 of the written combination unit 15 is the vacant area 52, the write target data is written as valid data. Further, by writing the write target data as one combination unit 15 to a position immediately after the last combination unit 15 stored in the first region 200, the plurality of combination units 15 are stored as consecutive combination units 15.

After step 32, the CPU 2 ends the data writing process, and the process proceeds to step 26.

However, if a negative determination is made in step 31, the process proceeds to step 33.

In step 33, the CPU 2 performs a process that saves the valid data stored by the data part 14 in the RAM 4. FIG. An example of saving valid data is in 9 (A) to (C) shown.

As in 9 (A) shown, when there is no writable area to which the write target data can be written in the first region 200, combining units 61, 62, 63 each having a flag in the first state save their valid data in the data part 14 in the RAM 4 as shown by an arrow A1.

In step 34, the CPU 2 performs a process that deletes the data stored in the first region 200 that has already been saved in step 33. As in 9 (B) shown, after erasing, the area turns into an empty area that is in the first state.

In step 35 following step 34, the CPU 2 performs a process that returns the valid data saved in step 33 to the first region 200 on which the deletion of the data in step 34 has been performed /restored. For example, an A2 in 9 (A) /(B) shown process performed.

In step 36, the CPU 2 writes the write target data, ie, the identifier and the data value, into the vacant areas starting from the third one-word area by locating the two vacant areas after the last combination unit 15 at an end of successive storage of the combination units 15 in series starting from the head of the first region 200 left unwritten. That is, as in 9 (c) 1, the write target data is stored as a combination unit 66 in the vacant area.

After step 36, the CPU 2 ends the data writing process, and the process proceeds to step 26.

In step 26, an invalidation process is performed which invalidates the data of the combination unit 15 having the same identifier as has been affirmatively determined in step 24. An example of step 26 is in 10 shown.

10 Fig. 12 is an illustration of a situation after performing a process of step 26 in Fig 8th shown first region 200. As in 10 1, the CPU 2 performs an invalidation process that invalidates the data by writing to a flag area 54 of a combination unit 15 having the same identifier as the write target data ("INVALID DATA OF SAME ID" in S26 of 6 ). In such a manner, the newest data is converted into old data at a time immediately after writing.

Thus, the write target data is written as the newest data by the process in step 25 and by the process in step 26, and the data of the combining unit 15 having the same identifier as the write target data is converted into old data, and thereby an update is performed of data completed. The CPU 2 ends the writing process after step 26.

If a negative determination is made in step 22, the process proceeds to step 27.

In step 27, the CPU 2 performs the data writing process just as in step 25. That is, a process of step 32 or a process of steps 33-36 is performed. After step 32 or step 36, the CPU 2 ends the data writing process and ends the writing process.

[1-3. reading process]

The reading process that reads the data stored in the first region 200 of the storage area of the flash memory 6 is described with reference to FIG 11 described.

The read process is started when the CPU 2 receives a read request to read read target data (i.e., data to be read).

In step 71 (i.e., S71), the CPU 2 executes a process, i.e., H. performs an empty check starting from the head of the first region 200 and detects an empty area. If an empty area that is one word in length is detected, the process proceeds to step 72 .

In step 72, the CPU 2 performs a process of judging whether the area detected in step 71 has the data. That is, it is specifically determined whether the one-word area detected in step 71 serves as the header 12 of a combination unit 15 . This can also be understood as a situation in which the CPU 2 regards the detected one-word area as a first area in a combining unit 15 and considers the next (i.e. the second) one-word area as the management part 13 and the next (i.e., the third) one-word area is considered the head of the data part 14 to determine whether there is any data in this combination unit 15.

Specifically, the CPU 2 performs an empty check on the third one-word area. When the third one-word area is in the second state, the CPU 2 determines that a combining unit 15 having the area detected in step 71 as the header 12 has the data.

On the other hand, when the third one-word area is in the first state, i. H. is an empty area, the CPU 2 determines that a combination unit 15 having as the header 12 the area detected in step 71 has no data.

Note that if a combination unit 15 that has the blank area detected in step 71 as the header 12 has no data, it means that a "writable" blank area has been found, i.e. that the detected combination unit 15 has the last combination unit 15 is written at an end of a successive storage of the combination units 15 starting from the head of the first region 200.

If an affirmative determination is made in step 72, the process proceeds to step 73.

In step 73, the CPU 2 performs a process of determining whether the data determined to exist in step 72 is valid data.

Specifically, the CPU 2 performs a process that determines whether the data determined in step 72 is valid data by performing an empty check on the second one-word area before the third one-word area obtained in step 72 has been processed.

If the second one-word area, i. H. the flag is in the first state, the CPU 2 determines that the data obtained in step 72 is valid data.

On the other hand, if the second one-word area, i. H. the flag is in the second state, the CPU 2 determines that the data obtained in step 72 is invalid data.

If a negative determination is made in step 73, the process returns to step 71.

In step 71, the CPU 2 performs a process that detects an empty area serving as the header 12 of the next combining unit 15 next following the combining unit 15 having the header 12 detected in the previous step 71.

If an affirmative determination is made in step 73, the process proceeds to step 74.

In step 74, the CPU 2 performs a process of determining whether the identifier of a combination unit 15 having the valid data determined in step 73 is an identifier of the read target data.

Specifically, the CPU 2 performs a process which, based on the bit values stored in the third and subsequent one-word areas, i.e., in the area after the second one-word area processed in step 73, are written, determines whether the identifier is that for the read target data.

If a negative determination is made in step 74, the process returns to step 71.

In step 71, which is similar to a negative determination in step 73, the CPU 2 performs a process that detects a blank area serving as the header 12 of the next combining unit 15 next following the combining unit 15 which has the header 12 detected in the previous step 71.

If an affirmative determination is made in step 74, the process proceeds to step 75.

In step 75, the CPU 2 performs a process that reads the data stored in the data part 14 of the combining unit 15 having the identifier determined in step 74 as the identifier of the read target data.

The CPU 2 ends the reading process after step 75.

If a negative determination is made in step 72, the CPU 2 determines that there is no read target data and ends the read process.

[1-4. effects]

Based on the first embodiment described in detail above, the following effects can be realized.

(1a) The CPU 2 of the first embodiment performs a process which writes data into the storage area so that the plurality of combination units 15 are stored sequentially starting from the head of the first region 200. That is, the CPU 2 performs a process which writes a plurality of pieces of data into the storage areas one by one writes richly by dividing the memory area into sections (ie, into a plurality of memory areas) using the empty area.

Therefore, the disadvantage of having many unused areas in the storage area depending on the data length, which is caused by a storage area pre-dividing measure and an information management apparatus implementing such a measure, is overcome. That is, the information management device according to the first embodiment of the present invention prevents or limits such unused areas, thereby improving memory use efficiency.

(1b) The CPU 2 of the first embodiment performs a process that detects a blank area in the first region 200. FIG.

Therefore, an address of a head position of the data need not be specified for reading or writing the data. That is, a head position of the data, or a storage position of the data in the storage area is identifiable by detecting an empty area. Thus, based on the detected blank area indicating a data storage position, the read target data is read.

(1c) The CPU 2 of the first embodiment performs a process which writes an identifier in a head of the data. Further, the CPU 2 performs a process that reads the read target data based on the identifier in the head of the data.

Therefore, data having a specific identifier can be written into the storage area, and data having a specific identifier can be read from the storage area. Thus, many types of data can be uniquely stored and recognized.

(1d) The CPU 2 of the first embodiment performs a process which writes the write target data as a combination unit 15 to an end position of the last combination unit 15 to a tail/tail of a series of combination units 15 sequentially starting from the head of the first region 200 have been memorized writes in an "attached" manner.

Thus, the write target data can be written to an end position after the last combining unit 15 regardless of the data length.

(1e) The CPU 2 of the first embodiment performs an invalidation process that invalidates valid write target data when the same, i.e. H. valid identifier is used in two different pieces of data. That is, by inserting two one-word spaces before the, i. H. when a head of the write target data is written, the valid data is invalidated.

Therefore, the newest data is converted into old data immediately after the write target data is written as the newest data. This means that the data can be updated without deleting the old data.

Furthermore, the CPU 2 of the first embodiment performs a process that determines whether data is valid or invalid and determines the identifier of the data. Therefore, an update state of the data is recognized for each of the data states. Thus, the latest read target data is determined and read.

(1f) When the CPU 2 of the first embodiment cannot write the write target data as a combination unit 15 in the vacant areas in the first region 200, i. H. if the writable areas in the first region 200 are insufficient, the CPU 2 saves the valid data in the RAM 4 and erases all the data in the first region 200.

Therefore, even if the first region 200 of the storage area is completely occupied by the data, i. H. even if the first region 200 is filled to the brim with the data, writable areas can be reserved in the storage area of the flash memory 6 to enable writing of data into the storage area.

In the first embodiment, the flash memory 6 can be referred to as a non-volatile memory. The CPU 2 when performing steps S32 and S36 can be referred to as a “writer”, and the CPU 2 when performing steps S71-S75 can be referred to as a reader.

When the CPU 2 performs steps S21 and S22, it can be referred to as an empty detector, when the CPU 2 performs steps S23 and S24, it can be referred to as a data detector, and when the CPU 2 performs step S26 performs may be referred to as an invalidation processor. The management part 13 can be referred to as a flag area.

The RAM 4 can be called a separate memory. The CPU 2 performing steps S33- Performing S35 can be referred to as a data saver.

[2. second embodiment]

[Difference from the first embodiment]

Since the configuration of the second embodiment of the present invention is basically the same as that of the first embodiment, the following description focuses on differences of the second embodiment with respect to the first embodiment. The same reference numerals as in the first embodiment represent the same configuration or component, and as such their respective descriptions are omitted for brevity.

According to the first embodiment mentioned above, in the writing process, the CPU 2 performs a process that saves the valid data stored in the first region 200 in the RAM 4 .

However, in the second embodiment, the CPU 2 performs a different process that saves the valid data stored in the first region 200 in a second region 300 which is in a different block 10. FIG.

The second region 300 is one of the plurality of blocks 10 in the storage area of the flash memory 6 and is a different block 10 from the block 10 having the first region 200.

[2-2. writing process]

The writing process performed by the CPU 2 of the second embodiment is described in more detail below. The CPU 2 in the second embodiment performs the writing process in a manner shown in the flowcharts of FIGS 12 and 13 detailed manner by which the flowcharts in 6 and 7 replace the first embodiment.

Since a process from Step 81 - Step 84 in 12 is the same as a process from step 21 - step 24 in 6 , the description of this part will be omitted.

If an affirmative determination is made in step 84 (i.e., S84), the process proceeds to step 85.

In step 85, the CPU 2 performs a data writing process. The concrete content of the data writing process will be described with reference to 13 described.

In step 91 (i.e., S91), the CPU 2 performs a process that determines whether there is any writable area, i.e., H. an empty area, in which the write target data is writable by the combination unit 15. If an affirmative determination is made in step 91, the process proceeds to step 92.

In step 92, the CPU 2 performs a data writing process which writes the write target data, i. H. writes the identifier and the data value into the empty areas starting at the third empty one-word area, d. H. by keeping the two blank areas left unwritten starting from the last combination unit 15 standing at one end of a successive storage of combination units 15 in series starting from the head of the first region 200.

After step 92, the CPU 2 ends the data writing process, and the process proceeds to step 86.

On the other hand, if a negative determination is made in step 91, the process proceeds to step 93.

In step 93, the CPU 2 performs a process that saves the valid data stored in the data part 14 in the second region 300, that is, performs a data movement process. An example of such a process is in 14 (A) to (F) shown.

As in 14 (A) shown, when there is no writable area in which the write target data is writable in the first region 200, the data stored in the data part 14, ie, in combination units 101, 102, 103 each having the flag in the first state valid data is saved in the second region 300 as shown by an arrow B1.

The second region 300 is a prior to performing the data movement process as shown in FIG 14 (B) shown, blank area.

In step 94, the CPU 2 performs a data writing process that writes the write target data, ie, the identifier and the data value, into the vacant areas starting from the third one-word area of the vacant areas, ie, by dividing the two vacant areas starting from the last Combination unit 15 standing at an end of successive storage of the combination units 15 in series from the head of the second region 300 can be kept unwritten. That is, as in 14 (D) shown, the write target data in the second region 300 is taken as a combination unit 105 is written/stored.

In the subsequent step 95, the CPU 2 performs an invalidation process that deletes the data stored in the first region 200. FIG. As in 14 (c) and (E), the data memorized in the first region 200 is deleted.

After step 95, the CPU 2 ends the data writing process, and the process proceeds to step 86.

In step 86, the CPU 2 performs a process which invalidates the data of the combination unit 15 having the identifier which has been affirmatively obtained in step 84. The CPU 2 ends the writing process after step 86.

If a negative determination is made in step 82, the process proceeds to step 87.

In step 87, the CPU 2 performs a data writing process just like step 85. That is, in step 87, a process of step 92 or a process of steps 93-95.

After step 92 or step 95, the CPU 2 ends the data writing process and ends the writing process.

[2-3. effects]

According to the second embodiment described in detail above, in addition to the above-mentioned effects (1a) - (1e) of the first embodiment, the following effects are also obtained.

(2a) The CPU 2 of the second embodiment saves the data in the second region 300 when there are insufficient vacant areas, i. H. writable areas, to which the write target data is writable by the combining unit 15. In such a case, because the second region 300 is a storage area implemented as a non-volatile memory, even if a power supply of the information management device 1 is cut off during erasing of the data, the data in the second region 300 is retained, i. H. kept undamaged.

In the second embodiment, the CPU 2 performing steps S92 and S94 can be referred to as a writer, the CPU 2 performing steps S81 and S82 can be referred to as an empty detector, the CPU 2 performing the performing steps S83 and S84 may be referred to as a data detector, the CPU 2 performing step S86 may be referred to as an invalidation processor, and the CPU 2 performing steps S93 and S95 may be referred to as a data mover.

[Other embodiments]

The above-described embodiments of the present invention can be further modified to have various configurations without being limited to the above.

(3a) Although the combination unit 15 is organized to include the management part 13 in the above embodiments, a combination unit need not include a management part. That is, a combination unit can be organized to have only a header and a data part.

A CPU can perform a data writing process that writes the write target data into the vacant areas starting from the second one-word area of the vacant area by creating an empty area starting from the last combination unit that is at an end of successive storage of the combination units in series starting from the head of the block left unwritten. In such a manner, even if a combination unit is organized to include only a header and a data part, data can be appropriately written into the memory area as a series of combination units sequentially stored therein.

Further, when reading the read target data, the CPU reads the last written data as valid data based on a determination that the data stored at a position closer to an end of the row of combination units in the first region is valid. In such a way, even if a combination unit is organized to include only a header and a data part, the latest read target data can be read.

(3b) Although the data stored in the data part 14 is shown as an identifier and a data value in the above-mentioned embodiment, the data in the data part 14 is not necessarily limited to such a configuration. That is, the data in the data part can only be one data value.

(3c) Although a write start position of write target data is identified in the above-mentioned embodiments by performing a process that includes three vacant areas in a row, ie, the first to third vacant areas in row detected by detection starting from the head of the first or second region 200 or 300, the write start position can be detected by other methods. That is, the CPU can perform a process that detects at least three blank areas in a row by detection starting from the head of a block to identify a write start position of write target data.

(3d) Although the header 12 and the management part 13 are each shown as a one-word area in the above-mentioned embodiments, the header 12 and the management part 13 are not necessarily limited to such a configuration. That is, a header can be two word lengths or longer, and a management part can be two word lengths or longer.

Furthermore, in the above-mentioned embodiment, consecutive empty areas are detected as a series of at least three "one-word" unit areas, or as empty areas of a first unit number (i.e., consecutive empty areas of at least a first unit number) by detection starts at the head of the storage area. However, the consecutive blank areas can be detected as a series of four or more one-word areas.

Furthermore, in the above-mentioned embodiment, the data is written in consecutive empty areas organized as a series of two one-word unit areas or as empty areas of a second unit number (i.e., written in the detected consecutive empty areas in series from a second unit number). However, the data can be written in the consecutive empty areas organized as a series of empty areas of the second unit number smaller than the first unit number. The second unit number can be at least one word length.

(3e) Although the CPU 2 performs a backup process that saves the valid data stored in the first region 200 in the RAM 4 in the above-mentioned first embodiment, the backup destination is not limited to the RAM 4. That is, the backup destination may be a volatile memory other than the RAM4.

(3f) Although an indeterminable state in which the bit value is not determined as "0" or "1" is defined as the first state, and a definite state in which the bit value is determined as either "0" or "1" is determined as the second state is defined, the definition of these states is not limited to the above. The first state may be a pre-write state, i. H. a state before writing data, and the second state may be a post-write state, i. H. a state after writing data.

(3g) The information management device 1 of the above-mentioned embodiment can be mounted and used in vehicles.

For example, an information management device can be used as a device that updates a memory of values learned in a vehicle controller such as an engine controller or the like.

For example, an information management device can also be used as a device that stores freeze frame data or the like including vehicle usage status data at the time of failure to diagnose the vehicle.

The information management device of the present invention is different from an information management device that predivides the memory area into multiple sections for writing the data, thereby preventing unused areas in the memory area or causing fewer unused areas in the memory area even by writing the data with different data lengths. Therefore, the information management device of the present invention can be suitable and effective for storing vehicle use status data, which typically has a large data volume and has different data lengths.

(3h) Two or more, i. H. a plurality of functions implemented by one component in the above embodiments may be performed by a plurality of components, or a function implemented by a plurality of components in the above embodiments may be implemented by only one component. A "vice versa" function implementation measure can also be applied.

Further, part of the above embodiment may be omitted, and/or part of one embodiment may be added to or replaced with the other embodiment.

Note that all modes of the technical thought described by the wording in the claims serve as the embodiment and are within the scope of the present invention.

(3i) The present invention, apart from the CPU 2 described above, can also be used as an information management system using the CPU 2 as a component, or an information management program for controlling a computer to perform the above-mentioned writing/reading process, or a non-volatile tangible storage medium storing such an information management program, or an information management method, or the like can be realized.

Claims (7)

Information management device comprising: a non-volatile memory (6) having a memory area in which data is writable and from which data is erasable; and a writer (2, S32, S36, S92, S94) configured to write data to an empty area in the storage area of the non-volatile memory, wherein deleting data from the memory area switches the memory area from a second state to a first state, the first state being a pre-write state of the memory area, writing data to the memory area switches the memory area from the first state to the second state, the second state being an after-write state of the memory area, and wherein the writer is configured to divide the memory area by means of the empty area to write a plurality of data pieces of data in the memory area in sequence. information management device claim 1 further comprising: a reader (2, S71-S75) configured to read read target data in the storage area, the reader being further configured to read the read target data by detecting the empty area in the storage area (2, S71). information management device claim 2 , wherein the writer is further configured to write an identifier as a head of the data to identify the data, and wherein the reader is further configured to read the read target data based on the identifier written as the head of the data (2, S74 ). Information management device according to one of Claims 1 until 3 further comprising: an empty detector (2, S21, S22, S81, S82), which is configured to detect the empty area in the storage area as consecutive empty areas in series of at least a first unit number, the detection of the empty area on a head part of the memory area and proceeds to subsequent parts of the memory area in order, and wherein the writer is further configured to write data in the empty area by using a detected location of the consecutive empty areas as a data writing start position and data in the detected consecutive ones writes blank areas in series of a second unit number, the second unit number being less than the first unit number. information management device claim 4 further comprising: a data detector (2, S23, S24, S83, S84) configured to detect valid data invalidated by writing write target data; and an invalidation processor (2, S26, S86) adapted to invalidate the valid data when the data detector detects the valid data, wherein part of the consecutive empty areas of the second unit number serves as a flag area (13). to show a validity of consecutive data written in a portion immediately following the flag area, the first state of the flag area showing that the subsequent data is valid and the second state of the flag area showing that the subsequent data is invalid, and wherein the invalidation processor invalidates the valid data by ascribing a value to the flag immediately preceding the valid data. information management device claim 5 further comprising: a data saver (2, S33-S35), which is designed to save the valid data in the memory area by (i) saving the valid data in a separate memory (4), which is one of the non-volatile memory ( 6) is separate storage, and (ii) restores the saved valid data from the separate storage (4) back to the storage area after deleting the data from the storage area if the storage area has no writable area to write the write target data , wherein the writer is configured, the writing target to write data (2, S36) into the memory area in which the valid data are restored by the data saver. information management device claim 5 further comprising: a data mover (2, S93, S95) configured to (i) move the valid data in a first region (200) of the storage area to a second region (300) of the storage area and (ii) the valid data to erase from the first region (200) when the first region has no writable area in which the write target data is writable and the second region has a writable area in which the write target data is writable, the writer being further configured which write (2, S94) write target data in the second region to which the valid data has been moved from the data saver.

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