DE102017215856A1 - Information management device - Google Patents

Abstract

An information management device comprises a flash memory (6) and a writer (2). The flash memory has a first region (200) and a second region (300) into which and from which data is writable and erasable, and the first / second region is configured to be switched to a first state, which is a forward Write state or a data clear state is to serve as an empty area and configured to be switched to a second state which is an after-write state. When data is deleted from the first region (200), that area is switched to the first state, and when data is written to an empty area in the first state, that area is switched to the second state. A writer of the information management apparatus is capable of storing a plurality of pieces of data one by one, i. H. in series, by dividing the first region (200) using the blank area.

Description

The present invention generally relates to an information management device.

Generally holds, d. H. saves a flash memory data in a writable and erasable manner. While the data is written in the flash memory in units of 2 bytes or 4 bytes, data is erased from the flash memory in a unit of blocks, that is, a unit of several tens of bytes to several kilobytes. The flash memory is limited to a certain number of data erasures, that is, a flash memory has a finite number of program / erase (P / E) cycles. Based on the above-mentioned characteristics of a flash memory, a flash memory uses a method of storing data by writing the data into blocks.

When such a method of storing data is used, an identifier at a header of each piece of data must be detected to find a desired piece of data in a plurality of pieces of data.

However, with an identifier represented by a bit value, i. H. using a value of "1" or "0", may sometimes be difficult to distinguish the identifier from a data bit value, which is also represented by a "1" or "0" bit value. That is, identification by such an identification measure can be difficult and prone to errors.

Therefore, a patent document 1 mentioned below uses a different measure in which a memory area is pre-divided into a plurality of sections and the header of each of the respective sections has a fixed address value to write the data into each of the pre-divided sections.

(Patent Document 1) Japanese Laid-Open Patent Publication No. H05-119777

However, the data writing method described above may waste memory if, for example, the data length of the data to be written in a particular pre-divided memory section is shorter than the capacity or the length of the pre-divided memory section. That is, the shorter the length of the written data is in terms of the capacity of the pre-split memory area, the less efficient is the use of the memory area.

It is an object of the present invention to provide an information management apparatus which limits the inefficient use of storage areas in a storage medium such as a flash memory or the like.

According to one aspect of the present invention, the information management apparatus includes: a nonvolatile memory and a writer.

The nonvolatile memory ( 6 ) has a memory area in which data can be written and from which data is erasable, and the recorder ( 2 , S32, S36, S92, S94) is configured to write data in an empty area in the memory area of the nonvolatile memory.

The erasure of data from the storage area switches the storage area from a second state to a first state, that is, a pre-write state of the storage area, and writing data into the storage area switches the storage area from the first state to the second state. that is, an after-write state of the storage area, and the writer divides the storage area by the empty area to write a plurality of pieces of data in succession (ie, one orderly / one after another) into the storage area.

According to the information management apparatus of the present invention, data is written into the storage area using the empty area as a "data splitter". Therefore, the loss of storage capacity, i. H. to unused areas, limited. That is, the inefficient use of the storage area is limited.

The numbers in parentheses in the above section and in the claims are merely to show relationships between the claim features and the components in the embodiments described later and are not intended to limit the technical scope of the present invention in any way.

Objects, features and advantages of the present invention will become more apparent from the following detailed description made with reference to the accompanying drawings, in which:

1 Fig. 10 is a block diagram of an information management apparatus according to a first embodiment of the present invention;

2 Represents storage areas in a flash memory;

3 Processes representing how a state of a cell is detected;

4 Fig. 10 illustrates an illustration of a data format for storing data in the storage area;

5 represents a plurality of pieces of data stored in a first region;

6 Fig. 10 is a flowchart of a writing process according to the first embodiment of the present invention;

7 Fig. 10 is a flowchart of a data writing process according to the first embodiment of the present invention;

8th Write target data written in the memory area;

9 represents backup of data based on the processes described herein;

10 Data invalidation based on the processes described herein;

11 Fig. 10 is a flowchart of a reading process according to the first embodiment of the present invention;

12 Fig. 10 is a flow chart of the writing process according to the second embodiment of the present invention;

13 Fig. 10 is a flowchart of the data writing process according to the second embodiment of the present invention; and

14 represents the movement of data based on the processes described herein.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[1. First embodiment]

[1-1. Configuration]

An information management device 1 is related to 1 described. The information management device 1 is a device that stores data in a flash memory 6 can write, acting as a memory or storage medium, and also in the memory 6 delete written data.

The information management device 1 is with a CPU 2 , a ROM 3 , a ram 4 , a flash controller 5 , the flash memory 6 and an input / output (I / O) 7 Mistake. Electrical energy becomes part of the information management device 1 from an energy source 11 provided. The I / O 7 serves as an input / output interface functioning as an input-output section with an external device.

The CPU 2 performs an overall control of the information management device 1 by running a flash driver software 8th and an application software 9 through that in the rom 3 stored programs.

In particular, the CPU controls 2 reading and writing data to and from the flash memory 6 via the flash control 5 by running the flash driver software 8th based on an access request to the flash memory 6 from the application software 9 ,

The RAM 4 is a volatile memory, one by the CPU 2 used workspace. The RAM 4 provides a temporary function to remove the flash memory 6 read data and in the flash memory 6 to keep writing data.

The flash control 5 performs a write process, a read process, an erase process and the like to transfer the data to and / or from the flash memory 6 based on an instruction from the CPU 2 to write, read and delete.

The flash memory 6 is a non-volatile memory, one from the CPU 2 has used memory area. The memory area of the flash memory 6 includes a variety of blocks 10 , and each of the blocks 10 serves as a unit for deletion.

The flash memory 6 stores data by writing a bit value of "0" or "1" into a cell. As in 2 shown, the data is stored in memory 6 written in a unit of "words" that are several bytes of the memory area.

On the other hand, the data from the flash memory 6 , ie from the memory area, in a unit of blocks 10 , which are larger units than words, deleted. That is, the block 10 can have a size that ranges from several tens of bytes to several kilobytes.

That is, data writing is performed in units of words (ie, word by word), and data erasing is performed in units of blocks (ie, block by block).

A state of the memory area after erasing data is referred to as "empty", and a memory area in an empty state is referred to as an "empty area".

Since the data is not writable into a memory area already described (i.e., overwriting the data already written to the memory area is not allowed), the data is written to the empty area. In other words, the empty area is a storage area in a first state, or in a pre-write state, before the data is written there. Thus, when a process of writing data in an empty area (ie, in the memory area in the first state) is performed, the memory area is converted to a second state or switched to a post-write state after the data there have been written.

In particular, the flash memory remains 6 after deleting the data, in the first state, ie, remaining in an indeterminable state (ie, "NON-DET" in FIG 3 ) in which the bit value of the memory is set as neither "0" nor "1", and after writing data in the flash memory remaining in the first state 6 , the flash memory turns off 6 in the second state, or a particular state in which the bit value is set as either "0" or "1".

As in 3 is shown by means of a command called "empty check" detectable whether a particular memory area is an empty area. The blank check is performed on a cell.

When a cell is determined to be in the first state by the empty check (ie, when a memory area is detected to be an empty area), any of the bit values "0" or "1" may be read out, but an actual read-out of the two bit values "0" or "1" can not be determined.

When a cell is determined by the blank check to be in the second state (ie, if a memory area is not determined to be an empty area: "NOT EMPTY" in 3 ), a bit value of either "0" or "1" can be read out therefrom.

[1-2. Writing process]

The format of the memory in the flash memory 6 stored data is related to 4 described. The data stored in the storage area is in an ordered combination of a header 12 , a management part 13 and a data part 14 organized, using a combination thereof (ie the three parts 12 to 14 ) serves as a unit for data storage. The unit of such a combination of the parts described above may also be used as a combination unit 15 be designated. That is, the combination unit 15 serves as a unit for data storage, and a plurality of pieces of data are stored in the storage area as successive combining units 15 stored in the memory area starting from the head of the memory area.

As in 5 for example, stores a first region 200 which is a specific block 10 under the memory areas of the flash memory 6 is, a plurality of data pieces as multiple combination units 15 , Note that, in the drawings, the headboard 12 may be referred to as "S", a flag described below may be referred to as "F", and an identifier also described below may be referred to as "ID".

The through the data part 14 stored data may include (i) the identifier for identifying one of the plurality of data types and (ii) a data value representing a value of the data of the specified identifier.

The identifier may be at a / a head of the data part 14 stored / written and can specify a name of a variable.

The data value can be a value of the variable.

The data length of the identifier and the data length of the data value may each be any length. That is, both the identifier and the data value may have any data length.

The headboard 12 is a head of unity combination 15 , which serves as a "header" and has a one-word length. This area is always in the first state, ie an empty area.

Since two or more pieces of data are stored by two or more combination units 15 consecutively, ie, stored in series, is a location of the stored data by each of the headers 12 identified.

The management part 13 is an area for storing a flag that shows whether the data part 14 stored data is valid or invalid, and the management part 13 has a one-word length.

If the management part 13 is an empty area, ie is in the first state, the flag in the management part shows 13 that the data is valid. If the management part 13 is in the second state, the flag in the management part shows 13 that the data is invalid. In the following description, data that is valid may simply be referred to as "valid data", and data that is invalid may simply be referred to as "invalid data".

If the data is valid, the data value of the valid data is the latest among the data values having the same identifier. If the data is invalid, the data value of the invalid data is not the latest value among the data values having the same identifier.

That is, even if there are many data values having the same identifier, basically only one data value has the flag showing that the data value is valid. Further, by switching the data to either have a valid / invalid state, i. H. by changing / switching the flag to either the first state or the second state, the data having a specific identifier is updated.

Next, the writing process that transfers data to the first region 200 the memory area of the flash memory 6 writes with reference to 6 described.

The writing process is started when the CPU 2 receives a write request for writing write target data (ie, data to be written).

In step 21 (ie, S21), the CPU performs 2 a process, ie an empty check, starting from the head of the first region 200 through and detects an empty area. If an empty area having a one-word length is detected, the process proceeds to step 22.

In step 22, the CPU performs 2 a process that determines whether the area detected in step 21 has the data. That is, in particular, it determines whether the area detected in step 21 as the header 12 a combination unit 15 serves any data in the data part 14 Has. In other words, the CPU considers 2 the detected one-word area as a first area of a combination unit 15 and considers the next (ie the second) one-word area as the management part 13 and considers the next (ie the third) one-word area as the head of the data part 14 to determine if there is any data in this combination unit 15 gives.

In particular, the CPU performs 2 an empty check for the third one-word range. Since the data already in the head of the data part 14 are written when the third one-word area is in the second state, the CPU provides 2 notice that a combination unit 15 indicative of the area detected in step 21 as the header 12 has, the data has.

Since the writing in the head of the data part 14 has not yet been performed when the third one word area is in the first state, ie, an empty area, sets the CPU 2 notice that a combination unit 15 indicative of the area detected in step 21 as the header 12 in such a case does not have any data, that is, when the third one-word area is in the first state.

A combination unit 15 indicative of the empty area detected in step 21 as the header 12 has no data, meaning that a "writable" empty area has been found. In other words, the combination unit 15 the last combination unit 15 at one end of successive memories of the combining units 15 (ie, at one end of a series of combination units 15 ), starting from the head of the first region 200 have been written.

If an affirmative determination has been made in step 22, the process proceeds to step 23.

In step 23, the CPU performs 2 a process that determines whether the data determined to exist in step 22 is valid data.

In particular, the CPU performs 2 performs a process that determines whether the data found in step 22 is valid data by performing an empty check for the second one-word area before the third one-word area processed in step 22 ,

When the second one-word area, ie flag, is determined to be in the first state, the CPU stops 2 determines that the data determined to exist in step 22 is valid data.

On the other hand, if the second one-word area, ie the flag, is determined to be in the second state, the CPU stops 2 determines that the data found to exist in step 22 is invalid data.

If a negative determination is made in step 23, the process returns to step 21.

In step 21, the CPU performs 2 a process that detects an empty area, which is the header 12 the next combination unit 15 serves as the next on the combination unit 15 follows that the detected in the previous step 21 header 12 Has.

If an affirmative determination is made in step 23, the process proceeds to step 24.

In step 24, the CPU performs 2 a process that determines if the identifier of the combination unit 15 which has been determined in step 23 to have the valid data which is the same identifier as the identifier of the write target data.

In particular, the CPU performs 2 a process that determines the identifier based on the bit value written in the area after the third one-word area, subsequent to the second one-word area processed in step 23.

If a negative determination is made in step 24, the process returns to step 21.

In step 21, the CPU performs 2 , just as in the negative determination process in step 23, a process detecting an empty area other than the header 12 the next combination unit 15 serving the combination unit detected in the previous step 21 15 next follows.

If an affirmative determination is made in step 24, the process proceeds to step 25.

In step 25, the CPU performs 2 a data writing process.

The concrete content of the data writing process will be related to 7 described.

In step 31 (ie, S31), the CPU performs 2 a process which determines if there is any writable area, ie the empty area, in which the write destination data from the combination unit 15 are writable.

If an affirmative determination is made in step 31, the process proceeds to step 32.

In step 32, the CPU performs 2 the data writing process which writes the writing target data, ie, the identifier and the data, into the blank areas starting at the third one-word area of the blank area. That is, placing the two empty areas after the last combination unit 15 at one end of a series of successive combination units- 15 Stores starting from the head of the first region 200 writing the write target data in the third one-word area, towards the subsequent empty areas.

The situation may be clearer with respect to 8th be understood, which is a state of the first region 200 shows after the process of step 32 for the in 5 shown first region 200 has been carried out.

As in 8th shown, the CPU writes 2 the write target data by the header 12 and the management part 13 in empty areas 51 and 52 , ie in a two-word length range, and written by the data part 14 in an area 53 which starts in the third one-word area and extends behind it, all of which are a combination unit 15 form a data write.

As the management part 13 the written combination unit 15 the empty area 52 is, the write target data is written as valid data. Further, by using the write target data as a combination unit 15 to a position immediately after that in the first region 200 stored last combination unit 15 be written, the variety of combination units 15 as successive combination units 15 saved.

After step 32, the CPU ends 2 the data writing process, and the process proceeds to step 26.

However, if a negative determination is made in step 31, the process proceeds to step 33.

In step 33, the CPU performs 2 a process that passes through the data part 14 stored valid data in the RAM 4 guaranteed. An example of saving valid data is in 9 (A) to (C) shown.

As in 9 (A) shown, if there is no writable area in which the write destination data in the first region 200 can be written, combination units 61 . 62 . 63 each having a flag in the first state, their valid data in the data part 14 in the RAM 4 as shown by an arrow A1.

In step 34, the CPU performs 2 a process by, that in the first region 200 saved data already saved in step 33 have been. As in 9 (B) As shown, the area after erasure changes to an empty area that is in the first state.

In step 35, following step 34, the CPU performs 2 perform a process that transfers the valid data saved in step 33 to the first region (s) 200 at which the deletion of the data has been performed in step 34, returns / restores. For example, an arrow indicated by an arrow A2 in FIG 9 (A) / (B) shown process performed.

In step 36, the CPU writes 2 the write target data, ie, the identifier and the data value, starting at the third one-word area into the empty areas, passing the two empty areas after the last combination unit 15 at one end of a successive storage of the combining units 15 in series starting from the head of the first region 200 left blank. That is, as in 9 (C) As shown, the write target data becomes a combination unit 66 stored in the empty area.

After step 36, the CPU ends 2 the data writing process, and the process proceeds to step 26.

In step 26, an invalidation process is performed which includes the data of the combination unit 15 which has the same identifier as confirmed in step 24, invalidated. An example of step 26 is in 10 shown.

10 FIG. 13 is an illustration of a situation after performing a process from step 26 in FIG 8th shown first region 200 , As in 10 shown, the CPU performs 2 a invalidation process that invalidates the data by placing it in a flag area 54 a combination unit 15 that has the same identifier as the write target data writes ("DECLARE DATA OF THE SAME ID INVALID" in S26 of FIG 6 ). In this way, the most recent data is converted to old data at a time immediately after writing.

Thus, the writing target data is written as the latest data from the process in step 25 and the process in step 26, and the data of the combining unit 15 which have the same identifier as the write target data are converted into old data, and thereby an update of the data is completed. The CPU 2 ends the writing process after step 26.

If a negative determination is made in step 22, the process proceeds to step 27.

In step 27, the CPU performs 2 the data writing process exactly as in step 25. That is, a process of step 32 or a process of steps 33-36 is performed. After step 32 or step 36, the CPU ends 2 the data writing process and ends the writing process.

[1-3. Reading process]

The reading process that takes place in the first region 200 the memory area of the flash memory 6 stored data is read with reference to 11 described. The reading process is started when the CPU 2 a read request receives read destination data (ie data to be read).

In step 71 (ie, S71), the CPU performs 2 a process, ie an empty check, starting from the head of the first region 200 through and detects an empty area. If an empty area having a one-word length is detected, the process proceeds to step 72.

In step 72, the CPU performs 2 a process that determines whether the area detected in step 71 has the data. That is, in particular, it is determined whether the one-word area detected in step 71 is designated as the header 12 a combination unit 15 serves. This can also be understood as a situation in which the CPU 2 the detected one-word area as a first area in a combination unit 15 and the next (ie second) one-word area as the management part 13 and the next (ie the third) one-word area as the head of the data part 14 To determine if there is any data in this combination unit 15 gives.

In particular, the CPU performs 2 an empty check on the third one-word area. When the third one-word area is in the second state, the CPU stops 2 notice that a combination unit 15 indicative of the area detected in step 71 as the header 12 has, the data has.

On the other hand, if the third one-word area is in the first state, ie, is an empty area, the CPU stops 2 notice that a combination unit 15 , which as the headboard 12 has the area detected in step 71, has no data.

Note that if a combination unit 15 indicative of the empty area detected in step 71 as the header 12 has no data, that is, a "writable" empty area has been found, that is, the combination unit determined 15 the last combination unit 15 at one end of a successive storage of the combining units 15 written starting from the head of the first region 200 is.

If an affirmative determination is made in step 72, the process proceeds to step 73.

In step 73, the CPU performs 2 a process that determines whether the data determined to exist in step 72 is valid data.

In particular, the CPU performs 2 perform a process that determines if the data obtained in step 72 is valid data by performing an empty check on the second one-word area before the third one-word area processed in step 72 ,

When the second one-word area, ie the flag, is in the first state, the CPU stops 2 determines that the data obtained in step 72 is valid data.

On the other hand, if the second one-word area, ie the flag, is in the second state, the CPU stops 2 determines that the data obtained in step 72 is invalid data.

If a negative determination is made in step 73, the process returns to step 71.

In step 71, the CPU performs 2 a process that detects an empty area, which is the header 12 the next combination unit 15 serves next to the combination unit 15 follows the head part detected in the previous step 71 12 Has.

If an affirmative determination is made in step 73, the process proceeds to step 74.

In step 74, the CPU performs 2 a process that determines if the identifier of a combination unit 15 having the valid data obtained in step 73 is an identifier of the read target data.

In particular, the CPU performs 2 determines a process written based on the bit values written in the third and subsequent one-word areas, that is, in the area after the second one-word area processed in step 73, whether the identifier is the one for the read target data.

If a negative determination is made in step 74, the process returns to step 71.

In step 71, which is similar to a negative determination in step 73, the CPU performs 2 a process that detects a blank area that is the header 12 the next combination unit 15 serves next to the combination unit 15 which follows the head part detected in the previous step 71 12 Has.

If an affirmative determination is made in step 74, the process proceeds to step 75.

In step 75, the CPU performs 2 a process that takes place in the data part 14 the combination unit 15 which has the identifier which has been determined in step 74 as the identifier of the read target data, reads data stored.

The CPU 2 ends the reading process after step 75.

If a negative determination is made in step 72, the CPU stops 2 determines that there is no read target data and ends the reading process.

[1-4. effects]

• (1a) Die CPU 2 des ersten Ausführungsbeispiels führt einen Prozess durch, welcher Daten so in den Speicherbereich schreibt, dass die Vielzahl von Kombinationseinheiten 15 aufeinanderfolgend beginnend von dem Kopf der ersten Region 200 gespeichert werden. Das heißt, die CPU 2 führt einen Prozess durch, der eine Vielzahl von Datenstücken eines nach dem anderen in den Speicherbereich mittels Teilen des Speicherbereichs in Abschnitte (d. h. in eine Vielzahl von Speicherbereiche) unter Verwendung des leeren Bereichs schreibt.

Based on the first embodiment described in detail above, the following effects can be realized.

• (1a) The CPU 2 of the first embodiment performs a process which writes data into the memory area such that the plurality of combination units 15 successively starting from the head of the first region 200 get saved. That is, the CPU 2 performs a process that writes a plurality of pieces of data into the memory area one by one by dividing the memory area into sections (ie, into a plurality of memory areas) using the blank area.

• (1b) Die CPU 2 des ersten Ausführungsbeispiels führt einen Prozess durch, der einen leeren Bereich in der ersten Region 200 detektiert. Deshalb muss eine Adresse einer Kopfposition der Daten nicht zum Lesen oder Schreiben der Daten spezifiziert werden. Das heißt, eine Kopfposition der Daten, oder eine Speicherposition der Daten in dem Speicherbereich, ist durch Detektieren eines leeren Bereichs identifizierbar. Somit werden, basierend auf dem detektierten leeren Bereich, der eine Datenspeicherposition anzeigt, die Lesezieldaten gelesen.
• (1c) Die CPU 2 des ersten Ausführungsbeispiels führt einen Prozess durch, welcher einen Identifizierer in einen Kopf der Daten schreibt. Ferner führt die CPU 2 einen Prozess durch, der die Lesezieldaten basierend auf dem Identifizierer in dem Kopf der Daten liest.

Therefore, the disadvantage is to have many unused areas in the memory area that depend on the data length, which is caused by a memory area pre-dividing action and an information managing device implementing such a measure. That is, the information management apparatus according to the first embodiment of the present invention prevents or limits such unused areas, thereby improving the memory usage efficiency.

• (1b) The CPU 2 of the first embodiment performs a process that includes an empty area in the first region 200 detected. Therefore, an address of a head position of the data need not be specified for reading or writing the data. That is, a head position of the data, or a storage position of the data in the storage area, is identifiable by detecting an empty area. Thus, based on the detected empty area, the indicates a data storage position that read read target data.
• (1c) The CPU 2 of the first embodiment performs a process which writes an identifier in a header of the data. Furthermore, the CPU performs 2 a process that reads the read target data based on the identifier in the header of the data.

• (1d) Die CPU 2 des ersten Ausführungsbeispiels führt einen Prozess durch, der die Schreibzieldaten als eine Kombinationseinheit 15 an eine Endposition der letzten Kombinationseinheit 15 an ein Ende/einen Schwanz einer Reihe von Kombinationseinheiten 15, die aufeinanderfolgend beginnend von dem Kopf der ersten Region 200 memoriert worden sind, auf eine „anhängende“ Weise schreibt. Somit können, ungeachtet der Datenlänge, die Schreibzieldaten an eine Endposition hinter der letzten Kombinationseinheit 15 geschrieben werden.
• (1e) Die CPU 2 des ersten Ausführungsbeispiels führt einen Ungültigerklärungsprozess durch, der gültige Schreibzieldaten für ungültig erklärt, wenn der gleiche, d. h. gültige, Identifizierer in zwei unterschiedlichen Datenstücken verwendet wird. Das heißt, indem zwei Ein-Wort-Leerbereiche vor die, d. h. als ein Kopf von den, Schreibzieldaten geschrieben wird, werden die gültigen Daten für ungültig erklärt.

Therefore, data having a specific identifier can be written in the memory area, and data having a specific identifier can be read out from the memory area. Thus, many kinds of data can be memorably stored and recognized.

• (1d) The CPU 2 of the first embodiment performs a process that the write target data as a combination unit 15 to an end position of the last combination unit 15 at one end / tail of a series of combination units 15 which are successively starting from the head of the first region 200 have been memorized, in a "pending" way. Thus, regardless of the data length, the write target data may be at an end position after the last combination unit 15 to be written.
• (1e) The CPU 2 of the first embodiment performs an invalidation process invalidating valid write target data when the same, ie, valid, identifier is used in two different pieces of data. That is, by writing two one-word void areas before, that is, as a head of, the write destination data, the valid data is invalidated.

Therefore, the newest data is converted to old data immediately after the write target data has been written as the newest data. Thus, without deleting the old data, an update of the data can be performed.

• (1f) Wenn die CPU 2 des ersten Ausführungsbeispiels die Schreibzieldaten nicht als eine Kombinationseinheit 15 in die leeren Bereiche in der ersten Region 200 schreiben kann, d. h. wenn die beschreibbaren Bereiche in der ersten Region 200 ungenügend sind, sichert die CPU 2 die gültigen Daten in dem RAM 4 und löscht all die Daten in der ersten Region 200.

Furthermore, the CPU performs 2 of the first embodiment, a process that determines whether data is valid or invalid, and determines the identifier of the data. Therefore, an update state of the data is recognized for each of the data states. Thus, the latest read target data is detected and read.

• (1f) If the CPU 2 of the first embodiment, the write target data not as a combination unit 15 into the empty areas in the first region 200 can write, ie if the writable areas in the first region 200 are insufficient, the CPU secures 2 the valid data in the RAM 4 and deletes all the data in the first region 200 ,

That's why, even if the first region 200 of the memory area is completely occupied by the data, ie even if the first region 200 is filled with the data "to the neck", writable areas in the memory area of the flash memory 6 reservable to allow the writing of data in the memory area.

In the first embodiment, the flash memory 6 be referred to as a non-volatile memory. The CPU 2 For example, if performing steps S32 and S36, it may be referred to as a "writer" and the CPU 2 For example, when performing steps S71-S75, it may be referred to as a reader.

If the CPU 2 performing steps S21 and S22, it may be referred to as an empty detector, the CPU 2 For example, if performing steps S23 and S24, it may be referred to as a data detector, and the CPU 2 For example, if it performs step S26, it may be referred to as an invalidation processor. The management part 13 may be referred to as a flag area.

The RAM 4 can be referred to as a separate store. The CPU 2 that performs steps S33-S35 may be referred to as a data save.

[2nd Second embodiment]

[Difference from the first embodiment]

Since the configuration of the second embodiment of the present invention is substantially the same as that of the first embodiment, the following description focuses on differences of the second embodiment with respect to the first embodiment. The same reference numerals as in the first embodiment represent the same configuration or component, and thus their respective descriptions have been omitted for the sake of brevity.

According to the above-mentioned first embodiment, the CPU performs 2 , in the writing process, a process by, that in the first region 200 stored valid data in the RAM 4 guaranteed.

In the second embodiment, the CPU performs 2 however, a different process by that in the first region 200 stored valid data in a second region 300 that in a different block 10 is, secures.

The second region 300 is one of the multitude of blocks 10 in the memory area of the flash memory 6 and is one to the block 10 who is the first region 200 has, different block 10 ,

[2-2. Writing process]

The one from the CPU 2 The writing process performed in the second embodiment is described in further detail below. The CPU 2 In the second embodiment, the writing process leads to one in the flowcharts of 12 and 13 shown in detail, the flowcharts in 6 and 7 replace the first embodiment.

Since a process of step 81-step 84 in FIG 12 the same is like a process from step 21-step 24 in 6 , the description of this part is omitted.

If an affirmative determination is made in step 84 (i.e., S84), the process proceeds to step 85.

In step 85, the CPU performs 2 a data writing process. The concrete content of the data writing process will be related to 13 described.

In step 91 (ie, S91), the CPU performs 2 a process which determines whether there is any writable area, ie, an empty area, in which the writing destination data is given by the combining unit 15 are writable. If an affirmative determination is made in step 91, the process proceeds to step 92.

In step 92, the CPU performs 2 a data writing process which writes the writing target data, ie, the identifier and the data, into the empty areas starting at the third one-word empty area, that is, the two empty areas starting from the last combining unit 15 at one end of a successive storage of combination units 15 in series starting from the head of the first region 200 stands to be kept blank.

After step 92, the CPU ends 2 the data writing process, and the process proceeds to step 86.

On the other hand, if a negative determination is made in step 91, the process proceeds to step 93.

In step 93, the CPU performs 2 a process that takes place in the data part 14 stored valid data in the second region 300 saves, ie performs a data movement process. An example of such a process is in 14 (A) to (F) shown.

As in 14 (A) when there is no writable area in which the writing destination data is writable, in the first region 200 There are in the data part 14 ie in combination units 101 . 102 . 103 , each having the flag in the first state, stored valid data in the second region 300 secured as shown by an arrow B1.

The second region 300 is one before performing the data movement process as described in 14 (B) shown is empty area.

In step 94, the CPU performs 2 a data writing process which writes the writing target data, ie, the identifier and the data value, into the blank areas starting from the third one-word area of the blank areas, ie, the two blank areas starting from the last combining unit 15 at one end of a successive storage of the combination units 15 in series from the head of the second region 300 stands to be kept blank. That is, as in 14 (D) As shown, the writing target data becomes the second region 300 as a combination unit 105 written / stored.

In the subsequent step 95, the CPU performs 2 an invalidation process by, that in the first region 200 deletes stored data. As in 14 (C) and (E) are shown in the first region 200 memorized data deleted.

After step 95, the CPU ends 2 the data writing process, and the process proceeds to step 86.

In step 86, the CPU performs 2 a process by which the data of the combination unit 15 having the identifier that has been confirmed in step 84, invalidated. The CPU 2 ends the writing process after step 86.

If a negative determination is made in step 82, the process proceeds to step 87.

In step 87, the CPU performs 2 a data writing process, just like step 85. That is, in step 87, a process of step 92 or a process of steps 93-95.

After step 92 or step 95, the CPU ends 2 the data writing process and ends the writing process.

[2-3. effects]

• (2a) Die CPU 2 des zweiten Ausführungsbeispiels sichert die Daten in der zweiten Region 300, wenn es ungenügende leere Bereiche, d. h. beschreibbare Bereiche, gibt, in welche die Schreibzieldaten durch die Kombinationseinheit 15 schreibbar sind. In solch einem Fall werden, weil die zweite Region 300 ein als ein nichtflüchtiger Speicher implementierter Speicherbereich ist, selbst wenn eine Energieversorgung der Informationsmanagementvorrichtung 1 während des Löschens der Daten unterbrochen wird, die Daten in der zweiten Region 300 beibehalten, d. h. unbeschädigt gehalten.

According to the second embodiment described above in detail, in addition to the above-mentioned effects (1a) - (1e) of the first embodiment, the following effects are also obtained.

• (2a) The CPU 2 of the second embodiment, the data secures in the second region 300 when there are insufficient blank areas, ie writeable areas, into which the write target data is given by the combination unit 15 are writable. In such a case, because the second region 300 is a memory area implemented as a non-volatile memory, even if a power supply of the information management device 1 while deleting the data is interrupted, the data in the second region 300 maintained, ie kept undamaged.

In the second embodiment, the CPU 2 performing steps S92 and S94 are referred to as a writer, the CPU 2 performing steps S81 and S82 may be referred to as an empty detector, the CPU 2 performing steps S83 and S84 may be referred to as a data detector, the CPU 2 that performs step S86 may be referred to as an invalidation processor, and the CPU 2 that performs steps S93 and S95 may be referred to as a data mover.

Other Embodiments

• (3a) Obgleich die Kombinationseinheit 15 in den obigen Ausführungsbeispielen organisiert ist, den Managementteil 13 zu umfassen, muss eine Kombinationseinheit keinen Managementteil umfassen. Das heißt, eine Kombinationseinheit kann organisiert sein, nur einen Kopfteil und einen Datenteil zu haben.

The above-described embodiments of the present invention may be further modified to have various configurations without being limited to the above.

• (3a) Although the combination unit 15 is organized in the above embodiments, the management part 13 a combination unit does not have to comprise a management part. That is, a combination unit may be organized to have only a header and a data part.

A CPU may perform a data writing process that writes the writing target data into the blank areas starting at the second one-word area of the blank area by placing a blank area starting from the last combining unit at one end of successively storing the combining units in series Retains blank starting from the head of the block. In such a way, even if a combination unit is organized to include only a header and a data part, data can be suitably written in the memory area as a series of combination units sequentially stored therein.

• (3b) Obgleich die in dem Datenteil 14 gespeicherten Daten in dem oben erwähnten Ausführungsbeispiel als ein Identifizierer und ein Datenwert gezeigt sind, sind die Daten in dem Datenteil 14 nicht notwendigerweise auf solch eine Konfiguration beschränkt. Das heißt, die Daten in dem Datenteil können nur ein Datenwert sein.
• (3c) Obgleich eine Schreibstartposition von Schreibzieldaten in den oben erwähnten Ausführungsbeispielen durch Durchführen eines Prozesses identifiziert wird, der drei leere Bereiche in einer Reihe, d. h. den ersten bis dritten leeren Bereich in Reihe, durch eine Detektion beginnend von dem Kopf der ersten oder zweiten Region 200 oder 300 detektiert, kann die Schreibstartposition durch andere Verfahren detektiert werden. Das heißt, die CPU kann einen Prozess durchführen, der zumindest drei leere Bereiche in einer Reihe durch eine an dem Kopf eines Blocks beginnende Detektion detektiert, um eine Schreibstartposition von Schreibzieldaten zu identifizieren.
• (3d) Obgleich der Kopfteil 12 und der Managementteil 13 in den oben erwähnten Ausführungsbeispielen jeweils als ein Ein-Wort-Bereich gezeigt sind, sind der Kopfteil 12 und der Managementteil 13 nicht notwendigerweise auf solch eine Konfiguration beschränkt. Das heißt, ein Kopfteil kann zwei Wortlängen oder länger sein, und ein Managementteil kann zwei Wortlängen oder länger sein.

Further, when the read target data is read, the CPU reads the last written data as valid data based on a determination that the data stored at a position closer to one end of the row of combiner units in the first region is valid. In such a way, even if a combination unit is organized to include only a header and a data part, the latest read target data can be read.

• (3b) Although those in the data part 14 stored data in the above-mentioned embodiment are shown as an identifier and a data value, the data in the data part 14 not necessarily limited to such a configuration. That is, the data in the data part can only be one data value.
• (3c) Although a write start position of write target data in the above-mentioned embodiments is identified by performing a process, the three blank regions in a row, ie, the first to third empty regions in series, are detected by detection from the head of the first or second region 200 or 300 detected, the write start position can be detected by other methods. That is, the CPU may perform a process that detects at least three blank areas in a row by detection starting at the head of a block to identify a write start position of write target data.
• (3d) Although the headboard 12 and the management part 13 In the above-mentioned embodiments, each shown as a one-word area are the header 12 and the management part 13 not necessarily limited to such a configuration. That is, a header may be two word lengths or longer, and a management part may be two word lengths or longer.

Further, in the above-mentioned embodiment, consecutive blank areas are detected as a series of at least three "one-word" unit areas, or as empty areas of a first unit number (ie, successive empty areas of at least a first unit number) a detection begins at the head of the storage area. However, the consecutive empty areas may be detected as a series of four or more one-word areas.

• (3e) Obgleich die CPU 2 in dem oben erwähnten ersten Ausführungsbeispiel einen Sicherungsprozess durchführt, der die in der ersten Region 200 gespeicherten gültigen Daten in dem RAM 4 speichert, ist das Sicherungsziel nicht auf den RAM 4 beschränkt. Das heißt, das Sicherungsziel kann ein anderer flüchtiger Speicher als der RAM 4 sein.
• (3f) Obgleich ein nicht bestimmbarer Zustand, in welchem der Bitwert nicht als „0“ oder „1“ bestimmt ist, als der erste Zustand definiert ist, und ein bestimmter Zustand, in welchem der Bitwert entweder als „0“ oder „1“ bestimmt ist, als der zweite Zustand definiert ist, ist die Definition dieser Zustände nicht auf das Obige beschränkt. Der erste Zustand kann ein Vor-Schreib-Zustand sein, d. h. ein Zustand vor dem Schreiben von Daten, und der zweite Zustand kann ein Nach-Schreib-Zustand sein, d. h. ein Zustand nach dem Schreiben von Daten.
• (3g) Die Informationsmanagementvorrichtung 1 des oben erwähnten

Further, in the above-mentioned embodiment, the data is written in successive blank areas, which are written as a series of two one-word unit areas or as empty ones Areas of a second unit number are organized (ie, written in the detected consecutive empty areas in series of a second unit number). However, the data may be written in the successive empty areas organized as a series of empty areas from the second unit number smaller than the first unit number. The second unit number may be at least one word length.

• (3e) Although the CPU 2 in the above-mentioned first embodiment, performs a backup process similar to that in the first region 200 stored valid data in the RAM 4 saves, the backup destination is not on the RAM 4 limited. That is, the backup destination may be a different volatile memory than the RAM 4 be.
• (3f) Although an indeterminable state in which the bit value is not designated as "0" or "1" is defined as the first state, and a certain state in which the bit value is designated as either "0" or "1". is determined as the second state is defined, the definition of these states is not limited to the above. The first state may be a pre-write state, ie, a state prior to writing data, and the second state may be an after-write state, ie, a state after writing data.
• (3g) The information management device 1 of the above

Embodiment may be arranged and used in vehicles. For example, an information management device may be used as a device that updates a memory of values learned in a vehicle control such as an engine control or the like.

For example, an information managing device may also be used as a device storing freeze frame data or the like including vehicle use state data at the time of failure to diagnose the vehicle.

• (3h) Zwei oder mehr, d. h. eine Vielzahl von, durch eine Komponente in den obigen Ausführungsbeispielen implementierte Funktionen können durch eine Vielzahl von Komponenten durchgeführt werden, oder eine durch eine Vielzahl von Komponenten in den obigen Ausführungsbeispielen implementierte Funktion kann nur durch eine Komponente implementiert werden. Eine „Vice versa“-Funktions-Implementierungsmaßnahme kann auch angewendet werden.

The information managing apparatus of the present invention is different from an information managing apparatus that pre-divides the storage area into plural sections for writing the data, thereby preventing unused areas in the storage area or causing less unused areas in the storage area even by writing the data with different data lengths. Therefore, the information management apparatus of the present invention can be suitable and effective for storing vehicle usage status data, which typically has a large data volume and different data lengths.

• (3h) Two or more, ie, a plurality of functions implemented by a component in the above embodiments may be performed by a plurality of components, or a function implemented by a plurality of components in the above embodiments may be implemented by only one component , A "vice versa" functional implementation action can also be applied.

Further, part of the above embodiment may be omitted, and / or a part of one embodiment may be added to the other embodiment or replaced with the other embodiment.

• (3i) Die vorliegende Erfindung kann, abgesehen von der oben beschriebenen CPU 2, auch als ein Informationsmanagementsystem, welche die CPU 2 als eine Komponente verwendet, oder ein Informationsmanagementprogramm zum Steuern eines Computers, um den oben erwähnten Schreib-/Leseprozess durchzuführen, oder ein nichtflüchtiges, materielles Speichermedium, welches solch ein Informationsmanagementprogramm speichert, oder ein Informationsmanagementverfahren oder Ähnliches verwirklicht werden.

Note that all modes of the technical idea described by the wording in the claims serve as the embodiment and are within the scope of the present invention.

• (3i) The present invention can be other than the CPU described above 2 Also called an information management system, which is the CPU 2 used as a component, or an information management program for controlling a computer to perform the above-mentioned read / write process, or a nonvolatile material storage medium storing such an information management program or an information management method or the like.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• JP 05-119777 H [0006]

Claims (7)

An information management device comprising: a non-volatile memory ( 6 ) having a memory area in which data is writable and from which data is erasable; and a scribe ( 2 , S32, S36, S92, S94) configured to write data to an empty area in the memory area of the nonvolatile memory, wherein clearing data from the memory area switches the memory area from a second state to a first state the first state is a pre-write state of the memory area, writing data to the memory area switches the memory area from the first state to the second state, the second state being an after-write state of the memory area, and wherein the writer is configured is to divide the storage area by means of the empty area to write a plurality of data pieces of data in sequence into the storage area. An information management apparatus according to claim 1 further comprising: a reader ( 2 , S71-S75) configured to read read target data in the memory area, the reader being further configured to read the read target data by detecting the empty area in the memory area ( 2 , S71). The information management apparatus of claim 2, wherein the writer is further configured to write an identifier as a header of the data to identify the data, and wherein the reader is further configured to read the read target data based on the identifier written as the head of the data ( 2 , S74). Information management device according to one of claims 1 to 3, further comprising: an empty detector ( 2 , S21, S22, S81, S82) configured to detect the empty area in the storage area as successive empty areas in series of at least a first unit number, the detection of the empty area beginning at a header of the storage area and subsequent parts of the memory area proceeds in order, and wherein the writer is further configured to write data in the blank area by using a detected location of the consecutive blank areas as a data write start position and writing data into the detected consecutive blank areas in series from a second unit number wherein the second unit number is smaller than the first unit number. An information management apparatus according to claim 4 further comprising: a data detector ( 2 , S23, S24, S83, S84) configured to detect valid data invalidated by writing of writing target data; and an invalidation processor ( 2 , S26, S86) configured to invalidate the valid data when the data detector detects the valid data, wherein a part of the successive empty areas of the second unit number counts as a flag area (Fig. 13 ) is used to show a validity of successive data written in a part immediately adjacent to the flag area, wherein the first state of the flag area shows that the subsequent data is valid, and the second state of the flag area shows the subsequent data is invalid, and the invalidation processor invalidates the valid data by assigning a value to the flag immediately preceding the valid data. An information management apparatus according to claim 5 further comprising: a data store ( 2 , S33-S35), which is designed to save the valid data in the memory area by (i) storing the valid data in a separate memory ( 4 ), one of the nonvolatile memory ( 6 ) is separate memory, and (ii) the secure valid data from the separate memory ( 4 ) is restored back to the memory area after the data has been erased from the memory area, if the memory area has no writable area to write the write target data, the writer is configured to write the write destination data into the memory area ( 2 , S36) in which the valid data is restored by the data backuper. The information management apparatus of claim 5 further comprising: a data mover ( 2 , S93, S95), which is configured, (i) the valid data in a first region ( 200 ) of the memory area to a second region ( 300 ) of the memory area and (ii) the valid data from the first region ( 200 ) when the first region has no writable area in which the write destination data is writable, and the second region has a writable area in which the write destination data is writable, the recorder being further configured to write the write destination data to the second region write ( 2 , S94) into which the valid data has been moved by the data store.

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