DE102017203479A1 - Circuit arrangement for monitoring a state basis in a timer - Google Patents

Abstract

The invention relates to a circuit arrangement for monitoring a state basis, which is incremented or decremented by pulses and these pulses carry information about properties of a system, wherein the circuit arrangement comprises a memory in which the state of the state base is to be buffered periodically, and wherein at least one comparator provided configured to compare the state of the state base prior to the buffering stored in the memory with the state of the state basis after the buffering, and wherein the circuitry is adapted to detect an error based on the comparison.

Description

The invention relates to a circuit arrangement for monitoring a state basis in a timer and to a method for monitoring a state basis in a timer. The method and the circuit arrangement serve in particular to monitor the activity of the state basis, i. H. to check if the state base is active.

State of the art

To support a processing unit, such as a CPU (Central Processing Unit), for time and position related processes are called timers, d. H. Timer units, known. Such timer units can be designed as individual components or as peripheral components of the processing unit and thereby provide more or less important functions for signal recording and generation in dependence on one or more clocks.

According to the current state of the art, different architectures for the implementation of timer units are used in processing units, such as, for example, in microcontrollers.

In a known generic timer module, also referred to as GTM (Generic Timer Module), several state bases are included which may contain both time and angle information. Usually, these state bases are either counted by a clock or incremented by angle information pulses or decremented. These state bases are of central importance, since a great many events and thus also output signals are based on the comparison of data with these state bases and output signals are generated which possibly violate a security objective. In addition, incorrect inactivation of the condition base can lead to such serious results. The monitoring of the state bases is provided in the prior art only by software on the system CPU. Information about the inactivity of a time base might not be available until very late if the CPU is not overly burdened with such tasks.

As the state basis, a time base is particularly considered herein. A time base is to be understood as a device which specifies, among other things, the most precise possible time span. This can also be used to generate timestamps in continuous operations or to display the continuous time within a period of time.

• bei der TBU0: 0 oder +1,
• bei der TBU1,2: 0, +1 oder -1,

weil bei letzteren auch eine Rückwärtsrichtung möglich ist.Another method describes how to detect errors in a time or angle basis. This method is for monitoring a state basis that is incremented or decremented by pulses and that includes information about system characteristics. In this case, the state base is temporarily stored with a system clock, wherein the current state base is compared with the previously cached state basis and based on this comparison, an error is detected. The pipeline stage provided there is operated at the system clock. This makes it possible to compare the "old" value with the new value using additional hardware. The new time base value can deviate at most by the value 1 if the system clock SYS_CLK is the clock with the highest frequency in the system or at least in the cluster and the clock that leads to incrementing the time / angle base has no higher frequency. The deviation possibilities are:

• at the TBU0: 0 or +1,
• at the TBU1,2: 0, +1 or -1,

because in the latter also a reverse direction is possible.

However, an inactivity of a state basis can not be detected by this measure.

Disclosure of the invention

Against this background, a circuit arrangement according to claim 1 and a method according to claim 6 are presented. Embodiments emerge from the dependent claims and from the description.

With the described circuit arrangement and the presented method it is proposed to provide a further pipeline register which is operated with the clock of the relevant TBU channel. This is an inactivity to discover immediately.

The presented circuit arrangement serves to monitor a state basis, which is incremented or decremented by pulses and these pulses carry information about properties, in particular information about time, angle, position, quantity, temperature, pressure or other properties of a system.

In one embodiment, a time base is monitored, i. h, it is checked if it is active or inactive.

The state base can thus be incremented or decremented with an active edge of the pulses or with a clock that provides pulses become. This clock is typically also cached.

Further advantages and embodiments of the invention will become apparent from the description and the accompanying drawings.

It is understood that the features mentioned above and those yet to be explained below can be used not only in the respectively specified combination but also in other combinations or in isolation, without departing from the scope of the present invention.

list of figures

• 1 shows a block diagram of a time base unit.
• 2 shows in a block diagram an additional central pipeline stage of a time base unit.
• 3 shows a block diagram of an implementation possibility of a set flip-flop.
• 4 shows in a block diagram an additional configuration bit.

Embodiments of the invention

The invention is schematically illustrated by means of embodiments in the drawings and will be described in detail below with reference to the drawings.

1 shows in a block diagram a time base unit or TBU (Time Base Unit), which is used, for example. In a generic timer module or GTM (Generic Time Module) and in total with the reference numeral 10 is designated. The illustration shows a number of TBU channels 12 , in each of which a time base 14 as an example of a state basis and a controller 16 are provided. Furthermore, a register BASE_MARK 20, a register BASE_CAPTURE 22 and a control register TBU_CHEN 24 are provided.

The activity of the time base 14 may be disturbed by transient or permanent errors, if z. B. in the control register TBU_CHEN 24 an enable bit is wrong. It may either be mistakenly set wrong or corrupted by the above events. Also, an error in the derived signal or an error in the implementation in the corresponding circuit has the same effect. It is therefore extremely important to detect such errors promptly. It should be noted, however, that testing via the CPU is often not sufficient because no permanent test can take place. Although tests over a longer period are also possible, these are usually only plausibility checks. Such tests would have to be performed periodically by the CPU in the fault tolerance time interval.

It is therefore desirable to free the CPU from such burdens and to achieve a higher quality with the permanent test.

At the in 1 shown TBU 10 is used for the TBU_CH0 of the TS-CLK for incrementing: this is one of the clocks of CMU_CLK [x]. For this purpose, the corresponding clock is selected by a configuration register in the test unit. It is not the configuration of the TBU 10 because it may be disturbed. For an additional pipeline stage of TBU_CH0, the same clock is used, thereby obtaining a value TBU_alt, the cached value, which is compared to the value before the pipeline stage, TBU_neu. It is on this 2 directed.

2 In one embodiment of the circuitry for monitoring the state base, an additional central pipeline stage is shown 100 a time base unit with activity monitoring. In this pipeline stage 100 goes over a first entrance 102 CMU_CLKx or SUBJNCyc and via a second input 104 TBU_neu. At an exit 106 TBU_alt is output. In a comparator 110 a comparison is made: $$\text{TBU\_neu}=\text{TBU\_alt?}$$

If the comparison shows an equality of the two values, the state basis is inactive and there may be an error. In case of inequality, it can be concluded that the state basis is active.

An exit 112 gives a set signal to a flip-flop 114 , in the at another entrance 116 CMU_CLKx or SUB_INCyc is received and possibly outputs an error signal (error) 120.

It should be noted that all n bits of TBU_CH0 are in the pipeline stage 100 be received and compared. If both values are equal, then there is an inactivity of the corresponding state basis. Should this state base actually be active, then that is an error corresponding to the flip-flop 114 is stored and stored until it is actively reset by the user or by the system. Such a possibility of storing the error is in the Set FF 3 shown.

3 shows a flip flop 200 with an OR gate 202 , Signals are "set" 204, "reset" 206 and an output signal 208 , There is thus a feedback of the flip-flop output and an OR operation in front of the flip-flop input with the input signal.

The same method is used for the time or angle bases TBU_CH1 ... 3. There is provided a special additional pipeline stage for each of these time or angle bases, the clock at this pipeline stage being identical to the clock incrementing or decrementing the corresponding time base. The comparison then takes place as in 2 instead of and with equality there is an inactivity. This inactivity is an error if the corresponding TBU channel should actually be active.

The comparison can be done, for example, by means of a subtraction of the two values. This subtraction can be carried out, for example, with an adder. Other comparison methods are also conceivable, for example a bitwise comparison on the basis of the EX-OR (Exclusive-Or) function, which is also conceivable in addition to other possibilities.

It is possible to use corresponding control bits for each channel in a configuration register of the test circuit, which are set at the desired activity of the corresponding TBU channel and it is decided in dependence on these control bits in the circuitry whether the inactivity is an error. By ANDing the output of the comparator with the control bit, the setting of the error signal in the case of intentional inactivity is not set. It is important that this filter function does not use the normal enable bits in the control register of the TBU for the particular channel itself. In this case you would not be able to see that the inactivity was unintentional if the enable bit was assigned incorrectly. These enable bits are also simply stored, although for setting or resetting two bits of the control register are to be driven accordingly.

With an additional control bit in each case in a configuration register of the test unit, two independent errors would have to be present in order to mask unwanted inactivity. This is typically so unlikely that such a case can be neglected if additional checks for latent errors are made, at least at longer intervals.

4 shows in a block diagram an additional configuration bit K 250, with which the desired activity is set. The illustration also shows a comparator 252 , an AND member 254 and a flip flop 256 , which in case of error an error signal 260 outputs.

Claims (10)

Circuitry for monitoring a state basis which is incremented or decremented by pulses and which carries information about system characteristics, the circuitry comprising a memory in which the state of the state basis is to be periodically latched, and at least one comparator (10) is provided which is adapted to compare the state of the state basis before the buffer stored in the memory with the state of the state basis after the buffering, and wherein the circuitry is adapted to detect an error based on the comparison. Circuit arrangement according to Claim 1 which is adapted to latch at a first frequency corresponding to a second frequency used to increment or decrement the state basis. Circuit arrangement according to Claim 1 or 2 in which an additional control bit is provided in a register adapted to indicate whether the activity of the state base is intentional and that control bit prevents the storage of an error if the activity is not wanted. Circuit arrangement according to one of Claims 1 to 3 , which is adapted to make at least a comparison between the state of the state basis and the previously cached state of the state basis by means of subtraction. Circuit arrangement according to Claim 4 comprising an adder for performing the subtraction. A method for monitoring a state basis that is incremented or decremented by pulses, and that carries information about system characteristics, the state of the state basis being periodically cached, and the state of the state basis prior to caching being compared to the state after caching, and Comparing an error is detected. Method according to Claim 6 in which the state of the state basis is incremented or decremented with an active edge of the pulses Method according to Claim 6 in which the state of the state base is incremented or decremented with a clock that provides pulses and in which, with the active edge of the clock, the state of the state basis is periodically latched. Method according to one of Claims 6 to 8th in which a time base (14) is monitored. Method according to one of Claims 6 to 8th in which an angular base is monitored.

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