DE102017126538A1 - LOAD OPTIMIZATION OF CRITICAL DIMENSIONS OF FINNEN - Google Patents

Abstract

Integrated circuit devices with optimized critical dimension loading of fins are disclosed herein. An exemplary integrated circuit device includes a core region that includes a first multiple fin structure and an input / output region that includes a second multiple fin structure. The first multiple fin structure has a first width and the second multiple fin structure has a second width. The first width is greater than the second width. In some implementations, the first multiple fin structure has a first fin spacing, and the second multiple fin structure has a second fin spacing. The first fin pitch is smaller than the second fin pitch. In some implementations, a first pitch of adjacent fins of the first multiple fin structure is greater than or equal to three times a minimum fin pitch and a second pitch of adjacent fins of the second multiple fin structure is less than or equal to twice the minimum fin pitch.

Description

BACKGROUND

This application claims the benefit of US Provisional Patent Application Serial No. 622/551 624, entitled "Fin Critical Dimension Loading Optimization," filed Aug. 29, 2017, the entire disclosure of which is hereby incorporated by reference.

The IC industry has experienced exponential growth. Technological advances in IC materials and design have spawned generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC development, the functional density (ie, the number of interconnected devices per die area) has generally increased while the geometry size (ie, the smallest component (or line) that can be produced using a fabrication process) has decreased , This reduction process generally provides benefits by increasing production efficiency and reducing associated costs.

Such downsizing has also increased the complexity of processing and manufacturing ICs, and in order for these advances to be realized, similar developments in IC processing and manufacturing are required. If z. For example, as fin-type field effect transistor (FinFET) technologies progress toward smaller feature sizes, FinFET fabrication processes are significantly limited by the reduction of process windows. In particular, when multiple fin densities are present, decreasing fin pitches and increasing fin heights prevent conventional etching techniques from completely or sufficiently removing the material between the fins. As a result, not all advantages of FinFET devices can be realized.

list of figures

• Die 1A-1C, 2A-2C, 3A-3C, 4A-4E, 5A-5E und 6A-6E sind schematische Teilansichten einer integrierten Schaltungsvorrichtung, in Teilen oder vollständig, in verschiedenen Herstellungsstufen gemäß verschiedenen Aspekten der vorliegenden Offenbarung.
• 7 ist ein Flussdiagramm eines Verfahrens zum Herstellen einer integrierten Schaltungsvorrichtung gemäß verschiedenen Aspekten der vorliegenden Offenbarung.
• 8 ist eine fragmentarische Querschnittsansicht einer integrierten Schaltungsvorrichtung, in Teilen oder vollständig, gemäß verschiedenen Aspekten der vorliegenden Offenbarung.

The present disclosure will be best understood from the following detailed description when read with the accompanying drawings. It is emphasized that, in accordance with the usual practice in the industry, various elements are not drawn to scale and are for description only. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description.

• The 1A-1C . 2A-2C . 3A-3C . 4A-4E . 5A-5E and 6A-6E 12 are partial schematic views of an integrated circuit device, in parts or in full, in various stages of manufacture in accordance with various aspects of the present disclosure.
• 7 FIG. 10 is a flowchart of a method of manufacturing an integrated circuit device according to various aspects of the present disclosure. FIG.
• 8th FIG. 12 is a fragmentary cross-sectional view of an integrated circuit device, in parts or in full, according to various aspects of the present disclosure. FIG.

DETAILED DESCRIPTION

The present disclosure relates generally to integrated circuit devices, and more particularly to fin-type field effect transistor (FinFET) devices.

The following disclosure provides many different embodiments or examples to implement various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course these are just examples and should not be limiting. For example, forming a first element over or on a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are interposed between the first element and the second element second element may be formed so that the first and the second element do not have to be in direct contact.

In addition, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and in itself does not enforce any relationship between the various described embodiments and / or configurations. Moreover, forming a feature associated with and / or coupled with another feature in the present disclosure may include embodiments in which the features are in direct contact, and may also include embodiments in which additional features are formed can be arranged between the features so that the features do not have to be in direct contact. In addition, spatially relative terms of the relationship of one feature to another feature, for example, "bottom,""top,""horizontal,""vertical,""above,""over,""below,""below," are referred to "," Down "," upper "," lower ", etc. as well as derivatives thereof (eg" horizontal "," after bottom, top, etc.) are used to simplify the present disclosure. The spatially relative terms are intended to cover various orientations of the device including features.

The 1A-1C . 2A-2C . 3A-3C . 4A-4E . 5A-5E and 6A-6E FIG. 13 are fragmentary schematic views of an integrated circuit device. FIG 10 in parts or in full, at various stages of manufacture in accordance with various aspects of the present disclosure. The integrated circuit device 10 includes various device areas, such as a core area (often referred to as a logic area), a memory area (such as a static random access memory (SRAM) area), an analog area, a peripheral area (often used as input / output ports). I / O) area), a dummy area, another suitable area or combinations thereof. In the embodiment shown, the integrated circuit device comprises 10 a core area 12 and an I / O area 14, both of which include various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar transistors (BJTs). , laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or combinations thereof. As described herein, the core area includes 12 and the I / O area 14 each have one or more fin-type field effect transistors (FinFETs). The integrated circuit device 10 may be provided in a microprocessor, memory and / or other integrated circuit device. In some implementations, the integrated circuit device may 10 Part of an IC chip, a system-on-chip (SoC) or a part thereof. The 1A-1C . 2A-2C . 3A-3C . 4A-4E . 5A-5E and 6A-6E have been simplified for clarity in order to better understand the inventive concepts of the present disclosure. Additional features may be found in the integrated circuit device 10 may be added, and some of the features described below may be used in other embodiments of the integrated circuit device 10 replaced, modified or eliminated.

Referring to the 1A-1C is 1A Fig. 10 is a plan view of the integrated circuit device 10 . 1B a fragmentary cross-sectional view of the integrated circuit device 10 along the line 1B - 1B from 1 and 1C a fragmentary cross-sectional view of the integrated circuit device 10 along the line 1C - 1C from 1A , The core area 12 and the I / O area 14 each comprise at least one fin structure which over a substrate (wafer) 16 is arranged. In the embodiment shown, the substrate comprises 16 Silicon. Alternatively or additionally, the substrate comprises 16 another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, silicon phosphide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor such as silicon germanium (SiGe), SiPC, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Alternatively, the substrate 16 a semiconductor on insulator substrate, such as a silicon on insulator (SOI) substrate, a silicon germanium on insulator (SGOI) substrate or a germanium on insulator (GOI) substrate. Semiconductor-on-insulator substrates can be made using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In some implementations, the substrate comprises 16 one or more Group III V materials. In some implementations, the substrate comprises 16 one or more Group II-IV materials. The substrate 16 includes various doped regions (not shown), depending on the design requirements of the core region 12 and the I / O area 14 , For example, the core area 12 an n-device region, a p-device region, or a combination thereof, and the I / O region 14 is an n-device region, a p-device region, or a combination thereof. In some implementations, the substrate comprises 16 p-type doped regions (eg, p-wells) doped with p-type dopants such as boron, indium, another p-type dopant, or combinations thereof. In some implementations, the substrate comprises 16 n-doped regions (eg, n-wells) doped with n-type dopants such as phosphorus, arsenic, another n-type dopant, or combinations thereof. In some implementations, the substrate comprises 16 doped regions formed with a combination of p-type dopants and n-type dopants. The various doped regions may be directly on and / or in the substrate 16 For example, by providing a p-well structure, an n-well structure, a dual well structure, a raised structure, or combinations thereof.

The core area 12 includes at least one fin structure with two fins or less and the I / O area 14 includes at least one fin structure with three fins or more. For example, the core area includes 12 a fin structure 20A (with two Finns 22A) and a fin structure 20B (with two Finns 22B) and the I / O area 14 includes a fin structure 20C (with six fins 22C) , Although the fin structures 20A - 20C In the embodiment shown, multiple fin structures are contemplated, the present disclosure contemplates embodiments in which the fin structure 20A and or the fin structure 20B include only one fin. In the embodiment shown, the fin structures are included 20A - 20C to a first FinFET device, a second FinFET device or a third FinFET device of the integrated circuit device 10 , Alternatively, in some implementations, the fin structure may be included 20A and the fin structure 20B to a first FinFET device and the fin structure 20C to a second FinFET device. In some implementations, the Finns are 22A - 22C a part of the substrate 16 (Such as a part of a material layer of the substrate 16 ). For example, if the substrate 16 Silicon includes the fins 22A - 22C Silicon. Alternatively, in some implementations, the fins are 22A - 22C defined in a material layer, such as one or more semiconductor material layers, overlying the substrate 16 lies. For example, the Finns 22A - 22C a semiconductor layer stack comprising different semiconductor layers (such as a heterostructure) overlying the substrate 16 are arranged. The semiconductor layers may include any suitable semiconductor materials such as silicon, germanium, silicon germanium, other suitable semiconductor materials, or combinations thereof. The semiconductor layers may comprise the same or different materials, etch rates, atomic proportions of the constituents, parts by weight, thicknesses, and / or configurations, depending on the design requirements of the integrated circuit device 10 , In some implementations, the semiconductor layer stack includes alternating semiconductor layers, such as silicon layers. B. semiconductor layers, which consist of a first material, and semiconductor layers, which consist of a second material. For example, the semiconductor layer stack alternates silicon layers and silicon germanium layers (for example, SiGe / Si / SiGe / Si / SiGe / Si from bottom to top). In some implementations, the semiconductor layer stack comprises semiconductor layers of the same material but with alternating atomic portions, such as semiconductor layers having a constituent of a first atomic portion and semiconductor layers having a constituent of a second atomic proportion. For example, the semiconductor layer stack of silicon-germanium layers includes alternating silicon and / or germanium atomic proportions (for example, Si _a Ge _b / Si _c Ge _d / Si _a Ge _b / Si _c Ge _d / Si _a Ge _b / Si _c Ge _d from bottom to top, where a and c are different atomic proportions of silicon and b and d are different atom proportions of germanium). In some implementations, the Finns include 22A , Finns 22B and / or the Finns 22C the same materials and / or the same semiconductor layer stacks, depending on the design requirements of their respective FinFET device. In some implementations, the Finns include 22A , Finns 22B and / or the Finns 22C different materials and / or different semiconductor layer stacks, depending on the design requirements of their respective FinFET device.

Filling optimization for critical dimensions (CD) of fins will be between the core area 12 and the I / O area 14 for subsequent processing achieved by fin structures of the core area 12 and the I / O area 14 be configured with different critical dimensions. In some implementations, critical dimension generally refers to a dimension, such as fin width and / or fin pitch, defined by design requirements, to a desired performance of the integrated circuit device 10 to achieve. In the 1A-1C have the Finns 22A one width each w ₁ , Finns 22B one width each w ₂ and the Finns 22C one width each w ₃ , where the fin width is the critical dimension, and the width w ₁ , the width w ₂ and the width w ₃ are configured to provide fin CD optimizing. In some implementations, fin CD charge is a difference between a core fines CD (or core fines width) of the core area 12 and an I / O fin CD (or I / O fin width) of the I / O area 14 Are defined. The fin CD charge optimizes the spacing between the fins for etch processes used during gate formation when the fin CD charge is greater than o (in other words, fin CD charge = core fines CD). I / O fin CD ≥ o). For example, if the core finned CD is larger than the I / O fin CD (in other words, the fins 22A and the Finns 22B each have a width that is greater than a width of the fins 22C is (for example w ₁ > w ₃ and w ₂ > w ₃ )), is a distance S ₁ (Distance) between adjacent fins 22A and / or a distance S ₂ between neighboring fins 22B less than a distance S ₃ between neighboring fins 22C (in other words, S ₁ <S ₃ and S ₂ <S ₃ ). In some implementations, the width is w ₁ about 1 nm to about 30 nm, the width w ₂ about 1 nm to about 30 nm and the width w ₃ about 1 nm to about 30 nm. In some implementations, the distance is S ₁ about 10 nm to about 30 nm, the distance S ₂ about 10 nm to about 30 nm and the distance S ₃ about 10 nm to about 30 nm. In continuation of the embodiment shown, the fins have 22A and the Finns 22B essentially the same width (in other words, w ₁ ≈ w ₂ ) and the fins 22A and the Finns 22B have substantially the same distance (in other words, S ₁ ≈ S ₂ ). In some implementations, the widths differ w ₁ and / or the distance S ₁ the Finns 22A from the width w ₂ and / or the distance S ₂ the Finns 22B , depending on the design requirements of the core area 12 , In the 1A-1C have the Finns 22A one height each h ₁ and a length ₁ ; Finns 22B each have a height h ₂ and a length l ₂ ; and the Finns 22C to have one height each h ₃ and a length l ₃ , In some implementations, the height is h ₁ about 30 nm to about 150 nm, the height h ₂ about 30 nm to about 150 nm and the height h ₃ about 30 nm to about 150 nm. In some implementations, the length l ₁ is about 30 nm to about 60 nm, the length l ₂ about 30 nm to about 60 nm and the length l ₃ about 30 nm to about 60 nm.

A center distance P ₁ the fin structure 20A generally denotes a sum of a width w ₁ the Finns 22A and a distance between adjacent fins 22A (as S ₁ ) (in other words, P ₁ = w ₁ + S ₁ ). A center distance P ₂ the fin structure 20B generally denotes a sum of a width w ₂ the Finns 22B and a distance between adjacent fins 22B (as S ₂ ) (in other words, P ₂ = w ₂ + S ₂ ). A center distance P ₃ the fin structure 20C generally denotes a sum of a width w ₃ the Finns 22C and a distance between adjacent fins 22C (as S ₃ ) (in other words, P ₃ = w ₃ + S ₃ ). In the embodiment shown, the center spacing define P ₁ , the center distance P ₂ and the center distance P ₃ a middle-to-middle distance between the fins. In some implementations, the pitch is P ₁ , the center distance P ₂ and the center distance P ₃ about 10 nm to about 80 nm. In some implementations, the pitch is P ₁ about 10 nm to about 600 nm, the center distance P ₂ about 10 nm to about 600 nm, and the center distance P ₃ from about 10 nm to about 80 nm. In some implementations, the fin structures have 20A - 20C about the same center distances. In some implementations, the fin structures have 20A - 20C different center distances. In some implementations, the pitch is P ₁ , the center distance P ₂ and / or the center distance P ₃ equal to a minimum fin pitch ( P _m ). In some implementations, the minimum fin center distance generally refers to a minimum fin pitch that is achievable by a lithography process and / or a fin fabrication process (eg, deposition, lithography, and / or etching processes) of a given IC technology node. In some implementations, the minimum fin pitch generally refers to a smallest fin pitch that is dictated by design requirements for the integrated circuit device 10 is specified.

Each of the Finns 22A - 22C has a pitch of adjacent fins that may be configured to further optimize the gaps between the fins for etching processes that occur during gate formation in the core region 12 and the I / O area 14 be used. A pitch of adjacent fins (P _adjacent ) is a sum of a center distance of the right fin of a fin (P _R ) and a pitch of the left fin of a fin ( P _L ). The center distance of the right fin P _R defines a center distance between a center of a fin and a center of an adjacent (adjacent) fin, which is located to the right of the fin, and the center distance of the left fin P _L defines a center distance between the center of the fin and a center of an adjacent (adjacent) fin located to the left of the fin. In some implementations, the fin and the adjacent fin belong to the same fin structure and / or the same FinFET device. In some implementations, the fin and the adjacent fin belong to different fin structures and / or different FinFET devices. The core area 12 has fin structures with a pitch of adjacent fins in the core (P _{core adjacent} ) that is greater than or equal to three times the minimum fin pitch (in other words, P _{core adjacent is} ≥ 3P _m ), and the I / O area 14 has fin structures with a pitch of adjacent fins in the I / O (P _{IO adjacent} ) that is less than or equal to twice the minimum fin pitch (in other words, P _{IO adjacent} ≤ 2P _m ). For example, in the core area 12 the farthest right fin 22A the fin structure 20A a center distance of the left fin, which is equal to the minimum fin center pitch (P _L = P _m ), and a center distance of the right fin, which is twice the minimum fin center pitch (P _R = 2P _m ), so that you Center pitch of adjacent fins is three times the minimum fin center pitch (in other words, P is _{20A adjacent} = P _m + 2P _m = 3P _m ). In some implementations, the center distance of the right fin is the rightmost fin 22A greater than twice the minimum fin center distance and / or the center distance of the left fin of the rightmost fin 22A is less than the minimum fin center distance. In contrast, in the I / O area 14 one of the middle fins 22C the fin structure 20C a center distance of the left fin, which is equal to the minimum fin pitch (P _L = P _m ), and a pitch of the right fin, which is equal to the minimum fin center pitch (P _R = P _m ), so that their pitch is adjacent Fins is equal to twice the minimum fin pitch (in other words, P _20C - _adjacent = Pm + Pm = 2P _m ). In some implementations, the center distance of the left fin and / or the center distance of the right fin is the middle fin 22C less than the minimum fin center distance. As in the embodiment shown, the fin structure 20A and the fin structure 20B have two Finns or less, the Finns show 22A and the Finns 22B each have a pitch of adjacent fins, the center distance of the left fin and / or the center distance of the right fin between a fin of a first FinFET device and a fin of a second FinFET device defined. As a continuation of the embodiment shown, the fin structure 20C have three Finns or more, the middle Finns have 22C at a pitch of adjacent fins, which defines the pitch of the left fin and the pitch of the right fin between fins of the same FinFET device.

The present disclosure contemplates deviations in height, width and / or length of the fins 22A - 22C arising from the processing and manufacture of the integrated circuit device 10 can result. In the embodiment shown, the fins 22A - 22C Tapered widths along their respective height, with the width w ₁ , the width w ₂ and the width w ₃ each represent an average of the varying widths. For example, take the latitudes of the Finns 22A - 22C from the lower sections of the fins 22A - 22C to the upper sections of the fins 22A - 22C so that the average widths of the upper portions are smaller than the average widths of the lower portions of the fins 22A - 22C , In some implementations, the widths may be from about 5 nm to about 15 nm along the fins 22A - 22C vary, depending on where the widths are along the height of the Finns 22A - 22C be measured. In some implementations, the fin width varies depending on a position of a fin relative to other fins and / or relative to other features of the integrated circuit device 10 , For example, is for fin structure 20C the width w ₃ the middle fin (in the embodiment shown, the fin structure comprises 20C four middle fins 22C) larger than the width w ₃ the edge fins 22C (here the leftmost Finn 22C and the farthest right fin 22C representing the four middle Finns 22C lock in). In another example, alternatively, the width w _{3 of} the middle fins is smaller than the width w ₃ the edge fins. In both such implementations, the width is w ₃ smaller than the width w ₁ and the width w ₂ , In continuation of such implementations, the width w ₃ the edge fins represent a mean width of the edge fins and the width w ₃ the middle fin may represent a mean width of the middle fin. Although the Finns 22A - 22C are shown to have a tapered width, the fins have 22A - 22C in some implementations, essentially the same width along their respective height.

Finns 22A - 22C are grown over the substrate using any suitable method 16 educated. In some implementations, a combination of deposition, lithography, and / or etching processes is performed on the fins 22A - 22C to define themselves from the substrate 16 extend, as in the 1A-1C is shown. For example, forming the fins includes 22A - 22C performing a lithography process to form a patterned resist layer over the substrate 16 (or a material layer, such as a heterostructure, over the substrate 16 and performing an etching process for transferring a pattern defined in the patterned resist layer to the substrate 16 (or the material layer, like the heterostructure, over the substrate 16 is arranged). The lithographic process may include forming a resist layer on the substrate 16 (for example, by spin-coating), performing a pre-exposure baking process, performing an exposure process using a mask, performing a post-exposure baking process, and performing a developing process. During the exposure process, the resist layer is irradiated with radiant energy (such as ultraviolet (UV) light, deep UV light (DUV), or extreme UV light (EUV)), which mask blocks, transmits, and / or reflects radiation onto the resist layer. depending on a mask structure of the mask and / or the mask type (for example, a binary mask, a phase shift mask or an EUV mask), so that an image is projected onto the resist layer corresponding to the mask pattern. Since the resist layer is sensitive to radiant energy, exposed portions of the resist layer chemically change, and exposed (or unexposed) portions of the resist layer are dissolved during the development process depending on the properties of the resist layer and the characteristics of the developing solution used in the development process. After development, the patterned resist layer comprises a resist pattern corresponding to the mask. The etching process uses the patterned resist layer as an etch mask around portions of the substrate 16 (or a layer of material over the substrate 16 is arranged) to remove. The etching process may include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, another suitable etching process, or combinations thereof. After the etching process, the patterned resist layer becomes from the substrate 16 removed, for example by a resist-stripping method. Alternatively, the Finns 22A - 22C formed by a multiple patterning process, such as a double pattern lithography (DPL) process (e.g., a lithographic etch-lithography etch (LELE) process, a self-aligned double-textured (SADP) process, a spacer-as- Dielectric (SID) SADP method, another double patterning method or combinations thereof), a triple patterning method (for example, a lithography-etching-lithography-etching-lithography-etching (LELELE) method, a self-aligned Triplicate structuring (SATP) method, another triple structuring method or combinations thereof), another multiple structuring method (for example, a self-aligned quadruple structuring (SAQP) method) or combinations thereof. In some implementations, directed self-assembly (DSA) techniques are implemented, while the fins 22A - 22C be formed. Further, in some implementations, the exposure method may implement maskless lithography, e-beam writing, ion beam writing, and / or nanoprinting technology for patterning the resist layer.

In some implementations, a structure defined in the patterned resist layer (or patterned mask layer) includes first openings having a first width for defining the fin structure 20A and the fin structure 20B and second openings having a second width for defining the fin structure 20C wherein the first width is greater than the second width. In such implementations, an etching process then uses the patterned resist layer as an etch mask around portions of the substrate 16 (or one above the substrate 16 arranged material layer), so that the fins 22A - 22C with fin CD loading between the core area 12 and the I / O area 14 as described herein. In some implementations, a structure defined in the patterned resist layer (or patterned mask layer) includes first openings, second openings, and third openings for defining the fin structure 20A , the fin structure 20B and the fin structure 20C wherein the first openings, the second openings and the third openings have the same width. In such implementations, an etching process then uses the patterned resist layer as an etch mask around portions of the substrate 16 (or a layer of material over the substrate 16 is arranged), so that the fins 22A - 22C have the same width. Continuing with such implementations, a trim method is then performed to determine the fin structure 20C to trim, reducing a width of the fins 22C is reduced so that the Finns 22A - 22C with a fin CD charge between the core area 12 and the I / O area 14 as described herein. The trim method implements any suitable method of reducing the size of the fins 22C , For example, in some implementations, the trim method includes an etching process that includes the fins 22C relative to other features of the integrated circuit device 10 can etch selectively. The etching method is a dry etching method, a wet etching method or combinations thereof. In some implementations, a wet etching process implements an etching solution comprising ammonium hydroxide (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), sulfuric acid (H ₂ SO ₄ ), tetramethylammonium hydroxide (TMAH), another suitable wet etching solution, or combinations thereof. For example, the wet etch solution may be a NH ₄ OH: H ₂ O ₂ solution, an NH ₄ OH: H ₂ O ₂ : H ₂ O solution (known as an ammonia peroxide mixture (APM)) or an H ₂ SO ₄ Use H ₂ O ₂ solution (known as sulfur peroxide mixture (SPM)). In some implementations, a dry etching process implements an etching gas comprising a fluorine-containing etching gas (e.g., CF ₄ , SF ₆ , CH ₂ F ₂ , CHF _3, and / or C ₂ F ₆ ), an oxygen-containing gas, a chlorine-containing gas (e.g., Cl ₂ , CHCl ₃ , CCl ₄ and / or BCl ₃ ), a bromine-containing gas (eg HBr and / or CHBr ₃ ), an iodine-containing gas, other suitable gases and / or plasmas or combinations thereof. In some implementations, the trim method implements an oxidation method. For example, the trim method may be the fins 22C exposing it to an ozone environment, causing some of the fins 22C is oxidized, which is subsequently removed by a cleaning process and / or an etching process.

Referring to the 2A-2C is 2A a plan view of the integrated circuit device 10 . 2 B a fragmentary cross-sectional view of the integrated circuit device 10 along the line 2 B - 2 B from 2A and 2C a fragmentary cross-sectional view of the integrated circuit device 10 along the line 2C - 2C from 2A , One or more isolation features 30 are above and / or in the substrate 16 formed to various areas, such as various device areas, the integrated circuit device 10 to isolate. For example, the isolation feature separates and isolates 30 the core area 12 from the I / O area 14 , The isolation feature 30 separates and isolates the Finns 22A - 22C from each other. In the embodiment shown, the isolation feature surrounds 30 a bottom area of the fins 22A - 22C , The isolation feature 30 includes silicon oxide, silicon nitride, silicon oxynitride, another suitable insulating material (comprising, for example, silicon, oxygen, nitrogen, carbon or other suitable insulating element) or combinations thereof. The isolation feature 30 may include different structures, such as shallow trench isolation (STI) structures, deep trench isolation (DTI) structures, and / or local oxidation of silicon (LOCOS) structures. In some implementations, the STI features may be deposited by depositing an insulator material over the substrate 16 after forming the fins 22A - 22C (In some implementations, such that the insulator material layer has gaps (trenches) between the fins 22A - 22C fills) and etch back the insulator material layer to form the isolation feature 30 train. In some implementations, the STI features may be obtained by etching a trench in the substrate 16 (for example, under Using a dry etching method and / or a wet etching method) and filling the trench with insulator material (for example, by using a chemical vapor deposition method or a spin on glass method). A chemical mechanical polishing (CMP) process may be performed to remove excess insulator material and / or an upper surface of the insulative feature 30 to planarize. In some implementations, the isolation feature includes 30 a multi-layer structure that fills trenches, such as a bulk dielectric layer disposed over a dielectric liner layer, wherein the bulk dielectric layer and the dielectric liner layer include materials depending on design requirements (eg, a bulk dielectric layer comprising silicon nitride) disposed over a dielectric lining layer comprising thermal oxide). In some implementations, the isolation feature includes 30 a dielectric layer disposed over a doped liner layer (eg, comprising borosilicate glass (BSG) or phosphosilicate glass (PSG)).

Referring to the 3A-3C is 3A a plan view of the integrated circuit device 10 . 3B a fragmentary cross-sectional view of the integrated circuit device 10 along the line 3B - 3B from 3A and 3C a fragmentary cross-sectional view of the integrated circuit device 10 along the line 3C - 3C from 3A , A gate layer 40 is above the fin structures 20A - 20C formed, each in the core area 12 and the I / O area 14 is arranged. For example, at least one deposition process is performed on the gate layer 40 above the substrate 16 form, especially over the fin structures 20A - 20C and the isolation feature 30 , The gate layer 40 fills gaps between the fin structures 20A - 20C and fill in gaps between the Finns 22A - 22C , The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma CVD (HDPCVD), organometallic CVD (MOCVD), remote plasma CVD (RPCVD), plasma assisted CVD (PECVD), low pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), plating, other suitable methods or combinations thereof. Thereafter, a CMP process may be performed to form an upper surface of the gate layer 40 to planarize. In the embodiment shown, the gate layer comprises 40 a polysilicon layer. In some implementations, the gate layer includes 40 an interface layer (comprising a dielectric such as silicon oxide) interposed between the fin structures 20A - 20C and the polysilicon layer is disposed. In some implementations, the gate layer is 40 a dummy gate stack including a dummy gate electrode and a dummy gate dielectric layer. In such implementations, a deposition process is performed to apply a dummy gate dielectric layer over the substrate 16 and a deposition process is performed to form a dummy gate electrode layer over the gate dielectric layer. Continuing such implementations, the dummy gate electrode comprises polysilicon or other suitable dummy gate material, and the dummy gate dielectric comprises a dielectric (eg, silicon oxide), a high-k dielectric, another suitable dielectric, or combinations thereof. Examples of high-k dielectrics include HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) alloy, other suitable high-k dielectrics, or combinations from that. The gate layer 40 may include numerous other layers, for example, overlays, interfacial layers, diffusion layers, barrier layers, hardmask layers, or combinations thereof. In one example, a capping layer, such as a titanium nitride (TiN) capping layer, is sandwiched between the dummy gate dielectric (or substrate) 16 when the dummy gate dielectric is omitted) and the dummy gate electrode are arranged.

Referring to the 4A-4C is 4A a plan view of the integrated circuit device 10 . 4B a fragmentary cross-sectional view of the integrated circuit device 10 along the line 4B - 4B from 4A . 4C a fragmentary cross-sectional view of the integrated circuit device 10 along the line 4C - 4C from 4A . 4D a fragmentary cross-sectional view of the integrated circuit device 10 along the line 4D - 4D from 4A and 4E a fragmentary cross-sectional view of the integrated circuit device 10 along the line 4E - 4E from 4A , In the 4A-4E is a structuring layer 50 over the gate layer 40 formed, wherein the structuring layer 50 openings 52 includes the parts of the gate layer 40 in the core area 12 expose, and openings 54 , the parts of the gate layer 40 in the I / O area 14 uncover. In the embodiment shown, the structuring layer comprises 50 a mask layer 56 that over the gate layer 40 is arranged, and a resist layer 58 (also referred to as a photoresist layer, photosensitive layer, imaging layer, patterning layer or radiation-sensitive layer) overlying the mask layer 56 is arranged. The mask layer 56 includes a material having a different etch rate than a material of the gate layer 40 , For example, the mask layer comprises 56 Silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, Silicon carbonitride, another suitable material, or combinations thereof. In some implementations, the mask layer includes 56 a material that compared to a material of the gate layer 40 has a low etch rate, leaving the gate layer 40 opposite the mask layer 56 can be selectively etched. The mask layer 56 is formed by any suitable method, such as a CVD method, of any suitable thickness. In some implementations, a silicon-containing and nitrogen-containing mask layer is formed using LPCVD. In some implementations, a silicon-containing and nitrogen-containing mask layer is formed by performing a method comprising thermal nitriding a silicon-containing layer. The resist layer 58 includes any suitable resist material. The structuring layer 50 is formed by a lithographic patterning process that includes resist coating (eg, spin coating), soft baking, mask alignment, exposure, post exposure baking, developing, rinsing, drying (eg, hard baking), other suitable methods, or combinations thereof. Alternatively, the lithography exposure process is assisted, implemented or replaced by other methods such as maskless lithography, electron beam writing or ion beam writing. In yet another alternative, the lithographic patterning technique implements nanoprinting technology. In some implementations, the lithography process implements an etching process, such as an etching process. Dry etching, wet etching, another etching process, or combinations thereof. A rinse process, such as deionized (DI) water rinse, may be performed prior to forming the patterning layer 50 on the gate layer 40 be applied.

Referring to the 5A-5C is 5A a plan view of the integrated circuit device 10 . 5B a fragmentary cross-sectional view of the integrated circuit device 10 along the line 5B - 5B from 5A . 5C a fragmentary cross-sectional view of the integrated circuit device 10 along the line 5C - 5C from 5A . 5D a fragmentary cross-sectional view of the integrated circuit device 10 along the line 5D - 5D from 5A and 5E a fragmentary cross-sectional view of the integrated circuit device 10 along the line 5E - 5E from 5A , In the 5A-5E becomes an etching process using the patterning layer 50 performed as a mask to exposed parts of the gate layer 40 to remove, creating gate structures 40A - 40H be formed. The etching process may include a dry etching process (for example, a reactive ion etching (RIE) process), a wet etching process, another suitable etching process, or combinations thereof. The etching process is unable to expose exposed portions of the gate layer 40 in the openings 54 in the I / O area 14 completely, leaving remaining gate layer portions 40 ' between the Finns 22C remain. The gate structures 40F - 40H thus have widths that vary along their length and height, while the gate structures 40A - 40E Have widths that are essentially the same along their length and height. In 5A is along its length a width of the gate structures 40F - 40H that about the Finns 22C are arranged smaller than a width of the gate structures 40F - 40H between the Finns 22C are arranged. Along their height have the gate structures 40F - 40H rejuvenated latitudes. For example, in 5E a section of a gate structure 40G , between the Finns 22C is arranged, a width that decreases along its height, so that a width of the portion of the gate structure 40G near the isolation feature 30 (or the substrate 16 ) is greater than a width of the portion of the gate structure 40G near the patterning layer 50 , In some implementations, a width of the portion of the gate structure is 40G over an upper surface of the fin structure 22C along its height substantially equal, while a width of the portion of the gate structure 40G below the upper surface of the fin structures 22C decreases along its height. In conventional integrated circuit devices in which a core region and an I / O region have fin structures of substantially the same critical dimensions (widths), such remaining gate layer components cause gate-source / drain breakdown, degrading device performance. In contrast, by implementing the fin CD load between the core area 12 and the I / O area 14 as described herein (and thus increasing the fin pitches in the I / O area 14 relative to the fin pitches in the core area 12 ) Minimizes etch-charge effects during the etching process, which adds size (especially thickness) to the remaining gate layer sections 40 ' significantly reduced compared to conventional integrated circuit devices. The disclosed fin CD loading increases a breakdown voltage window (FIG. V _BD ) for the I / O area 14 (For example, by increasing the center distance between the fins in the I / O area 14 ), while a smaller center distance between the fins, which helps to increase the power of the core area 12 is desirable (for example, by providing a core fines CD that is larger than the I / O fins CD). The VBD window for the I / O area 14 is thus increased without the performance of the core area 12 to affect and / or without affecting the gate manufacturing process (in particular polysilicon etching). Various embodiments may have various advantages, and no particular advantage necessarily required in any embodiment.

Referring to the 6A-6C is 6A a plan view of the integrated circuit device 10 . 6B a fragmentary cross-sectional view of the integrated circuit device 10 along the line 6B - 6B from 6A . 6C a fragmentary cross-sectional view of the integrated circuit device 10 along the line 6C - 6C from 6A . 6D a fragmentary cross-sectional view of the integrated circuit device 10 along the line 6D - 6D from 6A and 6E a fragmentary cross-sectional view of the integrated circuit device 10 along the line 6E - 6E from 6A , In the 6A-6C are after the structuring layer 50 from the gate layer 40 For example, was removed by a resist-stripping process, the gate structures 40A - 40H over the Finn 22A - 22C arranged. The gate structures 40A - 40H extend along the y-direction (for example, substantially perpendicular to the fins 22A - 22C) , In the embodiment shown, the gate structures are 40A - 40E over the fin structure 20A and the fin structure 20B arranged so that the gate structures 40A - 40E a section of the Finns 22A and Finns 22B envelop; and the gate structures 40F - 40H are above the fin structure 20C arranged so that the gate structures 40F - 40H a section of the Finns 22C envelop. The gate structures 40A - 40H are active gate structures or dummy gate structures, depending on the design requirements of the integrated circuit device 10 , "Active gate structure" generally refers to an electrically functional gate structure of the integrated circuit device 10 during "dummy gate structure" generally an electrically non-functional gate structure of the integrated circuit device 10 designated. In some implementations, a dummy gate structure mimics spatial characteristics of an active gate structure, such as spatial dimensions of the active gate structure, but is not operable in a FinFET (in other words, does not allow current flow). In some implementations, at least one of the gate structures envelops 40A - 40E Channel areas of the fins 22A and Finns 22B allowing them to pass between source / drain regions of the fins 22A and Finns 22B lie; and at least one of the gate structures 40F - 40H envelops channel areas of the fins 22C allowing them to pass between source / drain regions of the fins 22C lie. In such implementations, the at least one of the gate structures accesses 40A - 40H into the channel areas of the fins 22A - 22C a, allowing current during operation between the source / drain regions of the fins 22A - 22C can flow. In some implementations, the gate structures enable 40A - 40H a substantially uniform processing environment, such as uniform epitaxial growth of material in source / drain regions of the fins 22A - 22C (For example, in the formation of epitaxial source / drain features), uniform etch rates in source / drain regions of the fins 22A - 22C (For example, when source / drain wells are formed) and / or uniform, substantially planar surfaces (for example, by reducing (or preventing) CMP-induced dishing effects).

The integrated circuit device 10 may be subjected to further processing to complete the production. For example, in some implementations, gate spacers become adjacent to the gate structures 40A - 40H educated. For example, the gate spacers are adjacent (eg, along sidewalls) to the gate layer 40 arranged. The gate spacers are formed by any suitable method and include a dielectric. The dielectric may comprise silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (eg, silicon oxide, silicon nitride, silicon oxynitride or silicon carbide). For example, in the illustrated embodiment, a dielectric layer comprising silicon and nitrogen, such as a silicon nitride layer, may overlie the substrate 16 deposited and then anisotropically etched to form the gate spacers. In some implementations, the gate spacers include a multilayer structure, such as a first dielectric layer comprising silicon nitride and a second dielectric layer comprising silicon oxide. In some implementations, more than one set of spacers, such as gasket spacers, offset spacers, sacrificial spacers, dummy spacers, and / or main spacers, become adjacent to the gate structures 40A - 40H educated. In such implementations, the various sets of spacers may include materials having different etch rates. For example, a first dielectric layer comprising silicon and oxygen (eg, silicon oxide) may overlie the substrate 16 deposited and subsequently anisotropically etched to form a first spacer set adjacent to the gate structures 40A - 40H and a second dielectric layer comprising silicon and nitrogen (eg, silicon nitride) may overlie the substrate 16 and then anisotropically etched to form a second spacer set adjacent to the first spacer set.

In some implementations, source / drain features, such as heavily doped source / drain regions and / or lightly doped source / drain (LDD) features, are in the source / drain regions of the fins 22A - 22C educated. In some Implementations include epitaxial source features and epitaxial drain features (referred to as epitaxial source / drain features) in the source / drain regions of the fins 22A - 22C educated. For example, a semiconductor material becomes epitaxially on exposed portions of the fins 22A - 22C grown, whereby epitaxial source / drain features are formed. An epitaxy technique may use CVD deposition techniques (for example, VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth methods, or combinations thereof. The epitaxy process may use gaseous and / or liquid precursors that are related to the composition of the fins 22A - 22C to interact. The epitaxial source / drain features are doped with n-type dopants and / or p-type dopants. In some implementations, the epitaxial source / drain features are epitaxial layers comprising silicon and / or carbon, wherein silicon-containing epitaxial layers or silicon carbonaceous epitaxial layers are doped with phosphorus, another n-type dopant, or combinations thereof (e.g. Si: P epitaxial layer or Si: C: P epitaxial layer is formed). In some implementations, the epitaxial source / drain features are epitaxial layers comprising silicon and germanium, wherein the silicon germanium-containing epitaxial layers are doped with boron, another p-type dopant, or combinations thereof (whereby, for example, an Si: Ge : B epitaxial layer is formed). In some implementations, the epitaxial source / drain features materials and / or dopants that provide a desired tensile and / or compressive stress in the channel regions of the fins 22A - 22C to reach. In some implementations, the epitaxial source / drain features are doped during deposition by adding impurities to a source material of the epitaxial growth process. In some implementations, the epitaxial source / drain features are doped by an ion implantation process following a deposition process. In some implementations, annealing processes are performed to provide dopants in the epitaxial source / drain features and / or other source / drain regions of the integrated circuit device 10 (For example, HDD areas and / or LDD areas that are in the source / drain areas of the fins 22A - 22C and / or the epitaxial source / drain features are formed).

A gate replacement process may then be performed to form a dummy gate stack of at least one of the gate structures 40A - 40H by a gate, such as a metal gate stack. For example, an interlevel dielectric (ILD) layer may be over the substrate 16 by a deposition method (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods or combinations thereof). The ILD layer comprises a dielectric comprising, for example, silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, a low-k dielectric, another suitable dielectric, or combinations thereof. Exemplary low-k dielectrics include FSG, carbon-doped silica, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, airgel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide another low-k dielectric or combinations thereof. The ILD layer may comprise a multilayer structure with multiple dielectrics. After depositing the ILD layer, a CMP process may be performed such that an upper portion of the gate structures 40A - 40H is reached, such as a dummy gate electrode (for example, a polysilicon layer) of the gate layer 40 , Part of the at least one of the gate structures 40A - 40H (like the dummy gate electrode of the gate layer 40 ) is then removed, thereby forming a trench (opening) that can expose a barrier layer and / or a gate dielectric. In some implementations, an etching process selectively removes the dummy gate electrode (and in some implementations, a dummy gate dielectric). The etching method is a dry etching method, a wet etching method or combinations thereof. A selective etching process may be tuned such that the dummy gate electrode layer has a suitable etch rate relative to the barrier, the spacers, and / or the ILD layer.

A metal gate stack of the at least one of the gate structures 40A - 40H is then formed in the opening (trench). The metal gate stack of the at least one of the gate structures 40A - 40H includes a gate dielectric (eg, a gate dielectric layer) and a gate electrode (eg, a work function layer and a conductive bulk (or fill) layer). The gate stacks may include numerous other layers, for example, capping layers, interfacial layers, diffusion layers, barrier layers, hardmask layers, or combinations thereof. The gate dielectric layer comprises a dielectric, such as. As silicon oxide, a high-k dielectric, another suitable dielectric or combinations thereof. Examples of high-k dielectrics are hafnium dioxide (HfO ₂ ,), HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ), other suitable high-k dielectrics or Combinations of it. In some implementations, the gate dielectric layer is a high-k dielectric layer. The gate electrode comprises a conductive material, such as. Polysilicon, Aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), cobalt (Co), TaN, NiSi B. CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials or combinations thereof. In some implementations, the work function layer is a conductive layer that is tuned to have a desired work function (such as an n work function or a p work function), and the conductive bulk layer is a conductive layer formed over the work function layer is. In some implementations, the work function layer includes n-type work function materials such as Ti, silver (Ag), TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, manganese (Mn), zirconium (Zr), other suitable n-type workfunction materials, or combinations thereof. In some implementations, the work function layer includes a p-work function material, such as TiN, TaN, ruthenium (Ru), Mo, Al, WN, ZrSi _2, MoSi _2, TaSi _2, NiSi _2, WN, other suitable p-work function materials or combinations thereof , The conductive bulk layer comprises a suitable conductive material such as Al, W and / or Cu. In some implementations, the conductive bulk layer additionally or jointly comprises polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof. The gate dielectric layer, the work function layer, and the conductive bulk layer are formed by various deposition methods, such as ALD, CVD, PVD, and / or other suitable methods. A CMP process may be performed to remove excess material (such as all excess work function layer portions and / or excess metal fill layer portions), resulting in the gate structures 40A - 40H planarized. It is understood that the gate structures 40A - 40H Having gate stacks configured to provide the desired functionality in accordance with the design requirements of the integrated circuit device 10 to reach, so the gate structures 40A - 40H comprise the same or different layers and / or materials.

In some implementations, various contacts are formed to facilitate operation of the integrated circuit device 10 to facilitate. For example, additional ILD layers may be above the substrate 16 (In the embodiment shown above the ILD layer and the gate structures 40A - 40H) be formed. The contacts may be formed in the ILD layers, such as. B. contacts that are electrically connected to the gate structures 40A - 40H and contacts electrically connected to the source / drain regions of the fin structures 20A -20C are coupled. The contacts comprise a conductive material, such as metal. Metals include aluminum, aluminum alloy (such as aluminum / silicon / copper alloy), copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some implementations, the ILD layers and the contacts are part of a multilayer interconnect (MLI) feature that overlies the substrate 16 is arranged. The MLI feature connects various components of the integrated circuit device 10 electrically such that the various components are capable of functioning as specified by the design requirements. The MLI feature may include a combination of metal layers and ILD layers configured to form vertical interconnect features such as contacts and / or vias, and / or horizontal interconnect features such as lines. The various conductive features include materials similar to those of the contacts. In some implementations, a damascene process and / or a dual damascene process is used to form a copper-based multilayer interconnect structure. The integrated circuit device 10 may be subjected to subsequent processing to complete production depending on design requirements.

7 is a flowchart of a method 100 for manufacturing an integrated circuit device, such as the integrated circuit device 10 According to various aspects of the present disclosure. At block 102 includes the method 100 forming a first multiple fin structure having a first critical dimension in a core region and a second multiple fin structure having a second critical dimension in an input / output region. The first critical dimension is greater than the second critical dimension. In some implementations, the first multiple fin structure and the second multiple fin structure are configured as described with respect to FIGS 1A-1C is disclosed. At block 104 includes the method 100 forming a first gate structure over the first multiple fin structure and a second gate structure over the second multiple fin structure. In some implementations, the first gate structure and the second gate structure are formed as described with respect to FIG 2A-2C . 3A-3C 4A-4E 5A-5E and 6A-6E is disclosed. At block 106 can the procedure 100 continue to complete the manufacture of the FinFET device. For example, in implementations where the first gate structure and / or the second gate structure includes a dummy gate, a gate replacement process is performed to replace the one or more dummy gates with one or more metal gates. Additional steps may be taken before, during and after method 100 may be provided and some of the steps described may be for additional embodiments of the method 100 postponed, replaced or eliminated.

8th FIG. 12 is a fragmentary cross-sectional view of an integrated circuit device. FIG 200 in parts or in full, according to various aspects of the present disclosure. The integrated circuit device 200 may be provided in a microprocessor, memory and / or other integrated circuit device. In some implementations, the integrated circuit device is 200 Part of an integrated circuit chip, a SoC or a part thereof, which includes various passive and active microelectronic devices such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high voltage transistors, high frequency transistors, others include suitable components or combinations thereof. 8th has been simplified for the sake of clarity in order to better understand the inventive concepts of the present disclosure. Additional features may be found in the integrated circuit device 200 may be added, and some of the features described below may be used in other embodiments of the integrated circuit device 200 replaced, modified or eliminated.

In 8th includes the integrated circuit device 200 a substrate 116 that the substrate 16 the integrated circuit device 10 similar to the above with reference to the 1A-1C has been described. The integrated circuit device 200 further comprises a fin structure 220A , a fin structure 220B (Finns 222B includes) and a fin structure 220C (Finns 222C comprises). The fin structure 220A is between the fin structure 220B and the fin structure 220C arranged. In the embodiment shown, the fin structure is 220A a dense fin structure (for example, with three fins or more), and the fin structure 220B and the fin structure 220C are isolated fin structures (for example with two fins or less). Although the fin structures 220A - 220C In the embodiment shown, multiple fin structures are contemplated, the present disclosure contemplates embodiments in which the fin structure 220B and / or the fin structure 220C include only one fin. The present disclosure further contemplates embodiments in which the fin structure 220A has more or fewer Finns than in 8th shown. In some implementations, the fin structures are included 220A -220C to different FinFET devices of the integrated circuit device 200 , In some implementations, the fin structures are included 220A - 220C to the same FinFET device of the integrated circuit device 200 , In some implementations, the fin structures are included 220A - 220C to different areas of the integrated circuit device 200 , For example, in some implementations, the fin structure is 220A in an I / O area of the integrated circuit device 200 arranged and the fin structure 220B and / or the fin structure 220C are in a core area of the integrated circuit device 200 arranged.

The fin structure 220A has inter-fins or intermediate fins 222A-1 and intra-Finns or inside Finns 222A-2 on, with the intra-Finns 222A-2 between the inter-fins 222A-1 are arranged. In the embodiment shown, the inter-fins are 22A-1 the outermost fins of the fin structure 220A and the intra-Finns 222A-2 are the inner fins of the fin structure 220A , In some implementations, an inner fin generally refers to a fin that exists between fins of the same fin structure (here the fin structure 220A ), whereas an intermediate fin generally designates a fin formed between a fin of the same fin structure (or FinFET device) and a fin of another fin structure (or FinFET device) (here the fin structure 220B or the fin structure 220C ) is arranged. In some implementations, an inner fin generally designates a fin disposed between fins that share a gate structure and / or a source / drain feature, whereas an intermediate fin generally designates a fin disposed between fins that do not Share gate structure and / or no source / drain feature.

Fin CD optimizing is done by the Finns 222A-1 and the Finns 222A-2 achieved by the fin structure 220A is configured with different critical dimensions. In the embodiment shown, the inter-fins 222A-1 an inter-fin CD and the Intra-Finns 222A-2 an intra-fin CD, where the inter-fin CD is larger than the intra-fin CD. In some implementations, fin CD loading for a dense fin structure is defined as a difference between the inter-fin CD and the intra-fin CD, and the fin-CD loading optimizes the spacing between the fins for etch techniques used during the Gate training can be used when the fin CD load is greater than o (in other words, dense fin CD charge = inter-fin CD - intra-fin CD> o). For example, the inter-fins have 222A-1 one width each W _inter and the intra-Finns 222A-2 each have a width W _intra , If, as in the embodiment shown, the inter-fins 222A-1 have a width that is greater than a width of the intra-fins 222A-2 (in other words W _inter > W _intra ), is a distance S ₁ (Distance) between the intra-Finns 222A-2 smaller as a distance S ₂ between the inter-fins 222A-1 and the intra-Finns 222A-2 (in other words, S ₁ <S ₂ ). In some implementations, the width is W _inter about 1 nm to about 30 nm and the width W _intra about 1 nm to about 30 nm. In some implementations, the distance is S ₁ about 10 nm to about 30 nm and the distance S2 about 10 nm to about 30 nm. The inter-fins 222A-1 each have a height h _inter and the intra-Finns 222A-2 each have a height h _intra , In some implementations, the height is h _inter about 30 nm to about 150 nm and the height behind about 30 nm to about 150 nm. A pitch P of the fin structure 220A generally refers to a sum of a width w of the fins (which together are the inter-fins 222A-1 and the intra-Finns 222A-2 include) and the distance S between adjacent fins (in other words P = w + S). In the illustrated embodiment, a pitch Pintra of the fin structure 220A generally to a center-to-center distance between the intra-fins 222A-2 and a center distance P _inter the fin structure 220A generally refers to a sum of a center-to-center distance between one of the inter-fins 222A-1 and the adjacent inner fin 222A-2 , In some implementations, the pitch Pintra is about 10 nm to about 50 nm and the pitch P _inter about 30 nm to about 600 nm. In some implementations, the pitch is pintra and the pitch P _inter equal (for example, P _intra = P _intra ). In some implementations, the pitch is pintra and the pitch P _inter differently. For example, in some implementations, the pitch is P _intra greater than the center distance P _inter , In some implementations, the pitch is P _intra and / or the center distance P _inter equivalent to a minimum fin pitch ( P _m ). In some implementations, the minimum fin center-to-center spacing generally indicates a minimum fin center distance achievable by a lithography process and / or a fin fabrication process (the deposition, lithography, and / or etching process) of a given IC technology node. In some implementations, the minimum fin pitch generally refers to a smallest fin pitch that is dictated by design requirements for the integrated circuit device 200 is specified.

In continuation of the embodiment shown have the inter-fins 222A-1 an adjacent inter-fin pitch ( P _{inter-adjacent} ) and the intra-Finns 222A-2 an adjacent intra-fin center distance ( P _{intra-adjacent} ), which may be configured to further optimize gaps between fins for etching processes used during gate formation as described above. The adjacent inter-fin pitch is a sum of the center distance of an intermediate fin to a right fin and the center distance of the intermediate fin to a left fin. The center distance of the right fin ( P _R-inter ) of an intermediate fin defines a distance between a center of an intermediate fin and a center of an adjacent (adjacent) fin, which is located to the right of the fin, and a left fin pitch ( P _L-inter ) of an intermediate fin defines a distance between a center of an intermediate fin and a center of an adjacent (adjacent) fin disposed to the left of the fin. One of the center distance of the left fin of an intermediate fin and the center distance of the right fin of an intermediate fin is defined between an intermediate fin and an inner fin of the same fin structure, while the other of the center distance of the left fin of an intermediate fin and the center distance the right fin of an intermediate fin is defined between the intermediate fin and a fin of another fin structure. An adjacent intra-fin center distance is a sum of a center distance of the right fin of the inner fin and a center distance of the left fin of the inner fin. The center distance of the right fin ( P _{R intra} ) an inner fin defines a distance between a center of an inner fin and a center of an adjacent (adjacent) fin, which is located to the right of the inner fin, and a left fin pitch ( P _L-intra ) of an inner fin defines a distance between a center of an inner fin and a center of an adjacent (adjacent) fin located to the left of the inner fin. The center distance of the left fin of the inner fin and the center distance of the right fin of Inside fin are defined between fins of the same fin structure. In the embodiment shown, the inter-fins 222A-1 an adjacent inter-fin pitch greater than or equal to three times a minimum fin pitch (in other words, P is _{inter-adjacent} ≥ 3P _m ), and the intra-fins 222A-2 an adjacent intra-fin pitch that is less than or equal to twice a minimum fin pitch (in other words, P is _{intra-adjacent} ≤ 2Pm). For example, has the leftmost intermediate fin 222A-1 the fin structure 220A a center distance of the left fin equal to twice the minimum fin pitch (P _{L -inter} = 2P _m ), and a pitch of the right fin equal to the minimum fin pitch (P _{R -inter} = P _m ) such that the adjacent fin center distance of the intermediate fin is equal to three times the minimum fin center distance (in other words, P is _{inter-adjacent} = 2P _m + P _m = 3P _m ). In some implementations, the center distance of the left fin is the leftmost intermediate fin 222A-1 greater than twice the minimum fin center distance and / or the center distance of the left fin of the leftmost intermediate fin 222A-1 is smaller than that minimum fin center distance. In contrast, one of the intra-Finns 222A-2 a center distance of the left fin, which is equal to the minimum fin center pitch (P _L-intra = P _m ), and a center distance of the right fin, which is equal to the minimum fin pitch (P _R-intra = P _m ), such that the adjacent fin center distance of the inner fin is equal to twice the minimum fin center distance (in other words, P _{intra-adjacent} = Pm + Pm = 2P _m ). In some implementations, the center distance of the left fin and / or the center distance of the right fin of the inner fin 222A-2 less than the minimum fin pitch.

The present disclosure contemplates variations in the height, width and / or length of the inter-fins 222A-1 and the intra-Finns 222A-2 arising from the processing and manufacture of the integrated circuit device 200 can result. In the embodiment shown, the inter-fins 222A-1 and the intra-Finns 222A-2 tapered widths along their respective height, wherein the width W _inter and the width W _intra each represent an average of the varying widths. For example, the widths of the inter-fins decrease 222A-1 and / or the intra-Finns 222A-2 from lower sections of the inter-fins 222A-1 and / or the intra-Finns 222A-2 to upper sections of the inter-fins 222A-1 and / or the intra-Finns 222A-2 such that the average widths of the upper portions are smaller than the average widths of the lower portions. In some implementations, the widths may be from about 5 nm to about 15 nm along the inter-fins 222A-1 and / or the intra-Finns 222A-2 vary, depending on where the widths are along the height of the inter-fins 222A-1 and the intra-Finns 222A-2 be measured. Although the inter-fins 222A-1 and the intra-Finns 222A-2 The inter-fins are shown to have tapered widths 222A-1 and / or the intra-Finns 222A-2 in some implementations, essentially the same width along their respective height.

The present disclosure provides many different embodiments. An exemplary integrated circuit device includes a core region that includes a first multiple fin structure and an input / output region that includes a second multiple fin structure. The first multiple fin structure has a first width and the second multiple fin structure has a second width, wherein the first width is greater than the second width. In some implementations, the first multiple fin structure has a first fin spacing, and the second multiple fin structure has a second fin spacing, wherein the first fin spacing is less than the second fin spacing. In some implementations, the first multiple fin structure has two fins or less and the second multiple fin structure has three fins or more. In some implementations, a first pitch of adjacent fins of the first multiple fin structure is greater than or equal to three times a minimum fin pitch and a second pitch of adjacent fins of the second multiple fin structure is less than or equal to twice the minimum fin pitch. In some implementations, the first multiple fin structure and the second multiple fin structure include fins of tapered width.

In some implementations, the second multiple fin structure includes an intermediate fin having an inter-fin width and an inner fin having an intra-fin width, wherein the inter-fin width is larger than the intra-fin width. In some implementations, the intermediate fin has a pitch of adjacent fins of the intermediate fin that is greater than or equal to three times a minimum fin pitch. In some implementations, the inner fin has a pitch of adjacent fins of the inner fin that is less than or equal to twice the minimum fin center distance. In some implementations, the integrated circuit device further includes a first gate structure disposed over the first multiple fin structure and a second gate structure disposed over the second multiple fin structure. In some implementations, the core region further includes a third multiple fin structure having a third width greater than the second width, and further wherein a distance between the first multiple fin structure and the third multiple fin structure is greater than or equal to twice a minimum fin Middle distance is.

Another exemplary integrated circuit device includes a multi-fin structure disposed over a substrate, wherein the multiple fin structure includes intra-fins interposed between inter-fins. The inter-fins have an inter-fin width and the intra-fins have an intra-fin width, with the inter-fin width being greater than the intra-fin width. The inter-fins have a pitch of adjacent fins of the inter-fins that is greater than or equal to three times a minimum fin pitch. The intra-fins have a pitch of adjacent fins of the intra-fins that is less than or equal to twice the minimum fin-center pitch. In some implementations, the multiple fin structure is arranged in an input / output area. In some implementations, the adjacent center distance of the intra-fins includes a first center distance between a first inner fin of the intra-fins and a second inner fin of the intra-fins and a second center distance between the first inner fin and a third inner fin the Intra-Finns. In such implementations, the first pitch and the second pitch are equal to the minimum fin pitch. In some implementations, the integrated circuit device further includes a gate structure disposed over the multiple fin structure, wherein the gate structure traverses the multiple fin structure. In some implementations, the inter-fins and the intra-fins have tapered widths. In some implementations, the integrated circuit device further includes a multiple fin structure disposed in a first region. In such implementations, the adjacent center-to-center spacing of the intermediate fin comprises a first pitch between an intermediate fin of the inter-fins and an adjacent inner fin of the intra-fins and a second pitch between the intermediate fin and a fin in a second Area is arranged, which is adjacent to the first area. The first pitch is equal to the minimum fin pitch. The second center distance is greater than or equal to twice the minimum fin center distance. In some implementations, the first area is an input / output area and the second area is a logic area.

An exemplary method includes forming a first multiple fin structure in a core region, forming a second multiple fin structure in an edge region, and forming a first gate structure over the first multiple fin structure and a second gate structure over the second multiple fin structure. The first multiple fin structure has a first width. The second multiple fin structure has a second width. The first width is greater than the second width. In some implementations, the first multiple fin structure has two fins or less and the second multiple fin structure has three fins or more. In some implementations, a first pitch of adjacent fins of the first multiple fin structure is at least three times a minimum fin pitch and a second pitch of adjacent fins of the second multiple fin structure is less than or equal to twice the minimum fin pitch. In some implementations, the first multiple fin structure and the second multiple fin structure are formed simultaneously. In some implementations, forming the first multiple fin structure and forming the second multiple fin structure comprises forming a patterned mask layer over a substrate, wherein the patterned mask layer includes first openings for defining the first multiple fin structure and second openings for defining the second multiple fin structure. Fin structure, and etching through the first openings and the second openings in the patterned mask layer exposed substrate. In some implementations, the first gate structure and the second gate structure include dummy gates, and the method further includes replacing the dummy gates with metal gates.

The foregoing describes features of several embodiments so that one skilled in the art can better understand the aspects of the present disclosure. One skilled in the art should appreciate that the present disclosure may be readily utilized as a basis to design or modify other methods and structures to achieve the same objects and / or to realize the same advantages of the embodiments introduced herein. It should also be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims (20)

Integrated circuit device comprising: a core portion comprising a first multiple fin structure; an input / output area including a second multiple fin structure; and wherein the first multiple fin structure has a first width and the second multiple fin structure has a second width, wherein the first width is greater than the second width. Integrated circuit device according to Claim 1 wherein the first multiple fin structure has a first fin pitch and the second multiple fin structure has a second fin spacing, the first fin spacing being smaller than the second fin pitch. Integrated circuit device according to Claim 1 or 2 wherein: the first multiple fin structure has two fins or less, wherein a first pitch of adjacent fins of the first multiple fin structure is greater than or equal to three times a minimum fin center distance; and the second multiple fin structure has three fins or more, wherein a second center distance of adjacent fins of the second multiple fin structure is less than or equal to twice the minimum fin center distance. Integrated circuit device according to one of the preceding claims, wherein the second Multiple fin structure comprises an intermediate fin having an inter-fin width and an inner fin having an intra-fin width, wherein the inter-fin width is larger than the inter-fin width. Integrated circuit device according to Claim 4 wherein: the intermediate fin has a center distance between an adjacent fin and the intermediate fin that is greater than or equal to three times a minimum fin center distance; and the inner fin has a center distance between an adjacent fin and the inner fin that is less than or equal to twice the minimum fin center distance. The integrated circuit device of any one of the preceding claims, wherein the first multiple fin structure and the second multiple fin structure comprise fins of tapered width. The integrated circuit device of claim 1, further comprising a first gate structure disposed over the first multiple fin structure and a second gate structure disposed over the second multiple fin structure. The integrated circuit device of claim 1, wherein the core region further comprises a third multiple fin structure having a third width greater than the second width, and further wherein a distance between the first multiple fin structure and the third multiple fin structure is greater than or equal to is equal to twice a minimum fin center distance. Integrated circuit device comprising: a multiple fin structure disposed over a substrate, the multiple fin structure having intra-fins interposed between inter-fins; the inter-fins having an inter-fin width and the intra-fins having an intra-fin width, the inter-fin width being greater than the intra-fin width; wherein the inter-fins have a pitch to adjacent fins of the inter-fins that is greater than or equal to three times a minimum fin pitch; and wherein the intra-fins have a center-to-center distance to adjacent fins of the intra-fins that is less than or equal to twice the minimum fin-center distance. Integrated circuit device according to Claim 9 wherein: the multiple fin structure is disposed in a first region; the center distance between an adjacent fin and the inter-fin has a first center distance between an intermediate fin of the inter-fins and an adjacent inner fin of the intra-fins and a second center distance between the intermediate fin and a fin arranged in a second region which is adjacent to the first area; and the first pitch is equal to the minimum fin pitch; and the second pitch is greater than or equal to twice the minimum fin center distance. Integrated circuit device according to Claim 10 wherein the first area is an input / output area and the second area is a logic area. Integrated circuit device according to one of Claims 9 to 11 wherein: the center distance between an adjacent fin and the intra-fin includes a first center distance between a first inner fin and a second inner fin and a second center distance between the first inner fin and a third inner fin of the intra-fins ; and the first center distance and the second center distance are equal to the minimum fin pitch. Integrated circuit device according to one of Claims 9 to 12 wherein the multiple fin structure is arranged in an input / output area. Integrated circuit device according to one of Claims 9 to 13 wherein the inter-fins and the intra-fins have tapered widths. Integrated circuit device according to one of Claims 9 to 14 further comprising a gate structure disposed over the multiple fin structure, wherein the gate structure traverses the multiple fin structure. Method, comprising: Forming a first multiple fin structure in a core region, the first multiple fin structure having a first width; Forming a second multiple fin structure in an edge region, the second multiple fin structure having a second width, and wherein the first width is greater than the second width; and Forming a first gate structure over the first multiple fin structure and a second gate structure over the second multiple fin structure. Method according to Claim 16 , in which: the first multiple fin structure has two fins or less, wherein a first pitch of adjacent fins of the first multiple fin structure is at least three times a minimum fin pitch; and the second multiple fin structure has three fins or more, wherein a second center distance of adjacent fins of the second multiple fin structure is less than or equal to twice the minimum fin center distance. Method according to Claim 16 or 17 wherein the first multiple fin structure and the second multiple fin structure are formed simultaneously. Method according to one of Claims 16 to 18 wherein forming the first multiple fin structure and forming the second multiple fin structure comprises forming a patterned mask layer over a substrate, wherein the patterned mask layer includes first openings for defining the first multiple fin structure and second openings for defining the second multiple fin structure includes; and etching the substrate exposed by the first openings and the second openings in the patterned masking layer. Method according to one of Claims 16 to 19 wherein the first gate structure and the second gate structure comprise dummy gates, and the method further comprises replacing the dummy gates with metal gates.

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