DE102017111540A1 - PROCESS FOR SOURCE AND DRAIN MANUFACTURING FOR FINNEL FIELD EFFECT TRANSISTORS - Google Patents

Abstract

Here, methods for source and drain fabrication for fin field effect transistors (FinFETs) are described. An exemplary method of fabricating epitaxial source / drain features for a FinFET involves epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. The semiconductor material fuses into an epitaxial structure member extending over the plurality of fins, the plurality of fins having a fin pitch that is less than about 25 nm. A ratio of throughput of the silicon-containing precursor to throughput of the chlorine-containing precursor is less than about 5. The method further comprises re-etching the semiconductor material using the chlorine-containing precursor thereby modifying a profile of the epitaxial structural element. Epitaxial growth and re-etching only need to be done once. In some embodiments, where the FinFET is an n-FinFET, a phosphorus-containing precursor is also used for epitaxial growth.

Description

This application is a non-provisional application and claims priority from US Provisional Patent Application No. 62 / 434,608 filed Dec. 15, 2016, which is incorporated by reference.

Background of the invention

The integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and designs have spawned generations of ICs, with each generation having smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per die area) has generally increased while the feature size (i.e., the smallest component or line that can be produced with a fabrication process) has decreased. This process of downsizing generally provides benefits by increasing productivity and reducing associated costs.

However, this downsizing has also increased the complexity of processing and manufacturing ICs, and in order for these advances to be realized, similar developments in IC processing and fabrication are required. For example, as finFET (finFET: field effect transistor) technologies move to smaller feature sizes (such as 32 nanometers, 28 nanometers, 20 nanometers, and smaller), modern methods for accurately controlling profiles and / or dimensions of source / Drain features needed to ensure and / or optimize the reliability of FinFET devices. While existing methods of source and drain fabrication for FinFETs have heretofore been broadly adequate for their purpose, they are not satisfactory in every way.

list of figures

• 1 ist eine vereinfachte schematische Draufsicht (teilweise und vollständig) eines FinFET-basierten SRAM-Bauelements (SRAM: statischer Direktzugriffsspeicher) gemäß verschiedenen Aspekten der vorliegenden Erfindung.
• 2 ist ein Ablaufdiagramm eines Verfahrens zur Herstellung eines integrierten Schaltkreiselements mit FinFET-Bauelementen gemäß verschiedenen Aspekten der vorliegenden Erfindung.
• Die 3A bis 3J sind Teilschnittansichten eines integrierten Schaltkreises mit FinFET-Bauelementen (teilweise oder vollständig) auf verschiedenen Herstellungsstufen, wie etwa denen, die mit dem Verfahren von 2 assoziiert sind, gemäß verschiedenen Aspekten der vorliegenden Erfindung.

The present invention will be best understood from the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, according to common practice in the industry, various elements are not drawn to scale and are only illustrative. Rather, for the sake of clarity of the discussion, the dimensions of the various elements can be arbitrarily increased or reduced.

• 1 FIG. 5 is a simplified schematic plan view (partial and complete) of a FinFET based SRAM (SRAM) device in accordance with various aspects of the present invention.
• 2 FIG. 10 is a flowchart of a method of fabricating an integrated circuit device with FinFET devices according to various aspects of the present invention.
• The 3A to 3J 12 are partial cross-sectional views of an integrated circuit with FinFET devices (partially or completely) at various stages of fabrication, such as those obtained by the method of FIG 2 according to various aspects of the present invention.

Detailed description

The present invention relates generally to integrated circuit elements, and more particularly to fin field effect transistors (FinFETs).

The following description provides many different embodiments or examples for implementing various features of the invention. Hereinafter, specific examples of components and arrangements will be described in order to simplify the present invention. Of course these are just examples and should not be limiting. For example, the fabrication of a first element over or on a second element in the description below may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements are interposed between the first and second elements the second element can be formed so that the first and the second element are not in direct contact.

Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for simplicity and clarity and as such does not dictate any relationship between the various embodiments and / or configurations discussed. In addition, in the present invention described below, fabrication of one element on another element and / or fabrication of an element connected and / or coupled to another element may include embodiments in which the elements are made in direct contact, and it may also include embodiments in which additional elements can be made between the elements so that the elements are not in direct contact Contact are. Moreover, to simplify the description of the relationship of one element to another element, spatially relative terms such as "lower,""upper,""horizontal,""vertical,""above,""above,""below,"" under "," up "," down "," up "," down "etc., as well as their derivatives (eg the adverbs" horizontal "," down "," up ", etc.) , The spatially relative terms are intended to cover various orientations of the device comprising the structural elements.

1 is a simplified schematic plan view (partial and complete) of an SRAM device 10 according to various aspects of the present invention. In 1 becomes the SRAM device 10 considered in an XY plane at an intermediate stage of manufacturing. The SRAM device 10 may be included in a microprocessor, memory and / or other integrated circuit element. In some embodiments, the SRAM device may 10 be a part of an IC chip, a system on chip (SoC) or a part thereof and include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field effect transistors (PFETs) , N-type field effect transistors (NFETs), metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar-junction transistors (BJTs), laterally diffused MOS transistors (laterally diffused MOS transistors; LDMOS transistors), high voltage transistors, high frequency transistors, other suitable components or combinations thereof. 1 has been simplified for clarity, to better understand the inventive idea of the present invention. For the SRAM device 10 For example, other structural elements may be used, and some of the structural elements described below may be used in other embodiments of the SRAM device 10 replaced, modified or omitted.

The SRAM device 10 has various areas, such as a first area 12 , a second area 14 and a third area 16 according to the requirements of the design of the SRAM device 10 are configured. In the illustrated embodiment, the first area is 12 configured as an n-type device region, the second region 14 is also configured as an n-type device region, and the third region 16 is configured as a p-type device region. For example, the first area points 12 a pull-down FinFET (PD), the second area 14 also has a pull-down FinFET (PD), and the third area 16 has a pull-up FinFET (PU). In support of the illustrated embodiment, the pull-down FinFETs are in the first region 12 and the second area 14 configured as n-type FinFETs, while the pull-up FinFET is configured in the third range 16 is configured as a p-FinFET. In some embodiments, according to the design requirements of the SRAM device 10 one or more pass-gate FinFETs (not shown) and / or other functional FinFETs in the first region 12 , the second area 14 the third area 16 and / or another area.

The SRAM device 10 has different fins 20A . 20B . 20C . 20D and 20E (also referred to as active fin areas) located above a substrate 25 are arranged. Finns 20A to 20E are aligned substantially parallel to one another, each having a width defined in an X-direction, a length defined in a Y-direction, and a height (not shown) defined in a Z-direction. In 1 indicates the pull-down transistor in the first area 12 the Finn 20A and the Finn 20B on, the pull-down transistor in the second area 14 instructs the Finn 20C and the Finn 20D on, and the pull-up transistor in the third area 16 instructs the Finn 20E (in other words, the pull-down transistors are multi-finned FinFETs, while the pull-up transistor is a single-ended FinFET). Finns 20A to 20E each have a channel region, a source region and a drain region defined along their length in the Y direction, the channel region between the source region and the drain region (generally as source / drain regions) is designated) is arranged. In some embodiments, the fins are 20A to 20E a part of the substrate 25 (Such as a part of a material layer of the substrate 25 ). Alternatively, in some embodiments, the fins are 20A to 20E in a layer of material, such as one or more layers of semiconductor material, over the substrate 25 Are defined. In some embodiments, the fins are 20A to 20E over doped areas of the substrate 25 according to the configuration of the first area 12 , the second area 14 and / or the third area 16 arranged. For example, the Finns 20A to 20D be arranged over p-doped regions (wells), which are located in the substrate 25 in the first area 12 and the second area 14 are located while the Finn 20E may be disposed over an n-doped region (well) located in the substrate 25 in the third area 16 located.

Above the channel areas of the fins 20A to 20E are gate structures 30A . 30B , 30C and 30D. In some embodiments, the gate structures 30A-30D enclose the channel regions of the fins 20A to 20E , causing the Source / drain regions of the fins 20A to 20E be layered in between. In the illustrated embodiment, the gate structures extend 30A to 30D along the X direction (for example, substantially perpendicular to the fins 20A to 20E ). The gate structures 30A to 30D are in contact with the channel areas of the fins 20A to 20E such that, during operation, a current flows between the source / drain regions of the fins 20A to 20E can flow. The gate structures 30A to 30D have gate stacks that are configured according to whether the SRAM device 10 is made by the gate-last method or the gate-first method. In the illustrated embodiment, the SRAM device becomes 10 made with the gate-last method, in which the gate structures shown 30A to 30D Have dummy gate stack, which are then replaced by metal gate stack. The dummy gate stacks have, for example, an intermediate layer and a dummy gate electrode layer. The intermediate layer is between the dummy gate electrode layer and the fins 20A to 20E wherein the interlayer and the dummy gate electrode layer are configured to match the channel regions of the fins 20A to 20E enclose. In some embodiments, the interlayer comprises a dielectric material, such as silicon oxide, and the dummy gate electrode layer comprises polysilicon or other suitable dummy gate material. In some embodiments, the dummy gate stack further includes a dummy gate dielectric layer sandwiched between the barrier layer and the dummy gate electrode layer. The dummy gate dielectric layer may comprise a dielectric material (eg, silicon oxide), a high-k dielectric material, another suitable dielectric material, or a combination thereof. Examples of the high-k dielectric material are HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconia, alumina, hafnia-alumina (HfO ₂ -Al ₂ O ₃ ) alloy, other suitable high-k dielectric materials or combinations thereof. In some embodiments, the interlayer is removed from the dummy gate stack so that the dummy gate dielectric layer is between the fins 20A to 20E and the dummy gate electrode layer is layered. The dummy gate stacks may comprise numerous further layers, for example an interlayer, a capping layer, a diffusion layer, a barrier layer, a hardmask layer, other suitable layers or combinations thereof. In some embodiments, the gate structures 30A to 30D Spacers, which are arranged adjacent to the dummy gate stack. The spacers comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable dielectric materials, or combinations thereof. In some embodiments, the spacers include more than one group of spacers (eg, seal spacers, offset spacers, and dummy spacers). In some embodiments, the spacers have a multi-layer structure, such as a silicon nitride layer and a silicon oxide layer. The spacers are manufactured by a suitable method. For example, a silicon oxide layer may be deposited over the fins 20A-20D and then anisotropically etched (eg, dry-etched) to form a first set of spacers (such as seal spacers) adjacent the dummy gate stacks, and a silicon nitride layer may overflow the Finns 20A to 20D are deposited and then etched (e.g., dry etched) to form a second set of spacers (such as offset spacers or dummy spacers) adjacent the first set of spacers.

Although not shown, a gate replacement process is eventually performed to surround the dummy gate stacks of the gate structures 30A to 30D to replace with metal gate stacks. In gate-first method embodiments, the illustrated gate structures include 30A to 30D Metal gate stack. The metal gate stacks include, for example, a gate dielectric layer (which may include similar materials as the interlayer and / or the dummy gate electrode layer) and a gate electrode layer disposed over the gate dielectric layer. The gate electrode layer comprises a conductive material such as polysilicon, Al, Cu, Ti, Ta, W, Mo, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other conductive materials or Combinations of it. In some embodiments, the gate electrode layer includes a work function layer that is a conductive layer configured to have a desired work function (such as an n work function or a p work function) and a conductive layer that over the work function layer is made (sometimes also referred to as metal filling layer). In various examples, the work function layer comprises Ta, TaN, NiSi, CoSi, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, other materials suitable for achieving a desired work function, or combinations thereof. The conductive layer formed over the work function layer comprises a suitable conductive material, such as Al, W, Cu, or a combination thereof. The conductive layer may additionally or alternatively comprise polysilicon, Ti, Ta, metal alloys, other suitable materials, or combinations thereof. The metal gate stacks may comprise a plurality of further layers, for example an intermediate layer, a cover layer, a diffusion layer, a barrier layer, a Hard mask layer, other suitable layers or a combination thereof.

Over the source / drain regions of the fins 20A to 20D are epitaxially grown structural elements 40A . 40B . 40C . 40D . 40E and 40F arranged. In the illustrated embodiment, the epitaxially grown structural elements 40A to 40F over the source / drain regions of the fins 20A to 20D after a fin recessing process (eg, an etch back process), so that the epitaxial structural elements 40A to 40F from the recessed fins 20A to 20D be grown up. In some embodiments, the epitaxial structural elements enclose 40A to 40F the source / drain regions of the fins 20A to 20D , In these embodiments, the fins need 20A to 20D to undergo no fin-saving process. The epitaxial structural elements 40A to 40F are for n-type devices, such as the pull-down transistors in the first region 12 and the second area 14 , configured so that the epitaxial structural elements 40A to 40F alternatively may be referred to as epitaxial n-type source / drain structure elements. The epitaxial structural elements 40A to 40F For example, silicon or silicon carbon is doped with the silicon or silicon carbon doped with phosphorus, arsenic, other n-dopants, or a combination thereof. In some embodiments, the epitaxial structural elements are 40A to 40F epitaxially grown Si: P structural elements. In some embodiments, the epitaxial structural elements are 40A to 40F epitaxially grown Si: C: P structural elements. The epitaxial structural elements 40A to 40F extend (grow) laterally along the X direction (in some embodiments, substantially perpendicular to the fins 20A to 20D ), wherein the epitaxial structural elements 40A to 40F each have a corresponding transverse dimension a, such as a width of the epitaxial structural elements 40A to 40F , For example, a _{1 represents} a transverse dimension of the epitaxial structural element 40C and a ₂ represents a transverse dimension of the epitaxial structure element 40D represents.

Normally, n-type epitaxial source / drain features become n-type source / drain regions (such as the epitaxial features 40A to 40F ) with a CDE (cyclic deposition etch) method, which is a sequence of deposition processes and etching processes configured to alternately deposit and etch a semiconductor material. Each cycle of the CDE process includes a deposition process and an etch process, where multiple cycles are implemented for the CDE process to fabricate epitaxial source / drain features. In some embodiments, the deposition process is a CVD (Chemical Vapor Deposition) process configured to epitaxially grow a semiconductor material, such as silicon, from source / drain regions of fins. During the CVD process dopants may be added to the semiconductor material. As the thickness of the semiconductor material increases during the CVD process, the semiconductor material often exhibits crystal defects (also referred to as lattice defects) and / or crystal defects. The semiconductor material may, for example, have amorphous (non-crystalline) parts which may affect device performance. In some embodiments, the etching process is a selective etching process that can selectively remove the crystal defects and / or crystal defects, such as the amorphous portions of the semiconductor material. By adjusting various parameters of each CDE cycle (such as the CVD process and the selective etch process), the CDE process has evolved to produce n-type epitaxial source / drain features with minimal defects while achieving the desired voltage characteristics in the Channel area generally proved successful.

As FinFET technologies evolve toward smaller feature sizes (such as 16 nanometers, 10 nanometers, 7 nanometers, and smaller), limiting the lateral growth (and thus transverse dimension a) of epitaxial source / drain features, such as a ₁ and a _{2 of} the epitaxial source / drain structure elements 40A to 40F, vital for ensuring the reliability of the SRAM device 10 , It has been found that conventional CDE methods lack exact profile control in sophisticated FinFET technology nodes, particularly those methods that aim for a fin pitch of less than or equal to about 25 nm. In particular, in conventional CDE methods, the lateral epitaxial growth of the semiconductor material can not be adequately limited, so that large variations in the transverse dimension a of epitaxial source / drain structure elements arise, whereby epitaxial source / drain structure elements of different components can unintentionally merge and / or epitaxial source / drain features inadvertently into areas of a device (such as the SRAM device 10 ), which can damage the epitaxial source / drain features during fabrication. If, for example, in 1 a _{1 of} the epitaxial structural element 40C and a _{2 of} the epitaxial structural element 40D can not be properly limited, the epitaxial structural element 40C with the epitaxial structural element 40D fuse, resulting in an electrical short between the pull-down transistor of the first range 12 and the pull-down transistor of the second region 14 leads. In another example, if in 1 a _{2 of} the epitaxial structural element 40D is not properly limited, the epitaxial structural element 40D in an etching process window 50 into it, to the exclusion of the Finn 20E in the third area 16 is used, so that the epitaxial structural element 40D subjected to an etching process, which is to save the fin 20E is used, whereby the epitaxial structural element 40D is damaged. In some embodiments, the epitaxial structural element 40D into a process window for performing an epitaxial source / drain fabrication process on the fin 20E in the third area 16 is used so that the epitaxial structure element 40D is exposed to semiconductor materials (such as those used for a p-type device), which functions as the pull-down transistor in the second region 14 change and / or affect. Therefore, sophisticated epitaxial source / drain fabrication processes are needed to provide accurate profile control of epitaxial source / drain features with minimal width variation.

2 is a flowchart of a method 100 for producing an integrated circuit element according to various aspects of the present invention. In the present embodiment, the method 100 made an integrated circuit element having a FinFET device. In the block 110 For example, a first fin and a second fin are made over a substrate. The first and second fins have a fin pitch of less than about 25 nm. The first and second fins each have a channel region disposed between a source region and a drain region. In the block 120 For example, a gate structure is fabricated over the channel regions of the first and second fins. In some embodiments, the gate structure includes a dummy gate stack. In the block 130 For example, a combination of a deposition process and an etching process is performed only once to produce a fused epitaxial source structure extending across the source regions of the first and second fins and a fused epitaxial drain structure extending across the fused surface Drain regions of the first and second fin extends. In some embodiments, the deposition process comprises epitaxially growing a semiconductor material on the first and second fins using a silicon-containing precursor and a chlorine-containing precursor [eg, hydrogen chloride (HCl)]. The ratio of the silicon-containing precursor flow rate to the chlorine-containing precursor throughput is less than about 5. In some embodiments, the chlorine-containing precursor is used for the etching process, thereby modifying the profile of the fused epitaxial source structural element and the fused epitaxial drain structural element. In some embodiments, a dopant-containing precursor, such as a phosphorus-containing precursor, is also used for the deposition process, thereby doping the fused epitaxial source structure element and the fused epitaxial drain structure element. In the block 140 can the procedure 100 continue with the completion of the production of the integrated circuit element. For example, in some embodiments, a gate replacement process is performed to replace the dummy gate stack with a metal gate stack. Further steps may be provided before, during, and after method 100, and some of the steps described may be used in other embodiments of the method 100 moved, replaced or omitted.

The 3A to 3J are partial sectional views of an integrated circuit element 200 (partially or completely) at different stages of production (such as those with the method 100 according to various aspects of the present invention. The integrated circuit element 200 may be included in a microprocessor, memory and / or other circuit element. In some embodiments, the integrated circuit element 200 may be part of an IC chip, a SoC or a part thereof, and include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, PFETs, NFETs, MOSFETs, CMOS transistors, BJTs, LDMOS transistors, high voltage transistors , High frequency transistors, other suitable components or combinations thereof. The 3A to 3J have been simplified for clarity, to better understand the inventive idea of the present invention. In the integrated circuit element 200 For example, other structural elements may be used, and some of the structural elements described below may be used in other embodiments of the integrated circuit element 200 replaced, modified or omitted.

In 3A has the integrated circuit element 200 a substrate (wafer) 210 on. In the illustrated embodiment, the substrate 210 Silicon on. Alternatively or additionally, the substrate comprises 210 The following: another elemental semiconductor such as germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor such as silicon germanium (SiGe), GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; or combinations thereof. Alternatively, the substrate 210 a semiconductor-on-insulator substrate, such as an SOI substrate (SOI: silicon on insulator), an SGOI substrate (SGOI: silicon germanium on insulator) or a GOI substrate (GOI: germanium on insulator Germanium on insulator). Semiconductor-on-insulator substrates can be made by oxygen implantation (SIMOX) separation, wafer bonding, and / or other suitable methods. The substrate 210 may have different doped regions (not shown) depending on the design requirements of the integrated circuit device 200. In some embodiments, the substrate 210 p-type doped regions (eg, p-wells) doped with p-type dopants, such as boron, indium, other p-type dopants, or a combination thereof. In some embodiments, the substrate 210 n-type doped regions (eg, n-type wells) doped with n-type dopants such as phosphorus, arsenic, other n-type dopants, or a combination thereof. In some embodiments, the substrate 210 doped regions made with a combination of p-type dopants and n-type dopants. The various doped regions may be directly on and / or in the substrate 210 by, for example, providing a p-well structure, an n-well structure, a dual well structure, a raised structure, or a combination thereof. For producing the various doped regions in the substrate 210 For example, an ion implantation process, a diffusion process, and / or other suitable doping processes may be performed.

In the substrate 210 different areas are defined, such as a first area 212 , a second area 214 and a third area 216 , For the purposes of the discussion below, the first area is 212 configured as an n-type FinFET region, the second region 214 is also configured as an n-type FinFET region, and the third region 216 is configured as a p-type FinFET region. Doped areas on and / or in the substrate 210 are configured to accommodate the functionality of devices and / or features that are in the first region 212 , the second area 214 and the third area 216 are made. In some embodiments, the first region is formed 212 , the second area 214 and the third region 216 forms part of a memory area of the integrated circuit element 200 such as an SRAM area. For example, in the illustrated embodiment, the first region 212 comprises a pull-down FinFET, the second region 214 also has a pull-down FinFET, and the third area 216 has a pull-up FinFET. In these embodiments, the pull-down FinFETs are in the first region 212 and the second area 214 configured as n-type FinFETs, while the pull-up FinFET is configured in the third range 216 is configured as a p-FinFET. In some embodiments, the first region 212 corresponds to the second region 214 and the third area 216 the first area 12 , the second area 14 or the third area 16 of the SRAM device 10 from 1 , In some embodiments, one or more pass-gate FinFETs may be in the first region 212 , the second area 214 the third area 216 and / or another region included in the substrate 210 is defined. This configuration of the integrated circuit element 200 is for simplicity and understanding and does not necessarily limit the illustrated embodiment to a number of components, a number of ranges, or a configuration of structures and / or portions. For example, the integrated circuit element 200 further comprise one or more regions, depending on the design requirements of the integrated circuit element 200 are configured as a logic area, another memory area, an analog area, an input / output area (or peripheral area), a dummy area, or another area.

Above the substrate 210 becomes a fin structure 220 produced. In 3A has the fin structure 220 a variety of fins coming from the substrate 210 Although the present invention contemplates embodiments in which the fin structure 220 has only a single fin coming from the substrate 210 going on. For example, the fin structure indicates 220 Finns 222A in the first area 212 , Finns 222B in the second area 214 and a Finn 222C in the third area 216 on. In itself is the fin structure 220 configured to be a multi-finned FinFET in the first region 212, a multi-finned FinFET in the second region 214 and an introducing FinFET in the third region 216 Although the present invention contemplates different numbers of fins in the first range, it does take account 212 , the second area 214 and the third area 216 considers the performance of the integrated circuit element 200 to optimize. In some embodiments, the fin structure is 220 a portion of the substrate 210 (such as a portion of a material layer of the substrate 210 ). For example, in the illustrated embodiment, the substrate has 210 Silicon, including the fin structure 220 Silicon on. Alternatively, in some embodiments, the fin structure is 220 in a material layer, such as a semiconductor material layer, over the substrate 210 Are defined. In these embodiments, the fin structure 220 a semiconductor layer stack (for example, a heterostructure) having different semiconductor layers. The semiconductor layers comprise a suitable material, such as such as silicon, germanium, silicon germanium, other suitable materials, or a combination thereof. The semiconductor layers may vary depending on the design requirements of the integrated circuit element 200 have the same or different materials, dopants, etch rates, atomic percentages of their constituents, mass percentages of their constituents, thicknesses, and / or configurations.

Finns 222A , Finns 222B and the Finn 222C have a width defined in an X direction, a length defined in a Y direction (not shown), and a height defined in a Z direction. For example, the Finns have 222A a height h ₁ , a width w ₁ defined by a pair of side walls, and a length l ₁ defined by a pair of side walls (not shown in the illustrated view). Finns 222B have a height h ₂ , a width w ₂ defined by a pair of sidewalls, and a length l ₂ defined by a pair of sidewalls (not shown in the view shown). The Finn 222C has a height h ₃ , a width w ₃ defined by a pair of side walls, and a length l ₃ defined by a pair of side walls (not shown in the view shown). In some embodiments, the height h is about 10 nm to about 200 nm, and the width w ₁ is about 5 nm to about 50 nm. For example, in the illustrated embodiment, the height h is about 20 nm to about 40 nm, and the width w ₁ is about 5 nm to about 10 nm. Neighboring fins 222A are separated by a gap S ₁ , wherein a distance P _{1 of} the fins 222A generally the sum of a width of a special fin 222A (such as the width w ₁ ) and a width of a gap referred to the special fin 222A adjacent (such as S ₁ ) (in other words P ₁ = w ₁ + S ₁ ). Neighboring Finns 222B are separated by a gap S ₂ , wherein a distance P2 of the fins 222B generally the sum of a width of a special fin 222B (such as the width w ₂ ) and a width of a gap referred to the special fin 222B adjacent (such as S ₂ ) (in other words P ₂ = w ₂ + S ₂ ). The gap S ₁ and / or the gap S ₂ are less than about 25 nm, so that the distance P ₁ and / or the distance P2 are smaller than about 75 nm. For example, the gap S ₁ and / or the gap S _{2 are} about 5 nm to about 15 nm, and the pitch P ₁ and / or the pitch P2 are about 10 nm to about 75 nm. In some embodiments, the pitch P ₁ and / or the distance P2 is the minimum distance between the fins 222A and the fins 222B can be achieved with a lithographic process for a given technology node. In embodiments where the third region 216 is more than one fin 222C may have adjacent fins 222C be separated by a defined gap, such as a gap S ₃ , wherein a distance P _{3 of} the fins 222C generally the sum of a width of a special fin 222C (such as the width w ₃ ) and a width of a gap referred to the special fin 222C adjacent (such as S ₃ ) (in other words P ₃ = w ₃ + S ₃ ). The present invention contemplates variations in the height, width and length of the fins 222A , the Finn 222B and / or the Finn 222C that can result from machining and manufacturing.

A combination of deposition, lithographic and / or etching processes is performed to control the fin structure 220 to define that of the substrate 210 going off, like in 3A is shown. The manufacture of the fin structure 220 For example, performing a lithographic process to form a patterned resist layer over the substrate 210 (or a layer of material over the substrate 210 arranged), and performing an etching process to form a structure defined in the patterned resist layer on the substrate 210 (or the material layer over the substrate 210 is arranged) to transfer. The lithographic process may include forming a resist layer on the substrate 210 (for example by spin coating), performing a pre-cure process, performing an exposure process using a mask, performing a post-cure process, and performing a development process. During the exposure process, the resist layer is irradiated with a radiant energy [such as ultraviolet light (UV light), deep UV light (DUV) or extreme UV light (EUV)], the mask depending on its structure and / or Art (for example, binary mask, phase shift mask or EUV mask) blocks the radiation and / or transmits to the resist layer and / or reflected by it, so that an image is projected onto the resist layer corresponding to the mask structure. Since the resist layer is sensitive to the radiant energy, irradiated portions of the resist layer chemically change, and depending on the properties of the resist layer and the properties of a developing solution used in the development process, irradiated (or non-irradiated) portions of the resist layer of the development process dissolved. After development, the patterned resist layer has a structure corresponding to the mask. In the etching process, parts of the substrate become 210 removed, wherein for the etching process, the patterned resist layer is used as an etching mask. The etching process may be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. In some embodiments, an RIE process (RIE: reactive ion etching). After the etching process, the patterned resist layer of the substrate 210 removed, for example, by a resist removal process. Alternatively, the fin structure becomes 220 fabricated with a multiple patterning process, such as a lithographic double-structuring (DPL) process [e.g., a lithographic etching-lithography-etching process (LELE process), a self-aligned double-patterning (SADP) process; , a SID-SADP process (SID: spacer is a dielectric), another double-structuring process, or a combination thereof], a triple-structuring process [for example, a lithography-etching-lithography-etching-lithography-etching process (LELELE Process), a self-aligned triple structuring process (SATP process), another triple structuring process, or a combination thereof], another multiple structuring process [for example, a self-aligned quadruple structuring (SAQP) process, or a combination thereof. In some embodiments, DSA (Directed Self-Assembly) methods are used in making the fin structure 220 implemented. Moreover, in some alternative embodiments in the exposure process, maskless lithography, electron beam writing, ion beam writing, and / or nanoimprinting technology may be used to pattern the resist layer.

Over and / or in the substrate 210 become one or more separators 230 made to various areas, such as various device areas, of the integrated circuit element 200 to separate. For example, the separator separates 230 the first area 212 , the second area 214 and the third area 216 spatially and electrically from each other. The separating element 230 separates also the Finns, like the Finns 222A and the Finns 222B , the fin structure 220 spatially and electrically in each area. In the illustrated embodiment, the separating element encloses 230 a part of the fin structure 220 , such as a lower part. The separating element 230 comprises silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable separator, or a combination thereof. The separating element 230 may have different structures, such as STI structures (STI: shallow trench isolation), DTI (deep trench isolation) structures, and / or LOCOS (local oxidation of silicon) structures. In some embodiments, the separator comprises 230 STI structural elements, the active and / or passive device regions, such as the first region 212 , the second area 214 and the third area 216 , define and disconnect electrically. The STI structural elements may be, for example, by etching a trench in the substrate 210 (for example by means of a dry etching process and / or a wet etching process) and by filling the trench with an insulating material (for example by means of chemical vapor deposition or a spin-on-glass process). A chemical mechanical polishing (CMP) may be performed to remove excess insulating material and / or the top of the separator 230 to planarize. In another example, STI structural elements may be made by following the fabrication of the fin structure 220 an insulating material over the substrate 210 is deposited [in some embodiments so that the insulating material layer gaps (trenches) between the fins 222A , the Finns 222B and the Finns 222C füllt] and the insulating material layer is etched back, so that the separating element 230 arises. In some embodiments, the STI structural elements have a multilayer structure that fills the trenches, such as a silicon nitride layer disposed over a thermal oxide capping layer. In another example, the STI features have a dielectric layer disposed over a doped capping layer [such as a borosilicate glass (BSG capping) or phosphosilicate glass (PSG) capping layer). In yet another example, the STI structural elements have a solid dielectric layer disposed over a dielectric capping layer, the solid dielectric layer and the dielectric capping layer having materials that are dependent on the design requirements.

Finns 222A , Finns 222B and the Finn 222C each have a channel region, a source region, and a drain region defined along their length (here along the Y direction), the channel region between the source region and the drain region (collectively referred to as source / drain Areas) is arranged. The source / drain regions of the fins 222A , the Finn 222B and the Finn 222C are in the 3A to 3J shown. About parts of the Finns 222A , the Finn 222B and the fin 222C is a gate structure (not shown). For example, the gate structure encloses the channel regions of the fins 222A , the Finn 222B and the Finn 222C , whereby the source / drain regions of the fins 222A , the Finn 222B and the Finn 222C be layered in between. In some embodiments, the gate structures come into contact with the sidewall portions of the channel regions and an upper portion of the channel regions defined between the sidewall portions such that the gate structure contacts three sides of the channel regions of the fins 222A , the Finn 222B and the Finn 222C comes. In some embodiments the gate structures the gate structures 30A to 30D similar to the above with reference to 1 have been described. In the illustrated embodiment, the integrated circuit element becomes 200 for example, with a gate-last method, so that the gate structures have a dummy gate stack, as described in more detail above. The gate structures are made by a combination of deposition, lithographic, and / or etching processes, other suitable processes, or a combination thereof. For example, a deposition process may be performed to form an intermediate layer over the substrate 210 , especially over the fin structure 220 (here the Finns 222A , Finns 222B and the Finn 222C ) and the separating element 230 , and another deposition process may be performed to fabricate a dummy gate electrode layer over the intermediate layer. In some embodiments, a deposition process is performed to fabricate a dummy gate dielectric layer over the interface layer before the dummy gate electrode layer is fabricated. Deposition processes include CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high density plasma (CVD) chemical vapor deposition, metal-organic chemical vapor deposition (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), gravure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure chemical vapor deposition (APCVD), plating, other suitable methods or a combination from that. Thereafter, a process of lithographic patterning and etching may be performed to pattern the interlayer and the dummy gate dielectric layer (and in some embodiments, the dummy gate electrode layer) to form the dummy gate stack. The lithographic patterning processes include resist coating (for example, spin coating), precuring, mask alignment, exposure, post-exposure curing, resist development, rinsing, drying (for example, post cure), other suitable methods, or a combination thereof. Alternatively, the lithographic exposure is assisted, implemented or replaced by other methods such as maskless lithography, electron beam writing or ion beam writing. In yet other embodiments, nanoimprint technology is used for lithographic patterning. The etch processes include dry etch processes, wet etch processes, other etch processes, or a combination thereof.

In the 3B to 3F For example, epitaxial source and epitaxial drain features (referred to herein as epitaxial source / drain features) are in the source / drain regions of n-type FinFET regions, such as the first region 212 and the second region 214 , produced. In the 3B and 3C For example, processing involves sparing the source / drain regions of the fins in the n-type device regions, such as the first region 212 and the second area 214 , of the integrated circuit element 200 further. In 3B is above the substrate 210 (In the illustrated embodiment, over the separating element 230 ) a mask layer 240 made, and over the mask layer 240 becomes a structured resist layer 245 produced. The mask layer 240 has a material that has a different etch rate than the material of the fin structure 220 (especially the Finns 222A and the Finns 222B ) Has. The mask layer 240 For example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbon nitride, amorphous silicon, polysilicon, other suitable materials, or a combination thereof. In the illustrated embodiment, the mask layer 240 Silicon nitride on. In some embodiments, the mask layer 240 comprises a material having a lower etch rate than the material of the fin structure 220 so that the Finns 222A and the Finns 222B opposite the mask layer 240 can be selectively etched. The mask layer 240 is prepared by a suitable method, such as a CVD method, having a suitable thickness. In some embodiments, a silicon and nitrogen-containing mask layer is made by LPCVD. In some embodiments, a silicon and nitrogen-containing mask layer is made by performing a process that includes thermally nitriding the silicon-containing layer. In some embodiments, a pad layer (eg, a silicon oxide layer) is interposed between the mask layer 240 and the substrate 210 (In particular the separating element 230 ) produced.

The structured resist layer 245 has an opening, the n-type device regions, such as the first region 212 and the second area 214 , of the integrated circuit element 200 while the p-type device regions of the integrated circuit element 200 , such as the third area 216 stay covered. The structured resist layer 245 is also referred to as a photoresist layer, photosensitive layer, imaging layer, patterning layer or radiation-sensitive layer. The structured resist layer 245 is above the substrate 210 produced by a lithographic patterning process, resist coating (for example spin coating), precure, mask alignment, exposure, post exposure curing, development, washing, drying (e.g. Postcure), other suitable methods, or a combination thereof. Alternatively, the lithographic exposure is assisted, implemented or replaced by other methods such as maskless lithography, electron beam writing or ion beam writing. In yet other embodiments, nanoimprint technology is used for lithographic patterning. In some embodiments, an etching process is used for the lithographic process, such as dry etching, wet etching, other etching processes, or a combination thereof. Before producing the patterned resist layer 245 may be a watering, such as a dehydration with demineralized water (DI water) on the substrate 210 be performed.

In 3C An etching process is performed to parts of the fin structure 220 in the n-type device regions, such as the first region 212 and the second region 214, of the integrated circuit element 200 to remove. By the etching process, for example, parts of the source / drain regions of the fins 222A and the Finns 222B removed, leaving source / drain recesses 250A in the first area 212 and source / drain recesses 250B in the second area 214 arise. With the etching process, an appropriate amount of the fins 222A and the Finns 222B removed to a desired profile for the source / drain recesses 250A and the source / drain recesses 250B to achieve. In the illustrated embodiment, the source / drain recesses are sufficient 250A and the source / drain recesses 250B not to below the top of the separator 230 Although the present invention contemplates embodiments in which the source / drain recesses 250A and the source / drain recesses 250B until under the top of the separator 230 pass. The etching process is a dry etching process, a wet etching process or a combination thereof. To the Finns 222A and the Finns 222B selectively etch, various etch parameters can be set, such as etchant composition, etch temperature, etch solution concentration, etch duration, etch pressure, voltage source power, radio frequency bias, RF bias power, etchant flow rate, other suitable etch parameters, or a combination thereof , In some embodiments, the fins may 222A and the Finns 222B etched using etchants that have a high etch selectivity with respect to the fin 222A material and fins 222B to have. In some embodiments, a wet etch process uses an etchant solution comprising ammonia hydrate (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), sulfuric acid (H ₂ SO ₄ ), tetramethylammonium hydroxide (TMAH), another suitable wet etch solution, or a combination thereof. For the wet etching solution, for example, NH ₄ OH: H ₂ O ₂ solution, NH ₄ OH: H ₂ O ₂ : H ₂ O solution [known as ammonia-peroxide mixture (APM)] or H ₂ SO _4: H ₂ O ₂ solution [as sulfuric peroxide mixture (SPM) is known] are used. In some embodiments, the dry etching process uses an etching gas comprising a fluorine-containing etching gas (eg, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and / or C ₂ F ₆ ), an oxygen-containing gas, a chlorine-containing gas (e.g. Cl ₂ , CHCl ₃ , CCl ₄ and / or BCl ₃ ), a bromine-containing gas (eg HBr and / or CHBr ₃ ), an iodine-containing gas, other suitable gases and / or plasmas or a combination thereof.

In 3D For example, a deposition process is performed to form an epitaxial source / drain feature or other feature 255A over the source / drain regions of the fins 222A and an epitaxial source / drain feature or other feature 255B over the source / drain regions of the fins 222B manufacture. For example, a selective epitaxial growth (SEG) process is performed to deposit a semiconductor material on exposed, recessed portions of the fins 222A and the Finns 222B to grow up. The semiconductor material fills the source / drain recesses 250A and the source / drain recesses 250B at a height (defined in the Z direction) greater than the height h ₁ and the height h ₂ (initial heights of the fins 222A and the fins, respectively) 222B ). In the illustrated embodiment, the semiconductor material fuses from adjacent source / drain recesses 250A and adjacent source / drain recesses 250B is grown, so that the epitaxial source / drain structure element 255A about the two Finns 222A in the first area 212 extends and the epitaxial source / drain structure element 255B about the two Finns 222B in the second area 214 extends. The epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B may therefore be referred to as fused epitaxial source / drain structure elements. For the SEG process, CVD deposition methods [for example, vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), LPCVD and / or PECVD], molecular beam epitaxy (MBE), other suitable SEG processes, or a combination thereof can be used. For the SEG process, gaseous precursors (for example Si-containing gases such as SiH ₄ and / or Ge-containing gases such as GeH ₄ ) and / or liquid precursors having the composition of the fin structure are used 220 (here the Finns 222A and the Finns 222B ) to interact. In the SEG process dopants are introduced so that the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B be doped in situ during the SEG process. The epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B For example, dopants are doped to a starting material of the SEG process during deposition by the addition of dopants.

In the illustrated embodiment, the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B a silicon-containing material on when the first area 212 and the second area 214 n-type device areas are. In these embodiments, for the deposition process, a silicon-containing precursor such as silane (SiH ₄ ), disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), dichlorosilane (SiH ₂ Cl ₂ ), another silicon-containing precursor, or a combination used of it. Further, in these embodiments, the deposition process includes in-situ doping of the silicon-containing material using an n-dopant precursor, such as a phosphorous-containing gas [e.g., phosphine (PH ₃ )], an arsenic-containing gas for the deposition process [which has, for example, arsane (AsH ₃ )], another n-dopant-containing gas, or a combination thereof. The epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B are epitaxial Si: P source / drain features. In some embodiments, the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B a phosphorus doping concentration of about 1 × 10 ²¹ dopants / cm 3 to about 5 × 10 ²¹ dopants / cm 3. In some embodiments, the deposition process is performed at a temperature of about 550 ° C to about 650 ° C (eg, about 600 ° C). In some embodiments, the integrated circuit element becomes 200 subjected to a deposition process for about 200 seconds to about 400 seconds (for example, about 300 seconds) (for example, it is treated with the silicon-containing precursor and the phosphorus-containing precursor). In some embodiments, the deposition process is performed until the semiconductor material between the fins 222A and the Finns 222B beyond the height h ₁ or the height h ₂ also extends. In some embodiments, the deposition process further comprises in-situ doping of the silicon-containing material with a carbon-containing gas [such as monomethylsilane (MMS)]. In some embodiments, the epitaxial source / drain feature is 255A and the epitaxial source / drain structure element 255B epitaxial Si: P: C source / drain features.

To the formation of crystal defects and / or crystal defects in the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B as in amorphous parts (for example, the amorphous silicon parts) of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B In addition, in the deposition process, an etchant-containing precursor such as a chlorine-containing precursor [having, for example, chlorine (Cl ₂ ) or hydrogen chloride (HCl)] is further introduced into the silicon-containing precursor and the n-type dopant-containing precursor during the deposition process, albeit minimally, the silicon-containing material is etched simultaneously. The throughput of the silicon-containing precursor (D) and the throughput of the etchant-containing precursor (E) are adjusted so that the growth kinetics of the silicon-containing layer is improved and the lateral growth of the epitaxial source / drain structural element 255A and the epitaxial source / drain structure element 255B (such as the transverse dimension b ₁ and the transverse dimension b2) is limited. For example, in the illustrated embodiment, the ratio D / E of the silicon-containing precursor and the etchant-containing precursor is less than 5 (in other words, D / E <5). D / E ratios less than 5 minimize selectivity loss and crystal growth kinetics, thereby ensuring that the silicon-containing material does not grow on other features, such as silicon nitride-containing features and / or silicon oxide-containing features [such as the mask layer 240 , the separator 230 and / or the gate structure (such as the dummy gate stack)]. In other words, the deposition process shows no silicon selectivity loss. However, if the D / E ratio is too small, minimal epitaxial growth will occur, causing fusing of the semiconductor material from adjacent source / drain recesses 250A and / or source / drain recesses 250B is grown to the epitaxial source / drain structure element 255A or the source / drain structure element 255B is prevented. In some embodiments, the ratio (D / E) of the silicon-containing precursor and the etchant-containing precursor is greater than or equal to 1 (in other words, D / E ≥ 1). In the illustrated embodiment, in the deposition process, an HCl precursor is introduced into the silicon-containing precursor and phosphorus-containing precursor, with the ratio of HCl throughput to silicon precursor throughput being less than 5 but greater than 1 (in other words, 1 ≦ Si D / HCl E <5). In some embodiments, the throughput of the silicon-containing precursor is about 20 Ncm ³ / min to about 500 Ncm ³ / min while the etchant-containing precursor flow rate is about 20 Ncm ³ / min to about 100 Ncm ³ / min. In some embodiments, the throughput of the phosphorus-containing precursor is about 20 Ncm ³ / min to about 500 Ncm ³ / min.

In some embodiments, a pre-cleaning process is performed prior to the deposition process to, for example, native oxide or to remove other contaminants from surfaces that make up the source / drain recesses 250A and the source / drain recesses 250B define, such as from the tops of the fins 222A and the Finns 222B , The pre-cleaning process may be configured to include native oxide or other impurities from the fins 222A and the Finns 222B , the mask layer 240 , the separator 230 , the substrate 210 and / or the gate structure are removed. In some embodiments, the prepurification process includes a dry etch process in which a fluorochemical precursor [such as fluorine (such as F and / or F2), nitrogen trifluoride (NF ₃ ), hydrogen fluoride (HF), other fluorine-containing etchant components, or a combination thereof ] and a hydrogen-containing precursor [which includes, for example, hydrogen (such as H and / or H ₂ ), ammonia (NH ₃ ), other hydrogen-containing etchant components, or a combination thereof]. In some embodiments, the pre-cleaning process may selectively etch silicon oxide without etching silicon (in some embodiments crystalline silicon, amorphous silicon, and / or polysilicon) (or if so, then only minimally). In some embodiments, the pre-cleaning process uses the SICONT ™ technology available from Applied Materials, Inc. of Santa Clara, California. In some embodiments, the pre-clean process includes a wet etch process using a fluorochemical and a hydrogenous etch solution, such as dilute hydrofluoric acid (DHF). In some embodiments, the pre-cleaning process is performed at a temperature of about 550 ° C to about 650 ° C (for example, about 600 ° C). In some embodiments, the integrated circuit element becomes 200 for about 10 seconds to about 30 seconds subjected to the pre-cleaning process.

In 3E An etching process is performed to form portions of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B removing (re-etching) the profile of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B is modified. For the etching process, a chlorine-containing precursor (also referred to as chlorine-containing gas) is used, such as chlorine (Cl2) or hydrogen chloride (HCl). In the illustrated embodiment, for example, an HCl precursor having a throughput of about 100 Ncm ³ / min to about 1000 Ncm ³ / min is used for the etching process. In some embodiments, the etching process is performed at a temperature of about 650 ° C to about 750 ° C (for example, about 700 ° C). In some embodiments, the integrated circuit element becomes 200 for about 20 seconds to about 50 seconds (for example, about 40 seconds) subjected to the etching process. In some embodiments, the etching process is a selective etching process, with the crystal defects and / or crystal defects selectively selected from the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B, such as amorphous parts (eg, amorphous silicon parts) of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B ,

The etching process is adjusted so that the profile of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B can be controlled. For example, with the etching process, upper portions of the epitaxial source / drain structure element become 255A and the epitaxial source / drain structure element 255B planarized so that the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B show substantially flat tops, such as a top 260A and a top 260B , In some embodiments, the top 260A and the top 260B various peaks and valleys leading to a surface roughness, wherein a surface roughness variation of ≤ ± 5% provides substantially flat landing lands (for example, for bonding a contact of a bonding structure to the epitaxial source / drain features 255A and the epitaxial source / drain structure element 255B ). In the illustrated embodiment, by the etching process roughness depth variations of a fused part 262A the epitaxial source / drain structure element 255A and a merged part 262B the epitaxial source / drain structure element 255B minimized. The merged part 262A and the merged part 262B are portions of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element, respectively 255B in which the semiconductor material consists of adjacent source / drain recesses 250A and adjacent source / drain recesses 250B merges. The merged part 262A has a corresponding height h _1m , and the merged part 262B has a corresponding height h _2m . The height h _1m is above the fused part 262A is substantially constant, and the height h _2m is above the fused part 262B essentially constant. In some embodiments, the height h _{1m is} considered substantially constant as the heights are at a number of positions over a width of the fused portion 262A (in other words, along the X direction) differ by ± 5% from each other, and the height h _2m is considered substantially constant as the heights at a number of positions over a width of the fused portion 262B differentiate by ± 5%. By Minimize the roughness variations of the fused part 262A and the fused part 262B show the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B Profiles, the better landing lands (for example, for connecting a contact of a connection structure to the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B ) as the epitaxial source / drain features fabricated using conventional CDE processes. Sidewall portions of the epitaxial source / drain structure element can also be used with the etching process 255A and the epitaxial source / drain structure element 255B, so that the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B show substantially flat side wall surfaces, such as side wall surfaces 264A (between which the transverse dimension b _{1 is} defined) and side wall surfaces 264B (between which the transverse dimension b2 is defined). In some embodiments, the tops are 260A and 260B substantially parallel to the top of the separator 230 while the side panels 264A and 264B substantially perpendicular to the top of the separator 230 are.

For fin spacing less than about 25 nm, the method of making self-aligned sources and drains described above with reference to FIGS 3D to 3F in particular the one-time implementation of a deposition and etching process), the exact control of the lateral growth of the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B , whereby fluctuations of the transverse dimension b ₁ and the transverse dimension b2 can be minimized. In some embodiments, where the target for the transverse dimension b ₁ and the transverse dimension b2 is about 45 nm to about 55 nm, by adjusting the deposition process and the etching process, as set forth above, the transverse dimension may be in the range of about ± 7 nm [for example, within 6 sigma (standard deviation)], which is much narrower than what can be achieved with conventional CDE processes. In some embodiments, by adjusting the deposition process and the etching process, as set forth above, the standard deviation of the width variation (such as the 6 sigma value) can be reduced by 30%. This reduction is significant as modern technology nodes become smaller and smaller, leaving minimal room for excessive lateral growth that can degrade component performance. Various embodiments described herein have several advantages, and no particular preference is necessarily required for all embodiments.

In 3F a deposition process is performed to form an epitaxial capping layer 265A over the epitaxial source / drain structure element 255A and an epitaxial capping layer 265B over the epitaxial source / drain structure element 255B manufacture. The epitaxial capping layer 265A and the epitaxial capping layer 265B may be the device performance of the integrated circuit device 200 improve. A selective epitaxial growth (SEG) process is performed to form a semiconductor material on the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B to grow up. The semiconductor material is over the epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B grown conformal, so that the epitaxial capping layer 265A and the epitaxial capping layer 265B have substantially uniform thicknesses, such as about 1 nm to about 6 nm. For the SEG process, CVD deposition methods (for example, VPE, UHV-CVD, LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or a combination thereof can be used. For the SEG process gaseous precursors (for example Si-containing gases, such as SiH ₄ and / or Ge-containing gases, such as GeH ₄ ) and / or liquid precursors having the composition of the epitaxial source / Drain structure element 255A and the epitaxial source / drain structure element 255B to interact. In the illustrated embodiment, a silicon-containing precursor such as SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiH ₂ Cl ₂ , another silicon-containing precursor or a combination thereof is used for the deposition process. In some embodiments, the deposition process is performed at a temperature of about 700 ° C to about 800 ° C (eg, about 750 ° C). In some embodiments, the integrated circuit element becomes 200 for about 100 seconds to about 200 seconds (for example, about 150 seconds) undergoes a deposition process (it is treated, for example, with the silicon-containing precursor). In the SEG process dopants can be introduced so that the epitaxial capping layer 265A and the epitaxial capping layer 265B be doped in situ during the SEG process. The epitaxial source / drain structure element 255A and the epitaxial source / drain structure element 255B are doped during the deposition, for example, by addition of dopants to a starting material of the SEG process. In these embodiments, for the deposition process, an n-dopant precursor is used, such as a phosphorus-containing gas (having, for example, PH ₃ ), an arsenic-containing gas (which may be used to form the AsH ₃ example), another n-dopant-containing gas, or a combination thereof. In some embodiments, a carbonaceous precursor (having, for example, MMS) is further used for the deposition process. Subsequently, the structured resist layer 245 and the mask layer 240 removed with appropriate methods.

In the 3G to 3J For example, epitaxial source and epitaxial drain features (referred to herein as epitaxial source / drain features) are fabricated in source / drain regions of p-type regions, such as the third region 216 of the integrated circuit element 200 , In the 3G and 3H For example, processing involves sparing the source / drain regions of the fins in the p-type device regions, such as the third region 216 , the integrated circuit element 200. In 3G is above the substrate 210 (In the illustrated embodiment, over the separating element 230 ) a mask layer 270 made, and over the mask layer 270 becomes a structured resist layer 275 produced. The mask layer 270 has a material that has a different etch rate than the material of the fin structure 220 has (especially the Finn 222C ). The mask layer 270 For example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbon nitride, amorphous silicon, polysilicon, other suitable materials, or a combination thereof. In the illustrated embodiment, the mask layer 270 Silicon nitride on. In some embodiments, the mask layer 270 a material that has a lower etch rate than the material of the fin structure 220 has, so the Finn 222C opposite the mask layer 270 can be selectively etched. The mask layer 270 is prepared by a suitable method, such as a CVD method, having a suitable thickness. In some embodiments, a silicon and nitrogen-containing mask layer is made by LPCVD. In some embodiments, a silicon and nitrogen-containing mask layer is made by performing a process that includes thermally nitriding the silicon-containing layer. In some embodiments, a pad layer (eg, a silicon oxide layer) is interposed between the mask layer 270 and the substrate 210 (In particular the separating element 230 ) produced.

The structured resist layer 275 has an opening, the p-type device regions, such as the third region 216 , of the integrated circuit element 200, while the n-type device regions of the integrated circuit element 200, such as the first region 212 and the second area 214 stay covered. The structured resist layer 275 is also referred to as a photoresist layer, photosensitive layer, imaging layer, patterning layer or radiation-sensitive layer. The structured resist layer 275 is above the substrate 210 prepared by a lithographic patterning process comprising resist coating (e.g., spin coating), precure, mask alignment, exposure, post-exposure curing, development, rinsing, drying (eg, postcure), other suitable methods, or a combination thereof. Alternatively, the lithographic exposure is assisted, implemented or replaced by other methods such as maskless lithography, electron beam writing or ion beam writing. In yet other embodiments, nanoimprint technology is used for lithographic patterning. In some embodiments, an etching process is used for the lithographic process, such as dry etching, wet etching, other etching processes, or a combination thereof. Before producing the patterned resist layer 275 may be a watering, such as a dehydration with demineralized water (DI water) on the substrate 210 be performed.

In 3H An etching process is performed to parts of the fin structure 220 in the p-type device regions, such as the third region 216 , of the integrated circuit element 200 to remove. By the etching process, for example, parts of the source / drain regions of the fin 222C removed, leaving a source / drain recess 280 arises. With the etching process, a suitable amount of the fin 222C removed to a desired profile for the source / drain recess 280 to achieve. In the illustrated embodiment, the source / drain recess is sufficient 280 not to below the top of the separator 230 Although the present invention contemplates embodiments in which the source / drain recess 280 until under the top of the separator 230 enough. The etching process is a dry etching process, a wet etching process or a combination thereof. To the Finn 222C selectively etch, various etch parameters can be set, such as etchant composition, etch temperature, etch solution concentration, etch duration, etch pressure, voltage source power, radio frequency bias, RF bias power, etchant flow rate, other suitable etch parameters, or a combination thereof , In some embodiments, the fin may 222C etched using etchants that have a high etch selectivity with respect to the material of the fin 222C to have. In some embodiments, an etch solution comprising NH ₄ OH, H ₂ O ₂ , H ₂ SO ₄ , TMAH, another suitable wet etch solution, or a combination thereof is used in a wet etch process. For the wet etching solution, for example, an NH ₄ OH: H ₂ O ₂ solution, an APM solution or an SPM solution can be used. In some embodiments, an etch gas comprising a fluorine-containing etching gas (eg, CF ₄ , SF ₆ , CH ₂ F ₂ , CHF ₃ and / or C ₂ F ₆ ), an oxygen-containing gas, a chlorine-containing gas (US Pat. eg Cl ₂ , CHCl ₃ , CCl ₄ and / or BCl ₃ ), a bromine-containing gas (eg HBr and / or CHBr ₃ ), an iodine-containing gas, other suitable gases and / or plasmas or a combination thereof includes.

In 3I For example, a deposition process is performed to form an epitaxial source / drain structure element 290 over the source / drain regions of the fin 222C manufacture. For example, a SEG process is performed to apply a semiconductor material to exposed, recessed parts of the fin 222C to grow up. The semiconductor material fills the source / drain recess 290 at a height (defined in the Z direction) greater than a height h ₃ (initial height of the fin 222C ). For the SEG process, CVD deposition methods (for example, VPE, UHV-CVD, LPCVD, and / or PECVD), molecular beam epitaxy, other suitable SEG processes, or a combination thereof can be used. For the SEG process, gaseous precursors (for example Si-containing gases such as SiH ₄ and / or Ge-containing gases such as GeH ₄ ) and / or liquid precursors having the composition of the fin structure are used 220 (here the Finns 222A and the Finns 222B ) to interact. In the illustrated embodiment, where the third region 216 is a p-type device region, the epitaxial source / drain structure element 290 comprises a silicon germanium-containing material. In these embodiments, for the deposition process, a silicon-containing precursor (which is, for example, SiH ₄ , Si ₂ H ₆ , Si ₃ H ₈ , SiH ₂ Cl ₂ , another silicon-containing precursor, or a combination thereof) and a germanium-containing precursor [e.g. Monogerman (GeH ₄ ), germanium tetrachloride (GeCl ₄ ), another germanium containing precursor or a combination thereof] is used. In the SEG process dopants can be introduced so that the epitaxial source / drain structure element 290 is doped in situ during the SEG process. The epitaxial source / drain structure element 290 is doped during the deposition, for example, by adding dopants to the starting material of the SEG process. In these embodiments, the deposition process involves in-situ doping of the silicon germanium-containing material using a p-type dopant precursor for the deposition process, such as a boron-containing precursor [such as boron (B) and / or boron fluoride (BF ₂ )], another p-dopant-containing gas or a combination thereof. In these embodiments, the epitaxial source / drain feature is 290 an epitaxial Si: Ge: B source / drain structure element. In some embodiments, the epitaxial source / drain feature 290 a boron doping concentration of about 1 × 10 ²¹ dopants / cm 3 to about 5 × 10 ²¹ dopants / cm 3. Subsequently, the structured resist layer 275 and the mask layer 270 removed with appropriate procedures, as in 3I is shown.

The integrated circuit element 200 can then be subjected to further processing to complete the production. For example, a gate replacement process is performed to replace the dummy gate stack of the gate structures with a metal gate stack. In some embodiments, over the substrate 210 an inter-level dielectric (ILD) layer, for example, prepared by a deposition method (such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, plating, other suitable methods, or the like) Combination of these). The ILD layer comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, TEOS-made oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, another suitable dielectric material, or a combination thereof , Exemplary low-k dielectric materials are fluorosilicate glass (FSG), carbon doped silica, Black Diamond® (Applied Materials, Santa Clara, California), xerogel, airgel, amorphous fluorocarbon, parylene, BCB (bis-benzocyclobutenes), SiLK (Dow Chemicals, Midland, Michigan), polyimide, other suitable materials, or a combination thereof. In some embodiments, the ILD layer may be a multilayer structure having multiple dielectric materials.

After the deposition of the ILD layer, a CMP process may be performed so that an upper part of the gate structures such as an upper part of the dummy gate electrode layer (s) is reached (exposed). Then, a portion of the gate structures (such as the dummy gate electrode layer and, in some embodiments, the dummy gate dielectric layer) are removed to form a trench (opening) that defines the fin structure 220 , an intermediate layer and / or the gate dielectric layer. In some embodiments, an etching process selectively removes the dummy gate electrode layer (and in some embodiments, the dummy gate dielectric layer). The etching process is a dry etching process, a wet etching process or a combination thereof. The selective etching process may be adjusted so that the dummy gate electrode layer provides an adequate etch rate for the fin structure 220 having the interlayer, the gate dielectric layer, the spacers, and / or the ILD layer. Then, a metal gate stack is made from the gate structures in the opening (the trench). The metal gate Stack comprises a gate dielectric layer and a gate electrode layer as described above (for example, with reference to FIGS 1 ). In some embodiments, silicide features are fabricated in the gate regions and / or the source / drain regions. The silicide structural elements may be on the epitaxial capping layer, for example 265A , the epitaxial capping layer 265B , the epitaxial source / drain structure element 290 and / or the gate structures are made. The silicide structural elements are produced by a silicide formation process, such as a self-aligned silicide process (salicide process).

Various contacts can be made to the function of the integrated circuit element 200 to enable. For example, over the substrate 210 an ILD layer is made [in some embodiments, a second ILD layer is made over a first ILD layer (made during the gate replacement process]]. Contacts can then be made in the ILD layers. For example, a contact with the gate structures (in particular with the gate electrode layer) is electrically connected, and other contacts are made with the source / drain regions of the fin structure 220 electrically connected [in particular via the epitaxial source / drain structure elements 255A (and / or the epitaxial capping layer 265A ) in the first area 212 , the epitaxial source / drain structure elements 250B (and / or the epitaxial capping layer 265B ) in the second area 214 and / or the epitaxial structural elements 290 in the third area 216 ]. The contacts comprise a conductive material, such as a metal. The metals include aluminum, aluminum alloys (such as an aluminum-silicon-copper alloy), copper, copper alloys, titanium, titanium amide, tantalum, tantalum nitride, tungsten, polysilicon metal silicide, other suitable metals, or a combination thereof. The metal silicide may be nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or a combination thereof. In some embodiments, the ILD layers and the contacts (passing through, for example, the ILD layers) are part of an MLI (multilayer interconnect) structure element that overlies the substrate 210 is arranged. The MLI structure element connects various components of the integrated circuit element 200 electrically, so that the various components are operable to function as required in the design of the integrated circuit element 200 is fixed. The MLI structure element may comprise a combination of metal layers and ILD layers configured to form vertical interconnect features, such as contacts and / or vias, and / or horizontal interconnect features, such as leads. The various conductive features have materials similar to those of the contacts. In some embodiments, a single damascene process and / or a dual damascene process is used to fabricate a copper-based multilayer interconnect structure.

The present invention provides various source and drain fabrication methods for fin field effect transistors (FinFETs). An exemplary method includes forming a first fin and a second fin over a substrate. The first fin and the second fin have a fin pitch that is less than about 25 nm. The first fin and the second fin each have a channel region arranged between a source region and a drain region. The method further includes establishing a gate structure over the channel regions of the first and second fins. The method further comprises performing a deposition process and an etching process only once to fabricate a fused epitaxial source structural feature or feature extending over the source regions of the first fin and the second fin, and for fabricating a fused epitaxial drain structure element or feature extending over the drain regions of the first and second fins. In some embodiments, a silicon-containing precursor and a chlorine-containing precursor are used for the deposition process, with a ratio of throughput of the silicon-containing precursor to throughput of the chlorine-containing precursor being less than 5. In some embodiments, the chlorine-containing precursor is used for the etching process. In some embodiments, a phosphorus-containing precursor is further used for the deposition process.

In some embodiments, the method further includes recessing the first and second fins prior to fabricating the fused source epitaxial structure element and the fused epitaxial drain structure element. In some embodiments, the method further comprises forming an epitaxial capping layer over the fused epitaxial source structure element and the fused epitaxial drain structure element. In some embodiments, the method further comprises performing a gate replacement process after the fabrication of the fused epitaxial source structure element and the fused epitaxial drain structure element. In some embodiments, the fused epitaxial source structure element and the fused epitaxial drain structure element each have a fused portion that has a substantially constant height. In some embodiments, the fused epitaxial source structure element and the fused epitaxial drain device each have a transverse dimension of about 45 nm to about 55 nm, with the etching process and the deposition process adjusted to maintain the transverse dimension within about ± 7 nm ,

Another exemplary method includes forming a fin structure having at least two fins having a fin pitch that is less than about 25 nm and fabricating an epitaxial feature or feature over a source / drain region of the fin structure. Fabrication of the epitaxial structure element includes performing a single deposition process to fabricate an epitaxial layer over the fin structure and performing a single etch process on the epitaxial layer. For the single deposition process, a ratio of throughput of the silicon-containing precursor to a throughput of an etchant-containing precursor less than 5 is used. In some embodiments, the method further includes eliminating the at least two fins prior to fabrication of the epitaxial structure element.

In some embodiments, the single deposition process comprises growing a semiconductor material from the at least two fins, wherein the semiconductor material grown by the at least two fins fuses to the epitaxial structure element. In some embodiments, the silicon-containing precursor comprises silicon, the etchant-containing precursor comprises hydrogen chloride, and for the single-etching process, the etchant-containing precursor is used. In some embodiments, the single deposition process further uses a dopant-containing precursor comprising, for example, phosphorus.

Another exemplary method of fabricating epitaxial source / drain features or features for a FinFET involves epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor and a chlorine-containing precursor. The semiconductor material fuses into an epitaxial structure element that extends across the plurality of fins. The plurality of fins has a fin pitch that is less than about 25 nm. A ratio of throughput of the silicon-containing precursor to throughput of the chlorine-containing precursor is less than 5. The method further comprises re-etching the semiconductor material using the chlorine-containing precursor thereby modifying a profile of the epitaxial structural element. In some embodiments, epitaxial growth and re-etching are performed only once.

In some embodiments, the chlorine-containing precursor comprises hydrogen chloride. In some embodiments, a phosphorus-containing precursor is also used for epitaxial growth. In some embodiments, the method further includes eliminating the plurality of fins prior to epitaxial growth such that the semiconductor material is grown by a plurality of source / drain recesses. In some embodiments, fabricating the epitaxial source / drain features further includes performing a lithographic process to expose the plurality of fins corresponding to the n-FinFET. In some embodiments, the method further includes fabricating epitaxial source / drain features for a p-type FinFET.

Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other methods and structures to achieve the same objects and / or advantages of the same as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent interpretations do not depart from the spirit and scope of the present invention and that they may make various changes, substitutions and alterations here without departing from the spirit and scope of the present invention.

Claims (20)

Procedure with the following steps: Fabricating a first fin and a second fin over a substrate, wherein the first fin and the second fin have a fin pitch that is less than about 25 nm, and the first fin and the second fin each have a channel region that is sandwiched between a source fin and fin. Area and a drain region is arranged; Forming a gate structure over the channel regions of the first and second fins; and performing a deposition process and an etch process only once to fabricate a fused epitaxial source structure element extending over the source regions of the first and second fins, and for fabricating a fused epitaxial drain structure element extending across the drain regions of the fins first and second fin extends. Method according to Claim 1 wherein a silicon-containing precursor and a chlorine-containing precursor are used for the deposition process, wherein the ratio of throughput of the silicon-containing precursor to throughput of the chlorine-containing precursor is less than 5, and the chlorine-containing precursor is used for the etching process. Method according to Claim 2 wherein the chlorine-containing precursor comprises hydrogen chloride. The method of any one of the preceding claims, wherein a phosphorus-containing precursor is further used for the deposition process. The method of any one of the preceding claims, further comprising recessing the first and second fins prior to fabricating the fused source epitaxial structure element and the fused epitaxial drain structure element. The method of any one of the preceding claims, further comprising forming an epitaxial capping layer over the fused epitaxial source structural element and the fused epitaxial drain structural element. The method of any one of the preceding claims, further comprising performing a gate replacement process after fabrication of the fused epitaxial source structure element and the fused epitaxial drain structure element. The method of any one of the preceding claims, wherein the fused epitaxial source structure element and the fused epitaxial drain structure element each have a fused portion having a substantially constant height. The method of claim 1, wherein the fused epitaxial source structure element and the fused epitaxial drain structure each have a transverse dimension of from about 45 nm to about 55 nm, wherein the deposition process and the etching process are adjusted so that the transverse dimension within about ± 7 nm is maintained. Procedure with the following steps: Fabricating a fin structure having at least two fins having a fin pitch that is less than about 25 nm; and Producing an epitaxial structure element over a source / drain region of the fin structure, wherein the production of the epitaxial structure element comprises: Performing a single deposition process to fabricate an epitaxial layer over the fin structure, wherein the single deposition process uses a ratio of silicon precursor throughput to an etchant containing precursor flow that is less than 5, and Performing a single etch process on the epitaxial layer. Method according to Claim 10 wherein the single deposition process comprises growing a semiconductor material from the at least two fins, wherein the semiconductor material grown by the at least two fins fuses to the epitaxial structure element. Method according to Claim 10 or 11 further comprising recessing the at least two fins prior to fabrication of the epitaxial structural member. Method according to one of Claims 10 to 12 wherein the silicon-containing precursor comprises silicon, the etchant-containing precursor comprises hydrogen chloride, and the etchant-containing precursor is used for the individual etching process. Method according to one of Claims 10 to 13 wherein a dopant-containing precursor is further used for the single deposition process. Procedure with the following steps: Producing epitaxial source / drain structure elements for an n-FinFET (FinFET: Fin Field Effect Transistor), wherein the production of the epitaxial source / drain structure elements comprises: epitaxially growing a semiconductor material on a plurality of fins using a silicon-containing precursor, a phosphorus-containing precursor and a chlorine-containing precursor, wherein the plurality of fins has a fin pitch that is less than about 25 nm, a ratio of throughput of the silicon-containing precursor to a flow rate of the chlorine-containing precursor is less than 5 and fusing the semiconductor material into an epitaxial structure element extending across the plurality of fins; and Re-etching the semiconductor material using the chlorine-containing precursor thereby modifying a profile of the epitaxial structural element. Method according to Claim 15 wherein the chlorine-containing precursor comprises hydrogen chloride. Method according to Claim 15 or 16 which further comprises performing epitaxial growth and etch back only once. Method according to one of Claims 15 to 17 further comprising recessing the plurality of fins prior to epitaxial growth such that the semiconductor material is grown by a plurality of source / drain recesses. Method according to one of Claims 15 to 18 wherein forming the epitaxial source / drain features further comprises performing a lithographic process to expose the plurality of fins corresponding to the n-FinFET. Method according to one of Claims 15 to 19 which further comprises fabricating epitaxial source / drain features for a p-type FinFET.

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