DE102017120015A1 - Circuit arrangement for line break detection for continuously scanning measuring systems - Google Patents

Abstract

Circuit breakage detection circuit, comprising: - a clock generator (1) adapted to output a first clock signal having a frequency fals detector signal (1a) and to output a second signal having a frequency fals synchronization signal (1b), - a converter unit (2) adapted to convert the detector signal (1a) into an AC voltage which can be applied to the supply line of a sensor (8), - a selective amplifier (3) adapted to selectively produce a signal component of frequency f A filter (4) which is adapted to the signal component with the frequency faus the AC voltage, which is generated at the impedance of the sensor (8), to amplify AC voltage which is generated at the impedance of the sensor (8), - an analog-to-digital converter (5) which is connected downstream of the filter (4), which is clocked with the synchronization signal (1b) and which is adapted to one of the filter (4) out convert a given signal into a digital data stream, - a controller (6) which is designed to evaluate the signal output by the selective amplifier (3).

Description

The present invention relates to a circuit arrangement for line break detection for continuously scanning measuring systems and their use for line break detection, and a method for line breakage detection.

A common task in electronic measuring technology is the detection of sensor breakage of a sensor or the line break in the supply line to a measuring system with a sensor. It is particularly important to detect sensors or sensors which can also output valid voltages of zero volts within their measuring range, so that no statement can be made about the condition of the sensor due to the measuring signal itself. These include e.g. Thermocouples, which do not deliver a measuring voltage, if both line ends are at the same temperature.

In order to be able to check the functionality of the sensor arrangement, it is therefore customary in the prior art to let a small direct current flow through the sensor arrangement. If this method is used, for example, in a sensor arrangement with a thermocouple, a voltage that is more negative than the maximum possible negative thermoelectric voltage is produced at a sensor or line break at the measuring input. This makes it easy to detect a line or sensor break.

However, the known method for line break detection has various disadvantages. On the one hand, the current applied for line break detection can lead to errors in the sensor data. For example, in a thermocouple, a current applied to open circuit detection generates a constant voltage drop across the internal resistance of the sensor and its supply line. This error is detected by the measuring system as the offset temperature. To achieve accurate measurement results, the cable break detection must be switched off, which is associated with a corresponding loss of security.

The present invention has for its object to provide a line break detection, in which the above-mentioned disadvantages can be avoided. Specifically, a continuous line break detection is to be provided, which causes no distortion of the actual useful signal.

This object is achieved by a circuit arrangement for line breakage detection according to claim 1, and a method for line breakage detection according to claim 7 and a use of a circuit arrangement according to claim 9

• - einen Taktgeber, der dazu ausgebildet ist, ein erstes Taktsignal mit einer Frequenz f_D als Detektorsignal auszugeben und ein zweites Signal mit einer Frequenz f_S als Synchronisationssignal auszugeben;
• - eine Wandlereinheit, die dazu ausgebildet ist, das Detektorsignal in einen Wechselstrom zu wandeln, der an die Zuleitung eines Sensors anlegbar ist;
• - einen selektiven Verstärker, der dazu ausgebildet ist, selektiv eine Signalkomponente mit der Frequenz f_D aus einer Wechselspannung, die an der Impedanz des Sensors erzeugbar ist, zu verstärken;
• - einen Filter, der dazu ausgebildet ist, die Signalkomponente mit der Frequenz f_D aus der Wechselspannung, die an der Impedanz des Sensors erzeugbar ist, zu dämpfen;
• - einen Analog-Digital-Wandler, der dem Filter nachgeschaltet ist, der mit dem Synchronisationssignal getaktet ist, und der dazu ausgebildet ist, ein von dem Filter ausgegebenes Signal in einen digitalen Datenstrom zu konvertieren;
• - einen Controller, der dazu ausgebildet ist, das von dem selektiven Verstärker ausgegebene Signal auszuwerten.

In particular, the object is achieved by a circuit arrangement for line break detection, comprising:

• a clock adapted to output a first clock signal having a frequency f _D as a detection signal and to output a second signal having a frequency f _S as a synchronization signal;
• - A converter unit which is adapted to convert the detector signal into an alternating current, which can be applied to the supply line of a sensor;
• - A selective amplifier, which is adapted to selectively amplify a signal component with the frequency f _D from an AC voltage which can be generated at the impedance of the sensor;
• - A filter which is adapted to attenuate the signal component with the frequency f _D from the AC voltage, which is generated at the impedance of the sensor;
• - An analog-to-digital converter, which is connected downstream of the filter, which is clocked with the synchronization signal, and which is adapted to convert a signal output from the filter into a digital data stream;
• a controller adapted to evaluate the signal output by the selective amplifier.

A core idea of the present invention resides in the fact that, for line _break detection, an alternating current having a fixed frequency f _{D and} generated from the detector signal is used. This alternating current generates an alternating voltage with the frequency f _D at the impedance of the sensor to be tested. With the circuit arrangement according to the invention, a useful signal with a frequency different from f _D can be superimposed on the alternating current used for line break detection. This mixed signal is then fed to the selective amplifier and the filter. The selective amplifier isolates the AC signal generated at the impedance of the sensor with the frequency f _D and raises its amplitude to an evaluable level. This allows for a useful signal largely undisturbed wire break detection.

On the other hand, the mixed signal is fed to the filter which attenuates the signal component provided for line break detection with the frequency f _D , so that only very small portions of the interference signals generated by the line break detection are present at the input of the analog-to-digital converter. The analog-to-digital converter converts the applied input signal into a digital data stream at a predetermined sampling rate fs. The Line break detection can therefore be decoupled from the actual measurement at the sensor with the switching arrangement according to the invention. It is not necessary to impose a measurement falsifying direct current for lead breakage detection. The cable break detection can thus be carried out continuously, without falsifying the measurement at the detector. This increases the security of the detection system, without adversely affecting the measurement properties of the measuring system.

In a preferred embodiment of the invention, the frequency f _{S is} an integer multiple of the frequency f _D. The analog-to-digital converter for converting the useful signal is an integrating system. If a useful signal having a lower frequency than the frequency f _{D is} used, integration periods comprising a plurality of periods of the detector signal can be used on the analog-to-digital converter. Since the AC voltage generated for line break detection is a surface-symmetric signal, remaining components of this signal are always integrated to zero at the input of the analog-to-digital converter during an integration period. Thus, the interference of the line break monitoring on the useful signal can be further reduced.

It is preferred that the frequency f _{D of} the detector signal is in a range between 100 Hz and 10 MHz, more preferably between 3 MHz and 5 MHz.

In a further preferred embodiment, the filter is formed by a bandpass filter, preferably a low-pass filter, more preferably an anti-aliasing filter, wherein the frequency f _{D is} above the passband of the filter. This allows effective attenuation of the signal with the frequency f _D in the evaluation of the useful signal. If an anti-aliasing filter is used, the low-pass effect of the antialiasing filter can be used to attenuate signal components for line break monitoring to a very high degree.

In a further preferred embodiment, the analog-digital converter is formed by a sigma-delta converter, wherein the frequency f _D lies outside the passband of the sigma-delta converter. The use of a sigma-delta converter has the advantage that this converter has the effect of a multi-band blocking filter. If the frequency f _D lies in one of the stop bands, components of the detector signal can be efficiently removed from the digital useful signal stream.

In a further preferred embodiment, wherein between the selective amplifier and the controller, a detector is arranged, which is designed as a comparator or analog-to-digital converter. Thus, the signal generated for open-circuit detection with the frequency f _D isolated from the selective amplifier can be easily translated into a digital signal. If a comparator is used as the detector, the signal generated by the selective amplifier is compared with a reference voltage and it is determined whether the signal serving for line break detection is below or above a predefined threshold value. If an analog-to-digital converter is used as the detector, the signal generated for open-circuit detection can be used to measure the impedance of the sensor.

In one possible embodiment, the clock is integrated in the controller. This simplifies the structure of the circuit arrangement.

• - wobei ein Taktgeber ein erstes Taktsignal mit einer Frequenz f_D als Detektorsignal ausgibt und ein zweites Signal mit einer Frequenz f_S als Synchronisationssignal ausgibt;
• - wobei eine Wandlereinheit das Detektorsignal in eine Wechselspannung wandelt, die an die Zuleitung eines Sensors angelegt wird;
• - wobei ein selektiver Verstärker selektiv eine Signalkomponente mit der Frequenz f_D aus einer Wechselspannung, die an der Impedanz des Sensors (8) erzeugt wird, verstärkt;
• - wobei ein Filter die Signalkomponente mit der Frequenz f_D aus der Wechselspannung, die an der Impedanz des Sensors erzeugt wird, dämpft;
• - wobei ein Analog-Digital-Wandler, der dem Filter nachgeschaltet ist, der mit dem Synchronisationssignal getaktet ist, ein von dem Filter ausgegebenes Signal in einen digitalen Datenstrom konvertiert;
• - wobei ein Controller das von dem selektiven Verstärker ausgegebene Signal auswertet.

The above object is further achieved by a method for line break detection, in particular using the above circuit arrangement,

• - A clock generator outputs a first clock signal having a frequency f _D as a detector signal and outputs a second signal having a frequency f _S as a synchronization signal;
• - wherein a transducer unit converts the detector signal into an AC voltage which is applied to the supply line of a sensor;
• - wherein a selective amplifier selectively a signal component with the frequency f _D from an AC voltage, based on the impedance of the sensor ( 8th ) is amplified;
• - wherein a filter attenuates the signal component having the frequency f _D from the AC voltage generated at the impedance of the sensor;
• - wherein an analog-to-digital converter, which is connected downstream of the filter, which is clocked with the synchronization signal, converts a signal output by the filter into a digital data stream;
• - wherein a controller evaluates the signal output from the selective amplifier.

Preferably, the analog-to-digital converter operates with fixed sampling frequency integrating, wherein the frequency f _{s is} an integer multiple of the frequency f _d , the detector signal due to the blocking filter properties of the integrating analog-to-digital converter with a fixed sampling frequency and the useful signal superimposed detector signal is suppressed with an exact multiple of the sampling frequency.

The above object is further achieved by a use of the above circuit arrangement for line break detection.

The invention will also be described in terms of further features and advantages based on embodiments, which will be explained in more detail with reference to the figure.

This shows 1 a circuit diagram of a circuit arrangement for line break detection according to an embodiment of the present invention.

In 1 a circuit diagram of a circuit arrangement for line break detection for continuously scanning measuring systems is shown. The circuit arrangement is via a connection 9 with a sensor 8th connectable to be monitored. The circuit arrangement comprises a clock generator 1 , a transducer unit 2 , a selective amplifier 3 , a filter 4 , an analog-to-digital converter 5 , a controller 6 and an optional detector 7 ,

The clock 1 generates two clock signals, namely a detector signal 1a with a frequency f _D and a synchronization signal 1b with a frequency f _S which is higher than the frequency f _D. The frequencies f _D and f _S have a fixed split ratio.

The detector signal 1a becomes a transducer unit 2 supplied, which is formed in the present embodiment by an RC element and converts the detector signal into an alternating current with the frequency f _D. This one is about the connection 9 to a supply line to the sensor 8th created. The alternating current generated at the impedance of the sensor 8th an alternating voltage with the frequency f _D , which is superimposed on a useful signal, with which the sensor 8th is operated. The frequency of the useful signal is much smaller than the frequency f _D , preferably at least by a factor 10 ,

The mixed signal from the AC voltage and the useful signal is via a line 10 the selective amplifier 3 and the filter 4 fed. The selective amplifier 3 amplifies the input signal narrowband by the frequency f _D. It is the amplitude of the frequency component that is the detector signal 1a corresponds, raised to evaluable levels. As a result, the signal intended for line break detection is isolated from the mixed signal.

The signal thus isolated is applied to the input of the detector 7 created. The detector 7 can be designed as a comparator. In this case, a comparison voltage is supplied to the comparator and the signal generated in the selective amplifier is checked to see if it is below or above the comparison voltage. If the voltage drops below the reference voltage, a line break can be concluded.

Alternatively, the detector can 7 be executed as an analog-to-digital converter. In this case, the impedance of the sensor 8th be determined and a more accurate statement about the condition of the sensor 8th to be hit. If there is a line break, the measured impedance rises sharply, which in turn leads to a line break or a defect of the sensor 8th can be closed.

The mixed signal from the AC voltage and the useful signal is sent via the line 10 also the filter 4 fed. The filter 4 can be designed as a bandpass or lowpass filter, in particular as antialiasing filter. It is crucial that the frequency f _D outside the passband of the filter 4 lies. Since the frequency of the useful signal is smaller than the frequency f _D , the filter 4 chosen so that the frequency f _D above the passband of the filter 4 lies. Thus, the detector signal is strongly attenuated, so that at the output of the filter 4 only very small interference signals from the detector signal are present.

As a filter 4 For example, an anti-aliasing filter may be used which applies low pass filtering to the mix signal to attenuate high frequency components. The cutoff frequency is chosen so that f _{D is} outside the passband of the filter 4 lies.

That at the output of the filter 4 output, conditioned signal is the analog-to-digital converter 5 fed. The analog-to-digital converter 5 is the synchronization signal generated by the clock 1b clocked at the frequency fs. The analog-to-digital converter 5 works integrating and converts the processed signal with the sampling rate fs into a digital data stream.

As the useful signal, that in the conversion by the analog-digital converter 5 is to be obtained, a significantly lower frequency than the frequency f _{D of} the detector signal 1a , the integration period of the analog-to-digital converter may be long compared to the period of the detector signal 1a to get voted. That is, that during an integration period of the analog-to-digital converter 5 On integrated signals a plurality of periods of the detector signal 1a span.

The through the detector signal 1a caused signal component is a surface symmetric AC voltage with frequency f _D. If such a signal is integrated over several periods, the negative surface portions compensate for the positive area proportions, so that an integration value close to zero is obtained. Since the sampling rate f _{S of} the analog-to-digital converter 5 a multiple of the frequency f _{D of} the detector signal 1a is, the integration period, which is always an integer multiple of the reciprocal of the sampling rate f _S , can be selected so that in the signal to be converted remaining portions of the signal with the detector frequency f _D are always integrated into zero regardless of the phase position. Thus, a disturbing influence of the line break detection on the useful signal can be largely eliminated.

The analog-to-digital converter 5 can be designed as a sigma-delta converter. Due to the converter principle, a sigma-delta converter acts as an additional SINC filter, which can additionally attenuate remaining portions of the signal to be converted with the frequency f _D. Together with the filter 4 Thus, signal fractions having the frequency f _D originating from the line break detection can thus be attenuated below the noise limit of the useful signal so that they can no longer be detected in the converted signal current.

The controller 6 serves the evaluation of the amplified detector signal and the filtered useful signal. The above-described evaluations of the detector signal for detecting a possible line break may occur in the controller 6 be automated. For example, when an abnormal measured sensor impedance occurs, a warning signal can be output. Used as a detector 7 uses a comparator, the warning signal can be output if the signal applied to the comparator exceeds the reference voltage. Used as a detector 7 used an analog-to-digital converter, various warning signals can be set depending on the measured sensor impedance. Likewise, the controller 6 be configured, the measurement on the sensor 8th to interrupt when a preset sensor impedance is exceeded.

LIST OF REFERENCE NUMBERS

1

clock

1a

detector signal

1b

synchronization signal

2

converter unit

3

selective amplifier

4

filter

5

Analog to digital converter

6

controller

7

detector

8th

sensor

9

connection

10

management

Claims (9)

Circuit arrangement for open-circuit detection, comprising: - a clock generator (1) which is designed to output a first clock signal having a frequency f _D as a detector signal (1a) and to output a second signal having a frequency f _S as a synchronization signal (1b); - A converter unit (2) which is adapted to convert the detector signal (1a) into an AC voltage which can be applied to the supply line of a sensor (8); - a selective amplifier (3) adapted to selectively amplify a signal component having the frequency f _D from an AC voltage which is producible at the impedance of the sensor (8); - A filter (4) which is adapted to attenuate the signal component with the frequency f _D from the AC voltage, which is generated at the impedance of the sensor (8); - An analog-to-digital converter (5) which is the filter (4) connected downstream, which is clocked with the synchronization signal (1b), and which is adapted to a signal output from the filter (4) in a digital data stream convert; - A controller (6) which is adapted to evaluate the signal output by the selective amplifier (3). Circuit arrangement according to Claim 1 , where the frequency fs is an integer multiple of the frequency f _D. Circuit arrangement according to one of the preceding claims, wherein the filter (4) by a band-pass filter, preferably a low-pass filter, more preferably an anti-aliasing filter is formed, and wherein the frequency f _{D is} above the passband of the filter (4). Circuit arrangement according to one of the preceding claims, wherein the analog-digital converter (5) is formed by a sigma-delta converter, wherein the frequency f _{D is} outside the passband of the sigma-delta converter. Circuit arrangement according to one of the preceding claims, wherein between the selective amplifier (3) and the controller (6), a detector (7) is arranged, which is designed as a comparator or analog-to-digital converter. Circuit arrangement according to one of the preceding claims, wherein the clock generator (1) is integrated in the controller (6). Method for line break detection, in particular using the circuit arrangement according to one of the preceding claims, wherein a clock generator (1) outputs a first clock signal having a frequency f _D as a detector signal (1a) and outputs a second signal having a frequency f _S as a synchronization signal (1b); - wherein a transducer unit (2) converts the detector signal (1a) into an alternating voltage, which is applied to the supply line of a sensor (8); - wherein a selective amplifier (3) selectively amplifies a signal component having the frequency f _D from an AC voltage generated at the impedance of the sensor (8); - wherein a filter (4) attenuates the signal component having the frequency f _D from the AC voltage generated at the impedance of the sensor (8); - wherein an analog-to-digital converter (5), which is the filter (4) is clocked with the synchronization signal (1b) converts a signal output from the filter (4) in a digital data stream; - wherein a controller (6) evaluates the signal output by the selective amplifier (3). Method according to Claim 7 wherein the analog-to-digital converter (5) operates integrally at a fixed sampling frequency and the frequency f _{S is} an integer multiple of the frequency f _D , the detector signal due to the rejection filter characteristics of the fixed sampling frequency integrating analog-to-digital converter (5) of the useful signal superimposed, the detector signal with an exact multiple of the sampling frequency is suppressed. Use of the circuit arrangement according to one of the preceding Claims 1 to 6 for line break detection.

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