DE102017112560B4 - ADAPTIVE WEAR LEVELING - Google Patents

Abstract

An apparatus comprising: at least one processor configured to utilize sets of blocks of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the flash memory circuits and at least some of the blocks at least some of the sets of blocks as active are marked, wherein the at least some of the blocks of the at least some of the sets of blocks marked as active are used for the data storage operations; monitoring quality metrics of each block of each of the sets of blocks while the at least some of the blocks of the at least some of the Sets of blocks marked active are used for data storage operations; determining when the quality metric of any of the blocks of any of the sets of blocks falls below a minimum quality value; marking the one of the one of the sets of blocks as temporarily inactive, wherein of the one of the blocks of the one of the sets of blocks is not used for the data storage operations while it is marked as temporarily inactive; determining that at least one criterion is met if a number of the blocks of the one code rate associated with one of the sets of blocks the set of blocks marked active falls below a minimum number of active blocks, each of the sets of blocks being associated with the code rate; andif the at least one criterion is met, marking the one of the blocks of the one of the sets of blocks as active, the one of the blocks of the one of the sets of blocks being reused for the data storage operations while it is marked as active.

Description

REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of the preliminary U.S. Patent Application No. 62 / 368,967 entitled "Adaptive Wear Leveling", filed 7/29/2016, which is hereby incorporated by reference in its entirety for all purposes.

TECHNICAL AREA

The present description relates generally to wear leveling, including adaptive wear leveling for flash memory devices.

STATE OF THE ART

In a flash memory system, to achieve long life, the system typically employs a wear-leveling algorithm that keeps all physical blocks within a narrow range of cumulative programming / erasing (P / E) cycles. The assumption is that the physical blocks all have the same lifespan (if the weak blocks are disregarded, which are compensated by overprovisioning) and therefore all wear out at essentially the same time. In practice, however, the physical blocks do not all have the same lifespan. Thus, the flash memory system can reach its specified end of life even though many of the physical blocks are still usable. From the US 8,843,698 B2 an apparatus is known comprising at least one processor adapted to use flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the flash memory circuits, and at least some of the blocks at least some of the sets of blocks as active are marked, the at least some of the blocks of the at least some of the sets of blocks marked active being used for the data storage operations. Here, quality metrics of each block of each of the sets of blocks are monitored while the at least some of the blocks of the at least some of the sets of blocks that are marked as active are used for the data storage operations. It is also determined when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value. It is also provided that one of the blocks of the one of the sets of blocks is marked as temporarily inactive, the one of the blocks of the one of the sets of blocks not being used for the data storage operation while it is marked as temporarily inactive. If at least one criterion is met, one of the blocks of the one of the sets of blocks is marked as active, the one of the blocks of the one of the sets of blocks being used again for the data storage operation while it is marked as active.

Summary The present invention proposes a device with the features of patent claim 1, a method with the features of patent claim 12, a computer program product with the features of patent claim 19, and a system with the features of patent claim 21.

In another aspect, a method may include: using sets of blocks from a plurality of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the plurality of flash memory circuits and at least some of the blocks at least some of the sets of blocks are marked active, the at least some of the blocks of the at least some of the sets of blocks marked active being used for data storage operations. The method may further include: monitoring a remaining cycle count of each of the blocks of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks marked active are being used for the data storage operations, the remaining cycle count each of the blocks of each of the sets of blocks is based at least in part on an expected cycle count associated with each of the plurality of flash memory circuits including each of the blocks of each of the sets of blocks. The method may further include marking the one of the one of the sets of blocks as temporarily inactive when the remaining cycle count of one of the blocks of one of the sets of blocks meets at least a first criterion, the one of the blocks of the one of the sets of Block is not being used for data storage operations while marked as temporarily inactive. The method may further include: marking the one of the one of the sets of blocks as active when at least a second criterion is met, the one of the one of the sets of blocks being reused for the data storage operations while being active is marked.

In another aspect, a computer program product includes code stored in a non-transitory computer readable storage medium. The code may include code to quickly add a respective physical block to each of a variety of flash memory circuits cycle until a respective quality metric of the respective physical block of each of the plurality of flash memory circuits falls below a minimum quality value. The code may further include code to determine an expected cycle count for each of the plurality of flash memory circuits based at least in part on a number of fast cycles used to cause the respective quality metric of the respective physical block of each of the Large number of flash memory circuits fall below the minimum quality value. The code may further include code to store in at least one random access memory circuit the expected cycle count for each of the plurality of flash memory circuits in individual association with physical blocks of each of the plurality of flash memory circuits.

In another aspect, a system may include a plurality of flash memory circuits each comprising blocks, random access memory (RAM) configured to store a data structure including a status of each of the blocks of each of the plurality of flash memory circuits, the status of each the blocks of each of the plurality of flash memory circuits at least indicate whether each of the blocks of each of the plurality of flash memory circuits is marked active or is marked temporarily inactive, include an interface communicatively coupled to a host device, and a controller. The controller may be configured to use sets of the blocks of the plurality of flash memory circuits for data storage operations specified by the host device, each of the sets of the blocks including at least one block from each of the plurality of flash memory circuits and at least some the blocks of at least some of the sets of blocks in the data structure are marked active, the at least some of the blocks of the at least some of the sets of blocks marked active in the data structure being used for the data storage operations. The controller may further be configured to monitor a quality metric of each of the blocks of each of the sets of the blocks while the at least some of the blocks of the at least some of the sets of the blocks marked active in the data structure are being used for data storage operations. The controller can further be configured to determine when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value. The controller may further be configured to mark the one of the blocks of the one of the sets of blocks as temporarily inactive in the data structure, the one of the blocks of the one of the sets of blocks not being used for the data storage operations while it is temporarily inactive in the Data structure is highlighted. The controller may further be configured to mark the one of the blocks of the one of the sets of blocks as active in the data structure when at least one criterion is met, the one of the blocks of the one of the sets of blocks being used again for the data storage operations while it is marked as active in the data structure.

It should be understood that other configurations of the present technology will become readily apparent to those skilled in the art from the following detailed description, with various configurations of the present technology shown and described for purposes of illustration. It should be understood that the present technology can have other and different configurations, and its several details can be modified in various other respects, without each departing from the scope of the present technology. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not restrictive.

Figure list

• 1 zeigt ein beispielhaftes Flash-Speichersystem, das ein System zur Bereitstellung von adaptiver Abnutzungs-Nivellierung implementieren kann, gemäß einer oder mehreren Implementierungen.
• 2 zeigt beispielhafte logische Gruppierungen von physischen Blöcken von Flash-Speicherschaltungen in einer beispielhaften Flash-Speichervorrichtung gemäß einer oder mehreren Implementierungen.
• 3 zeigt ein Flussdiagramm eines beispielhaften Prozesses zur adaptiven Abnutzungs-Nivellierung unter Verwendung von Coderatenverschiebung gemäß einer oder mehreren Implementierungen.
• 4 zeigt ein Flussdiagramm eines beispielhaften Prozesses zur adaptiven Abnutzungs-Nivellierung unter Verwendung von empirisch bestimmten erwarteten Zykluszählwerten gemäß einer oder mehreren Implementierungen.

Certain features of the present technology are set out in the appended claims. For purposes of explanation, however, several embodiments of the present technology are presented in the following figures.

• 1 FIG. 10 shows an exemplary flash memory system that can implement a system for providing adaptive wear leveling, according to one or more implementations.
• 2 FIG. 10 shows example logical groupings of physical blocks of flash memory circuits in an example flash memory device according to one or more implementations.
• 3 FIG. 12 is a flow diagram of an exemplary process for adaptive wear leveling using code rate shifting, according to one or more implementations.
• 4th FIG. 10 is a flow diagram of an exemplary process for adaptive wear leveling using empirically determined expected cycle counts, according to one or more implementations.

DETAILED DESCRIPTION

The detailed description set forth below is intended as a description of various configurations of the present technology and is not intended to be the only configurations represent in which the present technology can be practiced. The appended drawings are incorporated herein and form a part of the detailed description. The detailed description includes specific details for the purpose of ensuring a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth and can be practiced using one or more implementations. In one or more cases, structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present technology.

In the present adaptive wear leveling system, prior to using flash memory circuits of a flash memory system for data storage, a single physical block on each flash memory circuit (e.g., a single flash memory chip or die) is rapidly cycled (P / E -cycled) until a quality metric assigned to the physical block (e.g. error count, error rate, time for programming) falls below a minimum quality value. The number of cycles used to cause the quality metric of the respective physical block of each respective flash memory circuit to fall below the minimum quality value is stored as the expected cycle count for all physical blocks of the respective flash memory circuit. Accordingly, an assumption is made that the lifetime deviation between physical blocks of a single flash memory circuit is minimal.

While the sets of blocks (or super blocks) arranged from the physical blocks of the flash memory circuits are used for data storage purposes, the present system monitors the expected number of cycles remaining for each of the physical blocks. The expected number of cycles remaining for a given block can be determined by subtracting the current cycle count for the block from the expected cycle count for the block. The present system determines when the expected remaining number of cycles in a block of a given set of blocks falls below the expected remaining number of cycles in other blocks of the given set of blocks. In this case, the present system marks the block as temporarily inactive, which prevents the block from being used in the data storage operations. When the expected remaining cycle counts of the other blocks in the set of blocks catch up with the expected remaining cycle count of the block, the present system marks the block as active, thereby making the block available again for use for data storage operations. The present system can also mark the block as active regardless of the expected remaining cycle counts, e.g. to meet other storage conditions, which are discussed further below.

As an alternative or in addition, the present system can also provide adaptive wear leveling through the use of code rate shifting. In this case, the present system cannot perform the initial fast cycling of a respective block of each of the flash memory circuits, but can instead monitor a quality metric of each of the blocks while the quantities of blocks are used for the data storage operations. If the quality metric of a block falls below a minimum quality value, the block is marked as temporarily inactive. When a certain number of blocks of a given set of blocks have been marked as temporarily inactive, the code rate for the given set of blocks is decreased to compensate for the degradation of the blocks that were temporarily inactive. After the code rate has been decreased for the given set of blocks, all blocks of the given set of blocks are marked as active. The present system can also decrease the code rate of a given set of blocks regardless of the number of blocks of the given set that have been marked as inactive and mark the blocks of the given set of blocks as active, e.g. to meet other storage requirements, which are discussed further below.

In one or more implementations, the present system can implement both the initial fast cycling of a respective block from each of the flash memory circuits and code rate shifting to provide adaptive wear leveling. For example, for each block of a set of blocks, the present system can estimate an expected number of cycles before the quality metric of each block at the current code rate falls below the minimum quality value, e.g. based on the expected cycle count for each block. The present system can then manage the used cycles of the blocks of the set of blocks, e.g. by temporarily deactivating one or more of the blocks as necessary so that most of the blocks of the set of blocks achieve the minimum quality value for the given code rate at substantially the same time. The code rate for the set of blocks is then decreased and all blocks of the set of blocks are marked as active and are again available for data storage operations.

1 Figure 3 shows an exemplary flash memory system 100 that may implement a system for providing adaptive wear leveling, according to one or more implementations. However, not all of the components depicted are required, and one or more implementations may include additional components not shown in the figure. Modifications to the arrangement and type of components can be made without deviating from the spirit or scope of protection of the claims as set out here. Additional components, different components, or fewer components can be provided.

The system 100 includes a flash memory device 110 and a host device 130 . The flash memory device 110 includes one or more flash memory circuits 112A-N , a controller 114 , a random access memory (RAM) 122 and an interface 124 . The control 114 comprises one or more decoders 116 such as ECC decoders, and one or more encoders 118 such as ECC encoder. The one or more decoders 116 and / or the one or more encoders 118 can have one or more dedicated circuits of control 114 and / or can be implemented via firmware running on the controller 114 running.

the interface 124 the flash memory device 110 couples the flash memory device 110 with the host device 130 . the interface 124 can be a wired interface such as a PCMCIA (Personal Computer Memory Card International Association) interface, a SATA (Serial AT Attachment) interface, a USB (Universal Serial Bus) interface, or in general any wired interface. As an alternative or in addition, the interface 124 be a wireless interface, such as a SATA wireless, bluetooth, or in general any wireless interface.

The control 114 is operable to read data from the flash memory circuits 112A-N and to write data into it. For example, the controller receives 114 Data, such as a stream of data, over the interface 124 from the host device 130 , with the data then in one or more of the flash memory circuits 112A-N to be written. The flash memory circuits 112A-N each may include one or more physical blocks, such as NAND blocks and / or NOR blocks. The physical blocks can each include one or more physical pages. The control 114 can use the RAM 122 use to read / write data to / from the flash memory circuits 112A-N to help. For example, the RAM 122 be used as a buffer for rate control or otherwise for storing information (e.g. variable, physical block status, tables of mapping from logical to physical addresses, service life / retention data, settings, etc.) that the control 114 for reading / writing data to / from the flash memory circuits 112A-N used. Since the RAM 122 Can be volatile memory, the controller can 114 Information permanently in one or more of the flash memory circuits 112A-N to save. When the flash memory device 110 is started up, the controller can 114 the information from the one or more flash memory circuits 112A-N and retrieve the information in RAM 122 to save.

The control 114 may include one or more algorithms or techniques associated with reading and / or writing data to the flash memory circuits 112A-N implement such as security techniques (e.g. encryption), error correction coding techniques (e.g. LDPC), compression techniques, redundancy techniques (e.g. redundant independent disk array (RAID) techniques), etc. For example, the controller can 114 Use redundancy techniques by dividing logical amounts of physical blocks across multiple flash memory circuits 112A-N which can be referred to as stripes, super blocks, or sets of blocks. The control 114 can write data as a single unit in a given set of blocks. In this way, the data is stored across several of the flash memory circuits 112A-B distributed and therefore may be recoverable if one or more of the flash memory circuits fail. Exemplary logical groupings of physical blocks of the flash memory circuits 112A-N will be later referring to 2 discussed further.

As the integrity of the flash memory circuits 112A-N deteriorates over time with use, thereby preventing data reading from flash memory circuits 112A-N associated raw bit error rate (RBER) can increase the code rate, such as an ECC code rate or any other code rate specified by the encoder 118 used to encode each of the data items may be different depending on the integrity of the set of blocks into which the encoded data items are written. For example, the flash memory circuits 112A-N be designed to reliably perform a maximum number of data transfer operations, such as program / erase (P / E) and / or read / write cycles, and the integrity of the flash memory circuits 112A-N may degrade as the cycle count increases and / or the flash Memory circuits 112A-N approach or exceed the maximum number of read and / or write operations. To account for this deterioration over time / use, the controller uses 114 Error correction coding with variable code rate, which is done by the encoder 118 Code rate used decreases when the integrity of the flash memory circuits 112A-N deteriorated in order to give the data additional protection.

To determine the correct code rate to use to write data in a given set of blocks, the controller can 114 the integrity of the blocks of the set of blocks of the flash memory circuits 112A-N monitor. The monitoring can be based, for example, on the RBER, which is the reading of data from the flash memory circuits 112A-N assigned. When the controller 114 determines that the integrity of the blocks of a set of blocks of the flash memory circuits 112A-N The control can deteriorate below a threshold amount 114 those by the encoder 118 change (e.g., decrease) the code rate used to perform error correction coding for the amount of blocks. Changing the code rate can be referred to as code rate shift.

However, since lots of blocks are blocks from different flash memory circuits 112A-N each of the blocks of any set of blocks can deteriorate at different rates. If the quality metric of a block of a given set of blocks falls below the minimum acceptable quality value, the controller deactivates 114 thus temporarily the block until a certain number of blocks of the set of blocks has been deactivated. At this point the control decreases 114 the code rate for the entire set of blocks and reactivates all blocks of the set of blocks. An exemplary process for adaptive wear leveling using code rate shifting is discussed later with reference to FIG 3 discussed further. For purposes of explanation, code rates are mentioned here in general; However, code rates can refer to ECC code rates or any code rates in general.

The control 114 can also, for example, quickly run numerous cycles of program / erase (P / E) on a single block of each of the flash memory circuits 112A-N To run. The controller can monitor a quality metric of the block (e.g., RBER, error count, time to program) to empirically determine how many cycles will be performed before the quality metric falls below a minimum acceptable quality value. The control 114 can for example in RAM 122 store the number of cycles performed for the block as the expected cycle count for all blocks of the flash memory circuit containing the block. The control 114 can then temporarily deactivate blocks as necessary to ensure that all blocks of a given set of blocks reach the expected end of life at substantially the same time. Thus, in one or more implementations, the expected cycle count may relate to an end-of-life cycle count, for example. An exemplary process for adaptive wear leveling using empirically determined expected cycle counts is discussed later with reference to FIG 4th discussed further.

In one or more implementations, the controller can 114 , the decoder 116 , the encoder 118 and / or the interface 124 and / or one or more parts thereof in software (e.g. firmware, subroutines and / or code) can be implemented in hardware (e.g. an ASIC (application-specific integrated circuit), an FPGA (Field Programmable Gate Array), a PLD (programmable logic device ), a controller, an automaton, gate logic, discrete hardware components and / or any other suitable devices) and / or a combination of both.

2 Figure 12 shows exemplary logical groupings of physical blocks of flash memory circuits 112A-N in an exemplary flash memory device 110 according to one or more implementations. However, not all of the components depicted are required, and one or more implementations may include additional components not shown in the figure. The arrangement and type of components can be modified without departing from the spirit or scope of the claims presented here. Additional components, different components, or fewer components can be provided.

The exemplary flash memory device 110 includes the interface 124 , the control 114 and one or more flash memory circuits 112A-N . The flash memory circuits 112A-N each comprise one or more physical blocks 202A-P of flash memory, also called blocks 202A-P can be designated. The flash memory circuit 112A includes the blocks 202A-D who have favourited Flash memory circuit 112B includes the blocks 202E-H who have favourited Flash memory circuit 112C includes the blocks 202I-L and the flash memory circuit 112N includes the blocks 202M-P .

As in 2 shown, the control groups 114 the blocks 202A-P of the flash memory circuits 112AN logical in logical sets of Blocks 210A-N , where each of the sets of blocks 210A-N at least one block from each of the flash memory circuits 112A-N includes. The control 114 can be any of the sets of blocks 210AN Use as individual RAID stripes with parity / ECC data to allow data recovery when one or more blocks 202A-P in the individual sets of blocks 210A-N break down. This allows in the flash memory circuits 112A-N written data will still be recovered if one or more of the flash memory circuits 112A-N and / or one or more of the blocks 202A-P fail in it. Any of the sets of blocks 210A-N is controlled by the controller 114 programmed and erased as a logical unit. In one or more implementations, the sets of blocks 210A-N referred to as stripes, super blocks, logical units, etc. Each of the set of blocks 210A-N can be assigned to a different code rate. The set of blocks 210A-N can initially be assigned to the same code rate as a whole; that of the set of blocks 210A-N assigned code rates can change over time and therefore be different.

As in 2 shown includes the set of blocks 210A the block 202A the flash memory circuit 112A , the block 202E the flash memory circuit 112B , the block 2021 the flash memory circuit 112C and the block 202M the flash memory circuit 112N . The set of blocks 210B includes the block 202B the flash memory circuit 112A , the block 202F the flash memory circuit 112B , the block 202J the flash memory circuit 112C and the block 202N the flash memory circuit 112N . The set of blocks 210C includes the block 202C the flash memory circuit 112A , the block 202G the flash memory circuit 112B , the block 202K the flash memory circuit 112C and the block 2020 the flash memory circuit 112N . The set of blocks 210N includes the block 202D the flash memory circuit 112A , the block 202H the flash memory circuit 112B , the block 202L the flash memory circuit 112C and the block 202P the flash memory circuit 112N .

The blocks 202A-P can each be assigned a status, for example by the controller 114 in RAM 122 can be saved. The status of the blocks can include, for example, active blocks, withdrawn blocks, MBBs (Manufacturer Bad Blocks), GBBs (Grown Bad Blocks) or temporarily inactive blocks, which can also be referred to as OVBs (On Vacation Blocks). Blocks that are active may be available for data storage operations (e.g. read / write); However, blocks that are withdrawn, MBBs, GBBs, or temporarily inactive may not be available for data store operations. In 2 are the blocks 202B , G, H, N that are hatched, blocks that are temporarily inactive and therefore not available for data storage operations.

In one or more implementations, the controller can 114 and / or the interface 124 and / or one or more parts thereof in software (e.g. firmware, subroutines and / or code) can be implemented in hardware (e.g. an ASIC (application-specific integrated circuit), an FPGA (Field Programmable Gate Array), a PLD (programmable logic device ), a controller, an automaton, gate logic, discrete hardware components and / or any other suitable devices) and / or a combination of both.

3 Figure 3 shows a flow diagram of an exemplary process 300 adaptive wear leveling using code rate shifting according to one or more implementations. For purposes of illustration, the exemplary process 300 here with reference to the controller 114 from 1 and 2 described; the exemplary process 300 however, is not on the controller 114 from 1 and 2 limited, and one or more blocks of the exemplary process 300 can be controlled by one or more other components 114 are executed. Further, for purposes of illustration, the blocks of the exemplary process 300 described here as occurring in series or linearly. However, there can be multiple blocks of the exemplary process 300 occur in parallel. You must also include the blocks of the exemplary process 300 may not be performed in the order shown and / or one or more of the blocks of the exemplary process 300 do not need to be run.

Before performing any data storage operations on the flash memory circuits 112A-N arranges the control 114 the blocks 202A-P of the flash memory circuits 112A-N in sets of blocks 210A-N at, taking any lot of blocks 210A-N one of the blocks 202A-P from each of the flash memory circuits 112A-N includes and each of the sets of blocks 210A-N is assigned to a code rate (302). For example, the controller can 114 the amount of blocks 210A-N when starting to arrange and / or control 114 can with the arrangement of the set of blocks 210A-N can be pre-configured. In one or more implementations, the controller may 114 the blocks at the same physical block addresses in each of the flash memory circuits 112A-N to form each of the sets of blocks 210A-N to use. The code rate can initially be for each of the Sets of blocks 210A-N be the same but can change over time in use. The blocks 202A-P of the flash memory circuits 112A-N can all be initially marked as active, with the exception of any Manufacturer Bad Blocks.

The control 114 uses the sets of blocks 210A-N to perform data storage operations initiated by the host device 130 specified (304). The data store operations can include one or more read and / or write operations on one or more of the sets of blocks 210A-N and the data storage operations can be performed on the blocks 202A-P of sets of blocks 210A-N that are marked as active are limited. The data storage operations can also result in one or more background operations, such as garbage collection, that require one or more cycles of programming / erasing with respect to one or more of the sets of blocks 210A-N can include.

The control 114 monitors a quality metric of each of the blocks 202A-P each of the sets of blocks 210A-N ( 306 ). The quality metric can include, for example, RBER, error count, time to program, and so on. The control 114 determines whether the quality metric for a block, such as the block 202B , one of the sets of blocks, such as the set of blocks 210B , falls below the minimum quality value ( 308 ). The minimum quality value can be, for example, the maximum RBER that can be sustained while adhering to predetermined performance constraints, such as read and / or write times.

When the controller 114 determines that the quality metric of a block is one of the sets of blocks, such as the block 202B the amount of blocks 210B , falls below the minimum quality value ( 308 ), the control shifts 114 all valid data in the block 202B e.g. in another active block ( 310 ). The control 114 marks the block 202B then as temporarily inactive ( 312 ). For example, the controller can 114 a status of the block 202B that is in RAM 122 will change to indicate that the block 202B temporarily inactive and therefore not available for programming / deletion.

Then the controller determines 114 whether the number of remaining active blocks 202F , J the set of blocks 210B is below a threshold of the minimum number of active blocks. The threshold can be based on the code rate, the amount of blocks 210B is assigned (314). For example, the controller can 114 one through each of the sets of blocks 210A-N Set the minimum available data capacity to be maintained. The available data capacity for a given set of blocks can be determined based on the number of blocks in the set of blocks that are currently active and the data capacity of each block at the given code rate associated with the set of blocks.

When the controller 114 determines the number of remaining active blocks 202F , J the set of blocks 210B for the code rate is below the threshold of the minimum number of active blocks ( 314 ), decreases the control 114 that of the set of blocks 210B assigned code rate ( 320 ) to reduce the quality of the temporarily inactive blocks 202B , N the set of blocks 210B to compensate. After reducing the code rate ( 320 ) marks the control 114 all temporarily inactive blocks 202B , N the set of blocks 210B as active, so the blocks 202B , N are available again for data storage operations ( 322 ).

When the controller 114 that determines the number of active blocks 202F , J in the set of blocks 210B does not fall below the threshold of the minimum number of active blocks ( 314 ), determines the control 114 whether the total number of active blocks 202A-P across all flash memory circuits 112A-N has fallen below the threshold of the minimum number of active blocks ( 316 ). For example, if the number of active blocks falls below a threshold of the minimum number of active blocks, overprovisioning of the flash memory device may be 110 reach a minimum value and therefore it may be necessary to make more blocks active.

When the controller 114 determines that the total number of active blocks 202A-P via the flash memory circuits 112A-N has fallen below the threshold of the minimum number of active blocks, the controller searches 114 after one of the sets of blocks 210A-N , such as the amount of blocks 210B that has one or more temporarily inactive blocks ( 318 ). For example, the controller can 114 after one of the sets of blocks 210A-N look that is relative to the other sets of blocks 210A-N has the highest number of temporarily inactive blocks. On the identification of a lot of blocks 210B down the control 114 the code rate of the identified set of blocks 210B ( 320 ), marks all temporarily inactive blocks 202B , N the set of blocks 210B as active ( 322 ) and repeat the process ( 318-322 ) until the total number of active blocks across all flash memory circuits 112AN exceeds the threshold of the minimum number of active blocks ( 316 ).

4th Figure 3 shows a flow diagram of an exemplary process 400 of adaptive wear leveling using empirical certain expected cycle counts according to one or more implementations. For purposes of illustration, the exemplary process 400 here with reference to the controller 114 from 1 and 2 described; the exemplary process 400 however, is not on the controller 114 from 1 and 2 limited, and one or more blocks of the exemplary process 400 can be controlled by one or more other components 114 are executed. Further, for purposes of illustration, the blocks of the exemplary process 400 described here as occurring in series or linearly. However, there can be multiple blocks of the exemplary process 400 occur in parallel. You must also include the blocks of the exemplary process 400 may not be performed in the order shown and / or one or more of the blocks of the exemplary process 400 do not need to be run.

Before performing any data storage operations on the flash memory circuits 112A-N selects the controls 114 the first flash memory circuit 112A the flash memory device 110 out ( 402 ). The control 114 performs fast programming / erasing (P / E) cycles on a block 202A from the first flash memory circuit 112A off until one of the block 202A associated quality metric falls below a minimum quality value (404). The quality metric can be, for example, RBER, error count, time to program, etc. The control 114 marks the block 202A then as inactive or withdrawn, leaving the block 202A will not be available for data storage operations (406). The control 114 stores the number of P / E cycles that caused the quality metric of the block 202A falls below the minimum quality value than the expected cycle count of the remaining blocks 202B-D the flash memory circuit 112A ( 408 ).

The control 114 determines if there is any additional flash memory circuitry 112B-N in the flash memory device 110 gives ( 410 ). When the controller 114 determines that there will be additional flash memory circuits 112B-N in the flash memory device 110 there, the controller chooses 114 the next flash memory circuit 112B out ( 412 ) and repeat the process ( 404-408 ). When the controller 114 determines that there are no more flash memory circuits 112A-N in the flash memory device 110 there, the controller assigns 114 the blocks 202A-P of the flash memory circuits 112A-N in sets of blocks 210A-N at, taking any lot of blocks 210A-N one block from each of the flash memory circuits 112A-N includes ( 418) .

The control 114 uses the sets of blocks 210A-N to perform data storage operations initiated by the host device 130 be specified ( 420 ). The data store operations can include one or more read and / or write operations on one or more of the sets of blocks 210A-N and the data storage operations can be performed on the blocks 202A-P of sets of blocks 210A-N that are marked as active are limited. The data storage operations can also result in one or more background operations, such as garbage collection, that require one or more cycles of programming / erasing with respect to one or more of the sets of blocks 210A-N can include.

The control 114 monitors an expected remaining cycle count of each of the blocks 202A-P each of the sets of blocks 210A-N ( 422 ). The expected remaining cycle count of each of the blocks 202A-P can be based on the for each of the blocks 202A-P stored expected cycle count minus the current cycle count (or number of cycles used) for each of the blocks 202A-P to be determined. The control 114 temporarily deactivates one or more blocks 202A-P each of the sets of blocks 210AN as necessary to get balanced remaining cycle counts of the blocks 202A-P each of the sets of blocks 210A-N while also maintaining a minimum number of active blocks for each of the sets of blocks 210A-N is maintained ( 424 ).

For example, if the remaining cycle count of the block 202A by a threshold amount behind the expected cycle count of another of the blocks 202E , I, M in the set of blocks 210A falls, the block can 202A can be set to temporarily inactive. The block 202A can remain temporarily inactive until the expected remaining cycle counts from one or more of the other blocks 202E , I, M of the set of blocks 210A the expected remaining cycle count of the block 202A catch up (or fall within a threshold). At this point the block can 202A marked as active and therefore available again for data storage operations. If the total number of active blocks 202E , I, M for the amount of blocks 210A however, below a minimum number of active blocks for the set of blocks 210A falls, the block can 202A marked as active regardless of the expected remaining cycles of the other blocks 202E , I, M the block 202A catch up.

The control 114 determines whether a total number of active blocks 202A-P in the flash memory device 110 has fallen below a minimum number of active blocks (426). When the controller 114 determines that the total number of active blocks 202A-P in the flash memory device 110 under the minimum number of active blocks has fallen (426), the controller is activated 114 some of the temporarily inactive blocks at least some of the sets of blocks 210A-N , for example, regardless of expected remaining cycles, the total number of active blocks in the flash memory device 110 to increase beyond the threshold of the minimum number of active blocks ( 428 ).

Implementations within the scope of the present disclosure may be realized in whole or in part using a tangible computer readable storage medium (or more tangible computer readable storage media of one or more types) that encodes one or more instructions. The tangible computer readable storage medium can also be non-transitory in nature.

The computer readable storage medium can be any storage medium that can be read and written to or otherwise accessed by general purpose or special purpose computing apparatus, including any processing electronics and / or processing circuitry capable of executing instructions. For example and without limitation, the computer readable medium can include any volatile semiconductor memory, such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. The computer readable medium can also include any non-volatile semiconductor memory such as ROM, PROM, EPROM, EEPROM, NVRAM, Flash, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, Racetrack memory, FJG and Millipede store.

Further, the computer readable storage medium can include any non-semiconductor storage medium, such as optical disk storage, magnetic disk storage, magnetic tape, other magnetic storage devices, or any other medium capable of storing one or more instructions. In some implementations, the tangible computer readable storage medium may be coupled directly to a computing device, while in other implementations the tangible computer readable storage medium may e.g. may be indirectly coupled to a computing device via one or more wired connections, one or more wireless connections, or any combination thereof.

Statements can be directly executable or can be used to develop executable statements. For example, instructions can be implemented as executable or non-executable machine code or as high-level language instructions that can be compiled to produce executable or non-executable machine code. Furthermore, instructions can also be implemented as data or can include such. Computer-executable instructions can also be organized in any format including routines, subroutines, programs, data structures, objects, modules, applications, applets, functions, etc. As will be appreciated by those skilled in the art, details including, but not limited to, the number, The structure, sequence and organization of instructions can be very different without changing the underlying logic, function, processing and output.

Although the above discussion mainly relates to microprocessors or multi-core processors that execute software, one or more implementations are carried out by one or more integrated circuits, such as ASICs (application specific integrated circuits) or FPGAs (field programmable gate arrays). In one or more implementations, such integrated circuits execute instructions that are stored on the circuit itself.

Those skilled in the art will recognize that the various example blocks, modules, elements, components, methods, and algorithms described herein can be implemented as electronic hardware, computer software, or combinations of both. In order to illustrate this interchangeability of hardware and software, various exemplary blocks, modules, elements, components, methods, and algorithms have been described above in general with regard to their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and design constraints that are imposed on the overall system. Those skilled in the art can implement the functionality described in different ways for each specific application. Various components and blocks can be rearranged (e.g., arranged in a different order or divided in a different way) without, in each case, departing from the scope of the present technology.

It should be understood that any specific order or hierarchy of blocks in the disclosed processes is an illustration of example approaches. Based on design preferences, it will be understood that the specific order or hierarchy of blocks in the processes can be rearranged or that all of the represented blocks can be executed. Any of the blocks can be executed at the same time. In one or more implementations, multitasking and parallel processing may be beneficial. Also should be the separation of different System components in the embodiments described above are not to be construed as requiring such separation in all embodiments, and it is to be understood that the program components and systems described can generally be integrated together in a single software product or packaged into multiple software products.

As used in the present specification and any claims of this application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technological devices . These terms exclude people or groups of people. For purposes of description, the terms "display" or "display" mean displaying on an electronic device.

As used herein, the term "at least one of" preceding a series of items, with the term "and" or "or" to separate any of the items, modifies the list as a whole, rather than each element of the list (i.e., each item) . The phrase "at least one of" does not require selecting at least one of each of the items listed; instead, the term allows for a meaning that includes at least one of any of the items and / or at least one of any combination of the items and / or at least one of any of the items. For example, the terms "at least one of A, B and C" or "at least one of" A, B or C "each refer to only A, only B, or only C; any combination of A, B and C; and / or at least one of each of A, B and C.

The predicates “designed for”, “operable for” and “programmed for” do not require any concrete, tangible or intangible modification of a subject, but should instead be used interchangeably. In one or more implementations, a processor designed to monitor and control an operation or component may also mean that the processor is programmed to monitor and control the operation, or the processor is operable to monitor and control the operation. Similarly, a processor designed to execute code can be thought of as a processor programmed to execute code or operable to execute code.

Expressions such as an aspect, the aspect, another aspect, some aspect, one or more aspects, an implementation, the implementation, another implementation, some implementations, one or more implementations, an embodiment, the embodiment, another embodiment, some embodiments , one or more embodiments, a configuration, the configuration, another configuration, some configurations, one or more configurations, the present technology, the disclosure, the present disclosure, or other variations thereof, and the like are for convenience and are not intended to imply any such expression or disclosure relating to such expressions is essential to the present technology or that such disclosure applies to all configurations of the present technology. A disclosure regarding such a term or such terms may apply to all configurations or to one or more configurations. A disclosure relating to such a term or expressions may give one or more examples. A term, such as an aspect or some aspects, can refer to one or more aspects and vice versa, and the same applies to other expressions above.

The word “exemplary” is used here to mean “serving as an example, case, or illustration”. Any embodiment described herein as “exemplary” or as an “example” is not necessarily to be construed as preferred or advantageous over other embodiments. Further, to the extent that the term “contain”, “have” or the like is used in the specification or claims, such term is intended to be inclusive in a manner similar to the term “comprise” since “comprise” is interpreted when used as a transitional word is used in a claim.

The above description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will readily occur to those skilled in the art, and the generic principles defined herein can be applied to other aspects. The claims are therefore not to be restricted to the aspects shown here, but are to be given the full scope of protection compatible with the language claims, whereby mention of an element in the singular is not intended to mean “one and only one”, unless it is specifically stated as such, but “ one or more ". Unless specifically stated otherwise, the term “some” refers to one or more. Male pronouns (e.g. his) include the feminine and neutral gender (e.g. her and his) and vice versa. Any titles and subtitles are provided for convenience only and do not limit the present disclosure.

Claims (21)

Apparatus comprising: at least one processor designed for Using sets of blocks of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the flash memory circuits and at least some of the blocks of at least some of the sets of blocks being marked active, the at least some of the blocks that at least some of the sets of blocks marked active are used for data storage operations; Monitoring quality metrics of each block of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks marked as active are being used for data storage operations; Determining when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value; Marking the one of the blocks of the one of the sets of blocks as temporarily inactive, the one of the blocks of the one of the sets of blocks not being used for the data storage operations while it is marked as temporarily inactive; Determining that at least one criterion is met if, for a code rate assigned to one of the sets of blocks, a number of the blocks of the one of the sets of blocks that are marked as active falls below a minimum number of active blocks, each of the sets of blocks the code rate is assigned; and if the at least one criterion is met, marking the one of the blocks of the one of the sets of blocks as active, the one of the blocks of the one of the sets of blocks being reused for the data storage operations while it is marked as active. Device according to Claim 1 wherein the at least one processor is further configured, in response to determining that the criterion is met, reducing the code rate associated with the one of the sets of blocks; and in response to decreasing the code rate, marking any blocks of the one of the sets of blocks marked temporarily inactive as active, wherein any blocks of the one of the sets of blocks marked active are reused for the data storage operations become. Device according to Claim 2 , where the minimum number of active blocks for the code rate is smaller than another minimum number of active blocks for the reduced code rate. Device according to Claim 2 or 3 wherein the at least one processor is further configured to determine that the at least one criterion is met when a current storage capacity falls below a minimum storage capacity across all sets of blocks; in response to determining that the criterion is met, identifying at least one of the sets of blocks for which at least one block is marked temporarily inactive; Reducing the code rate associated with the identified at least one of the sets of blocks; and in response to reducing the code rate, marking any blocks of the at least one of the sets of blocks marked as temporarily inactive as active, with any blocks of the at least one of the sets of blocks marked as active again for the Data storage operations can be used. Device according to Claim 4 wherein the at least one processor is further configured to repeat the identifying, reducing and marking until the current storage capacity over the entire set of blocks exceeds the minimum storage capacity. Device according to Claim 4 or 5 wherein the at least one processor is further configured to determine the current storage capacity based at least in part on a number of blocks of each of the sets of blocks marked as active and the code rate associated with each of the sets of blocks. Device according to one of the Claims 4 to 6th wherein the at least one processor is further configured to identify the at least one of the sets of blocks for which at least one block is marked as temporarily inactive by determining that the at least one of the sets of blocks is greatest relative to another of the sets of blocks Includes number of temporarily inactive blocks. Device according to one of the preceding claims, wherein the at least one processor is further configured to move any valid data in the one of the blocks of the one of the sets of blocks prior to marking the one of the blocks of the one of the sets of blocks as temporarily inactive. Apparatus according to any preceding claim, wherein the apparatus further comprises at least one random access memory circuit and the flash memory circuits comprising blocks of physical blocks of the flash memory circuits and the at least one processor is further configured to Using the sets of the blocks of the flash memory circuits to perform the data storage operations as indicated by a host device; and Maintaining a data structure stored in the at least one random access memory circuit, the data structure comprising a status of each block of each of the sets of blocks, the status of each block of each of the sets of blocks at least indicating whether each block of each of the sets of blocks is marked as active or is marked as temporarily inactive. Device according to one of the preceding claims, wherein the quality metric comprises an error count and / or an error rate and / or a time for programming. Device according to one of the preceding claims, wherein the at least one processor is configured to arrange the blocks of the flash memory circuits into the sets of blocks. Method comprising: Using sets of blocks from a plurality of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the plurality of flash memory circuits and at least some of the blocks at least some of the sets of blocks being marked as active, wherein the at least some of the blocks of the at least some of the sets of blocks marked as active are used for the data storage operations; Monitoring a remaining cycle count of each of the blocks of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks marked active are being used for the data storage operations, the remaining cycle count of each of the blocks of each of the sets of Blocks based at least in part on an expected cycle count associated with each of the plurality of flash memory circuits including each of the blocks of each of the sets of blocks; Marking the one of the blocks of the one of the sets of blocks as temporarily inactive when the remaining cycle count of one of the blocks of one of the sets of blocks meets at least a first criterion, the one of the blocks of the one of the sets of blocks not being used for data storage operations while marked as temporarily inactive; Determine that at least a second criterion is met when a number of the blocks of one of the sets of blocks marked as active falls below a minimum number of active blocks for a code rate associated with the one of the sets of blocks, each of the Sets of blocks are assigned the code rate; and Marking the one of the blocks of the one of the sets of blocks as active when at least a second criterion is met, the one of the blocks of the one of the sets of blocks being reused for the data storage operations while it is marked as active. Procedure according to Claim 12 wherein the remaining cycle count of the one of the blocks of the one of the sets of blocks satisfies the at least one first criterion if the remaining cycle count of the one of the blocks of the one of the sets of blocks by a threshold number of cycles from another remaining cycle count of another of the blocks one of the sets of blocks is different. Procedure according to Claim 13 , further comprising: determining that the at least one second criterion is met if the remaining cycle count associated with the one of the blocks of the one of the sets of blocks is equal to the other remaining cycle count associated with the other of the blocks of the one of the sets of blocks. Method according to one of the Claims 12 to 14th further comprising: cycling a respective block of each of the plurality of flash memory circuits prior to using any of the blocks of any of the sets of blocks for read or write operations until a respective quality metric of the respective block of each of the plurality of flash memory circuits falls below a minimum quality value ; Determining the expected cycle count for each of the plurality of flash memory circuits based at least in part on a number of fast cycles used to cause the respective quality metric of the respective block of each of the plurality of flash memory circuits to fall below the minimum quality value; and storing the expected cycle count for each of the plurality of flash memory circuits in association with each of the blocks of each of the plurality of flash memory circuits. Procedure according to Claim 15 further comprising: marking the respective block of each of the plurality of flash memory circuits as inactive after cycling the respective block of each of the plurality of flash memory circuits. Procedure according to Claim 15 or 16 , further comprising: Determining the remaining cycle count for each of the blocks of each of the sets of blocks based at least in part on the expected cycle count associated with each of the blocks of each of the sets of blocks and a number of cycles used for the data storage operations for each of the blocks of each of the sets of blocks becomes. Method according to one of the Claims 12 to 17th , further comprising: determining that the at least one second criterion is met if a current storage capacity falls below a minimum storage capacity across all sets of blocks. A computer program product comprising code stored in a non-transitory computer readable storage medium, the code comprising: Code for using sets of blocks of flash memory circuits for data storage operations, each of the sets of blocks including at least one block from each of the flash memory circuits and at least some of the blocks of at least some of the sets of blocks being marked as active, the at least some the blocks of the at least some of the sets of blocks marked active are used for the data storage operations; Code for monitoring quality metrics of each block of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks that are marked active are used for data storage operations; Code for determining when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value; Code for marking the one of the blocks of the one of the sets of blocks as temporarily inactive, the one of the blocks of the one of the sets of blocks not being used for data storage operations while it is marked as temporarily inactive; Code for determining that the at least one criterion is met if, for the code rate assigned to the one of the sets of blocks, a number of the blocks of the one of the sets of blocks that are marked as active falls below a minimum number of active blocks, each of the Sets of blocks are assigned the code rate; and Code for marking the one of the blocks of the one of the sets of blocks as active when the at least one criterion is met, the one of the blocks of the one of the sets of blocks being reused for data storage operations while it is marked as active. Computer program product according to Claim 19 the code further comprising: code for decreasing the code rate associated with the one of the sets of blocks when the criterion is met; and code for marking any blocks of the one of the sets of blocks marked temporarily inactive as active when the code rate has been decreased, wherein any blocks of the one of the sets of blocks marked active are reused for the data storage operations become. A system comprising: a plurality of flash memory circuits each including blocks; a random access memory (RAM) configured to store a data structure including a status of each of the blocks of each of the plurality of flash memory circuits, the status of each of the blocks of each of the plurality of flash memory circuits at least indicating whether each of the blocks of each of the plurality marked as active or temporarily inactive by flash memory circuits; an interface communicatively coupled to a host device; and a controller configured to use amounts of the blocks of the plurality of flash memory circuits for data storage operations indicated by the host device, each of the amounts of the blocks including at least one block from each of the plurality of flash memory circuits and at least some marking the blocks of at least some of the sets of blocks in the data structure as active, the at least some of the blocks of the at least some of the sets of blocks marked active in the data structure being used for the data storage operations; Monitoring a quality metric of each of the blocks of each of the sets of the blocks while the at least some of the blocks of the at least some of the sets of the blocks marked active in the data structure are being used for the data storage operations; Determining when the quality metric of one of the blocks of one of the sets of the blocks falls below a minimum quality value; Marking the one of the one of the sets of blocks in the data structure as temporarily inactive, the one of the blocks of the one of the sets of blocks not being used for data storage operations while it is marked as temporarily inactive in the data structure; Determining that at least one criterion is met if, for a code rate assigned to one of the sets of blocks, a number of the blocks of the one of the sets of blocks that are marked as active falls below a minimum number of active blocks, each of the sets of blocks the code rate is assigned; and marking the one of the blocks of the one of the sets of blocks as active in the data structure when the at least one criterion is met, the one of the blocks of the one of the sets of blocks being reused for the data storage operations while it is in the data structure as active is marked.

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