DE102017112560A1 - ADAPTIVE WEAR ADJUSTMENT - Google Patents

Abstract

An apparatus that provides adaptive wear leveling includes at least one processor. The at least one processor uses sets of blocks of flash memory circuits for data storage operations, each set of blocks comprising one block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked as active are used for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum value and marks the block as temporarily inactive, which block is not used for the data storage operations while being marked as temporarily inactive. If a criterion is met, the at least one processor marks the block as active so that the block can be reused for the data storage operations.

Description

REFER TO RELATED APPLICATIONS

 The present application claims the benefit of US Provisional Patent Application No. 62 / 368,967, entitled "Adaptive Wear Leveling", filed July 29, 2016, which is hereby incorporated by reference in its entirety for all purposes.

TECHNICAL AREA

 The present description relates generally to wear leveling, including adaptive wear leveling for flash memory devices.

STATE OF THE ART

 In a flash memory system, the system typically uses a wear leveling algorithm to maintain long life, keeping all physical blocks within a narrow range of cumulative programming / erasing (P / E) cycles. The assumption is that the physical blocks all have the same life (ignoring the weak blocks that are compensated for by over provisioning) and therefore all wear out at substantially the same time. However, in practice, the physical blocks do not all have the same lifetime. Thus, the flash memory system can reach its specified end of life, although many of the physical blocks are still usable.

SHORT VERSION

 The disclosed subject matter relates to a device comprising at least one processor. The at least one processor may be configured to use sets of blocks of flash memory circuits for data storage operations, each of the sets of blocks comprising at least one block of each of the flash memory circuits and marking at least some of the blocks of at least some of the sets of blocks as active wherein the at least some of the blocks of the at least some of the sets of blocks marked active are used for the data storage operations. The at least one processor may be further configured to monitor quality metrics of each block of each of the sets of blocks while using the at least some of the blocks of the at least some of the sets of blocks marked as active for the data storage operations. The at least one processor may be further configured to determine when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value. The at least one processor may be further configured to mark one of the blocks of the one of the sets of blocks as temporarily inactive, wherein the one of the blocks of the one of the sets of blocks is not used for the data storage operations while being marked as temporarily inactive. The at least one processor may be further configured to mark one of the blocks of the one of the sets of blocks as active if at least one criterion is satisfied, wherein the one of the blocks of the one of the sets of blocks is reused for the data storage operations while it is being used marked as active.

 In another aspect, a method may include using sets of blocks from a plurality of flash memory circuits for data storage operations, each of the sets of blocks comprising at least one block of each of the plurality of flash memory circuits and at least some of the blocks of at least some the sets of blocks are marked active, the at least some of the blocks of the at least some of the sets of blocks marked active being used for the data storage operations. The method may further comprise monitoring a remaining cycle count of each of the blocks of each of the sets of blocks, while using the at least some of the blocks of the at least some of the sets of blocks marked as active for the data storage operations, the remaining cycle count each of the blocks of each of the sets of blocks is based at least in part on an expected cycle count associated with each of the plurality of flash memory circuits containing each of the blocks of each of the sets of blocks. The method may further comprise marking the one of the blocks of the one of the sets of blocks as temporarily inactive if the remaining cycle count of one of the blocks of one of the sets of blocks meets at least a first criterion, wherein the one of the blocks is one of the sets of Blocks is not used for the data storage operations while it is marked as temporarily inactive. The method may further comprise marking the one of the blocks of the one of the sets of blocks as active if at least a second criterion is met, wherein the one of the blocks of the one of the sets of blocks is reused for the data storage operations while serving as is active.

In another aspect, a computer program product includes code stored in a non-transitory computer-readable storage medium. The code may include code to quickly access a respective physical block of each of a plurality of flash memory circuits until a respective quality metric of the respective physical block of each of the plurality of flash memory circuits falls below a minimum quality value. The code may further comprise code for determining an expected cycle count for each of the plurality of flash memory circuits based at least in part on a number of fast cycles used to cause the respective quality metric of the respective physical block to be any one of Variety of flash memory circuits falls below the minimum quality value. The code may further comprise code to store in at least one random access memory circuit the expected cycle count for each of the plurality of flash memory circuits in individual association with physical blocks of each of the plurality of flash memory circuits.

 In another aspect, a system may include a plurality of flash memory circuits, each comprising blocks, a random access memory (RAM) configured to store a data structure comprising a status of each of the blocks of each of the plurality of flash memory circuits, the status of each the blocks of each of the plurality of flash memory circuits at least indicate whether each of the blocks of each of the plurality of flash memory circuits is marked active or temporarily inactive, an interface and controller communicatively coupled to a host device. The controller may be configured to use sets of the blocks of the plurality of flash memory circuits for data storage operations specified by the host device, each of the sets of blocks comprising at least one block of each of the plurality of flash memory circuits and at least some the blocks of at least some of the sets of blocks in the data structure are marked active, the at least some of the blocks of the at least some of the sets of blocks marked active in the data structure being used for the data storage operations. The controller may be further configured to monitor a quality metric of each of the blocks of each of the sets of blocks while the at least some of the blocks of the at least some of the sets of blocks marked active in the data structure are used for the data storage operations. The controller may be further configured to determine when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value. The controller may be further configured to mark one of the blocks of the one of the sets of blocks as temporarily inactive in the data structure, wherein the one of the blocks of the one of the sets of blocks is not used for the data storage operations while being temporarily inactive in the data storage operations Data structure is highlighted. The controller may be further configured to mark one of the blocks of the one of the sets of blocks as active in the data structure when at least one criterion is met, wherein the one of the blocks of the one of the sets of blocks is reused for the data storage operations it is marked as active in the data structure.

 It will be understood that other configurations of the present technology will become readily apparent to those skilled in the art from the following detailed description, with various configurations of the present technology shown and described by way of illustration. It should be understood that the present technology may have other and different configurations and its several details may be modified in various other respects without departing from the scope of the present technology. The drawings and detailed description are accordingly to be regarded as illustrative and not restrictive.

BRIEF DESCRIPTION OF THE DRAWINGS

 Certain features of the present technology are set forth in the appended claims. However, for purposes of explanation, several embodiments of the present technology are set forth in the following figures.

1 FIG. 12 shows an exemplary flash memory system that may implement a system for providing adaptive wear leveling, according to one or more implementations.

2 FIG. 12 shows exemplary logical groupings of physical blocks of flash memory circuits in an exemplary flash memory device according to one or more implementations.

3 FIG. 12 shows a flowchart of an exemplary adaptive wear leveling process using code rate shift according to one or more implementations.

4 FIG. 12 is a flowchart of an exemplary adaptive wear leveling process using empirically determined expected cycle counts according to one or more implementations. FIG.

DETAILED DESCRIPTION

The detailed description given below is a description of various Concepts of the present technology are not intended to be the only configurations in which the present technology can be practiced. The attached drawings are incorporated herein and form a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth herein and may be practiced using one or more implementations. In one or more instances, structures and components are shown in block diagram form to avoid obscuring the concepts of the present technology.

 In the present adaptive wear leveling system, prior to using flash memory circuits of a flash memory system for data storage, a single physical block on each flash memory circuit (eg, a single flash memory chip) is quickly cycled (P / E -cycled) until a quality metric associated with the physical block (eg, error count, error rate, time to program) falls below a minimum quality value. The number of cycles used to cause the quality metric of the respective physical block of each respective flash memory circuit to fall below the minimum quality value is stored as the expected cycle count for all physical blocks of the respective flash memory circuit. Accordingly, there is an assumption that the life deviation between physical blocks of a single flash memory circuit is minimal.

 While the amounts of blocks (or super blocks) arranged from the physical blocks of the flash memory circuits are used for data storage purposes, the present system monitors the expected remaining number of cycles for each of the physical blocks. The expected remaining number of cycles for a given block can be determined by subtracting the current cycle count for the block from the expected cycle count for the block. The present system determines when the expected remaining number of cycles in a block of a given set of blocks falls short of the expected remaining number of cycles of other blocks in the given set of blocks. In this case, the present system marks the block as temporarily inactive, preventing the block from being used in the data storage operations. If the expected remaining cycle counts of the other blocks in the set of blocks catch up with the expected remaining cycle count of the block, the present system marks the block as active, making the block available again for use in data storage operations. The present system may also mark the block active, regardless of the expected remaining cycle counts, e.g. to meet other storage conditions, which will be discussed further below.

 Alternatively or additionally, the present system may also provide adaptive wear leveling by using code rate shifting. In this case, the present system can not perform the initial fast cycling of a respective block of each of the flash memory circuits, but instead can monitor a quality metric of each of the blocks while using the sets of blocks for the data storage operations. If the quality metric of a block falls below a minimum quality value, the block is marked as temporarily inactive. If a certain number of blocks of a given set of blocks have been marked as temporarily inactive, the code rate for the given set of blocks is decreased to compensate for the quality reduction of the blocks that were temporarily inactive. After the code rate has been reduced for the given set of blocks, all blocks of the given set of blocks are marked as active. The present system can also reduce the code rate of a given set of blocks regardless of the number of blocks of the given set marked as inactive and mark the blocks of the given set of blocks as active, e.g. to meet other storage conditions, which will be discussed further below.

In one or more implementations, the present system may implement both the initial fast cycling of a respective block of each of the flash memory circuits and the code rate shift to provide adaptive wear leveling. For example, for each block of a set of blocks, the present system may estimate an expected number of cycles before the quality metric of each block at the current code rate falls below the minimum quality value, eg, based on the expected cycle count for each block. The present system can then manage the used cycles of the blocks of the set of blocks, eg by temporarily deactivating one or more of the blocks as necessary, so that most of the blocks of the set of blocks at substantially the same time for the given one Code rate reach the minimum quality value. The code rate for the set of blocks is then decreased and all blocks of the set of blocks are marked as active and are available again for data storage operations.

1 shows an exemplary flash memory system 100 , which may implement a system for providing adaptive wear leveling, according to one or more implementations. However, not all imaged components may be required, and one or more implementations may include additional components not shown in the figure. Modifications of the arrangement and nature of the components may be made without departing from the spirit or scope of the claims as set forth herein. Additional components, other components, or fewer components may be provided.

The system 100 includes a flash memory device 110 and a host device 130 , The flash memory device 110 includes one or more flash memory circuits 112A -N, a controller 114 , a random access memory (RAM) 122 and an interface 124 , The control 114 includes one or more decoders 116 , such as error correction code (ECC) decoder, and one or more encoders 118 , such as ECC encoders. The one or more decoders 116 and / or the one or more encoders 118 can control one or more dedicated circuits 114 be and / or can be implemented via firmware that runs on the controller 114 running.

the interface 124 the flash memory device 110 couples the flash memory device 110 with the host device 130 , the interface 124 may be a wired interface, such as a PCMCIA (Personal Computer Memory Card International Association) interface, a Serial AT Attachment (SATA) interface, a Universal Serial Bus (USB) interface, or generally any wired interface. As an alternative or in addition, the interface 124 a wireless interface, such as a wireless SATA, Bluetooth, or generally any wireless interface.

The control 114 is operable to read data from the flash memory circuits 112A -N and to write data into it. For example, the controller receives 114 Data, such as a stream of data, over the interface 124 from the host device 130 wherein the data is then stored in one or more of the flash memory circuits 112A -N be written. The flash memory circuits 112A -N may each comprise one or more physical blocks, such as NAND blocks and / or NOR blocks. The physical blocks may each include one or more physical pages. The control 114 can the RAM 122 to read / write data to / from the flash memory circuits 112A -N to help. For example, the RAM 122 may be used as a rate control buffer or otherwise for storing information (eg, variable, physical block status, logical-to-physical address mapping tables, lifetime / retention data, settings, etc.) that control 114 for reading / writing data to / from the flash memory circuits 112A -N used. Because of the RAM 122 can be volatile memory, the controller 114 Information permanently in one or more of the flash memory circuits 112A Save -N. When the flash memory device 110 can be ramped up, the controller 114 the information from the one or more flash memory circuits 112A -N and retrieve the information in RAM 122 to save.

The control 114 may include one or more algorithms or techniques associated with reading and / or writing data to the flash memory circuits 112A -N, such as security techniques (eg, encryption), error correction coding techniques (eg, LDPC), compression techniques, redundancy techniques (eg, redundant independent array (RAID) techniques), etc. For example, the controller may 114 Use redundancy techniques by placing logical sets of physical blocks across multiple flash memory circuits 112A -N, which can be referred to as stripes, super blocks, or sets of blocks. The control 114 can write data as a single unit in a given set of blocks. In this way, the data is shared across several of the flash memory circuits 112A -B and therefore may be recoverable if one or more of the flash memory circuits fails. Exemplary logical groupings of physical blocks of the flash memory circuits 112A -N will be related later 2 discussed further.

As the integrity of the flash memory circuits 112A -N deteriorates with use over time, thereby reducing the data read from the flash memory circuits 112A For example, to increase the raw bit error rate (RBER) associated with -N, the code rate, such as an ECC code rate or any other code rate, may be used by the encoder 118 used to encode each of the data items, depending on the integrity of the set of blocks into which the encoded data items are written. For example, the flash memory circuits 112A -N be designed to reliably handle a maximum number of data transfer operations, eg programming / erasing (P / E) cycles and / or read / write operations, and the integrity of the flash memory circuits 112A -N may degrade as the cycle count increases and / or the flash memory circuits increase 112A -N approach or exceed the maximum number of read and / or write operations. To account for this degradation with time / use, the controller uses 114 Error correction coding with variable code rate, wherein the by the encoder 118 used when the integrity of the flash memory circuits 112A -N deteriorates, thereby providing the data with additional protection.

To determine the correct code rate for use in writing data into a given set of blocks, the controller may 114 the integrity of the blocks of the set of blocks of the flash memory circuits 112A -N monitor. The monitoring may be based, for example, on the RBER, which is the data read from the flash memory circuits 112A -N is assigned. If the controller 114 determines that the integrity of the blocks of a set of blocks of the flash memory circuits 112A -N has deteriorated to below a threshold amount, the controller can 114 through the encoder 118 change (eg decrease) the code rate used to perform error correction coding on the set of blocks. Changing the code rate can be called a code rate shift.

However, since lots of blocks blocks from different flash memory circuits 112A -N, each of the blocks of any set of blocks at different rates may degrade. If the quality metric of a block of a given set of blocks falls below the least acceptable quality value, the controller disables 114 thus temporarily blocking the block until a certain number of blocks of the set of blocks has been deactivated. At this time, the controller decreases 114 the code rate for the entire set of blocks and reactivates all blocks of the set of blocks. An exemplary adaptive wear leveling process using code rate shifting will be described later with reference to FIG 3 discussed further. For explanatory purposes, code rates are generally mentioned here; However, code rates may refer to ECC code rates or generally any code rate.

The control 114 For example, at startup, too, can quickly cycle numerous programming / erasing (P / E) cycles on a single block of each of the flash memory circuits 112A -N execute. The controller may monitor a quality metric of the block (eg, RBER, error count, time to program) to empirically determine how many cycles are performed before the quality metric falls below a least acceptable quality value. The control 114 can eg in RAM 122 store the number of cycles performed for the block as the expected cycle count for all blocks of the flash memory circuit containing the block. The control 114 can then temporarily disable blocks as necessary to ensure that all blocks of a given set of blocks reach the expected end of life at substantially the same time. Thus, in one or more implementations, the expected cycle count may refer to, for example, an end-of-life cycle count. An exemplary adaptive wear leveling process using empirically determined expected cycle counts will be described later with reference to FIG 4 discussed further.

In one or more implementations, the controller may 114 , the decoder 116 , the encoder 118 and / or the interface 124 and / or one or more portions thereof may be implemented in software (eg, firmware, subroutines, and / or code), may be implemented in hardware (eg, ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device) ), a controller, a state machine, gate logic, discrete hardware components, and / or any other suitable devices), and / or a combination of both.

2 shows exemplary logical groupings of physical blocks of flash memory circuits 112A In an exemplary flash memory device 110 according to one or more implementations. However, not all imaged components may be required, and one or more implementations may include additional components not shown in the figure. Modifications of the arrangement and nature of the components may be made without departing from the spirit or scope of the claims set forth herein. Additional components, other components or fewer components may be provided.

The exemplary flash memory device 110 includes the interface 124 , the control 114 and one or more flash memory circuits 112A -N. The flash memory circuits 112A -N each include one or more physical blocks 202A -P of flash memory, also called blocks 202A -P can be designated. The flash memory circuit 112A includes the blocks 202A -D, the flash memory circuit 112B includes the blocks 202E -H, the flash memory circuit 112C includes the blocks 202i -L and the flash memory circuit 112N includes the blocks 202M -P.

As in 2 shown, the controller groups 114 the blocks 202A -P of the flash memory circuits 112A -N logical in logical sets of blocks 210A -N, where each of the sets of blocks 210A -N at least one block from each of the flash memory circuits 112A -N includes. The control 114 can any of the sets of blocks 210A Use -N as individual RAID stripes with parity / ECC data to allow data recovery if one or more blocks 202A -P in the individual sets of blocks 210A -N break. In this way, in the flash memory circuits 112A -N data are still restored when one or more of the flash memory circuits 112A -N and / or one or more of the blocks 202A -P fail in it. Each of the sets of blocks 210A -N will be through the controller 114 programmed and deleted as a logical unit. In one or more implementations, the sets of blocks 210A -N are called stripes, super blocks, logical units, and so on. Each of the set of blocks 210A -N can be assigned to a different code rate. The amount of blocks 210A -N can be initially assigned to the same code rate as a whole; that of the set of blocks 210A However, code clocks may change over time and therefore be different.

As in 2 shown, includes the set of blocks 210A the block 202A the flash memory circuit 112A , the block 202E the flash memory circuit 112B , the block 202i the flash memory circuit 112C and the block 202M the flash memory circuit 112N , The amount of blocks 210B includes the block 202B the flash memory circuit 112A , the block 202F the flash memory circuit 112B , the block 202J the flash memory circuit 112C and the block 202N the flash memory circuit 112N , The amount of blocks 210C includes the block 202C the flash memory circuit 112A , the block 202G the flash memory circuit 112B , the block 202K the flash memory circuit 112C and the block 202o the flash memory circuit 112N , The amount of blocks 210N includes the block 202D the flash memory circuit 112A , the block 202H the flash memory circuit 112B , the block 202L the flash memory circuit 112C and the block 202P the flash memory circuit 112N ,

The blocks 202A -P can each be assigned to a status, for example, by the controller 114 in the RAM 122 can be stored. The status of the blocks may include, for example, active blocks, withdrawn blocks, Manufacturer Bad Blocks, GroB Bad Blocks, or temporarily inactive blocks, which may also be referred to as On Vacation Blocks (OVBs). Blocks that are active may be available for data storage operations (eg, read / write); However, blocks that are retired, MBBs, GBBs, or temporarily inactive may not be available for data storage operations. In 2 are the blocks 202B , G, H, N, which are hatched, blocks that are temporarily inactive and therefore not available for data storage operations.

In one or more implementations, the controller may 114 and / or the interface 124 and / or one or more portions thereof may be implemented in software (eg, firmware, subroutines, and / or code), may be implemented in hardware (eg, ASIC (Application Specific Integrated Circuit), FPGA (Field Programmable Gate Array), PLD (Programmable Logic Device) ), a controller, a state machine, gate logic, discrete hardware components, and / or any other suitable devices), and / or a combination of both.

3 shows a flowchart of an example process 300 adaptive wear leveling using code rate shifting according to one or more implementations. For explanatory purposes, the exemplary process 300 here with respect to the controller 114 from 1 and 2 described; the exemplary process 300 but not on the controller 114 from 1 and 2 limited, and one or more blocks of the exemplary process 300 can be controlled by one or more other components of the controller 114 be executed. Further, for purposes of explanation, the blocks of the example process 300 described here as occurring in series or linear. However, there may be multiple blocks of the example process 300 occur in parallel. In addition, the blocks of the example process must 300 not performed in the order shown and / or one or more of the blocks of the example process 300 do not have to be executed.

Before performing any data storage operations on the flash memory circuits 112A -N maps the controller 114 the blocks 202A -P of the flash memory circuits 112A -N in amounts of blocks 210A -N, with lots of blocks 210A -N one of the blocks 202A -P off each of the flash memory circuits 112A -N includes and each of the sets of blocks 210A -N is assigned to a code rate ( 302 ). For example, the controller 114 the amount of blocks 210A -N at startup and / or the controller 114 can with the arrangement of the amount of blocks 210A -N are preconfigured. In one or more implementations, the controller may 114 the blocks at the same physical block addresses in each of the flash memory circuits 112A -N to form each of the sets of blocks 210A Use -N. The code rate may initially be for each of the sets of blocks 210A -N may be the same, but may change over time in use. The blocks 202A -P of the flash memory circuits 112A -N can all initially be marked as active, with the exception of any Manufacturer Bad Blocks.

The control 114 uses the amounts of blocks 210A -N for performing data storage operations by the host device 130 be specified ( 304 ). The data storage operations may include one or more read and / or write operations on one or more of the sets of blocks 210A Include -N and the data storage operations can access the blocks 202A -P of the quantities of blocks 210A -N that are marked as active. The data storage operations may also result in one or more background operations, such as garbage collection, involving one or more cycles of programming / deletion with respect to one or more of the sets of blocks 210A -N can include.

The control 114 monitors a quality metric of each of the blocks 202A -P each of the sets of blocks 210A -N ( 306 ). The quality metric may include, for example, RBER, error count, time to program, and so on. The control 114 determines if the quality metric for a block, such as the block 202B , one of the sets of blocks, such as the amount of blocks 210B , below the minimum quality value falls ( 308 ). For example, the minimum quality value may be the maximum RBER that can be maintained while meeting predetermined performance limitations, such as read and / or write times.

If the controller 114 determines that the quality metric of a block is one of the sets of blocks, such as the block 202B the amount of blocks 210B , below the minimum quality value falls ( 308 ), relocates the controller 114 all valid data in the block 202B eg into another active block ( 310 ). The control 114 marks the block 202B then as temporarily inactive ( 312 ). For example, the controller 114 a status of the block 202B in the ram 122 is saved, change to indicate that the block 202B temporarily inactive and therefore not available for programming / deletion.

Then the controller determines 114 , whether the number of remaining active blocks 202F , J the amount of blocks 210B is below a threshold of the minimum number of active blocks. The threshold may be based on the code rate, that of the set of blocks 210B assigned ( 314 ). For example, the controller 114 one through each of the sets of blocks 210A -N maintain at least available data capacity. The available data capacity for a given set of blocks may be determined based on the number of blocks in the set of blocks that are currently active and the data capacity of each block at the given code rate associated with the set of blocks.

If the controller 114 determines that the number of remaining active blocks 202F , J the amount of blocks 210B for the code rate is below the threshold of the minimum number of active blocks ( 314 ), reduces the control 114 that of the set of blocks 210B assigned code rate ( 320 ) to reduce the quality of temporarily inactive blocks 202B , N the amount of blocks 210B to compensate. After decreasing the code rate ( 320 ) marks the controller 114 all temporarily inactive blocks 202B , N the amount of blocks 210B as active, leaving the blocks 202B , N are available again for data storage operations ( 322 ).

If the controller 114 determines that the number of active blocks 202F , J in the amount of blocks 210B does not fall below the threshold of the minimum number of active blocks ( 314 ), determines the controller 114 whether the total number of active blocks 202A -P over all flash memory circuits 112A -N has fallen below the threshold of the minimum number of active blocks ( 316 ). For example, if the number of active blocks falls below a threshold of the minimum number of active blocks, overprovisioning of the flash memory device may occur 110 reach a minimum value and therefore it may be necessary to make more blocks active.

If the controller 114 determines that the total number of active blocks 202A -P via the flash memory circuits 112A -N has fallen below the threshold of the minimum number of active blocks, seeks control 114 according to one of the sets of blocks 210A -N, such as the amount of blocks 210B which has one or more temporarily inactive blocks ( 318 ). For example, the controller 114 according to one of the sets of blocks 210A -N search, relative to the other sets of blocks 210A -N has a highest number of temporarily inactive blocks. On the identification of a lot of blocks 210B down reduces the control 114 the code rate of the identified set of blocks 210B ( 320 ) marks all temporarily inactive blocks 202B , N the amount of blocks 210B as active ( 322 ) and repeats the process ( 318 - 322 ) until the total number of active blocks across all flash memory circuits 112A -N exceeds the threshold of the minimum number of active blocks ( 316 ).

4 shows a flowchart of an example process 400 adaptive wear leveling using empirically determined expected cycle counts according to one or more implementations. For explanatory purposes, the exemplary process 400 here with respect to the controller 114 from 1 and 2 described; the exemplary process 400 but not on the controller 114 from 1 and 2 limited, and one or more blocks of the exemplary process 400 can be controlled by one or more other components of the controller 114 be executed. Further, for purposes of explanation, the blocks of the example process 400 described here as occurring in series or linear. However, there may be multiple blocks of the example process 400 occur in parallel. In addition, the blocks of the example process must 400 not performed in the order shown and / or one or more of the blocks of the example process 400 do not have to be executed.

Before performing any data storage operations on the flash memory circuits 112A -N selects the controller 114 the first flash memory circuit 112A the flash memory device 110 out ( 402 ). The control 114 performs fast programming / erasure (P / E) cycles on a block 202A from the first flash memory circuit 112A out until one of the block 202A assigned quality metric falls below a minimum quality value ( 404 ). The quality metric may be, for example, RBER, error count, time to program, and so on. The control 114 marks the block 202A then as inactive or withdrawn, leaving the block 202A will not be available for data storage operations ( 406 ). The control 114 stores the number of P / E cycles that has caused the quality metric of the block 202A below the minimum quality value than the expected cycle count of the remaining blocks 202B -D the flash memory circuit 112A ( 408 ).

The control 114 determines if there are any additional flash memory circuits 112B -N in the flash memory device 110 gives ( 410 ). If the controller 114 determines that there are additional flash memory circuits 112B -N in the flash memory device 110 gives, chooses the controller 114 the next flash memory circuit 112B out ( 412 ) and repeats the process ( 404 - 408 ). If the controller 114 determines that there are no more flash memory circuits 112A -N in the flash memory device 110 gives, arranges the control 114 the blocks 202A -P of the flash memory circuits 112A -N in amounts of blocks 210A -N, with lots of blocks 210A -N one block from each of the flash memory circuits 112A Includes -N ( 418 ).

The control 114 uses the amounts of blocks 210A -N for performing data storage operations by the host device 130 be specified ( 420 ). The data storage operations may include one or more read and / or write operations on one or more of the sets of blocks 210A Include -N and the data storage operations can access the blocks 202A -P of the quantities of blocks 210A -N that are marked as active. The data storage operations may also result in one or more background operations, such as garbage collection, involving one or more cycles of programming / deletion with respect to one or more of the sets of blocks 210A -N can include.

The control 114 monitors an expected remaining cycle count of each of the blocks 202A -P each of the sets of blocks 210A -N ( 422 ). The expected remaining cycle count of each of the blocks 202A -P can be based on the for each of the blocks 202A -P stored expected cycle count minus the current cycle count (or number of cycles used) for each of the blocks 202A -P be determined. The control 114 temporarily disables one or more blocks 202A -P each of the sets of blocks 210A -N, as necessary, to balance the remaining cycle counts of the blocks 202A -P each of the sets of blocks 210A -N while simultaneously maintaining a minimum number of active blocks for each of the sets of blocks 210A -N is maintained ( 424 ).

For example, if the remaining cycle count of the block 202A by a threshold amount behind the expected cycle count of another of the blocks 202E , I, M in the amount of blocks 210A falls, the block can 202A be set to temporarily inactive. The block 202A may temporarily remain inactive until the expected remaining cycle counts of one or more of the other blocks 202E , I, M the amount of blocks 210A the expected remaining cycle count of the block 202A (or within a threshold). At this time, the block 202A be marked as active and therefore available again for data storage operations. If the total number of active blocks 202E , I, M for the amount of blocks 210A but below a minimum number of active blocks for the set of blocks 210A falls, the block can 202A be marked as active, regardless of the expected remaining cycles of the other blocks 202E , I, M the block 202A seek.

The control 114 determines if a total number of active blocks 202A -P in the flash memory device 110 under a minimum number of active Blocks has fallen ( 426 ). If the controller 114 determines that the total number of active blocks 202A -P in the flash memory device 110 has fallen below the minimum number of active blocks ( 426 ), activates the controller 114 some of the temporarily inactive blocks of at least some of the sets of blocks 210A -N, for example, regardless of expected remaining cycles, by the total number of active blocks in the flash memory device 110 to increase beyond the threshold of the minimum number of active blocks ( 428 ).

 Implementations within the scope of the present disclosure may be implemented in part or in full using a tangible computer-readable storage medium (or more tangible computer-readable storage media of one or more types) that encodes one or more instructions. The tangible computer readable storage medium may also be non-transitory in nature.

 The computer readable storage medium may be any storage medium that may be read, written to, or otherwise accessed by a general purpose or specialized computing device, including any processing electronics and / or processing circuitry capable of executing instructions. By way of example and not limitation, the computer-readable medium may include any volatile semiconductor memory such as RAM, DRAM, SRAM, T-RAM, Z-RAM, and TTRAM. The computer readable medium may also include any nonvolatile semiconductor memory such as ROM, PROM, EPROM, EEPROM, NVRAM, Flash, nvSRAM, FeRAM, FeTRAM, MRAM, PRAM, CBRAM, SONOS, RRAM, NRAM, Racetrack Memory, FJG, and Millipede memory.

 Further, the computer readable storage medium may include any non-semiconductor memory, such as optical disk storage, magnetic disk storage, magnetic tape, other magnetic storage devices, or any other media capable of storing one or more instructions. In some implementations, the tangible computer readable storage medium may be directly coupled to a data processing device, while in other implementations the tangible computer readable storage medium may be e.g. may be indirectly coupled to a data processing device via one or more wired connections, one or more wireless connections, or any combination thereof.

 Instructions can be directly executable or can be used to develop executable statements. For example, instructions may be implemented as executable or non-executable machine code or as high-level instructions that may be compiled to produce executable or non-executable machine code. Further, instructions may also be implemented as data or may include such. Computer-executable instructions may also be organized in any format, including routines, subroutines, programs, data structures, objects, modules, applications, applets, functions, etc. As will be appreciated by those skilled in the art, details including, but not limited to, the number, Structure, sequence and organization of instructions, be very different, without changing the underlying logic, function, processing and output.

 Although the above discussion relates primarily to microprocessor or multi-core processors executing software, one or more implementations are performed by one or more integrated circuits, such as ASICs (Application Specific Integrated Circuits) or FPGAs (Field Programmable Gate Arrays). In one or more implementations, such integrated circuits execute instructions stored on the circuit itself.

 It will be appreciated by those skilled in the art that the various example blocks, modules, elements, components, methods, and algorithms described herein may be implemented as electronic hardware, computer software, or combinations of both. To illustrate this interchangeability of hardware and software, various exemplary blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends on the particular application and design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each particular application. Various components and blocks may be rearranged (e.g., arranged in a different order or otherwise partitioned) without departing from the scope of the present technology.

It will be understood that each specific order or hierarchy of blocks in the disclosed processes is an exemplification of exemplary approaches. On the basis of design preferences, it is understood that the specific order or hierarchy of blocks in the processes may be rearranged or that all the blocks presented may be executed. Any of the blocks can be executed simultaneously. In one or more implementations, multitasking and parallel processing may be beneficial. Moreover, the separation of various system components in the embodiments described above should not be construed as requiring such a separation in all embodiments, and it should be understood that the described program components and systems are generally integrated together into a single software product or into several Software products can be packed.

 As used in the present specification and claims of the present application, the terms "base station", "receiver", "computer", "server", "processor" and "memory" all refer to electronic or other technological devices , These expressions exclude persons or groups of persons. For purposes of description, the terms "display" or "display" mean displaying on an electronic device.

 As used herein, the phrase "at least one of" preceding a series of items modifies the term "and" or "or" to separate any of the items, the list as a whole, rather than each item of the list (ie, each item). , The phrase "at least one of" does not require selection of at least one of each listed item; instead, the term allows a meaning that includes at least one of any of the items and / or at least one of any combination of items and / or at least one of each of the items. For example, the terms "at least one of A, B and C" or "at least one of" A, B or C "refer to A, B only or C only. any combination of A, B and C; and / or at least one each of A, B and C.

 The predicates "designed to," "operable to," and "programmed to" do not imply any concrete tangible or intangible modification of a subject, but are instead to be used interchangeably. In one or more implementations, a processor configured to monitor and control an operation or a component may also mean that the processor is programmed to monitor and control the operation, or the processor is operable to monitor and control the operation. Similarly, a processor designed to execute code may be construed as a processor programmed to execute code or operable to execute code.

 Expressions such as one aspect, the aspect, another aspect, some aspects, one or more aspects, an implementation, the implementation, another implementation, some implementations, one or more implementations, an embodiment, the embodiment, another embodiment, some embodiments , one or more embodiments, a configuration, the configuration, another configuration, some configurations, one or more configurations, the present technology, the disclosure, the present disclosure or other variants thereof, and the like are of convenience and do not require that a such term or expression is essential to the present technology or that such disclosure applies to all configurations of the present technology. A revelation regarding such term (s) may apply to all configurations or one or more configurations. A disclosure relating to such term (s) may give one or more examples. An expression, such as an aspect or some aspects, may refer to one or more aspects and vice versa, and the like applies to other terms above.

 The word "exemplary" is used herein to mean "serving as an example, case, or illustration." Any embodiment described herein as "exemplary" or as an "example" is not necessarily to be construed as preferred or advantageous over other embodiments. As far as the term "contain", "comprise" or the like is used in the specification or in the claims, such expression shall further be inclusive in a similar manner as the term "comprise", as "to include" is interpreted as a transitional word used in a claim.

 All structural and functional equivalents of the elements of the various aspects described in the course of the present disclosure which are known or later will become apparent to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. In addition, nothing here disclosed should be devoted to the public, regardless of whether this disclosure is explicitly stated in the claims. No claim element is under the provisions of the sixth paragraph of 35 U.S.C. §112 unless the item is expressly cited using the term "means for" or, in the case of a claim, the item is cited using the phrase "move to".

 The above description is provided to enable any person skilled in the art to practice the various aspects described herein. Those skilled in the art will readily appreciate various modifications of these aspects, and the generic principles defined herein may be applied to other aspects. The claims should therefore not be limited to the aspects shown here, but should be given the full scope of protection compatible with the language claims, with mention of an element in the singular should not mean "one and only one", unless it is specifically stated, but " one or more ". Unless otherwise stated, the term "some" refers to one or more. Male pronouns (e.g., being) include the female and neutral sex (e.g., her and his) and vice versa. Any titles and subtitles are for convenience only and do not limit the present disclosure.

Claims (22)

 Apparatus comprising: at least one processor designed for Using sets of blocks of flash memory circuits for data storage operations, wherein each of the sets of blocks comprises at least one block of each of the flash memory circuits and at least some of the blocks of at least some of the sets of blocks are marked active, the at least some of the blocks the at least some of the sets of blocks marked active are used for the data storage operations; Monitoring quality metrics of each block of each of the sets of blocks while using the at least some of the blocks of the at least some of the sets of blocks marked as active for the data storage operations; Determining when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value; Marking the one of the blocks of the one of the sets of blocks as temporarily inactive, wherein the one of the blocks of the one of the sets of blocks is not used for the data storage operations while being marked as temporarily inactive; and if at least one criterion is met, marking one of the blocks of the one of the sets of blocks as active, wherein the one of the blocks of the one of the sets of blocks is reused for the data storage operations while being marked as active.  The apparatus of claim 1, wherein each of the sets of blocks is associated with a code rate and the at least one processor is further configured for Determining that the at least one criterion is met when, for the code rate associated with one of the sets of blocks, a number of the blocks of the one of the sets of blocks marked as active falls below a minimum number of active blocks; in response to determining that the criterion is met, decreasing the code rate associated with one of the sets of blocks; and in response to decreasing the code rate, marking any blocks of the one of the sets of blocks marked as temporarily inactive as active, with any blocks of the one of the sets of blocks marked active being used again for the data storage operations ,  The apparatus of claim 2, wherein the minimum number of active blocks for the code rate is less than another minimum number of active blocks for the reduced code rate.  The device of claim 2, wherein the at least one processor is further adapted for Determining that the at least one criteria is met if an actual storage capacity falls below a minimum storage capacity across all sets of blocks; in response to determining that the criterion is met, identifying at least one of the sets of blocks for which at least one block is marked as temporarily inactive; Decreasing the code rate associated with the identified at least one of the sets of blocks; and in response to decreasing the code rate, marking any blocks of the at least one of the sets of blocks marked as temporarily inactive as being active, with any blocks of the at least one of the sets of blocks marked as being active again for the data storage operations to be used.  The apparatus of claim 4, wherein the at least one processor is further configured to repeat the identify, reduce, and mark until the current storage capacity over the entire set of blocks exceeds the minimum storage capacity.  The apparatus of claim 4, wherein the at least one processor is further configured to determine the current storage capacity based at least in part on a number of blocks of each of the sets of blocks marked as active and the code rate associated with each of the sets of blocks. The apparatus of claim 4, wherein the at least one processor is further configured to identify the at least one of the sets of blocks for which at least one block is marked as temporarily inactive by determining that the at least one of the sets of blocks is relative to other of the sets of blocks comprises a largest number of temporarily inactive blocks.  The apparatus of claim 1, wherein the at least one processor is further configured to move any valid data in the one of the blocks of the one of the sets of blocks before marking the one of the blocks of the one of the sets of blocks as temporarily inactive.  The apparatus of claim 1, wherein the apparatus further comprises at least one random access memory circuit and the flash memory circuits, the blocks comprising physical blocks of the flash memory circuits and the at least one processor is further adapted for Using the sets of the blocks of the flash memory circuits to perform the data storage operations as indicated by a host device; and Maintaining a data structure stored in the at least one random access memory circuit, the data structure comprising a status of each block of each of the sets of blocks, the status of each block of each of the sets of blocks indicating at least whether each block of each of the sets of blocks is marked active or is marked as temporarily inactive.  Apparatus according to claim 1, wherein the quality metric comprises an error count and / or an error rate and / or a time for programming.  The apparatus of claim 1, wherein the at least one processor is configured to arrange the blocks of the flash memory circuits into the sets of blocks.  Method, comprising: Using sets of blocks of a plurality of flash memory circuits for data storage operations, each of the sets of blocks comprising at least one block of each of the plurality of flash memory circuits and at least some of the blocks of at least some of the sets of blocks being marked as active, wherein the at least some of the blocks of the at least some of the sets of blocks marked active are used for the data storage operations; Monitoring a remaining cycle count of each of the blocks of each of the sets of blocks, while using the at least some of the blocks of the at least some of the sets of blocks marked as active for the data storage operations, the remaining cycle count of each of the blocks of each of the sets of Blocks based at least in part on an expected cycle count associated with each of the plurality of flash memory circuits containing each of the blocks of each of the sets of blocks; Marking the one of the blocks of the one of the sets of blocks as temporarily inactive when the remaining cycle count of one of the blocks of one of the sets of blocks meets at least a first criterion, wherein the one of the blocks of the one of the sets is not used for the data storage operations while it is marked as temporarily inactive; and Marking the one of the blocks of the one of the sets of blocks as active when at least a second criterion is satisfied, wherein the one of the blocks of the one of the sets of blocks is reused for the data storage operations while being marked as active.  The method of claim 12, wherein the remaining cycle count of the one of the blocks of the one of the blocks satisfies the at least one first criterion if the remaining cycle count of the one of the blocks of the one of the sets of blocks is one threshold number of cycles from another remaining cycle count another of the blocks that is different from one of the sets of blocks.  The method of claim 13, further comprising: Determining that the at least one second criterion is met when the remaining cycle count associated with one of the blocks of the one of the sets of blocks equals the other remaining cycle count associated with the other of the blocks of the one of the sets of blocks.  The method of claim 12, further comprising: rapidly cycling a respective block of each of the plurality of flash memory circuits prior to using any of the blocks of any of the sets of blocks for the data storage operations until a respective quality metric of the respective block of each of the plurality of flash memory circuits falls below a minimum quality value; Determining the expected cycle count for each of the plurality of flash memory circuits based at least in part on a number of fast cycles used to cause the respective quality metric of the respective block of each of the plurality of flash memory circuits to fall below the minimum quality value; and Storing the expected cycle count for each of the plurality of flash memory circuits in individual association with each of the blocks of each of the plurality of flash memory circuits. The method of claim 15, further comprising: Marking the respective block of each of the plurality of flash memory circuits as inactive after fast cycling the respective block of each of the plurality of flash memory circuits.  The method of claim 15, further comprising: Determining the remaining cycle count for each of the blocks of each of the sets of blocks based at least in part on the expected cycle count associated with each of the blocks of each of the sets of blocks and a number of cycles used for the data storage operations for each of the blocks of each of the sets of blocks becomes.  The method of claim 12, further comprising: Determining that the at least one second criterion is met when a number of the blocks of the one of the sets of blocks marked as active falls below a minimum number of active blocks.  The method of claim 12, further comprising: Determining that the at least one second criterion is met when a current storage capacity falls below a minimum storage capacity across all sets of blocks.  A computer program product comprising code stored in a non-transitory computer-readable storage medium, the code comprising: Code for rapidly cycling a respective physical block of each of a plurality of flash memory circuits until a respective quality metric of the respective physical block of each of the plurality of flash memory circuits falls below a minimum quality value; Code for determining the expected cycle count for each of the plurality of flash memory circuits based, at least in part, on a number of fast cycles used to cause the respective quality metric of the respective physical block of each of the plurality of flash memory circuits to fall below the minimum quality value becomes; Code for storing the expected cycle count for each of the plurality of flash memory circuits in individual association with physical blocks of each of the plurality of flash memory circuits in at least one random access memory circuit.  The computer program product of claim 20, wherein the code further comprises: Code for arranging the physical blocks of each of the plurality of flash memory circuits in amounts of physical blocks, each of the sets of physical blocks comprising at least one of the physical blocks of each of the plurality of flash memory circuits, and at least some of the physical blocks of at least some of the sets physical blocks are marked as active; Code for monitoring the cycle count of each of the physical blocks of each of the sets of physical blocks, while the at least some of the physical blocks of the at least some of the sets of physical blocks marked active are used for data storage operations; and Code for temporarily disabling at least one of the physical blocks of each of the sets of blocks so that the cycle count of each of the physical blocks of each of the sets of physical blocks substantially matches the expected cycle count associated with each of the physical blocks of each of the sets of physical blocks reached the same time. A system comprising: a plurality of flash memory circuits each comprising blocks; a random access memory (RAM) configured to store a data structure comprising a status of each of the blocks of each of the plurality of flash memory circuits, wherein the status of each of the blocks of each of the plurality of flash memory circuits at least indicates whether each of the blocks is each of the plurality is marked active by flash memory circuits or marked as temporarily inactive; an interface communicatively coupled to a host device; and a controller configured to use sets of the blocks of the plurality of flash memory circuits for data storage operations specified by the host device, each of the sets of blocks comprising at least one block of each of the plurality of flash memory circuits and at least some the blocks of at least some of the sets of blocks in the data structure are marked active, the at least some of the blocks of the at least some of the sets of blocks marked active in the data structure being used for the data storage operations; Monitoring a quality metric of each of the blocks of each of the sets of the blocks while using the at least some of the blocks of the at least some of the sets of blocks marked active in the data structure for the data storage operations; Determining when the quality metric of one of the blocks of one of the sets of blocks falls below a minimum quality value; Marking one of the blocks of one of the sets of blocks in the data structure as temporarily inactive, wherein the one of the blocks of one of the sets of blocks is not for the Data storage operations while being marked as temporarily inactive in the data structure; and marking one of the blocks of the one of the sets of blocks as active in the data structure when at least one criterion is satisfied, wherein the one of the blocks of the one of the sets of blocks is reused for the data storage operations while being active in the data structure is marked.

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