DE102017104229A1 - Battery system with active balancing circuit - Google Patents

Abstract

The invention relates to a battery system (1) comprising a rechargeable battery (2), which has two poles (3, 4) and a plurality of battery cells (Z ₁ , Z ₂ , ...) connected in series between the poles (3, 4). , Z _n ), and an active-balancing circuit (6) for monitoring and active control of the charge states of the battery cells (Z ₁ , Z ₂ , ..., Z _n ). In this case, in the active balancing circuit (6) for each accumulator cell (Z ₁ , Z ₂ ,..., Z _n ), an intermediate circuit (S ₁ , S ₂ ,...) Acting as bidirectional DC-DC converter S _n ), wherein each intermediate circuit (S ₁ , S ₂ , ..., S _n ), the two poles of the respective accumulator cell (Z ₁ , Z ₂ , ..., Z _n ) with the interposition of an inductance (L) and a first transistor (Q1) connects. In each intermediate circuit (S ₁ , S ₂ ,..., S _n ), a branch is provided between the inductance (L) and the first transistor (Q1) which, with the interposition of a second transistor (Q2), is connected to one of the intermediate circuits (S ₁ , S ₂ , ..., S _n ) is connected to DC-link (7) which connects in a conductive manner, the DC link (7) being coupled to a reference potential (GND) via a capacitor (C). The active balancing circuit (6) is further suitable and configured in a regular operating mode to keep the DC link (7) at a predeterminable potential which is either greater than the potential at the positive pole (3) of the battery (3). 2) or smaller than the potential at the negative pole (4) of the battery (2).

Description

The present invention relates to a battery system comprising a rechargeable battery having two poles and a plurality of battery cells connected in series between the poles, and an active balancing circuit for monitoring and actively controlling the respective state of charge of the battery cells.

Such a battery system is basically known from the prior art.

In the case of rechargeable batteries having a plurality of battery cells connected in series, the problem already known from the prior art arises that the individual battery cells of the battery can have different states of charge at any given time, ie the capacity that is original or changes with the state of aging (= maximum charge amount) of different battery cells may be different, that the battery cells have different self-discharges or may be exposed to different environmental conditions that when charging the battery, the end-of-charge voltage of a battery cell with the result of damage can be exceeded and / or that the individual battery cells on different ways of aging differently.

Therefore, various types of battery systems are already known from the prior art, in which - taking into account the respective charge and health conditions of the battery cells - taking place during operation of the battery system charging and discharging the various battery cells for the purpose of increasing the battery life and the possible long retention of sufficient battery capacity have been improved.

In so-called passive balancing, the (in terms of their state of charge), the most highly charged battery cells of a battery are charged with a resistor connected in parallel at the end of the charging cycle, limiting the voltage at the respective cells to their charge end voltage can be. The cells with the highest state of charge are then only slightly charged further (or possibly even discharged), while the other cells of the battery, which have not yet reached their charge end voltage, continue to be supplied with the full charging current. Discharging of the battery is typically stopped during passive balancing when the battery's (in terms of its state of charge) worst battery cell has reached its discharge end voltage. Despite these measures, it remains to be noted that even in passive balancing the worst cells of the battery are exposed to the greatest "stress", which worsens their state of health in terms of self-accelerating aging. In addition, the usable capacity of the battery is determined by the capacity of the worst cell.

Better lifetime extension results of rechargeable batteries having a plurality of battery cells connected in series are achieved with the so-called active balancing, which is also used in the context of the present invention.

In this case, by means of a suitable active balancing circuit during a charging energy or electrical charge from bad to good cells and transferred during a discharge energy from good to bad cells, so that both charging and discharging the battery any inequalities in the state of charge the accumulator cells (based on their respective current capacity) can always be compensated, as a result, all cells are exposed to the same "stress".

The advantage of active balancing consists in a (compared to the passive balancing) significantly higher efficiency, since typically energy is converted only to a small degree in (loss) heat and, for example, not "burned" in the passive balancing required resistors , Furthermore, it is advantageous in active balancing that there is achieved a total capacity of the accumulator which is increased in comparison to passive balancing, since each accumulator cell is in each case completely charged and discharged. On the other hand, it proves to be disadvantageous in the active balancing higher circuit complexity and the associated higher costs, so that active balancing has been primarily used in high performance areas, such as traction batteries in the field of electromobility or battery storage power plants. However, active balancing proves to be fundamentally suitable in all types of rechargeable batteries typically used in the prior art, which are constructed from a plurality of rechargeable battery cells.

For active balancing already exists a variety of electronic circuits with different switching topologies, which are often designed comparatively complex and expensive to manufacture.

In part, the known from the prior art active balancing circuits allow only a charge or energy transfer between adjacent battery cells of the battery, which in particular for batteries with a large number of accumulator cells as not suitable or otherwise not optimal proves. Furthermore, various embodiments of active balancing circuits are known in which inductive charge exchange between the cells on expensive transformers must be used, which is to be avoided with the present invention.

A - designed as a bidirectional voltage transformer - circuit for active balancing is, for example, in 12 of the article "A Review of Passive and Active Battery Balancing based on MATLAB / Simulink" ( Daowd et al., International Review of Electrical Engineering (IREE) -Nov / Dec2011, Vol. 6, Issue 7, p. 2974-2989 ). In this active balancing circuit, an intermediate circuit functioning as bidirectional DC-DC converter is provided for each accumulator cell or each module of the rechargeable battery, each intermediate circuit having one inductor, two transistors and one capacitor and all the capacitors of the different intermediate circuits are connected in series there between the not connected directly to the two poles of the battery battery connection. In this active balancing circuit, a simultaneous charge transfer between different battery cells / modules of the battery can be done, which proves to be advantageous. A disadvantage, however, is that there always the whole for charging or discharging the battery added or discharged energy must be passed through the converter, since the local battery on the left in the figure shown (and not directly connected to both poles of the battery) battery connection is charged or discharged, which increases losses and ultimately proves to be less efficient. In addition, this circuit is relatively expensive, since each inductor and each transistor or switch must be designed to be comparatively large.

Against the background of the above-described prior art, it is thus the object of the present invention to provide a simple and inexpensive to manufacture battery system of the type mentioned with the most efficient active balancing circuit based on a novel switching topology and an advantageous method of operation to provide such a battery system.

This object is achieved with a battery system according to claim 1 and a method for operating a battery system according to the invention according to claim 8. Further preferred embodiments of the present invention will become apparent from the dependent claims and from the present description.

The battery system according to the invention comprises a rechargeable battery which has two poles and a plurality of battery cells connected in series between the poles, and an active balancing circuit for monitoring and actively regulating the charge states of the battery cells. In this case, an intermediate circuit functioning as a bidirectional DC-DC converter is provided in the active balancing circuit for each accumulator cell, each intermediate circuit connecting the two poles of the respective accumulator cell with the interposition of an inductance and a first transistor. In each intermediate circuit, a branch is provided between the inductance and the first transistor, which is connected with the interposition of a second transistor to a DC link which conductively connects all intermediate circuits, the DC link being coupled to a reference potential via a capacitor. In this case, the active balancing circuit of the battery system according to the invention is suitable and configured in a regular operating mode to hold the DC link at a predeterminable potential which is either greater than the potential at the positive pole of the battery or less than the potential at the negative Pole of the battery is.

In a battery system according to the invention, the concrete operation will be explained in detail below with reference to an embodiment of the invention, during the operation of the battery system taking place charging and discharging by suitable control of the provided in the respective intermediate circuits transistors electrical charge from a first battery cell in the DC-Link and be transferred via this into a second (any other) accumulator cell. The inductances arranged in the intermediate circuits also serve as intermediate storage for the energy to be exchanged between different accumulator cells. Furthermore, in the context of the active balancing desired balancing of the charge states of all battery cells in the present invention can be such that during operation of the battery system - virtually simultaneously - charge (via the DC link) can be exchanged between any plurality of battery cells. Due to the possibility of simultaneous charge exchange between arbitrarily selectable accumulator cells, the duty cycle of the active balancing circuit and the average current through the switches and inductors can be kept relatively small, which ultimately comparatively small-sized and inexpensive components can be used.

In the context of the present invention, the reference potential with which the DC link is coupled via the capacitor can be more expedient Be defined by the (electrical) potential at the positive or negative terminal of the battery, wherein it may be in the appropriate (but not mandatory) embodiment of the invention, the reference potential in a grounding (= zero potential). So if, for example, the reference potential in the sense of grounding corresponds to the zero potential and at the same time the negative pole of the battery is at the reference potential, then the voltage dropping across the capacitor corresponds exactly to the potential of the DC link, which then has to be kept in magnitude to a value is greater than the battery voltage applied between the poles of the battery.

Whether a value above the potential at the positive pole of the battery or a value below the potential at the negative pole of the battery is selected for the potential of the DC link is ultimately dependent on the order of the in the respective intermediate circuits in the connection of the opposite poles of Accumulator cells intermediate inductance and the first transistor.

The battery system according to the invention is relatively inexpensive to produce, since the active-balancing circuit as electrical components - in addition to the other control electronics and a capacitor - requires only two transistors and an inductance per accumulator cell or intermediate circuit. It proves to be extremely efficient due to the omission of resistors (and not merely current sensing) and / or other electrical components in the intermediate circuits as well as largely lossless charge exchange via the DC link configured as a conductive connection. This results in a total of very low power loss.

For the operation of the battery system according to the invention should first be noted that the (electrical) potential of the DC link can be varied by appropriate circuit of the various DC link transistors by the transistors are switched so that the sum of all the intermediate circuits via the respective second transistors in the DC link flowing and flowing from the DC link into the DC link currents is greater or lesser zero.

When the battery system according to the invention is put into operation, it is therefore advantageous for the capacitor coupling the DC link to the reference potential to be charged once to a predefinable nominal voltage which defines the voltage level of the DC link against the reference potential and thus the (absolute) potential of the DC link. In the further regular operation of the battery system according to the invention, active balancing can be used to ensure that the sum of the (signed) currents flowing from the intermediate circuits into the DC link and from the DC link into the other intermediate circuits always equals zero , so that the potential of the DC link in the regular operation of the battery system according to the invention preferably remains at least substantially constant.

Of course, in the context of the present invention, state of charge and health characteristics of the various battery cells are determined in active balancing in a manner known per se from the prior art in order to determine the need for equalization between the individual battery cells of the battery and then - by suitable control of the transistors to provide for a suitable charge transfer between the different battery cells.

As a health indicator, the so-called SOH ("State of Health") is typically determined in the context of active balancing, which indicates (in a percentage manner) which capacity the respective accumulator cell has in comparison to the typical delivery state of such a storage cell. In addition, the so-called SOC ("state of charge") is typically determined as the state of charge, which indicates (also in a percentage), which charge the respective battery cell currently contains compared to the total possible charge. For example, 80% SOH for a 1000 mAh cell would mean that the cell only has a capacity of 800 mAh. An SOC of 50% then means for this cell that it currently holds just 400 mAh. The SOC may e.g. be determined from the cell voltage and a known discharge or charging curve, this determination is relatively inaccurate, especially in medium SOC states (20% to 80%) due to the very flat curve.

Each cell type has a defined end-of-charge voltage at which the cell is fully charged. This is, for example, 4.2 V for typical lithium-ion cells. Likewise, a discharge end voltage is specified by the manufacturer for each cell type. This is typically 2.5V to 2.9V for lithium-ion cells.

The control unit of the active balancing circuit typically requires the following measurements to determine SOH and SOC: Current (individual) cell voltage of each battery cell, total charge / discharge current into or out of the battery, differential current of each cell (into the DC Link into or out of this) due to balancing as well as the elapsed time.

From the total current, the individual differential currents and the time can then be calculated in a conventional manner, the charge that has been transmitted in a given charging / discharging from / to each battery cell. The control or computing unit can then derive the SOH and the SOC for each accumulator cell from the transferred charge and the measured cell voltage. These health and state of charge parameters (to be updated further in the operation of the active balancing circuit) can then be used in subsequent charging or discharging cycles, wherein initially it may be necessary to first suspend the battery for a complete charge and discharge cycle to be able to determine the charging and health states of the individual battery cells required for the operation of the active balancing circuit. Of course, in the context of the present invention, it is possible to resort to all known and suitable active balancing methods from the state of the art, provided that they are compatible with the other features of the invention.

It should also be pointed out that in the context of the present invention an "accumulator cell" does not necessarily have to be a single galvanic (secondary) cell, but that in a broader sense it is also a plurality (in particular parallel) switched) individual galvanic (secondary) cells having battery cell can act. By such (optional) parallel connection of individual cells within an accumulator cell, an increased overall capacity can obviously be provided.

To understand the operation of the battery system according to the invention should also be noted that the anodes of the battery cells downstream are at different voltage levels, whereby each intermediate circuit for DC link has a different potential difference, which in the context of the operation of the present invention provided active balancing circuit must be taken into account.

A first particularly preferred embodiment or development of the present invention provides that the battery system has a central control unit and, for each intermediate circuit, at least one local gate drive directly or indirectly connected to the central control unit for controlling the transistors provided in the respective intermediate circuit the central control unit is set up to specify different operating modes for each local gate drive in a timely manner, and each local gate drive is set up to control the at least one transistor to be driven by evaluating the voltage applied to the relevant transistor, that through the respective transistor flowing current and the current of the central control unit predetermined operating mode 'to switch.

This embodiment variant of the invention is particularly advantageous since the circuit of the transistors, which is preferably to be realized in a particularly high frequency within the scope of the invention, can be performed by the at least one local gate drive with evaluation of the local currents and voltages. The local gate drives can be clocked at high frequency (eg with a first high frequency of greater than or equal to 0.5 MHz, greater than or equal to 0.9 MHz and particularly preferred in a frequency range between 0.9 and 1.1 MHz), while the by the central control unit time-wise setting of the currently applicable operating mode with a contrast (significantly) lower second frequency (eg in the range between 10 Hz and 100 kHz, advantageously with a frequency in the range of about 100 Hz to 1 kHz) can be varied ,

In that regard, in a preferred embodiment of the invention, it is provided that the central control unit is set up to preset or update the operating modes to be preset for each gate drive at a first low frequency (eg in the range between 100 Hz and 100 kHz), and in that the local gate drives and the transistors are set up for a high-frequency drive and circuit with a higher (eg with a factor of at least 10 or 100 higher) frequency (in particular greater than 0.5 MHz).

Since the operating mode specification has to be carried out by the central control unit by evaluating the respective charge and health state characteristics of all battery cells, it proves to be advantageous that this operating mode specification only has to be transmitted to the respective local gate drives with low frequency. Furthermore, such - comparatively slow - signals can also be transmitted more easily over the different voltage levels, e.g. without having to rely on expensive optocouplers or level shifters.

A more detailed description of the interaction of the central control unit and the local gate drives can be found below in the description of a preferred embodiment of the present invention.

In the embodiment of the invention described above, either for each switching transistor may be provided a separate local gate drive (ie a total of two local gate drives per intermediate circuit) or it may be provided per intermediate circuit only one gate drive, with which then both transistors of the respective intermediate circuit are driven. By suitable choice or specification of the switching times of the two transistors of an intermediate circuit, the current flowing in from the DC link into the accumulator cell (or from the accumulator cell into the DC link) flowing into the respective intermediate circuit can then be set as desired.

Furthermore, it may be advantageously provided that the predetermined by the central control unit for each local gate drive mode is specified by transmitting at least one operating parameter that specifies whether the respective intermediate circuit associated accumulator currently loaded via the DC link, discharged or neither still to be unloaded. In this way, it is merely predetermined whether current should flow from the respective accumulator cell into the DC link or from the DC link into the accumulator cell (or neither).

This alone can then be used for the individual transistors to specify a particularly simple to implement switching scheme, with which the respective local gate drive can switch the associated transistor high frequency under evaluation of this purpose to be determined in a suitable manner local voltages and currents. The current through the respective transistor can be determined, for example, via the voltage drop across a measuring resistor (in particular a shunt resistor assigned to the local gate drive), which can be connected upstream or downstream of the respective transistor.

In addition, it may be provided that the central control unit not only prescribes the respective current direction (ie, for a predetermined period of time) for each accumulator cell, but also specifies the amount of the currently required current as a further operating parameter. to which - as this becomes even more apparent from the following description of an embodiment of the invention - the switching times of the respective transistors must be suitably adapted. For this purpose, e.g. a digital or analogue reference value is transmitted to the local gate drive, which in turn is sufficient, although this reference value with the comparatively low frequency of e.g. 1 kHz is transmitted or updated.

In the context of the present invention, it can be advantageously provided that each local gate drive is realized by a separate integrated circuit (IC). In principle, however, it is also possible that all local gate drives are realized by a single IC.

Furthermore, it proves to be advantageous, particularly for cost reasons, that according to a further preferred embodiment of the present invention it may be provided that the inductors built into the intermediate circuits are designed as air coils or conductor track coils. In fact, it follows that an active balancing circuit according to the invention - in particular with high frequency driving of the transistors with frequencies of the order of about 1 MHz - with coils with very low inductances of e.g. only 500 nH is operable.

1. A) Vorgabe eines Potentials, welches entweder größer als das Potential am positiven Pol der Batterie oder kleiner als das Potential am negativen Pol der Batterie ist
2. B) Aufladen des den DC-Link mit dem Referenzpotential koppelnden Kondensators auf eine Soll-Spannung, bei der das Potential des DC-Links dem in Schritt (A) vorgegebenen Potential entspricht
3. C) Betrieb der Active-Balancing-Schaltung in einem regulären Betriebsmodus derart, dass das Potential des DC-Links im Wesentlichen unverändert bleibt.

Finally, the present invention also relates to a method for operating a battery system according to the invention comprising the following steps:

1. A) specification of a potential which is either greater than the potential at the positive pole of the battery or less than the potential at the negative pole of the battery
2. B) Charging the capacitor coupling the DC link to the reference potential to a desired voltage at which the potential of the DC link corresponds to the predetermined potential in step (A)
3. C) Operating the active balancing circuit in a regular operating mode such that the potential of the DC link remains substantially unchanged.

• 1 einen Schaltplan eines Ausführungsbeispiels eines erfindungsgemäßen Batteriesystems,
• 2 einen Schaltplan zu dem Ausführungsbeispiel nach 1 mit insgesamt fünf Akkumulatorzellen, in welchem zusätzlich auch die zentrale Steuereinheit und die lokalen Gate-Ansteuerungen für die verschiedenen Transistoren in den verschiedenen Zwischenschaltkreisen dargestellt sind,
• 3 den Schaltplan aus 1, ergänzt um verschiedene Definitionen zu den in der Active-Balancing-Schaltung vorherrschenden Spannungen und Strömen,
• 4a eine schematische Darstellung des durch die Induktivität eines Zwischenschaltkreises fließenden Stroms im zeitlichen Verlauf in einem ersten Betriebsmodus,
• 4b eine schematische Darstellung des durch die Induktivität eines Zwischenschaltkreises fließenden Stroms im zeitlichen Verlauf in einem zweiten Betriebsmodus,
• 5a/b Ergebnisse einer numerischen Simulation zu verschiedenen sich im Betrieb einer erfindungsgemäßen Batteriesystems bei Ladungsentnahme aus einer Akkumulatorzelle einstellenden Strom- und Spannungsverläufen, und
• 6a/b Ergebnisse einer numerischen Simulation zu verschiedenen sich im Betrieb einer erfindungsgemäßen Batteriesystems bei Ladungszufuhr zu einer Akkumulatorzelle einstellenden Strom- und Spannungsverläufen.

For the advantages and particularly expedient developments of the method according to the invention may be made to the already described description of the battery system according to the invention and the following description of an embodiment of the present invention with reference to the drawings. It shows

• 1 a circuit diagram of an embodiment of a battery system according to the invention,
• 2 a circuit diagram for the embodiment according to 1 with a total of five battery cells, in which additionally also the central control unit and the local gate drives for the different transistors in the different intermediate circuits are shown,
• 3 the circuit diagram 1 , supplemented by various definitions of the active Balancing circuit prevailing voltages and currents,
• 4a a schematic representation of the current flowing through the inductance of an intermediate circuit current over time in a first operating mode,
• 4b a schematic representation of the current flowing through the inductance of an intermediate circuit current over time in a second operating mode,
• 5a / b results of a numerical simulation of different current and voltage characteristics occurring during operation of a battery system according to the invention when discharging a charge from an accumulator cell, and
• 6a / b Results of a numerical simulation of various current and voltage curves occurring during operation of a battery system according to the invention when charge is supplied to an accumulator cell.

1 shows the circuit diagram of an embodiment of a battery system according to the invention 1 , This includes the battery system 1 a rechargeable battery 2 , which in the present case is formed by a plurality of battery cells Z ₁ , Z ₂ ,..., Z _n connected in series. Between the plus pole (= anode) 3 and the negative pole (= cathode) 4 of the battery defining a reference potential (GND) 1 is a direct with both poles 3 . 4 the battery 2 connected battery connection 5 intended. At the battery connection 5 which allows both to connect a consumer to the battery 2 (in the sense of a charge removal from the battery 2 ) as well as to recharge the battery 2 serves, the battery voltage U _{B is applied} .

Furthermore, a - in 1 still without control unit shown - active balancing circuit 6 provided, which during a charging or discharging process for monitoring and active control of the charge states of the battery cells Z ₁ , Z ₂ , ..., Z _n is used. The active balancing circuit 6 has for each accumulator cell Z ₁ , Z ₂ , ..., Z _n an intermediate circuit S ₁ , S ₂ , ..., S _n , which the anode of the respective battery cell Z ₁ , Z ₂ , ..., Z _n with the interposition of an inductance L and a first transistor Q1 to the cathode of the respective battery cell Z ₁ , Z ₂ , ..., Z _n connects. In this case, in each intermediate circuit S ₁ , S ₂ ,..., S _n, a branch is provided between the inductance L and the first transistor Q1, which, with the interposition of a second transistor Q2, is connected to an intermediate circuit S ₁ , S ₂ ,. , S _n conductively interconnecting DC link 7 connected. The DC link 7 is coupled via a capacitor C with a reference potential, wherein the reference potential in the given embodiment by the (grounded in the present example) potential of the negative pole (cathode) 4 the battery 2 is predetermined. It is also possible, instead of the negative pole 4 the positive pole (anode) 3 the battery 2 To couple with the reference potential, the latter embodiment even has the advantage that then held by the capacitor voltage (= difference between the potential of the DC link and the potential at the positive pole 3 the battery) is significantly lower than in the illustrated embodiment, whereby the capacitor C can be made smaller, which is advantageous for reasons of cost.

During operation of the battery system 1 For example, the capacitor C is initially charged to a desired voltage U _Z , which is to be preset suitably, and which is the voltage level of the DC link 7 defined relative to the reference potential. The target voltage U _Z is chosen so that the potential of the DC link 7 greater than that of the anode 3 the battery 2 , In further regular operation of the active balancing circuit 6 can then charge or discharge the battery 2 by appropriate switching of the various intermediate circuits S _1, S _2, ..., S _n provided for transistors Q1, Q2 charge between different battery cells Z _1, Z _2, ..., Z _n via the DC link 7 exchanged, while at the same time ensuring that the potential of the DC link 7 (at least largely) remains constant.

In an alternative embodiment of the battery system according to the invention, in which then the local inductance L would have to exchange space with the first transistor Q1 in each intermediate circuit S ₁ , S ₂ , ..., S _n , the DC link could 7 also be kept at a potential smaller than that at the negative pole 4 the battery 2 prevailing potential. Even so, the battery system according to the invention could be operated in otherwise completely analogous manner.

The transistors Q1, Q2 in the various intermediate circuits (each functioning as a bidirectional DC-DC converter) S ₁ , S ₂ ,..., S _n in the given exemplary embodiment are commercially available (field effect) transistors with integrated or external Free-wheeling diode or transistors with freewheeling diode function, as the circuit diagram used illustrates. In the present case, it is possible to use high-frequency transistors, in particular GaN transistors, with which, in particular, high switching frequencies greater than 0.5 MHz, for example in the range of 0.9-1.1 MHz or higher, can be realized.

Charge transfer from a first accumulator cell Z _i to a second accumulator cell Z _j can take place by charging in the time average means by suitable switching of the transistors Q1, Q2 in the relevant intermediate circuits S _i , S _j the first (the first accumulator cell Z _i associated) intermediate circuit S _i in the DC link 7 and from the DC link 7 in the second (the second accumulator cell Z _j associated) intermediate circuit S _{j is} shifted. In the present case, all intermediate circuits S ₁ , S ₂ ,..., S _{n are} connected to the common DC link via the respectively second transistor Q _{2 of} the relevant intermediate circuit 7 can be connected, in the battery system according to the invention 1 Also, a simultaneous charge transfer between any plurality of battery cells can be realized. For this purpose, the existing in the various intermediate circuits S ₁ , S ₂ , ..., S _n transistors Q1, Q2 are switched so that - in the time average - each current from a first (arbitrarily predetermined) group of intermediate circuits in the DC link into and out of this flows to a second (predeterminable) group of intermediate circuits.

The selection of those accumulator cells that during a charge or discharge of the battery (via the DC link) to transfer additional charge to other battery cells or receive charge from other battery cells, takes place in the context of active balancing by a (in 1 not shown) control unit in a manner known per se from the prior art under evaluation of the current charge and health conditions (SOC and SOH) of all battery cells Z ₁ , Z ₂ , ..., Z _n , as already above was explained.

2 shows again an embodiment of a (electrotechnically identical as the circuit diagram 1 built) circuit diagram for a battery system according to the invention 1 with there a total of five battery cells Z ₁ , Z ₂ , Z ₃ , Z ₄ , Z ₅ and the associated intermediate circuits S ₁ , S ₂ , ..., S ₅ , in which in addition to the in 1 components already shown now also one for controlling the active balancing circuit 6 serving central control unit 8th and a plurality of local gate drives G1 and G2 for driving the provided in the individual intermediate circuits S ₁ , S ₂ , ..., S ₅ transistors Q1, Q2 are shown or provided.

The central control unit 8th is connected via two (shown with dashed lines) control lines to each local gate drive G1, G2 at the local terminals "RUN" and "ACT", each local gate drive G1, G2 exactly one of its associated transistor Q1, Q2 is controlled and wherein each local gate drive is assigned to the determination of the current through the respective transistor Q1, Q2 serving measuring or shunt resistor R _S. Each local gate drive G1, G2 has - in addition to the terminals "RUN" and "ACT" connected to the central control unit - still further connections "S", "D" and "G" which are connected to the source, drain and gate of the to be driven transistor Q1 and Q2 are connected. In addition, at each local gate drive G1, G2, a further connection designated "REF" is provided, which is connected to a location of the intermediate circuit (in the present case on the source or source side) beyond the measuring resistor R _S , so that for determining the through the current flowing through the respective transistor Q1 or Q2, the voltage difference between the terminals "S" and "REF" can be measured, which corresponds to the voltage drop across the measuring resistor. From this it is then possible to calculate the current flowing through the transistor by simple application of Ohm's law. Between the terminals "D" and "S", the voltage applied to the transistor Q1 or Q2 can be measured.

As part of the operation of the battery system according to the invention 1 is now through the central control unit 8th with a first low frequency (preferably a frequency in the range of 10 Hz - 100 kHz, preferably about 100 Hz or 1 kHz) for each local gate drive G1, G2 given by this moment to be observed operating mode. The high-frequency driving of the transistors Q1, Q2 in contrast can then be controlled by the respective local gate drive G1, G2, taking into account that of the central control unit 8th low-frequency updated operating mode specification based on the locally determined by the respective gate drive voltages and currents. By generating the high-frequency switching signals by means of the local gate drives G1, G2 it is avoided that the switching signals required for this purpose (with a high frequency of preferably greater than 0.5 MHz) are generated by a central control unit and then transmitted to the different voltage levels have to.

• a) RUN=Low, ACT=(Low oder High): Die Gate-Ansteuerung G1 bzw. G2 bleibt (unabhängig von dem am Eingang ACT anliegenden Signal) insgesamt inaktiv, so dass keine aktive Schaltung des der Gate-Ansteuerung G1 bzw. G2 zugeordneten Transistors Q1 bzw. Q2 erfolgt. Wenn dies für beide lokalen Gate-Ansteuerungen G1, G2 beider Transistoren Q1, Q2 eines Zwischenschaltkreises S₁, S₂, ..., S_n vorgegeben ist, dann wird die zugeordnete Akkumulatorzelle Z₁, Z₂, ..., Z_n nicht mit Ladung aus dem DC-Link 7 bespeist und kann auch keine Ladung an den DC-Link 7 abgeben.
• b1) RUN=High, ACT=Low: Die Gate-Ansteuerung ist aktiv. Abschaltung des Transistors erfolgt bei Erreichen eines (in der lokalen Gate-Ansteuerung oder ggfs. durch die zentrale Steuereinheit) vorgegebenen Schwellwerts von z.B. 1 A für den vorzeichenbehafteten Strom durch den Transistor.
• b2) RUN=High, ACT=High: Die Gate-Ansteuerung ist aktiv. Abschaltung des anzusteuernden Transistors erfolgt bei Erreichen eines (in der lokalen Gate-Ansteuerung oder ggfs. durch die zentrale Steuereinheit) vorgegebenen Schwellwerts von z.B. 4 A für den vorzeichenbehafteten Strom durch den Transistor.
• Ein Einschalten des Transistors erfolgt bei aktiver Gate-Ansteuerung (also in den vorgenannten Fällen b1 und b2) immer dann, wenn der Zustand am Eingang „RUN“ von Low nach High wechselt und gleichzeitig ACT High ist oder wenn die (Arbeits-) Spannung zwischen Source und Drain an dem der Gate-Ansteuerung zugeordneten Transistor Null wird. Durch die letztgenannte Regel wird Einschaltvorgänge ein sogenanntes Zero-Voltage-Switching realisiert, womit die in der Active- Balancing-Schaltung gegebenen Verluste deutlich reduziert werden.
• Ferner sei erwähnt, dass bei aktiver Gate-Ansteuerung das „ACT“-Signal für die beiden zu demselben Zwischenschaltkreis gehörigen Gate-Ansteuerungen G1 und G2 (für die beiden in dem jeweiligen Zwischenschaltkreis vorgesehenen) Transistoren Q1, Q2 gegensätzlich angesteuert werden muss. Wenn somit für die erste lokalen Gate-Ansteuerung G1 zu einem bestimmten Zeitpunkt RUN=High und ACT=Low vorgegeben ist, dann muss zur gleichen Zeit für die zweite lokale Gate-Ansteuerung RUN=High und ACT=High gelten (oder umgekehrt) .

In this case, the local gate drives G1, G2 can then be operated with a comparatively simple circuit diagram, with only two binary control signals (with values "Low" or "High") being given as the operating parameter to the connections for specifying the operating mode by the central control unit. RUN "and" ACT "of the respective gate drive G1, G2 must be transmitted. In this way, the three modes of operation to be differentiated for each intermediate circuit (accumulator cell should be loaded from the DC link, accumulator cell should emit charge to the DC link, neither of which is shown). For example, this can be realized with the following operating mode specification:

• a) RUN = Low, ACT = (Low or High): The gate drive G1 or G2 remains (regardless of the signal applied to the input ACT) in total inactive, so that no active circuit of the gate drive G1 or G2 assigned transistor Q1 or Q2 takes place. If this is predetermined for both local gate drives G1, G2 of both transistors Q1, Q2 of an intermediate circuit S ₁ , S ₂ ,..., S _n , then the associated accumulator cell Z ₁ , Z ₂ ,..., Z _n not with charge from the DC link 7 fed and can not charge to the DC link 7 submit.
• b1) RUN = High, ACT = Low: The gate control is active. Shutdown of the transistor takes place upon reaching a (in the local gate drive or possibly. By the central control unit) predetermined threshold value of eg 1 A for the signed current through the transistor.
• b2) RUN = High, ACT = High: The gate control is active. Shutdown of the transistor to be controlled takes place upon reaching a (in the local gate drive or possibly. By the central control unit) predetermined threshold value of eg 4 A for the signed current through the transistor.
• When the gate is activated (ie in the aforementioned cases b1 and b2), the transistor is switched on whenever the state at the "RUN" input changes from low to high and at the same time ACT is high or when the (working) voltage between Source and drain at the gate drive associated transistor is zero. The latter rule realizes switch-on processes so-called zero-voltage switching, whereby the losses given in the active balancing circuit are significantly reduced.
• It should also be noted that with active gate drive, the "ACT" signal for the two gate drives G1 and G2 belonging to the same intermediate circuit (for the two transistors Q1, Q2 provided in the respective intermediate circuit) must be driven in opposite directions. Thus, if RUN = High and ACT = Low are specified for the first local gate drive G1 at a particular time, then RUN = High and ACT = High must apply at the same time for the second local gate drive (or vice versa).

In this circuit diagram, the circuit then oscillates independently (with the high frequency of preferably greater than or equal to 0.5 MHz, see above) in each active intermediate circuit between two extreme values I _max and I _min . The central control unit only has to specify the current direction (via ACT) and the duty cycle resulting from the time profile of the "RUN" signal, these signals being low-frequency (eg with the low frequency in the range from 100 Hz to 100 kHz). preferably about 1 kHz) and therefore can easily be transmitted across different voltage levels. These relationships may be explained in more detail below with reference to FIGS. 3, 4a and 4b.

3 shows again the wiring diagram 1 , where omitted for better clarity, different reference numerals and instead additional labels for different current and voltage values have been added.

Here, generally, U _b ^(j) denotes the cell voltage between the anode and the cathode (at a given time) in the j-th intermediate circuit S _j , of the battery cell Z _{j associated with} the j-th intermediate _circuit . I _i ^(j) denotes the (signed) current through the inductance L of the j-th intermediate circuit S _j , I _q ^(j) the current through the first transistor Q1 of the j-th intermediate circuit S _j and I _z ^(j) the current through the second transistor Q2 of the j-th intermediate circuit S _j , which - depending on the sign - a current from the intermediate circuit S _j in the DC link 7 or a current from the DC link 7 in the intermediate circuit S _j . With U _x ⁽³⁾ is between the anode of the j-th accumulator cell Z _j and the (advantageously lying at the reference or ground potential) cathode 4 the battery 2 given voltage, where for j = 1 U _x ⁽¹⁾ = U _B and for j = n U _x ⁽ⁿ⁾ = U _b ⁽ⁿ⁾ holds.

Due to the different voltage levels of the anodes of the different battery cells Z _j , the following relationship applies: $$\frac{I_Z^{\left(j\right)}}{I_q^{\left(j\right)}}=\frac{U_b^{\left(j\right)}}{U_Z-U_x^{\left(j\right)}}$$

That of an intermediate circuit S _j in the DC link 7 Thus, the larger the difference (U _Z -U _x ^(j) ) compared to U _b ^(j) , the smaller the current I _Z ^(j) flowing is compared to I _q ^(j) .

By way of example, in a battery with a total of 14 accumulator cells, U _Z = 75 V, U _B = U _x ^{(1) of} the uppermost accumulator cell may be equal to 56V and U _b equal to 4V. Thus, I _Z ^{(1) is} about 21% of I _q ⁽¹⁾ for the topmost cell. Because it applies: $$I_Z^{\left(1\right)}=\frac{4}{75-56}*I_q^{\left(1\right)}\approx 0.21*I_q^{\left(1\right)}$$

For the lowest cell Z _{14 of} a battery consisting of a total of 14 battery cells 2 If I _Z ^{(14) would be} only about 5.6% of I _q ⁽¹⁴⁾ .

Since everyone (from or to the DC link 7 flowing) current I _Z ^(j) always flows through the lower accumulator cells Z _i with i> j, applies to the equalizing current of the j-th accumulator cell Z _j : $$I_{AusGleicH}^{\left(j\right)}=I_q^{\left(j\right)}+{\displaystyle \underset{i=1}{\overset{j}{\Sigma }}{I}_Z^{\left(i\right)}}$$

For the operation of the battery system according to the invention 1 necessary specification of the potential of the DC link 7, which is defined by the voltage U _Z at the capacitor C (and the reference potential), the following aspects apply:

The voltage difference between the anode of an accumulator cell Z _j and the DC link 7 In comparison with the actual cell voltage U _b ^(j) , the ratio of the current I _Z ^(j) into (or out of) the DC link to the current I _q ^{(j) is} determined by the first transistor Q1. The higher the potential of the DC link 7 is, the greater the current I _q ^(j) through the first transistor Q1 of an intermediate circuit S _j compared with the current I _Z ^(j) from the intermediate circuit S _j in the DC link. However, the current I _Z ^(j) in the DC link affects all subsequent accumulator cells, ie, all cells in the representations in accordance with 1 and 3 lower in the row. Therefore, this must generally be compensated for by a suitable correction in the (low frequency) operating mode setting for the local gate drives in the lower intermediate circuits, which will slightly increase the overall losses of the circuit.

Investigations on batteries with 14 serially connected accumulator cells Z _i have shown that in the case of typical capacitance distributions (SOH distributions) in the cells, a DC link potential U _Z of approximately 10 V above the battery voltage U _{B is} already sufficient to provide the additional losses due to said correction to approx. 10% compared to the other losses in the active balancing circuit 6 to limit. This is because a low DC link potential mainly affects the uppermost battery cells. The lower battery cells automatically set a higher differential voltage.

In addition, it should be noted that the withstand voltage of commercially available and in principle suitable transistors is typically 60V, 80V, 100V or higher. A dielectric strength of 80V is thus the lowest possible dielectric strength in a battery with 14 battery cells connected in series, since the battery voltage U _B = U _x ⁽¹⁾ for lithium-ion batteries (with an accumulator cell voltage of not more than 4, 2 V) can already reach a value of 14 * 4,2V = 58.8V. With the above considerations regarding the total losses, therefore, a DC link potential of, for example, about 75 V can be selected in the example mentioned, with which transistors with a dielectric strength of (only) 80 V can be used for a battery system according to the invention.

The 4a and 4b Now show the adjusting in a battery system according to the invention in different operating modes of the local gate drive timing of flowing through the inductor L in any intermediate circuit current I _i , which in a substantially sawtooth manner between two different values I _min and I _max by one Mean I _mean fluctuates.

It is in 4a First, that operating mode is shown in which during the active balancing charge from an accumulator cell in the DC link 7 is transmitted, which is shown by the fact that the (over time) average current I _mean by the inductance L is positive.

In this mode of operation, the first local gate drive G1 of an intermediate circuit, which switches the first transistor Q1 of the relevant intermediate circuit, is connected to its inputs RUN and ACT (cf. 2 ) from the central control unit 8th is driven with the control signals RUN = High and ACT = High as operating characteristics, while the second local gate drive G2, which drives the second transistor Q2, with the control signals RUN = High and ACT = Low is driven. As a result, both the first local gate drive G1 switching the first transistor Q1 and the second gate drive G2 switching the second transistor Q2 are active.

The first transistor Q1 is switched on at the instant t ₀ (ie conducting in the sense of a closed switch). The current I _i through the inductance L, which corresponds to the current I _q through the first transistor Q1 in the time interval [t ₀ , t ₁ ] with t ₁ = t ₀ + T ₁ , initially drops in absolute value starting from an initially negative value I _min and in a linear manner to zero, and then - after the reversal of direction at the zero crossing - in a linear subsequent manner continue to increase in a positive direction. Upon reaching a predetermined threshold of, for example, I _max = 4 A or I _max = 4.5 A for the current flowing through the first transistor Q1 current I _q turns off the first transistor. The second transistor Q2 turns on immediately as soon as the drain-source voltage at the second transistor Q2 drops to below zero. Since this switch-on at disappearing voltage, this takes place in the sense of a zero-voltage switching largely lossless.

Then takes the flowing through the inductor L and in 4a shown current I _i in the time interval [t ₁ , t ₂ ] with t ₂ = t ₁ + T ₂ when the second transistor Q2 turned on again in a linear manner, the current I _i in this time interval the signed current I _Z from the intermediate circuit in corresponds to the DC link. After again reversing the direction of the zero crossing, the current I _i again increases linearly in a negative direction until the current I _{i reaches} the threshold I _min effecting the switching off of the second transistor Q ₂ at time t ₂ . Then, the first transistor Q1 turns on again when there is the working voltage between its drain and source has its zero crossing, and the entire cycle starts from the beginning.

4b in a sense represents the opposite operating mode, during which additional charge is taken from the DC link during active balancing 7 is transferred to an accumulator cell, resulting in 4b thereby shows that the average current I _mean by the inductance L is negative.

In this mode of operation, the first local gate driver G1, which switches the first transistor Q1, is connected to its inputs RUN and ACT (see FIG. 2 ) from the central control unit 8th with the (only low frequency to be updated) control signals RUN = High and ACT = Low driven as operating parameters, while the second local gate drive G2, which drives the second transistor Q2, with the complementary control signals RUN = High and ACT = High is driven ,

As a result, both the first local gate switching G2 switching the first transistor Q1 and the second gate driver switching the second transistor Q2 are active, whereby initially the second transistor Q2 is switched on (ie conducting in the sense of a closed switch) while the second transistor Q2 is turned on first transistor Q1 first turned off and therefore only in the flow direction of the freewheeling diode is conducting.

$$\begin{array}{ccc}{I}_{mittel}=\frac{I_{max}+I_{min}}{2}& I_z=I_{mittel}\frac{T_2}{T}& I_q=I_{mittel}\end{array}\frac{T_1}{T}$$

$$\begin{array}{cc}\frac{T_1}{T}=\frac{U_z-U_x}{\left(U_z-U_x\right)+U_b}& \frac{T_2}{T}=\frac{U_b}{\left(U_z-U_x\right)+U_b}\end{array}$$

$$\begin{array}{ccc}{I}_q=I_{mittel}\frac{U_z-U_x}{\left(U_z-U_x\right)+U_b}& I_z=I_{mittel}\frac{U_b}{\left(U_z-U_x\right)+U_b}& \frac{I_z}{I_q}=\frac{U_b}{U_z-U_x}\end{array}$$

For the various voltages, currents and time intervals, the following formulas apply in each intermediate circuit: $$\begin{array}{ccc}{\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="DE102017104229A1\_0008.png,DE102017104229A1\_0009.png"\; state="\{\{state\}\}">T</figure-callout>}}_1=\left(I_{max}-I_{min}\right)\frac{L}{{\mathrm{<figure-callout\; id="2"\; label="U\; b\; T"\; filenames="DE102017104229A1\_0008.png,DE102017104229A1\_0009.png"\; state="\{\{state\}\}">U\; </figure-callout>}}_b}& T_{}{}_2=\left(I_{max}-I_{min}\right)\frac{L}{U_z-U_x}& T={\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="DE102017104229A1\_0008.png,DE102017104229A1\_0009.png"\; state="\{\{state\}\}">T</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="T"\; filenames="DE102017104229A1\_0008.png,DE102017104229A1\_0009.png"\; state="\{\{state\}\}">T</figure-callout>}}_2\end{array}$$

$$\begin{array}{ccc}{I}_{mittel}=\frac{I_{max}+I_{min}}{2}& I_z=I_{mittel}\frac{T_2}{T}& I_q=I_{mittel}\end{array}\frac{T_1}{T}$$

$$\begin{array}{cc}\frac{T_1}{T}=\frac{U_z-U_x}{\left(U_z-U_x\right)+U_b}& \frac{T_2}{T}=\frac{U_b}{\left(U_z-U_x\right)+U_b}\end{array}$$

$$\begin{array}{ccc}{I}_q=I_{mittel}\frac{U_z-U_x}{\left(U_z-U_x\right)+U_b}& I_z=I_{mittel}\frac{U_b}{\left(U_z-U_x\right)+U_b}& \frac{I_z}{I_q}=\frac{U_b}{U_z-U_x}\end{array}$$

In this case, U _x corresponds to the voltage between the anode of the respective battery cell and the cathode 4 the battery 2 ; U _b corresponds to the respective cell voltage between anode and cathode of the respective intermediate circuit associated accumulator cell.

The 5a . 5b and 6a . 6b finally show still electrical engineering simulations of various current and voltage waveforms in an intermediate circuit of the active balancing circuit of a battery system according to the invention.

The 5a and 5b show again (comparable to the representation of 4a ) the application that - is transferred in accordance with operating mode specification by the central control unit of a battery system according to the invention charge from the accumulator cell associated with the considered intermediate circuit in the DC link. In this case, in turn, a substantially sawtooth-like and on average positive current I _i through the inductance of the considered intermediate circuit, wherein the (resulting from the high-frequency gate drive) on times T ₁ and T _{2 of} the respective transistors in the calculation example according to 5a and 5b Recognizable in a different ratio than in the - rather schematic - representation 4a , Furthermore, the show 5a and FIG. 5b shows the voltage _profiles U _Q1 and U _{Q2 of} the drain-source voltage prevailing at the transistors Q1 and Q2 of the intermediate circuit under consideration, and the respective profile of the associated control voltages U _G1 , U _G2 (generated by the local gate drive) the respective local gate drive G1 or G2 acts on the gate of the respectively associated transistor Q1 or Q2.

The 6a and 6b in turn relate to this alternative use case, in which additional charge from the DC link is transferred to the accumulator cell.

Good to see is that the respective control voltages U _G1 , U _{G2 are turned on} only when the respective drain-source voltage U _Q1 and U _Q2 has dropped below zero in the sense of a zero-voltage switching and that the respective transistors are turned off when the respective current I _i through the inductance exceeds a certain threshold.

Since the battery system according to the invention is characterized in particular by a very low power loss, finally a few more measures for further loss minimization are mentioned, which can be implemented in the context of the present invention. The losses in FETs or transistors can be divided into switch-on losses, line losses, switch-off losses and drive losses.

The line losses and the losses due to the control can not be avoided in principle, but reduced by suitable component selection. The turn-on losses are dependent on the voltage across the transistor at the time of switching. The voltage can thereby be reduced or even brought to zero, that in each case a small backflow through the inductance is allowed.

If the considered accumulator cell is to be discharged into the DC link, then the currents normally flow into the in 3 marked directions. When Q2 is conducting, the current I _i, and therefore also I _z, decrease linearly with the velocity [U _z -U _x ] / L. The second transistor Q2 of the subject intermediate circuit can advantageously be only switched off now, when the current I _i has become negative by the inductance, so if a small current (for example, equal to 25% of I _max) flowing back into the battery cell. Despite switching off Q2, however, the current in the inductor must continue to flow. This feeds from all parasitic capacitors, which are effective at the node. This reduces their voltage. If the negative current was large enough, the voltage is reduced to zero. At this moment, preferably the first transistor Q1 of the intermediate circuit is turned on. Since no voltage is applied to Q1 at the moment of switch-on, there are no switch-on losses. When turning on the second transistor Q2 (virtually) no turn-on, because at shutdown of Q1, the current charges the parasitic capacitances until the (drain-source) voltage to Q2, the polarity changes. At this moment, therefore, the voltage at the second transistor Q2 is zero and it can be turned on without loss.

If the considered accumulator cell is to be loaded from the DC link, then the currents normally flow against the in 3 marked directions. If the first transistor Q1 is turned on and thus conducts, then the current I _i and thus I _q decreases linearly at the speed [U _b ] / L. In this case, I _i decreases in magnitude from eg -4 A in the direction of 0 A. The first transistor Q1 of the considered intermediate circuit can now advantageously be switched off only when the current I _i has become positive, ie when a low current (eg in Height of 25% of I _max ) flows back out of the accumulator cell. However, in spite of turning Q1 off, the current in the inductor must continue to flow. It then fills all the parasitic capacitors that are active at the node, thus increasing their voltage. If the positive current was large enough, the voltage can be increased up to Uz. At this moment, advantageously, the second transistor Q2 can be turned on. Since no voltage is applied to Q2 at the moment of switch-on, no relevant switch-on losses occur. In contrast, when switching on the first transistor Q1 (practically) no turn-on losses, because when switching off Q2, the current discharges the parasitic capacitances until the (drain-source) voltage at Q1 changes the polarity. At this moment, however, the voltage across Q1 is zero and Q1 can be switched off without voltage, ie without losses.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited non-patent literature

• Daowd et al., International Review of Electrical Engineering (I.R.E.E.) - Nov / Dec2011, Vol. 6, Issue 7, p. 2974-2989 [0011]

Claims (8)

Battery system (1) comprising - a rechargeable battery (2), which two poles (3, 4) and a plurality of connected between the poles (3, 4) in series battery cells (Z ₁ , Z ₂ , ..., Z _n ), and - an active balancing circuit (6) for monitoring and active control of the charge states of the battery cells (Z ₁ , Z ₂ , ..., Z _n ), wherein in the active balancing circuit (6) each accumulator cell (Z ₁ , Z ₂ , ..., Z _n ) is provided as a bidirectional DC-DC converter intermediate circuit (S ₁ , S ₂ , ..., S _n ), wherein each intermediate circuit (S ₁ , S ₂ , ..., S _n ) the two poles of the respective accumulator cell (Z ₁ , Z ₂ , ..., Z _n ) with the interposition of an inductance (L) and a first transistor (Q1) connects, and wherein in each Intermediate circuit (S ₁ , S ₂ , ..., S _n ) between the inductance (L) and the first transistor (Q1) is provided a branch which, with the interposition of a second transistor (Q2 ) is connected to a DC link (7), which conductively connects all intermediate circuits (S ₁ , S ₂ ,..., S _n ), the DC link (7) being connected to a reference potential (GND) via a capacitor (C). is coupled, and wherein the active balancing circuit (6) is suitable and is arranged in a regular operating mode to keep the DC link (7) at a predeterminable potential, which is either greater than the potential at the positive pole (3 ) of the battery (2) or smaller than the potential at the negative pole (4) of the battery (2). Battery system (1) after Claim 1 , characterized in that the battery system, a central control unit (8) and for each intermediate circuit (S ₁ , S ₂ , ..., S _n ) at least one with the central control unit (8) directly or indirectly connected local gate drive (G1 G2) for driving the transistors (Q1, Q2) provided in the respective intermediate circuit, the central control unit (8) being arranged to specify different operating modes for each local gate driver (G1, G2) in a time-wise manner, and each local gate -Ansteuerung (G1, G2) is adapted to the at least one of them to be controlled transistor (Q1, Q2) under evaluation of the voltage applied to the respective transistor (Q1, Q2) voltage (U _Q1 , U _Q2 ), by the respective transistor (Q1, Q2) flowing current (I _q , I _Z ) and of the predetermined by the central control unit (8) operating mode conductive or non-conductive. Battery system (1) after Claim 2 , characterized in that for measuring the current flowing through the respective transistors (Q1, Q2) (I _q , I _Z ) upstream of the transistor upstream or downstream measuring resistor (R _s ) is provided. Battery system (1) after Claim 2 or 3 , characterized in that the operating mode to be preset by the central control unit (8) for each local gate drive (G1, G2) is specified by transmitting at least one operating parameter (RUN, ACT) which determines whether the respective intermediate circuit (S ₁ , S ₂ , ..., S _n ) associated accumulator cell (Z ₁ , Z ₂ , ..., Z _n ) via the DC link (7) loaded, unloaded or should neither be loaded nor unloaded. Battery system (1) according to one of Claims 2 to 4 , characterized in that the central control unit (8) is arranged to preset or update the operating modes to be preset for each gate drive (G1, G2) at a first frequency in the range between 100 Hz and 100 kHz, and in that local gate drives (G1, G2) and the transistors (Q1, Q2) for a high-frequency drive and circuit having a frequency that is greater by a factor of at least 10 than the first frequency, in particular a frequency greater than or equal to 0.5 MHz, are set up. Battery system according to one of Claims 2 to 5 , characterized in that each local gate drive (G1, G2) is realized by a separate integrated circuit. Battery system according to one of the preceding claims, characterized in that in the intermediate circuits (Z ₁ , Z ₂ , ..., Z _n ) built-inductances (L) are designed as air coils or conductor track coils. A method for operating a battery system according to any one of the preceding claims comprising the following steps: A) Specification of a potential which is either greater than the potential at the positive pole (3) of the battery (2) or less than the potential at the negative pole (4) Battery (2) is B) charging the capacitor coupling the DC link to the reference potential to a target voltage (U _Z ) at which the potential of the DC link (7) corresponds to the predetermined potential in step (A) C) Operating the active balancing circuit in a regular operating mode such that the potential of the DC link (7) remains substantially unchanged.

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