DE102016215276B4 - CONTACT SOI SUBSTRATES - Google Patents

Abstract

An integrated circuit including a semiconductor bulk substrate; a buried oxide layer formed on the semiconductor bulk substrate; a plurality of cells (350, 355) formed over the buried oxide layer, each cell having a transistor device; a plurality of gate electrode lines (318), which pass through the plurality of cells (350, 355) and provide gate electrodes for the transistor devices of the cells (350, 355); anda plurality of tap cells (110, 310) configured to electrically contact the semiconductor solid substrate and arranged at positions different from positions below or above the plurality of cells (350, 355) with the transistor components, at least one of which of the plurality of tap cells (110, 310) is arranged between embedded edge cells (120, 220, 220 ', 320); andwherein at least one of the plurality of tap cells (110, 310) is arranged between embedded edge cells (120, 220, 220 ', 320) which are crossed by edge gate electrode lines (320) which have a greater width than the gate electrode lines ,

Description

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

In general, the present invention relates to integrated circuits and semiconductor devices, and more particularly to the formation of contacts to semiconductor substrates of SOI devices.

DESCRIPTION OF THE PRIOR ART

The production of modern integrated circuits, such as CPUs, memory devices, ASICs (application-specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area in accordance with a specified circuit arrangement. In a variety of electronic circuits, field effect transistors are an important type of circuit element, which essentially determine the performance of the integrated circuits. In general, a variety of process technologies are currently being practiced for manufacturing field effect transistors (FETs), with MOS technology currently being one of the most promising approaches for many types of complex circuits due to the good properties in terms of operating speed and / or current consumption and / or cost efficiency is. During the fabrication of complex integrated circuits using, for example, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate that includes a crystalline semiconductor layer.

Nowadays, the FETs are usually produced on silicon-on-insulator (SOI) substrates and in particular fully depleted silicon-on-insulator (FDSOI) substrates. The channels of the FETs are formed in thin semiconductor layers, which are typically made of or comprise a silicon material or another semiconductor material, the semiconductor layers being formed on insulating layers, buried oxide (BOX) layers, which in turn are formed on semiconductor solid substrates. A serious problem caused by the aggressive scale down of the semiconductor devices must be seen in the occurrence of leakage currents. Since the leakage currents depend on the threshold voltages of the FETs, biasing the substrate (back-biasing) can reduce the power loss. With this advanced technique, the substrate or a suitable well is biased to increase the transistor thresholds, thereby reducing leakage currents. In PMOS devices, the body of the transistor is biased with a voltage that is higher than the positive supply voltage V _DD . In NMOS devices, the body of the transistor is biased to a voltage lower than the negative supply voltage Vss.

In the US 8 443 306 B1 describes an integrated circuit based on FDSOI, in which PMOS transistors are biased using tap cells. In the US 2014/0 176 216 A1 describes an integrated circuit which comprises standard cells with transistors and clock tree cells which are surrounded by the standard cells and also have transistors. In the US 2011/0 278 581 A1 describes an integrated circuit with MOSFETs which are formed above dopant diffusion regions of an SOI substrate, the dopant diffusion regions being connected to metal lines via connections led through the insulating layer of the SOI substrate.

1a shows an SOI configuration with a solid semiconductor substrate 10 , with an N ⁺ doped region 11 and a P ⁺ doped region 12 in the solid semiconductor substrate 10 are trained. The SOI configuration also includes a BOX layer 13 that are on the semiconductor full substrate 10 is formed, and a semiconductor layer 20 that are on the BOX layer 13 is formed and provides a channel area. 1a also shows a layer of a gate electrode material 14 , for example polysilicon, over the semiconductor layer 20 is trained. The N ⁺ doped region 11 and the P ⁺ doped region 12 are used for back-biasing the P-channel FET gates or N-channel FET gates. In integrated circuits (IC), cell structures are formed by gate electrode lines (poly lines) 14a formed, the standard cells of the active semiconductor devices, such as that in 1a shown, define. In general, the polysilicon (poly) lines (lines) run 14a ( 1b and 1e) parallel to each other. It is pointed out that the gates of the FETs can comprise a metal material in addition to the polymer material. In advanced ICs, the gate constructs are so small that they cannot be manufactured as arbitrarily placed gates using current technologies. Instead, a regular grid (grid) of poly lines must be used 14a are made using parallel poly-wire shapes 14a with a precisely defined width and spacing, as in 1b is shown. Then, in additional manufacturing steps, unwanted poly lines 14a with a poly line (PC) - clipping mask removed. The regular poly line grid ("Sea of Gates") must be surrounded by edge cells, the parallel poly lines 15 of wider widths to include the regular poly lines 14a of the Protect standard cells against polishing defects during manufacture.

To reduce the time it takes to complete the design process, cell libraries have been created in which standard cell designs are available. Of course, there are applications that may require one or more specialized cells, in which case the designers either create an individual cell for the layout or change a library cell in a way that is dictated by the desired design. The resulting layout is used to create the desired integrated circuit. Depending on the design and library used, back biasing can be done for the PMOS or NMOS devices or for both. To bias the body of the NMOS and PMOS of the standard cells, voltages are generated by charge pumps, which are user-defined blocks that provide V _DDbias and V _SSbias voltages. Each standard cell row must have at least one (body or tub) tap cell. However, designers sometimes have a rule for arranging a tap cell in a standard cell row at any given interval at regular intervals.

Similar to the grid of standard cells, a grid of tap cells is commonly used in an integrated circuit design to provide a bias for the body of the transistors. The tap cells must have electrical connections between a network that provides bias and the P ⁺ / N ⁺ regions, such as the areas 11 and 12 , in the 1a are shown form. Since the bias network is carried out on metal layers, the multiple layers above the BOX layer 13 , in the 1a is shown to be routed, and since the P ⁺ / N ⁺ areas 11 and 12 itself below the BOX layer 13 in the full substrate 10 parts of the BOX layer 13 (which is a very good insulator) to be removed to make contact with the areas 11 . 12 to accomplish. Because the BOX layer 13 is relatively thick, the openings must be in the BOX layer 13 be etched, be relatively large. Therefore, there is a particular problem with the conventional techniques as in the 1c to 1e illustrated.

1c shows an arrangement similar to that in 1a shown, after structuring the semiconductor layer 20 an opening in the BOX layer 13 is formed with the poly material layer 14 which is used to form the gate electrodes 14a is used by FETs. The opening of the BOX layer 13 is formed in the area of the regular poly line grid, which in 1b is shown. The poly material layer 14 after the formation of the opening in the BOX layer 13 formed for the formation of a back bias contact. A layer of mask 16 is over the poly material layer 14 formed as in 1c is shown. As in 1d the mask layer is shown 16 structured by a standard lithography process to create a structured mask 17 to obtain that for the formation of poly-lines (gates) 14a over the BOX layer 13 is used (see 1e) ,

However, it forms during the etching process to produce the poly gates 14a a thin poly ridge 19 in the opening of the BOX layer 13 , In fact, the formation of the poly ridge 19 cannot be properly controlled because the focus of the lithography device used is on the positions where the poly gates 14a must be trained. On the other hand, the formation of the poly ridge 19 cannot be avoided due to the regular poly line grid. The undesirable formation of the poly ridge 19 in the opening of the BOX layer 13 leads to contamination of the wafer because of the unstable poly ridge structure 19 easily breaks off during further processing.

In view of the situation described above, the present invention provides a technique for forming substrate contacts that avoids wafer contamination due to poly residues caused by the formation of thin poly ridges in large BOX openings in prior art manufacturing processes.

SUMMARY OF THE INVENTION

In general, the subject matter disclosed herein relates to the formation of semiconductor devices with transistor devices and, more particularly, to integrated circuits with (MOS) FETs including tap cells for back-biasing the transistor devices.

It is provided: an integrated circuit having a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate, a plurality of cells formed over the buried oxide layer, each cell having a transistor device, a plurality of gate electrode lines passing through the A plurality of cells extend and provide gate electrodes for the transistor components of the cells, and a plurality of tap cells which are designed for electrically contacting the semiconductor full substrate and are arranged at positions which are different from positions below or above the plurality of cells with the transistor components , wherein at least one of the plurality of tap cells is arranged between embedded edge cells and at least one of the plurality of tap cells is arranged between embedded edge cells Gate electrode lines are crossed, which have a greater width than the gate electrode lines. The integrated circuit may also have a plurality of fill cells in areas which may or may not contain transistors, for example to connect the PC lines.

The tap cells provide electrical connections between N-doped / P-doped regions of a solid semiconductor substrate, over which the transistor components are formed, and a bias network, which is used for back-biasing the transistor components. The transistor components can have gate electrodes, which can be produced from a metal material and a polysilicon material, the polysilicon material being provided in the form of (poly) gate electrode lines which run through a grid of regular (standard) cells.

list of figures

• 1a-1e ein herkömmliches Back-Biasing eines Standardzellengitters veranschaulichen, wobei 1a eine SOI-Konfiguration zeigt, die dotierte Bereiche in einem Halbleitervollsubstrat aufweist, die für ein Back-Biasing verwendet werden, 1b ein regelmäßiges Standardzellenraster mit parallelen Poly-Leitungen und Grenzzellen zeigt, und die 1c-1e ein Problem der Waferverschmutzung im Zusammenhang mit dünnen Poly-Graten in relativ großen Öffnungen, die in BOX Schichten gebildet sind, veranschaulichen;
• die 2a bis 2c Tap-Zellen - Standardzellen-Designs für ICs, wobei Substratkontakte außerhalb eines regulären Poly-Leitungsraster positioniert werden, veranschaulichen;
• die 3a und 3b alternative Tap-Zellen - Standardzellen-Designs für ICs zeigen, die nicht Bestandteil der vorliegenden Erfindung sind, wobei Substratkontakte außerhalb eines regulären Poly-Leitungsraster positioniert werden; und
• 4 ein weiteres alternatives Tap-Zellen-Standardzellen-Design für ICs zeigt, das nicht Bestandteil der vorliegenden Erfindung ist, wobei Substratkontakte außerhalb eines regulären Poly-Leitungsraster positioniert werden.

The invention may be understood in conjunction with the accompanying drawings with reference to the following description, in which like reference numerals identify like elements, and in which:

• 1a-1e illustrate conventional back biasing of a standard cell grid, wherein 1a FIG. 2 shows an SOI configuration that has doped regions in a semiconductor full substrate that are used for back biasing, 1b shows a regular standard cell grid with parallel poly lines and boundary cells, and the 1c-1e illustrate a problem of wafer contamination associated with thin poly burrs in relatively large openings formed in BOX layers;
• the 2a to 2c Tap Cells - Illustrate standard cell designs for ICs with substrate contacts positioned outside of a regular poly line grid;
• the 3a and 3b alternative tap cells - show standard cell designs for ICs that are not part of the present invention with substrate contacts positioned outside of a regular poly line grid; and
• 4 shows another alternative tap cell standard cell design for ICs, which is not part of the present invention, wherein substrate contacts are positioned outside of a regular poly line grid.

DETAILED DESCRIPTION

As will be readily apparent to those skilled in the art after a full reading of the present application, the present methods are applicable to a variety of technologies, such as NMOS, PMOS, CMOS, etc., and can be readily applied to a variety of devices, including, but not limited to, logic devices, SRAM devices, etc., particularly used in the context of FDSOI technologies for manufacturing integrated circuits (ICs). In general, manufacturing techniques and semiconductor devices in which back (substrate) -biased N-channel transistors and / or P-channel transistors can be formed are described here. The manufacturing techniques can be integrated into CMOS manufacturing processes. The techniques and technologies described here can be used to fabricate MOS integrated circuit devices, including NMOS integrated circuit devices, PMOS integrated circuit devices, and CMOS integrated circuit devices. In particular, the method steps described herein are used in conjunction with any semiconductor device manufacturing process that forms gate structures for integrated circuits including both planar and non-planar integrated circuits. Although the term “MOS” actually refers to a component that has a metal gate electrode and an oxide gate insulator, this term is used throughout to refer to any semiconductor device that has a conductive gate electrode (be it metal another conductive material) disposed over a gate insulator (whether oxide or other insulator), which in turn is positioned over a semiconductor bulk substrate.

The present invention generally provides techniques for contacting full substrates of FDSOI devices to enable back biasing and design for tap cells and standard cells, a poly material used for the manufacture of poly gate Lines is formed, is not formed in openings in a BOX layer of an FDSOI substrate.

Exemplary tap cell standard cell designs for ICs according to the present invention are shown in US Pat 2a to 2c shown. Substrate contacts for back-biasing FETs are provided outside the regular grid (grid) of standard cells, each of which has an FET. The cell design 100 , this in 2a is shown by a tap Cell / BOX opening 110 characterized, which is provided in an area of a wafer in which no poly material is formed as part of a regular polyline grid (polyline grid) or a polygate. The wafer substrate can be in a P-doped region 130 and an N-doped region 135 that the in 1a shown areas 11 and 12 may be similar. The tap cell / BOX opening 110 is between embedded edge cells / polycables 120 arranged. The embedded marginal cells 120 can the marginal cells 15 of conventional design (see 1b) be similar, but they are formed in an otherwise regular grid of standard cells instead of on the edges of the grid.

The standard cells can be any type of logic cell that includes FETs, such as inverters, NAND gate cells, multiplexers, and the like. Like it in 2 B is shown, in particular lower marginal cells 220 (top drawing of the 2 B) and upper marginal cells 220 ' (lower drawing of the 2 B) can be formed. The wafer substrate can be in the P-doped region 230 and the N-doped region 235 through the opening 210 be contacted. As a result of the illustrated design, poly lines of the grid of standard cells are always sufficient of openings in BOX layers (namely outside the edge cells 120 ) spaced so that no poly contamination is caused by undesirable formation of unstable poly structures in these openings, as described above with reference to the prior art.

As a result of the wider poly shape 320 In the embedded edge cells next to the substrate contacts, tap cells can no longer be placed above or below normal standard cells, since these standard cells use the regular poly line grid. Instead, tap cells can be placed in tap cell columns that begin at the bottom standard cell border row and end at the top standard cell border row, as shown in 2c is shown. In detail shows 2c a tap cell - standard cell design 300 for an IC with standard cells 350 at a lower limit and standard cells 355 at an upper limit of a specified region of a wafer. Edge cells and edge polycables are similar to a conventional design 315 provided on the left and right borders of the region. The boundary polyline forms 315 have larger widths than the poly cables 318 the standard cells around these regular poly lines 318 Protect against polishing defects during further production.

Poly-lines 318 the standard cells run parallel to each other. The conventional regularity of the poly line grid is through the provision of columns of embedded (inner) edge cells / poly lines 320 Broken. Between two columns of embedded edge cells / poly lines 320 , there are openings in the BOX layer 310 and tap cells for contacting N-doped and P-doped regions of the semiconductor full substrate of the wafer. The N-doped region may be a region that is heavily doped with an N-type dopant such as phosphorus, arsenic, or the like. The P-doped region may be a region that is heavily doped with a P-type dopant such as boron, indium, or the like. For example, "heavily doped" can include any dopant concentration of over 10 ¹⁹ / cm ³ . The tap cells provide electrical connections between the N-doped / P-doped regions of a full substrate, over which the transistor components are formed, and a bias voltage network, which is used for back-biasing the transistor components.

It should be noted that in the 2c Design Tap cells shown can be positioned at evenly spaced intervals in columns of the IC configuration. It may be preferred that the spacing between tap cells does not exceed the maximum allowable spacing obtained using the design rules associated with the IC. In particular, the design rules can specify the maximum distance from any point in the substrate or well region to the closest substrate or well tap. It should also be noted that in addition to connecting doped regions of the semiconductor solid substrate, the tap cells can provide decoupling capacitors for energy lines in order to use regions which are occupied by the tap cells more efficiently.

The tap cells can be arranged in an IC design layout before, after or simultaneously with the layout of standard cells. Leakage current reduction and control can be optimized by the number and positioning of the tap cells. The interval of the tap cells may depend on the geometric dimensions of the associated FETs and other devices, so that as the geometry continues to decrease, the frequency and spacing of the tap cells may be increased or decreased as desired.

Each of the tap cells can also comprise a bias voltage source and / or controller (for example a controller) which is separate from the voltage source and / or a controller of the associated components. The voltage source and / or control for the tap cells can be located locally or relatively to the associated devices, possibly even on a separate die or chip. Each tap cell can have separate voltage sources. Alternatively, all tap cells can be controlled by a single voltage source. Clusters of tap cells within an IC can each share a voltage, so that each cluster of tap cells in an IC connects to one appropriate voltage source and / or control is connected.

Here and in the following examples, the layouts disclosed may be integrated into an IC design tool, which may include a variety of electronic software design tools that may be associated with various databases, such as a semiconductor foundry and / or one or more Foundry customers. In particular, the IC design tool can contain a plurality of component libraries that can be accessed via a graphical user interface, wherein cells from individual component libraries can be arranged in an IC design layout.

In this example and in the examples not according to the invention, which are described below with reference to FIG 3a . 3b and 4 , the disclosed tap cell standard cell design can be used in connection with the manufacture of semiconductor devices, which can include SOI or FDSOI FETs. The FETs that can be back-biased using the tap cells can include FETs that have configurations similar to that in FIG 1a have shown. Specifically, an FET, which may be back-biased using the design disclosed herein, can be formed on an FDSOI substrate that is a bulk substrate, a BOX layer that is formed on the bulk substrate, and a semiconductor layer that is on the BOX Layer is formed.

The solid semiconductor substrate can be a silicon substrate, in particular a single crystal silicon substrate. Other materials can be used to form the semiconductor substrate, such as germanium, silicon germanium, gallium phosphate, gallium arsenide, etc. The semiconductor bulk substrate includes N ⁺ / P ⁺ doped regions for back biasing. The BOX layer may comprise a dielectric material, such as silicon dioxide, and may have a thickness of at least 50 nm, for example. The semiconductor layer may provide the channel region of the FET and may include any suitable semiconductor material, such as silicon, silicon / germanium, silicon / carbon, other II-VI or III-V semiconductor compounds, and the like. The semiconductor layer can have a thickness that is suitable for a fully depleted field effect transistor, for example a thickness in a range of approximately 5-8 nm.

The FET includes a gate electrode that is formed over the semiconductor layer. The gate electrode may include a metal gate and polysilicon gate materials. The material of the metal gate may depend on whether the transistor device that is to be formed is a P-channel transistor or an N-channel transistor. In embodiments in which the transistor device is an N-channel transistor, the metal can comprise La, LaN or TiN. In embodiments in which the transistor device is a P-channel transistor, the metal can comprise Al, AlN or TiN.

The metal gate may comprise a work function adjusting material, for example TiN. In particular, the metal gate may comprise a work function adjusting material comprising a suitable transition metal nitride, for example one from groups IV-VI of the periodic table, including, for example, titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum nitride (TiAIN), tantalum -Aluminium nitride (TaAIN), niobium nitride (NbN), vanadium nitride (VN), tungsten nitride (WN) and the like, with a thickness of approx. 1-60 nm. In addition, the effective work function of the metal gate can be increased by adding dopants, for example Al, C or F, can be set. The poly gate can be formed on the metal gate.

The gate electrode can be separated from the semiconductor layer of the FDSOI substrate by a gate dielectric. The gate dielectric can comprise a material layer with a large k with a dielectric constant k of over 4. The large k material layer may include a transition metal oxide, such as at least one of hafnium oxide, hafnium dioxide and hafnium silicon oxynitride, and may be formed directly on the semiconductor layer of the FDSOI substrate.

Other exemplary tap cell standard cell designs for ICs that are not part of the present invention are shown in US Pat 3a and 3b shown. The designs 400 and 500 integrate elements of the marginal cells from above and below comparable to those in the 2a to 2c are shown, but with an increased cell width, as from the 3a and 3b be removed.

The tap cells of the layouts 400 and 500 need compared to those in the 2a-2c are shown, more area per cell, but they can be placed anywhere within the layout. Therefore, the placement of the tap cells can be accomplished in a more flexible manner and fewer tap cells may be required if they are arranged in a checkerboard design. Also, no special edge cells are required at the placement limits to adapt to the tap cell polyline grid.

As in 3a shown includes the layout 400 embedded marginal cells 420 and an upper / lower cell structure 440 , An opening 410 is in the BOX layer between the structures 420 and 440 arranged. The opening 410 enables electrical contacting of the P-doped area 430 and the N-doped region 435 formed in the semiconductor bulk substrate for back-biasing a transistor device formed over the semiconductor layer and in the semiconductor bulk substrate. Such a tap cell layout 400 can be in a tap cell standard cell layout 500 used as it is in 3b is illustrated.

Similar to the layout in 2c the one that is shown in 3b is shown, columns of edge cells / polycables 515 and polylines arranged in parallel 518 on. There are also embedded edge cells / poly lines 520 provided between which openings 510 can be arranged in the BOX layer and thus tap cells.

According to another example not according to the invention, which in 4 As shown, there may be a need for relatively wide embedded poly-leads, such as those in the 3a and 3b is shown, can be avoided by suitably chosen post-design compensation (re-targeting) and corresponding design rules. This can reduce the space required to implement the tap cell that is suitable for any placement. The layout 600 , this in 4 shown includes embedded edge cells / polylines 620 and a structure 640 of embedded upper / lower cells with an opening in the BOX layer 610 for contacting P-doped 630 and N-doped 635 regions as described above.

As a result, the present invention provides tap cell standard cell layouts that avoid the formation of poly material in openings that are in BOX layers of FDSOI substrates for contacting doped regions of full substrates of the FDSOI substrates for a back- Biasing of the FETs are formed. As a result, contamination of wafers due to poly impurities which are formed from unstable poly structures which are formed in the openings of the BOX layers can be avoided.

Claims (6)

An integrated circuit with a solid semiconductor substrate; a buried oxide layer formed on the semiconductor bulk substrate; a plurality of cells (350, 355) formed over the buried oxide layer, each cell having a transistor device; a plurality of gate electrode lines (318) running through the plurality of cells (350, 355) and providing gate electrodes for the transistor devices of the cells (350, 355); and a plurality of tap cells (110, 310) which are designed for electrical contacting of the semiconductor solid substrate and are arranged at positions which are different from positions below or above the plurality of cells (350, 355) with the transistor components, at least one of the plurality of tap cells (110, 310) is arranged between embedded edge cells (120, 220, 220 ', 320); and wherein at least one of the plurality of tap cells (110, 310) is arranged between embedded edge cells (120, 220, 220 ', 320) which are crossed by edge gate electrode lines (320) which have a greater width than the gate electrode lines , The integrated circuit from Claim 1 , in which the semiconductor solid substrate comprises at least one of an N-doped and a P-doped region, which is associated with one of the plurality of tap cells (110, 310) and electrically through the one of the plurality of tap cells (110, 310) is connected to a bias voltage source via a contact formed in an opening of the buried oxide layer. The integrated circuit of one of the preceding claims, in which the plurality of tap cells (110, 310) is arranged in at least one column parallel to columns of the plurality of cells (350, 355) with the transistor components such that the tap cells (110, 310) in which at least one column is arranged adjacent to one another. The integrated circuit of any of the preceding claims, further comprising boundary cells located adjacent to the outermost of the plurality of cells (350, 355) and gate electrode lines (315) having a width greater than the width of the gate electrode lines defined by the plurality of cells ( 350, 355) with transistor components. The integrated circuit of one of the preceding claims, in which the buried oxide layer and the solid semiconductor substrate are part of a fully depleted silicon-on-insulator substrate. The integrated circuit of one of the preceding claims, in which the gate electrode lines are at least partially made of a polysilicon material.

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