DE102016212924A1 - power converter - Google Patents

Abstract

A power converter for a three-phase rotary electric machine (80) including first and second winding sets (81, 82) includes: first and second inverters (10, 20) corresponding to the first and second winding sets, respectively; and a control unit (41, 42, 43) that calculates a command calculation unit (52 to 54, 62, 63) that calculates a first and second voltage command value with respect to voltages to be applied to the first and second coil sets, and an excess correction unit (552 ) which corrects values corresponding to first and second voltage commands corresponding to the first and second voltage command values. When one of the values corresponding to a first and second voltage command exceeds a threshold value set according to a voltage that can be output, the excess correction unit executes an excess correction processing for correcting the other of the value corresponding to a first and second voltage command in accordance with an excess amount over the limit value ,

Description

The present disclosure relates to a power converter.

Heretofore, a motor driving apparatus for driving a multi-winding motor including a plurality of winding sets has been known. For example, in Patent Document 1, a fifth order harmonic and a seventh order harmonic are superposed to reduce a voltage spike to suppress torque ripple.

In Patent Document 1, a current phase has to be obtained to perform correction using the fifth order harmonic components and the seventh order harmonic components, resulting in a relatively large computational load. Further, computation error may occur in calculating the components of 5th order and 7th order harmonics. Thus, there is a possibility that torque ripple can not be adequately controlled due to the calculation error.
Patent Document 1: JP-2014-121189-A

It is an object of the present disclosure to provide a power converter that can improve a voltage utilization rate while minimizing current ripple.

According to one aspect of the present disclosure, a power converter for converting electric power of a three-phase rotary electric machine including a first winding set and a second winding set includes: a first inverter corresponding to the first winding set; a second inverter corresponding to the second winding set; and a control unit including a command calculation unit that calculates a first voltage command value with respect to a voltage to be applied to the first coil set and a second voltage command value with respect to a voltage to be applied to the second coil set, and an excess correction unit that receives a first voltage command corresponding value corresponding to the first voltage command value, and corrects a second voltage command corresponding value corresponding to the second voltage command value. When one of the value corresponding to a first voltage command and the value corresponding to a second voltage command exceeds a threshold that is set in accordance with a voltage that can be output, the excess correction unit performs excess correction processing for correcting the other of the value corresponding to a first voltage command and the one second voltage command corresponding value according to an excess amount above the limit value.

When one of the value corresponding to the first voltage command and the value corresponding to the second voltage command exceeds a threshold that is set in accordance with a voltage that can be output, the excess correction unit performs excess correction processing for correcting the other of the value corresponding to the first voltage command and that second voltage command corresponding value according to an excess amount above the limit value. In this case, when a combination of the winding set and the inverter is referred to as a system, in a case where a value of a system corresponding to the voltage command exceeds the limit set in advance with a voltage that can be output the other system is the surplus. Thus, it is possible to improve a voltage utilization rate while minimizing current ripple.

The foregoing and other objects, features and advantages of the present disclosure will become more apparent upon a consideration of the following detailed description taken in conjunction with the drawings.

Show it:

1 12 is a schematic configuration diagram illustrating a configuration of an electric power steering system according to a first embodiment of the present disclosure;

2 12 is a circuit diagram for explaining an electric configuration of a power converter according to the first embodiment of the present disclosure;

3 a block diagram for explaining a control unit according to the first embodiment of the present disclosure;

4 FIG. 10 is a diagram for explaining voltage control processing according to the first embodiment of the present disclosure; FIG.

5 FIG. 10 is a flowchart for explaining an excess correction processing according to the first embodiment of the present disclosure; FIG.

6 12 is a diagram for explaining a first zero-point voltage change value according to the first embodiment of the present disclosure;

7 12 is a diagram for explaining a first upper-lower limit limit processing value according to the first embodiment of the present disclosure;

8th FIG. 14 is a diagram for explaining a first excess amount according to the first embodiment of the present disclosure; FIG.

9 FIG. 14 is a diagram for explaining a first correction amount according to the first embodiment of the present disclosure. FIG

10 12 is a diagram for explaining a second zero-point voltage change value according to the first embodiment of the present disclosure;

11 FIG. 14 is a diagram for explaining a second upper-lower limit limit processing value according to the first embodiment of the present disclosure; FIG.

12 FIG. 10 is a diagram for explaining a second excess amount according to the first embodiment of the present disclosure; FIG.

13 FIG. 14 is a diagram for explaining a second correction amount according to the first embodiment of the present disclosure; FIG.

14A and 14B Diagrams for explaining a first excess correction value according to the first embodiment of the present disclosure;

15A and 15B Diagrams for explaining a second excess correction value according to the first embodiment of the present disclosure;

16 FIG. 10 is a circuit diagram for explaining an electric configuration of a power converter according to a second embodiment of the present disclosure; FIG.

17 FIG. 10 is a flowchart for explaining an excess correction processing according to the second embodiment of the present disclosure; FIG.

18 FIG. 10 is a flowchart for explaining the surplus correction processing according to the second embodiment of the present disclosure; FIG.

19 12 is a diagram for explaining a first zero point voltage change value according to the second embodiment of the present disclosure;

20 10 is a diagram for explaining a first upper-lower limit limit processing value according to the second embodiment of the present disclosure;

21 FIG. 10 is a diagram for explaining a first excess amount according to the second embodiment of the present disclosure; FIG.

22 12 is a diagram for explaining a first phase conversion amount according to the second embodiment of the present disclosure;

23 12 is a diagram for explaining a second zero-point voltage change value according to the second embodiment of the present disclosure;

24 FIG. 14 is a diagram for explaining a second upper-lower limit limit processing value according to the second embodiment of the present disclosure; FIG.

25 FIG. 14 is a diagram for explaining a second excess amount according to the second embodiment of the present disclosure; FIG.

26 FIG. 14 is a diagram for explaining a second phase conversion amount according to the second embodiment of the present disclosure; FIG.

27 FIG. 14 is a diagram for explaining a second correction amount according to the second embodiment of the present disclosure; FIG.

28A and 28B Diagrams for explaining a first excess correction value according to the second embodiment of the present disclosure;

29 FIG. 14 is a diagram for explaining a first correction amount according to the second embodiment of the present disclosure; FIG.

30A and 30B Diagrams for explaining a second excess correction value according to the second embodiment of the present disclosure;

31 a block diagram for explaining a control unit according to a third embodiment of the present disclosure;

32 FIG. 10 is a block diagram for explaining a current correction value calculation unit according to the third embodiment of the present disclosure; FIG. and

33 a diagram for explaining a control unit according to a fourth embodiment of the present disclosure.

Hereinafter, a power converter according to the present disclosure will be described based on the drawings. In several subsequent embodiments, substantially the same configurations are given the same reference numerals, and a repetitive description thereof will be omitted.

FIRST EMBODIMENT

A power converter according to the first embodiment of the present disclosure will be described with reference to FIG 1 to 15 described. A power converter 1 The present embodiment relates to an electric power steering apparatus 5 for assisting a driver's steering operation together with a motor 80 applied, which represents a rotary electric machine. 1 shows an overall configuration of a steering system 90 including the electric power steering device 5 , The steering system 90 includes a steering wheel 91 as a steering component or steering element, a steering column 92 , a pinion 96 , a rack 97 , a pair of wheels 98 , the electric power steering device 5 and the same.

The steering wheel 91 is with the steering column 92 connected. The steering column 92 is with a torque sensor 94 for detecting a steering torque input by the driver, who controls the steering wheel 91 served. The pinion 96 is at the top of the steering column 92 provided, and engages the rack 97 one. The wheels 98 are with the respective ends of the rack 97 connected by a hub or the like.

When the driver turns the steering wheel 91 turns, becomes the steering column 92 that with the steering wheel 91 connected, turned. The pinion 96 converts the rotational movement of the steering column 92 in a linear movement of the rack 97 and the pair of wheels 98 is at an angle corresponding to an offset amount of the rack 97 directed.

The electric power steering device 5 includes: the engine 80 for outputting the assist torque, steering the steering wheel 91 supported by the driver; the power converter 1 , which is used to drive the motor 80 is used, a reduction gear 9 , which is a power transmission element that controls the rotation of the motor 80 reduced and the rotation on the steering column 92 or the rack 97 transfers; and the same.

By the engine 80 with energy from a battery 105 (see 2 ), which is a DC power source, is supplied to the engine 80 driven to the reduction gear 9 normal or reverse. Below is a voltage of the battery 105 as a power supply voltage Vb. As in 2 is shown is the engine 8th a three-phase brushless motor including a rotor and a stator, both of which are not shown. The rotor is a cylindrical member having a permanent magnet adhered to its surface and has magnetic poles. winding sets 81 . 82 are wound on the stator. The first winding set 81 has a U1 coil 811 , a V1 coil 812 and a W1 coil 813 , The second winding set 82 has a U2 coil 821 , a V2 coil 822 and a W2 coil 823 , The U1 coil 811 and the U2 coil 821 are in positions with phases offset by 30 °. This also applies to the V phase and the W phase. Thus, in the first embodiment, the first winding set 81 and the second winding set electrically conductive, wherein the phases are offset by 30 °.

The power converter 1 includes a first inverter 10 , a second inverter 20 , Current detection units 17 . 27 , a rotation angle sensor 29 , Power supply relay 31 . 32 , a control unit 41 and the same. The first inverter 10 has six switching elements 11 to 16 and converts a current to the first winding set 81 , Hereinafter, a switching element is also referred to as a SW element. The switching elements 11 to 13 are connected to the high potential side and the switching elements 14 to 16 are connected to the low potential side. A connection point of the U-phase switching elements 11 . 14 in the pair is with one end of the U1 coil 811 connected. A connection point of the V-phase switching elements 12 . 15 in the pair is with one end of the V1 coil 812 connected. A connection point of the W-phase switching elements 13 . 16 in the pair is with one end of the W1 coil 813 connected.

The second inverter 20 has six switching elements 21 to 26 and converts a current to the second winding set 82 , The switching elements 21 to 23 are connected to the high potential side and the switching elements 24 to 26 are connected to the low potential side. A connection point of the U-phase switching elements 21 . 24 in the pair is with one end of the U2 coil 821 connected. A connection point of the V-phase switching elements 22 . 25 in the pair is with one end of the V2 coil 822 connected. A connection point of the W-phase switching elements 23 . 26 in the pair is with one end of the W2 coil 823 connected. Each of the switching elements 11 to 16 . 21 to 26 of the present embodiment is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) but can also be an IGBT ( Insulated gate bipolar transistor), a thyristor or the like. In the present embodiment, the switching elements correspond 11 to 13 . 21 to 23 the high potential side switching element and the switching elements 14 to 16 . 24 to 26 correspond to the low potential side switching element.

The first current detection unit 17 has current sensing elements 171 . 172 . 173 , The U1 current sensing element 171 is on a connection line between the connection point of the U-phase switching elements 11 . 14 and the U1 coil 811 provided and detects a current in the U1 coil 811 , The V1 current detection element 172 is on a connection line between the connection point of the V-phase switching elements 12 . 15 and the V1 coil 812 provided and detects a current in the V1 coil 812 , The W1 current sensing element 173 is on a connection line between the connection point of the W-phase switching elements 13 . 16 and the W1 coil 813 provided and detects a current in the W1 coil 813 , A detection value of the current in the U1 coil 811 is referred to as a U1 current sense value Iu1. A detection value of the current in the V1 coil 812 is referred to as a V1 current detection value Iv1. A detection value of the current flowing in the W1 coil 813 is referred to as a W1 current detection value Iw1.

The second current detection unit 27 has current sensing elements 271 . 272 . 273 , The U2 current sensing element 271 is on a connection line between the connection point of the U-phase switching elements 21 . 24 and the U2 coil 821 provided and detects a current in the U2 coil 821 , The V2 current detection element 272 is on a connection line between the connection point of the V-phase switching elements 22 . 25 and the V2 coil 822 provided and detects a current in the V2 coil 822 , The W2 current sensing element 273 is on a connection line between the connection point of the W-phase switching elements 23 . 26 and the W2 coil 823 provided and detects a current in the W2 coil 823 , A detection value of the current in the U2 coil 821 is referred to as a U2 current sense value Iu2. A detection value of the current in the V2 coil 822 is referred to as a V2 current detection value Iv2. A detection value of the current in the W2 coil 823 is referred to as a W2 current detection value Iw2. The current detection elements 171 to 173 . 271 to 273 In the present embodiment, Hall elements. The rotation angle sensor 29 detects a rotation angle of the motor 80 , An electrical angle θ of the motor 80 by the rotation angle sensor 29 is detected, is sent to the control unit 41 output.

The first power supply relay 31 can supply power from the battery 105 to the first inverter 10 interrupt. The second power supply relay 32 can supply power from the battery 105 to the second inverter 20 interrupt. In the present embodiment, each of the power supply relays 31 . 32 a MOSFET similar to the switching element 11 and the like, but may be an IGBT, a mechanical relay or the like. Further, in the case where the MOSFETs for the power supply relays 31 . 32 is preferred, to provide a reverse voltage protection relay, not shown, in series with the power supply relays 31 . 32 connected to reverse a direction of a parasitic diode, thus, when the battery 105 is erroneously connected in a reverse direction, a current in the reverse direction is prevented from flowing through the parasitic diode.

The first capacitor 33 is in parallel with the battery 105 and the first inverter 10 connected. The second capacitor 34 is in parallel with the battery 105 and the second inverter 20 connected. The capacitors 33 . 34 store charges to power the inverter 10 . 20 and suppress a noise component such as a peak current.

In the present embodiment, the first winding set 81 , the first inverter 10 regarding the line control for the first winding set 81 , the first current detection unit 17 , the first power supply relay 31 and the first capacitor 33 as a first system 101 used. Furthermore, the second winding set 82 , the second inverter 20 regarding line control for the second winding set 82 , the second current detection unit 27 , the second power supply relay 32 and the second capacitor 34 as a second system 102 used.

The control unit 41 controls the entirety of the power converter 1 and includes a microcomputer or the like that performs various calculations. Any processing by the control unit 41 may be a software processing executed by executing a pre-stored program in a CPU, or may be a hardware processing executed using a dedicated electronic circuit. The control unit 41 generates a control signal for controlling the on / off of each of the switching elements 11 to 16 . 21 to 26 on the basis of the steering torque, that of the torque sensor 94 (see 1 ), the electrical angle θ generated by the rotation angle sensor 29 is obtained, and the like. The generated control signal is applied to gates of the switching elements 11 to 16 . 21 to 26 by a drive circuit 35 output.

As in 3 is shown, the control unit has 41 a three-phase to two-phase conversion unit 51 , a control device 52 , a voltage limiting unit 53 , a two-phase-to-three-phase conversion unit 54 a modulation calculation unit 55 and the same.

The three-phase-to-two-phase conversion unit 51 has a three-phase-to-two-phase conversion unit 511 for a first system and a three-phase-to-two-phase conversion unit 512 for a second system. The three-phase-to-two-phase conversion unit 511 for a first system, dq conversion results in the U1 current sense value Iu1, the V1 current sense value Iv1, and the W1 current sense value Iw1 received from the first current sense unit 17 obtained on the basis of the electrical angle θ and calculates a first d-axis current detection value Id1 and a first q-axis current detection value Iq1. The three-phase-to-two-phase conversion unit 512 for a second system, dq conversion results in U2 current sense value Iu2, V2 current sense value Iv2, and W2 current sense value Iw2 coming from the second current sense unit 27 are obtained on the basis of the electrical angle θ and calculate a second d-axis current detection value Id2 and a second q-axis current detection value Iq2.

Based on a d-axis current command value Id * and a q-axis current command value Iq * in accordance with a torque command value, the d-axis current detection values Id1, Id2 and the q-axis current detection values Iq1, Iq2, the controller calculates 42 a first pre-limit d-axis voltage command value Vd1 * _a, a first pre-limit q-axis voltage command value Vq1 * a, a second pre-limit d-axis voltage command value Vd2 * _a, and a second pre-limit q-axis voltage command value Vq2 * _a by PI calculation or the like.

The voltage limiting unit 53 has a first voltage limiting unit 531 and a second voltage limiting unit 532 and limits a voltage using an amplitude of a dq axis voltage. The first voltage limiting unit 531 delimits the first pre-limit d-axis voltage command value Vb1 * _a and the first pre-limit q-axis voltage command value Vq1 * _a, and calculates a first d-axis voltage command value Vd1 * and a first q-axis voltage command value Vq1 *. The second voltage limiting unit 532 delimits the second pre-limit d-axis voltage command value Vd2 * _a and the second pre-limit q-axis voltage command value Vq2 * _a, and calculates a second d-axis voltage command value Vd2 * and a second q-axis voltage command value Vq2 *.

A voltage limiting processing in the first voltage limiting unit 531 will be referred to below with reference to 4 described. Processing in the second voltage limiting unit 532 is similar to the processing in the first voltage limiting unit 531 and thus a description thereof will be omitted. A voltage vector having a d-axis component that is the first pre-limit d-axis voltage command value Vd1 * _a and having a q-axis component that is the first pre-limit q-axis voltage command value Vq1 * _a is referred to as a first pre-limit voltage vector A1_a. When the magnitude of the first biasing voltage vector A1_a is not greater than an amplitude threshold V_lim, the first biasing d-axis voltage command value Vd1 * _a is set to the first d-axis voltage command value Vd1 *, and the first biasing q-axis voltage command value Vq1 * _a is set to the first q-axis voltage command value Vq1 *. Further, as in 4 That is, when the magnitude of the first bias voltage vector A1_a is larger than the amplitude threshold V_lim, the first bias d-axis voltage command value Vd1 * _a is set to the first d-axis voltage command value Vd1 *, and the q-axis component becomes so limits the voltage vector A1 to reach the amplitude threshold V_lim after being limited, and the obtained value is set to the first q-axis voltage command value Vq1 *.

The amplitude limitation value V_lim at dq axis coordinates is calculated by formula (1). For example, when the power supply voltage Vb is set to 12 V and a duty cycle maximum value Dmax is set to 103.5%, the amplitude threshold V_lim is about 8.87 V. In the case where a later-described excess correction processing is not performed, the duty ratio is the maximum value Dmax 100% and the amplitude limit V_lim is about 8.49 V. V_lim = Vb × (√2) × Dmax / 100 (1)

The duty cycle maximum value Dmax is set beforehand by a calculation that is executed off-line, so that the value becomes a value that can be output when executing the excess-correction processing described later. In the present embodiment, the current detection elements become 171 to 173 . 271 to 273 used as the Hall elements, and the currents in the winding sets 81 . 82 are detected directly, and the duty cycle is up to 100% usable. When the current is detected using a shunt resistor as in the later-described second embodiment, the sampling is usable only up to a predetermined maximum duty ratio (for example, 93%). In this case, the duty ratio maximum value Dmax is a value obtained by multiplying the predetermined maximum duty ratio by 103.5%, and the amplitude limit value V_lim is also a different value.

The two-phase-to-three-phase conversion unit 54 has a two-phase-to-three-phase conversion unit 541 for a first system and a two-phase-to-three-phase conversion unit 542 for a second system. The two-phase-to-three-phase conversion unit 541 For a first system, reverse dq conversion for the first d-axis voltage command value Vd1 * and the first q-axis voltage command value Vq1 * is performed based on the electrical angle θ and calculates a U1 voltage detection value Vu1 *, a V1 voltage detection value Vv1 * and a W1 voltage detection value Vw1 *. The two-phase-to-three-phase conversion unit 542 for a second system, performs reverse dq conversion for the second d-axis voltage command value Vd2 * and the second q-axis voltage command value Vq2 * based on the electrical angle 0 and calculates a U2 voltage command value Vu2 *, a V2 voltage command value Vv2 * and a W2 voltage command value Vw2 *.

Hereinafter, the U1 voltage command value Vu1 *, the V1 voltage command value Vv1 * and the W1 voltage command value Vw1 * are appropriately referred to as (first) voltage command values Vu1 *, Vv1 *, Vw1 *. The U2 voltage command value Vu2 *, the V2 voltage ^{command value Vv2 *,} and the W2 voltage command value Vw2 * are appropriately referred to as (second) voltage command values Vu2 *, Vv2 *, Vw2 *.

The modulation calculation unit 55 calculates duty ratio command values Du1, Dv1, Dw1, Du2, Dv2, Dw2 based on voltage command values Vu1 *, Vv1 *, Vw1 *, Vu2 *, Vv2 *, Vw2 *. The duty command values Du1, Dv1, Dw1, Du2, Dv2, Dw2 are applied to the inverters 10 . 20 through the drive circuit 35 newly issued (in 3 not shown).

The modulation calculation unit 55 has a duty ratio conversion unit 551 and an excess correction unit 552 , The duty cycle conversion unit 551 performs duty cycle conversion on the first voltage command values Vu1 *, Vv1 *, Vw1 * and calculates first duty cycle conversion values Du1_c, Dv1_c, Dw1_c. Furthermore, the duty ratio conversion unit performs 551 Duty cycle conversion for the second voltage command values Vu2 *, Vv2 *, Vw2 * and calculates second duty cycle conversion values Du2_c, Dv2_c, Dw2_c. The excess correction unit 552 executes an excess correction processing in which the excess exceeds a threshold of the voltage supplied by the system 101 can be issued on the side of the second system 102 is compensated, and the excess is above a threshold voltage, that of the second system 102 can be issued on the side of the first system 101 compensated. This processing improves the voltage utilization rate.

The excess correction processing of the present embodiment will be described with reference to FIG 5 illustrated flowchart described. The excess correction processing of the present embodiment is performed by the excess correction unit 552 executed. At step S101, the excess correction unit determines 552 a maximum duty ratio MaxD1 which is the largest one of the first duty ratio conversion values Du1_c, Dv1_c, Dw1_c obtained by performing the duty conversion of the first voltage command values Vu1 *, Vv1 *, Vw1 *. Subsequently, step S101 is omitted and written as S101. This also applies to the other steps.

At S102, the excess correction unit determines 552 a minimum duty cycle MinD1 that is the smallest of the first duty cycle conversion values Du1_c, Dv1_c, Dw1_c. At S103, the excess correction unit determines 552 an intermediate duty MidD1. The intermediate duty ratio MidD1 is expressed by Formula (2). In formula (2), "150" represents that when an average value of each phase duty ratio is 50%, a sum of the three phase duty ratios 150 is. This also applies to formula (6). MidD1 = 150 - MaxD1 - MinD1 (2)

At S104, the excess correction unit calculates 552 the first zero point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11. The first zero point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11 are calculated by formulas (3-1), (3-2) and (3-3), respectively. In this calculation processing, the zero-point voltage is changed by making the maximum and minimum duty ratios equal. Even if the zero point voltage is changed, this affects the driving of the motor 80 not, unless a line voltage is changed. The first zero point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11 are as in 6 shown. In 6 is a U-phase value indicated by a solid line, a value of the V phase is indicated by a broken line, and a value of the W phase is indicated by a broken line. This also applies to the other drawings described later. Du1_ca11 = Du1_c - MidD1 × 0.5 + 50 (3-1) Dv1_ca11 = Dv1_c - MidD1 × 0.5 + 50 (3-2) Dw1_ca11 = Dw1_c - MidD1 × 0.5 + 50 (3-3)

At S105, the excess correction unit limits 552 the first zero-point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11 so as to be within the range between a predetermined lower limit value RL1 and a predetermined upper limit value RH1, and calculate first upper-lower limit limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12. When the first zero-point voltage change value Du1_ca11 is not smaller than the lower limit value RL1 and not larger than the upper limit value RH1, the first zero-point voltage change value Du1_ca11 is used as the upper-lower limit limit processing value Du1_ca12. When the first zero voltage change value Du1_ca11 is smaller than the lower limit value RL1, the lower limit value RL1 is set to the first upper lower limit limit processing values Du1_ca12. When the first zero-point voltage change value Du1_ca11 is greater than the upper limit value RH1, the upper limit value RH1 is set to the first upper-lower limit limit processing values Du1_ca12. This also applies to the first upper-lower limit limit processing values Dv1_ca12, Dw1_ca12.

The first upper-lower bound limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12 are as in 7 shown. 7 is an example where the lower limit value RL1 is 0% and the upper limit value RH1 is 100%. This also applies to 11 , as described later. The lower limit value RL1 and the upper limit value RH1 can be set arbitrarily. For example, in terms of the dead time, the on-time required for current detection, and the like, the lower limit value RL1 may be set to 4% and the upper limit value RH1 to 93%.

At S106, the excess correction unit calculates 552 the first excess amounts Du1_h10, Dv1_h10, Dw1_h10. The first excess amounts Du1_h10, Dv1_h10, Dw1_h10 are amounts by which the first zero-point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11 exceed the lower limit value RL1 or the upper limit value RH1 and are represented by formulas (4-1), (4-2) and (4-3). Further, the first surplus amounts Du1_h10, Dv1_h10, Dw1_h10 are as in 8th shown. 8th shows a modulation ratio of 0% in enlarged form. This also applies to 9 . 12 . 13 and the same. Du1_h10 = Du1_ca11 - Du1_ca12 (4-1) Dv1_h10 = Dv1_ca11 - Dv1_ca12 (4-2) Dw1_h10 = Dw1_ca11 - Du1_ca12 (4-3)

At S107, the excess correction unit calculates 552 first correction amounts Du1_h11, Dv1_h11, Dw1_h11, which are values obtained by converting the first excess amounts Du1_h10, Dv1_h10, Dw1_h10 into the coordinate system of the second system 102 be obtained using a rotation matrix. The first correction amounts Du1_h11, Dv1_h11, Dw1_h11 can be obtained by executing the dq conversion of the first excess amounts Du1_h10, Dv1_h10, Dw1_h10 in the coordinate system of the first system 101 and performing the reverse dq conversion of the dq conversion values in the coordinate system of the second system 102 be calculated. The first correction amounts du1_h11, dv1_h11, dw1_h11 are expressed by the formulas (5-1), (5-2) and (5-3), respectively. Du1_h11 = (Du1_h10 - Dv1_h10) / (√3) (5-1) Dv1_h11 = (Dv1_h10 - Dw1_h10) / (√3) (5-2) Dw1_h11 = (Dw1_h10 - Du1_h10) / (√3) (5-3)

The first correction amounts Du1_h11, Dv1_h11, Dw1_h11 are as in 9 shown. It should be noted that a position indicated by "u, v" means that Du1_h11 and Dv1_h11 are the same value and lines are superimposed thereon or lines are superimposed thereon. Similarly, "u, w" means that Du1_h11 and Dw1_h11 have the same value and "v, w" means that Dv1_h11 and Dw1_h11 have the same value. This also applies to 13 ,

At S108, the excess correction unit determines 552 a maximum duty ratio MaxD2 which is the largest value of the second duty ratio conversion values Du2_c, Dv2_c, Dw2_c obtained by performing the duty conversion of the second voltage command values Vu2 *, Vv2 *, Vw2 *. At S109, the excess correction unit determines 552 a minimum duty cycle MinD2, which is the minimum value of the second duty cycle conversion values Du2_c, Dv2_c, Dw2_c. At S110, the excess correction unit determines 552 an intermediate duty MidD2. The intermediate duty MidD2 is expressed by formula (6). MidD2 = 150 - MaxD2 - MinD2 (6)

Hereinafter, a description of the processing of S111 to S114 is appropriately omitted because it is substantially similar to the processing of S104 to S107. At S111, the excess correction unit calculates 552 second zero point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11. The second zero point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11 are calculated by formulas (7-1), (7-2) and (7-3), respectively. The second zero point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11 are as in 10 shown. Du2_ca11 = Du2_c - MidD2 × 0.5 + 50 (7-1) Dv2_ca11 = Dv2_c - MidD2 × 0.5 + 50 (7-2) Dw2_ca11 = Dw2_c - MidD2 × 0.5 + 50 (7-3)

At S112, the excess correction unit limits 552 the second zero-point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11 to be within the range between the predetermined lower limit value RL1 and the predetermined upper limit value RH1, and calculates second upper-lower limit limit processing values Du2_ca12, Dv2_ca12, Dw2_ca12. The second upper-lower limit limit processing values Du2_ca12, Dv2_ca12, Dw2_ca12 are as in 11 shown.

At S113, the excess correction unit calculates 552 second surplus Du2_h10, Dv2_h10, Dw2_h10. The second excess amounts Du2_h10, Dv2_h10, Dw2_h10 are amounts by which the second zero-point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11 exceed the lower limit value RL1 or the upper limit value RH1, and are represented by the formulas (8-1), (8-2 ), (8-3). Further, the second excess amounts Du2_h10, Dv2_h10, Dw2_h10 are as in 12 shown. Du2_h10 = Du2_ca11 - Du2_ca12 (8-1) Dv2_h10 = Dv2_ca11 - Dv2_ca12 (8-2) Dw2_h10 = Dw2_ca11 - Du2_ca12 (8-3)

At S114, the excess correction unit calculates 552 second correction amounts Du2_h11, Dv2_h11, Dw2_h11, which are values obtained by converting the second excess amounts Du2_h10, Dv2_h10, Dw2_h10 into the coordinate system of the first system 101 be obtained using a rotation matrix. The second correction amounts Du2_h11, Dv2_h11, Dw2_h11 can be obtained by executing the dq conversion of the second excess amounts Du2_h10, Dv2_h10, Dw2_h10 in the coordinate system of the second system 102 and performing the reverse dq conversion of the dq conversion values in the coordinate system of the first system 101 be calculated. The second correction amounts Du2_h11, Dv2_h11, Dw2_h11 are expressed by formulas (9-1), (9-2) and (9-3), respectively. Further, the second correction amounts Du2_h11, Dv2_h11, Dw2_h11 are as in 13 shown. Du2_h11 = (Du2_h10 - Dw2_h10) / (√3) (9-1) Dv2_h11 = (Dv2_h10 - Du2_h10) / (√3) (9-2) Dw2_h11 = (Dw2_h10 - Dv2_h10) / (√3) (9-3)

The processing from S101 to S107 and the processing from S108 to S114 may be performed in the order of processing from S108 to S114 and the processing from S101 to S107, or may be performed simultaneously in parallel.

At S115, the first upper-lower limit limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12 are corrected by the second correction amounts Du2_h11, Dv2_h11, Dw2_h11 to give first excess correction values Du1_ca13, Dv1_ca13, Dw1_ca13. The first excess correction values Du1_ca13, Dv1_ca13, Dw1_ca13 are expressed by formulas (10-1), (10-2) and (10-3), respectively. Du1_ca13 = Du1_ca12 + Du2_h11 (10-1) Dv1_ca13 = Dv1_ca12 + Dv2_h11 (10-2) Dw1_ca13 = Dw1_ca12 + Dw2_h11 (10-3)

At S116, the second upper-lower limit limit processing values Du2_ca12, Dv2_ca12, Dw2_ca12 are corrected by the first correction amounts and Du1_h11, Dv1_h11, Dw1_h11 to give second excess correction values Du2_ca13, Dv2_ca13, Dw2_ca13. The second excess correction values Du2_ca13, Dv2_ca13, Dw2_ca13 are expressed by formulas (11-1), (11-2) and (11-3), respectively. Du2_ca13 = Du2_ca12 + Du1_h11 (11-1) Dv2_ca13 = Dv2_ca12 + Dv1_h11 (11-2) Dw2_ca13 = Dw2_ca12 + Dw1_h11 (11-3)

In the present embodiment, the surplus correction values Du1_ca13, Dv1_ca13, Dw1_ca13, Du2_ca13, Dv2_ca13, Dw2_ca13 are applied to the drive circuit 35 is output as the duty command values Du1, Dv1, Dw1, Du2, Dv2, Dw2.

14A and 14B show the first excess correction values Du1_ca13, Dv1_ca13, Dw1_ca13 and 15A and 15B show the second excess correction values Du2_ca13, Dv2_ca13, Dw2_ca13. 14A the entirety of the first excess correction values Du1_ca13, Dv1_ca13, Dw1_ca13 and 14B shows a modulation ratio of 0% in enlarged form. In 14 thin lines indicate the first upper-lower limit limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12 before being corrected by the second correction amounts Du2_h11, Dv2_h11, Dw2_h11. This also applies to 15A and 15B ,

In the present embodiment, at S104 and S111, the duty ratio conversion values Du1_c, Dv1_c, Dw1_c, Du2_c, Dv2_c, Dw2_c are modulated to change the zero-point voltage with the zero-point voltage obtained by the modulation with the pre-change voltage the same is compared, whereby improvement of the voltage utilization rate is achieved. Further, as in 14A and 14B 1, the first surplus correction values Du1_ca13, Dv1_ca13, Dw1_ca13 are values obtained by correcting the first upper-lower limit limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12 by the second correction amounts Du2_h11, Dv2_h11, Dw2_h11. The second correction amounts Du2_h11, Dv2_h11, Dw2_h11 are values that are in the second system 102 are calculated based on the second excess amounts Du2_h10, Dv2_h10, Dw2_h10, which are the excess over the lower limit value RL1 or the upper limit value RH1.

Similar, as in 15A and 15B 2, the second surplus correction values Du2_ca13, Dv2_ca13, Dw2_ca13 are values obtained by correcting the second upper-lower limit limit processing values Du2_ca12, Dv2_ca12, Dw2_ca12 by the first correction amounts Du1_h11, Dv1_h11, Dw1_h11. The first correction amounts Du1_h11, Dv1_h11, Dw1_h11 are values that are in the first system 101 are calculated based on the first excess amounts Du1_h10, Dv1_h10, Dw1_h10, which are the excess over the lower limit value RL1 or the upper limit value RH1. Thus, it is possible to improve the voltage utilization rate by using a cancel winding without increasing the torque ripple. Furthermore, the erase winding of the first winding set 81 the second winding set and the erasing winding of the second winding set 82 is the first winding set 81 ,

In the present embodiment, a voltage phase is not used in the calculation of the correction amounts Du1_h11, Dv1_h11, Dw1_h11, Du2_h11, Dv2_h11, Dw2_h11, thereby eliminating the need for calculating an arctangent. Thus, it is possible to reduce a calculation load as compared with the case by performing correction using a value calculated using a voltage phase such as a fifth-order harmonic, a seventh-order harmonic, or the like. Further, since the amount corresponding to the excess amount is corrected above the lower limit or the upper limit on the other system side, it is possible to minimize the current ripple. Further, unlike the case where the correction is performed on the basis of the fifth order harmonic or the seventh order harmonic, the dq conversion increases or decreases duty ratios in the first system 101 and the second system 102 by the same amount, thereby avoiding occurrence of an error in the processing for calculating the correction amount.

As described in detail above, the power converter converts 1 In the present embodiment, power of the three-phase motor 80 who made the first winding set 81 and the second winding set 82 has and the first inverter 10 , the second inverter 20 and the control unit 41 includes. The first inverter 10 is according to the first winding set 81 intended. The second inverter 20 is according to the second winding set 82 intended. The control unit 41 has the controller 52 , the voltage limiting unit 53 , the two-phase-to-three-phase conversion unit 54 , the duty ratio conversion unit 551 and the excess correction unit 552 , The control device 52 , the voltage limiting unit 53 and the two-phase-to-three-phase conversion unit 54 calculate the first voltage command values Vu1 *, Vv1 *, Vw1 * with respect to a voltage corresponding to the first winding set 81 is to be applied, and the second voltage command values Vu2 *, Vv2 *, Vw2 * with respect to a voltage corresponding to the second winding set 82 is to create.

The excess correction unit 552 corrects the first duty ratio conversion values Du1_c, Dv1_c, Dw1_c and the second duty ratio conversion values Du2_c, Dv2_c, Dw2_c, which are values according to the first voltage command values Vu1 *, Vv1 *, Vw1 *. When one of the value corresponding to the first voltage command and the value corresponding to the second voltage command exceeds the lower limit value RL1 or the upper limit value RH1 set according to a voltage that can be output, the excess correction unit corrects 552 the other of the value corresponding to the first voltage command and the value corresponding to the second voltage command according to the excess amounts Du1_h10, Dv1_h10, Dw1_h10, Du2_h10, Dv2_h10, Dw2_ h10 above the lower limit RL1 or the upper limit RH1.

Specifically, when the first zero-point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11 exceed the lower limit value RL1 or the upper limit value RH1 set according to a voltage that can be output, the excess correction unit corrects 552 the second upper-lower limit limit processing values Du2_ca12, Dv2_ca12, Dw2_ca12 according to the first excess amounts Du1_h10, Dv1_h10, Dw1_h10. Further, when the second zero-point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11 exceed the lower limit value RL1 or the upper limit value RH1 set according to a voltage that can be output, the excess correction unit corrects 552 the first upper-lower limit limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12 according to the second excess amounts Du2_h10, Dv2_h10, Dw2_h10. In the present embodiment, when the value of one system corresponding to the voltage command exceeds the lower limit value RL1 or the upper limit value RH1 set according to a voltage that can be output, the excess in the other system is compensated. Thus, it is possible to improve the voltage improvement rate while minimizing current ripple.

The excess correction unit 552 executes the surplus correction processing for the zero point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11, Du2_ca11, Dv2_ca11, Dw2_ca11, which are obtained by changing the zero point voltage. Changing the zero point voltage can lead to further improvement of the voltage utilization rate.

The power converter 1 further includes the current detection units 17 . 27 for detecting a current of each phase of the first winding set 81 and the second winding set 82 may happen. Further, the first voltage command values Vu1 *, Vv1 *, Vw1 * and the second voltage command values Vu2 *, Vv2 *, Vw2 * are calculated on the basis of the current detection values Iu1, Iv1, Iw1, Iu2, Iv2, Iw2 generated by the current detection units 17 . 27 be recorded. This allows adequate calculation of the voltage command values Vu1 *, Vv1 *, Vw1 *, Vu2 *, Vv2 *, Vw2 * by current feedback control and current regulation, respectively.

The first voltage command values Vu1 *, Vv1 *, Vw1 * and the second voltage command values Vu2 *, Vv2 *, Vw2 * are values limited by the predetermined amplitude limitation value V_lim to be values calculated according to the excess amounts Du1_h10, Dv1_h10, Dw1_h10, Du2_h10, Dv2_h10, Dw2_h10 can be corrected. Thus, it is possible to adequately perform the surplus correction processing.

The motor 80 becomes for the electric power steering device 5 used and supported by the output torque steering the steering wheel 91 the driver. In the power converter 1 According to the present embodiment, since the torque ripple is reduced, sound and vibration generated in the electric power steering apparatus 5 can be reduced.

In the present embodiment, the control means correspond 52 , the voltage limiting unit 53 and the two-phase-to-three-phase conversion unit 54 the command calculation unit and the lower limit value RL1 and the upper limit value RH2 correspond to the limit value. Further, in the present embodiment, the first zero point voltage change values Du1_ca11, Dv1_ca11, Dw1_ca11 correspond to the value corresponding to a first voltage command and the second zero point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11 correspond to the value corresponding to a second voltage command. Further, it is assumed that correcting the first upper-lower limit limit processing values Du1_ca12, Dv1_ca12, Dw1_ca12 which limit the upper and lower limits of the first zero voltage variation values Du1_ca11, Dv1_ca11, Dw1_ca11, and correct the second upper lower limit limit processing values Du2_ca12, Dv2_ca12, Dw2_ca12, which limit the upper and lower limits of the second zero-point voltage change values Du2_ca11, Dv2_ca11, Dw2_ca11, are included in the concept of correcting the other of the value corresponding to a first voltage command and the value corresponding to a second voltage command.

SECOND EMBODIMENT

16 to 30 show a second embodiment of the present disclosure. As in 16 is shown, a power converter is different 2 the present embodiment of the power converter 1 the first embodiment in that current detection units 18 . 28 instead of the current detection units 17 . 27 are provided. The first current detection unit 18 has current sensing elements 181 . 182 . 183 , The U1 current sensing element 181 is between the U-phase switching element 14 and the ground and detects a current in the U1 coil 811 , The V1 current detection element 182 is between the V-phase switching element 15 and the ground and detects a current in the V1 coil 812 , The W1 current sensing element 183 is between the W-phase switching element 16 and the ground and detects a current in the W1 coil 813 ,

The second current detection unit 28 has current sensing elements 281 . 282 . 283 , The U2 current sensing element 281 is between the U-phase switching element 24 and the ground is provided and detects a current in the U2 coil 821 , The V2 current detection element 282 is between the V-phase switching element 25 and the ground provided and detects a current in the V2 coil 822 , The W2 current sensing element 283 is between the W-phase switching element 26 and the ground and detects a current in the W2 coil 823 , The current detection elements 181 to 183 . 281 to 283 The present embodiments are shunt resistors.

With the between the switching elements 14 to 16 and the ground provided current detection elements 181 to 183 is when the switching elements 14 to 16 are off, a current is not allowed in the current sensing elements 181 to 183 to flow and thus the current can not be detected. This makes it necessary to carry out the current detection in a state in which all phases or two phases of the switching elements 14 to 16 are one. The current detection is carried out in the state in which the two phases of the switching elements 14 to 16 1, a current in the phase that is off can be calculated using current sense values of the two phases that are on. This also applies to the current detection in the second current detection unit 28 ,

In the present embodiment, assuming that the power supply voltage Vb is 12V and the duty-cycle maximum value Dmax is 100.2%, the amplitude-limiting value V_lim at dq-axis coordinates is voltage-limited in the voltage-limiting unit 53 about 8.5 V (compare formula (1-2)). The duty cycle maximum value Dmax is a value that is set in advance off-line or computer-independent, similar to the first embodiment. In the case where the surplus correction processing is not performed, if on periods of the switching elements 14 to 16 . 24 to 26 , which are required for the current detection, the amplitude limiting value V_lim is about 8.32 V, since the maximum value of the line voltage or line voltage at duty cycle conversion is 98%.

Further, the second embodiment is different from the first embodiment in the excess correction processing performed by the excess correction unit 552 is performed. Thereafter, a modulation method for carrying out modulation such that a duty cycle of the smallest phase has a predetermined lower limit is called a flat bed modulation, and a modulation method for carrying out a modulation such that a duty cycle of the largest phase has a predetermined upper limit is called a flat peak modulation designated. The excess correction processing of the present embodiment will be described with reference to FIG 17 and 18 illustrated flowcharts described. Processing from S201 to S203 in 17 is similar to the processing of S101 to S103 in FIG 5 ,

At S204, the excess correction unit compares 552 a lower all-phase-on-duty ratio PD1 having a lower two-phase-on-duty ratio PD2, respectively, wherein the duty ratio PD1 corresponding to an all-phase-on period P1, which is a period in which all the phases the switching elements 14 to 16 at the time of the flat bed modulation, the duty ratio PD2 corresponding to a two-phase on period P2 which is one period in which two phases of the switching elements 14 to 16 are turned on. The lower all-phase-on-duty PD1 and the lower two-phase-on duty PD2 are expressed by formulas (12-1) and (12-2), respectively. PD1 = 100 - (MaxD1 - MinD1) (12-1) PD2 = MaxD1 - MidD1 (12-2)

When the lower all-phase-on-duty PD1 is compared with the lower two-phase-on-duty PD2, and the lower all-on-phase duty PD1 is not smaller than the lower two-phase on-duty PD2 , the all-phase-on period P1 is not shorter than the two-phase-on period P2. Thus, it is assumed that the current is detected when all the phases of the switching elements 14 to 16 are what the flatbed modulation represents. Further, when the lower two-phase on-duty ratio PD2 is greater than the lower all-phase-on duty ratio PD1, the two-phase on-period P2 is longer than the all-phase-on period P1. Thus, it is assumed that the current is detected when two phases of the switching elements 14 to 16 are what the flat-tip modulation represents.

If it is determined that the lower all-phase duty ratio PD1 is not smaller than the lower two-phase duty ratio PD2 (S204: NO), the processing proceeds to S208. If it is determined that the lower two-phase duty ratio PD2 is larger than the lower all-phase duty ratio PD1 (S204: YES), the processing proceeds to S205.

At S205 takes the excess correction unit 552 a stationary phase in the first system 101 as the maximum phase. When the lower two-phase on-duty ratio PD2 is greater than the lower all-phase-on duty ratio PD1, the zero point voltage is changed by the flat peak modulation.

At S206, the excess correction unit calculates first zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 at the time of the flat peak modulation. The zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 at the time of the flat peak modulation are expressed by formulas (13-1), (13-2) and (13-3), respectively. Du1_ca21 = Du1_c - MaxD1 + RH2 (13-1) Dv1_ca21 = Dv1_c - MaxD1 + RH2 (13-2) Dw1_ca21 = Dw1_c - MaxD1 + RH2 (13-3)

At S207, the excess correction unit limits 552 the first zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 at the time of the flat peak modulation to be within the range between a predetermined lower limit value RL2 and a predetermined upper limit value RH2, and calculates first upper limit lower limit processing values Du1_ca22, Dv1_ca22, Dw1_ca22 at the time of flat peak modulation , A detail of the upper-lower limit limitation processing is similar to that of S105.

The lower limit value RL2 and the upper limit value RH2 can be set arbitrarily. In the present embodiment, the lower limit value RL2 is set to 2%, taking the dead time into consideration. Further, the upper limit RH2 is set to 100% because it is assumed that the current detection is performed at the time when the two phases of the switching elements 14 to 16 are one.

At S208, to which the processing continues when it is determined that the lower all-phase duty ratio PD1 is not smaller than the lower two-phase duty factor PD2 (S204: NO), the excess correction unit uses 552 the stationary phase in the first system 101 as the minimal phase. When the lower all-phase-on-duty PD1 is larger than the lower two-phase-on duty PD2, the zero-point voltage is changed by the flat-bed modulation.

At S209, the excess correction unit calculates 552 the first zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 at the time of the flatbed modulation. The first zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 at the time of the flat bed modulation are expressed by formulas (14-1), (14-2) and (14-3), respectively. The first zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 calculated at S206 or S209 are in 19 shown. Du1_ca21 = Du1_c - MinD1 + RL3 (14-1) Dv1_ca21 = Dv1_c - MinD1 + RL3 (14-2) Dw1_ca21 = Dw1_c - MinD1 + RL3 (14-3)

At S210, the excess correction unit limits 552 the first zero point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 at the time of the flat bed modulation to be within the range between a predetermined lower limit value RL3 and a predetermined upper limit value RH3, and calculates upper upper limit lower limit processing values Du1_ca22, Dv1_ca22, Dw1_ca22 at the time of Flatbed modulation.

The lower limit RL3 and the upper limit RH3 are arbitrarily definable. In the present embodiment, the lower limit value RL3 is set to 0%. Further, since the current detection is performed at the time when all the phases of the switching elements 14 to 16 are one, the upper limit RH3 is set to 93% in terms of the time required to turn on all the phases of the switching elements 14 to 16 and converging the clutter of currents in the current sensing elements 141 to 143 and the like is required. The first upper-lower limit limit processing values Du1_ca22, Dv1_ca22, Dw1_ca22 calculated at S207 or S210 are in 20 shown.

At S211, with which processing proceeds from S207, the excess correction unit calculates 552 first Excess amounts Du1_h20, Dv1_h20, Dw1_h20. The first excess amounts Du1_h20, Dv1_h20, Dw1_h20 are amounts by which the first zero-point voltage change values Du1_ca21, Dv1_ca21, Dw1_ca21 exceed the lower limit value RL2 or the upper limit value RH2 and are represented by formulas (15-1), (15-2) and (15-3). Du1_h20 = Du1_ca21 - Du1_ca22 (15-1) Dv1_h20 = Dv1_ca21 - Dv1_ca22 (15-2) Dw1_h20 = Dw1_ca21 - Du1_ca22 (15-3)

At S212, the excess correction unit calculates 552 the first phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21, which are values obtained by converting the first excess amounts Du1_h20, Dv1_h20, Dw1_h20 into the coordinate system of the second system 102 be obtained using a rotation matrix. The first phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21 can be obtained by executing the dq conversion for the first and the first excess amounts Du1_h20, Dv1_h20, Dw1_h20 in the coordinate system of the first system, respectively 101 and performing the reverse dq conversion of the dq conversion values in the coordinate system of the second system. The first phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21 are expressed by formulas (16-1), (16-2) and (16-3), respectively. Du1_h21 = (Du1_h20 - Dv1_h20) / (√3) (16-1) Dv1_h21 = (Dv1_h20 - Dw1_h20) / (√3) (16-2) Dw1_h21 = (Dw1_h20 - Du1_h20) / (√3) (16-3)

The first excess amounts Du1_h20, Dv1_h20, Dw1_h20 are 0 at the time of the flatbed modulation in calculation. As a result, the calculation of the first excess amounts Du1_h20, Dv1_h20, Dw1_h20 and the calculation of the first phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21 are omitted. Although the processing proceeds from S210 to S213 in the present embodiment, similarly to the time of the flat-tip modulation, the first excess amounts Du1_h20, Dv1_h20, Dw1_h20 and the first phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21 can be calculated. The first excess amounts Du1_h20, Dv1_h20, Dw1_h20 are as in 21 and the first phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21 are as shown in FIG 22 is shown.

As in 18 is the processing from S213 to S215 to which the processing proceeds from S210 or S212, similar to the processing from S108 to S110 in FIG 5 , At S216, the excess correction unit compares 552 a lower all-phase-on-duty ratio PD3 having a lower two-phase-on-duty ratio PD4, wherein the duty ratio PD3 corresponds to an all-phase-on period P1 which is a period in which all the phases of the switching elements 24 to 26 at the time of the flat bed modulation, and the duty ratio PD4 corresponds to a two-phase on-period P4 which is a period in which two phases of the switching elements 24 to 26 are turned on. The lower all-phase-on duty PD3 and the lower two-phase duty-on ratio PD4 are expressed by formulas (17-1) and (17-2), respectively. PD3 = 100 - (MaxD2 - MinD2) (17-1) PD4 = MaxD2 - MidD2 (17-2)

Similar to S204, when the lower all-phase on-duty PD3 is compared with the lower two-phase on-duty PD4 and the lower all-on duty PD3 is not smaller than the lower two-phase duty PD3. Duty ratio PD4, the all-phase-on period P3 is not shorter than the two-phase-on period P4. Thus, it is assumed that the current is detected when all the phases of the switching elements 24 to 26 are what the flatbed modulation represents. Further, when the lower two-phase-on ratio PD4 is greater than the lower all-phase-on duty ratio PD3, the two-phase on-period P4 is longer than the all-phase-on period P3. Thus, it is assumed that the current is detected when two phases of the switching elements 24 to 26 are one, as the flat-tip modulation and what the flat-tip modulation represents.

When the lower all-phase-on duty PD3 is determined to be not smaller than the lower two-phase duty ratio PD4 (S216: NO), the processing proceeds to S220. When the lower two-phase duty ratio PD4 is determined to be larger than the lower all-phase duty ratio PD3 (S216: YES), the processing proceeds to S217.

Hereinafter, a detailed description of the processing of S217 to S224 is appropriately omitted since it is substantially similar to the processing of S205 to S212. At S217, the excess correction unit takes 552 a stationary phase in the second system S102 as the maximum phase. When the lower two-phase on-duty ratio PD4 is greater than the lower all-phase-on duty ratio PD3, the zero point voltage is changed by the flat peak modulation.

At S218, the excess correction unit calculates 552 second zero point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 at the time of the flat peak modulation. The second zero point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 at the time of the flat peak modulation are expressed by the formulas (18-1), (18-2) and (18-3), respectively. Du2_ca21 = Du2 - MaxD2 + RH2 (18-1) Dv2_ca21 = Dv2 - MaxD2 + RH2 (18-2) Dw2_ca21 = Dw2 - MaxD2 + RH2 (18-3)

At S219, the excess correction unit limits 552 the second zero point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 at the time of the flat peak modulation to be within the range between the lower limit value RL2 and the upper limit value RH2, and calculates second upper-lower limit limit processing values Du2_ca22, Dv2_ca22, Dw2_ca22 at the time of the flat peak modulation.

At S220, with which processing continues to determine that the lower all-phase duty ratio PD3 is not smaller than the lower two-phase duty ratio PD4 (S216: NO), the excess correcting unit takes 552 the stationary phase in the second system 102 as the minimum phase. When the lower all-phase-on duty PD3 is not smaller than the lower two-phase duty-on ratio PD4, the zero-point voltage is changed by the flat-bed modulation.

At S221, the excess correction unit calculates 552 second zero point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 at the time of the flatbed modulation. The second zero point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 at the time of the flat bed modulation are expressed by formulas (19-1), (19-2) and (19-3), respectively. The second zero point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 calculated at S217 or S220 are in 23 shown. Du2_ca21 = Du2_c - MinD2 + RL3 (19-1) Dv2_ca21 = Dv2_c - MinD2 + RL3 (19-2) Dw2_ca21 = Dw2_c - MinD2 + RL3 (19-3)

At S222 limits the excess correction unit 552 the second zero-point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 at the time of the flat bed modulation to be within the range between the predetermined lower limit value RL3 and the predetermined upper limit value RH3, and calculates second upper-lower limit limit processing values Du2_ca22, Dv2_ca22, Dw2_ca22 at the time of Flatbed modulation. The second upper-lower limit limit processing values Du2_ca22, Dv2_ca22, Dw2_ca22 calculated at S219 or S222 are as in FIG 24 shown.

At S223, with which processing continues from S219, the excess correction unit calculates 552 second surplus Du2_h20, Dv2_h20, Dw2_h20. The second excess amounts Du2_h20, Dv2_h20, Dw2_h20 are amounts by which the second zero-point voltage change values Du2_ca21, Dv2_ca21, Dw2_ca21 exceed the lower limit value RL2 or the upper limit value RH2 and are represented by formulas (20-1), (20-2) and (20-2) (20-3). Du2_h20 = Du2_ca21 - Du2_ca22 (20-1) Dv2_h20 = Dv2_ca21 - Dv2_ca22 (20-2) Dw2_h20 = Dw2_ca21 - Du2_ca22 (20-3)

At S224, the excess correction unit calculates 552 second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21, which are values obtained by converting the second excess amounts Du2_h20, Dv2_h20, Dw2_h20 into the coordinate system of the first system 101 be obtained using a rotation matrix. The second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21 can be obtained by performing the dq conversion of the second excess amounts Du2_h20, Dv2_h20, Dw2_h20 in the coordinate system of the second system 102 and performing the reverse dq conversion of the dq conversion values in the coordinate system of the first system 101 be calculated. The second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21 are expressed by formulas (21-1), (21-2) and (21-3), respectively. Du2_h21 = (Du2_h20 - Dw2_h20) / (√3) (21-1) Dv2_h21 = (Dv2_h20 - Du2_h20) / (√3) (21-2) Dw2_h21 = (Dw2_h20 - Dv2_h20) / (√3) (21-3)

Similar to the first system 101 are the second excess amounts Du2_h20, Dv2_h20, Dw2_h20 0 at the time of the flatbed modulation in calculation. As a result, the calculation of the second excess amounts Du2_h20, Dv2_h20, Dw2_h20 and the calculation of the second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21 are omitted. Although the processing proceeds from S122 to S225 in the present embodiment, similarly to the time of the flat peak modulation, the second excess amounts Du2_h20, Dv2_h20, Dw2_h20 and the second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21 can be calculated. The second excess amounts Du2_h20, Dv2_h20, Dw2_h20 are as in 25 and the second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21 are as shown in FIG 26 shown. The processing of S210 to S212 and the processing of S213 to S214 may be performed in the order of processing of S213 to S224 and the processing of S210 to S212, or may be performed simultaneously in parallel.

At S225, the excess correction unit modulates 552 the second phase conversion amounts Du2_h21, Dv2_h21, Dw2_h21 such that the second correction amount for correcting the stationary phase is 0, and calculates second correction amounts Du2_h22, Dv2_h22, Dw2_h22.

When the stationary phase in the first system 101 is the U phase, the second correction amounts Du2_h22, Dv2_h22, Dw2_h22 are expressed by formulas (22-1), (22-2) and (22-3), respectively. Du2_h22 = 0 (22-1) Dv2_h22 = Dv2_h21 - Du2_h21 (22-2) Dw2_h22 = Dw2_h21 - Du2_h21 (22-3)

When the stationary phase in the first system 101 is the V phase, the second correction amounts Du2_h22, Dv2_h22, Dw2_h22 are expressed by formulas (23-1) (23-2) and (23-3), respectively. Du2_h22 = Du2_h21 - Dv2_h21 (23-1) Dv2_h22 = 0 (23-2) Dw2_h22 = Dw2_h21 - Dv2_h21 (23-3)

When the stationary phase in the first system 101 is the W phase, the second correction amounts Du2_h22, Dv2_h22, Dw2_h22 are expressed by formulas (24-1) (24-2) and (24-3), respectively. Du2_h22 = Du2_h21 - Dw2_h21 (24-1) Dv2_h22 = Dv2_h21 - Dw2_h21 (24-2) Dw2_h22 = 0 (24-3)

The second correction amounts Du2_h22, Dv2_h22, Dw2_h22 are as in 27 is shown.

At S226, the excess correction unit corrects 552 the first upper-lower limit limit processing values Du1_ca22, Dv1_ca22, Dw1_ca22 by the second correction amounts Du2_h22, Dv2_h22, Dw2_h22 to give first correction values Du1_ca23, Dv1_ca23, Dw1_ca23. The first excess correction values Du1_ca23, Dv1_ca23, Dw1_ca23 are expressed by formulas (25-1), (25-2) and (25-3), respectively. Du1_ca23 = Du1_ca22 + Du2_h22 (25-1) Dv1_ca23 = Dv1_ca22 + Dv2_h22 (25-2) Dw1_ca23 = Dw1_ca22 + Dw2_h22 (25-3)

The first excess correction values Du1_ca23, Dv1_ca23, Dw1_ca23 are as in 28A and 28B is shown. 28A shows the entirety of the first excess correction values Du1_ca23, Dv1_ca23, Dw1_ca23. 28B shows a modulation ratio around 0% in an enlarged form, and thin lines indicate the first upper-lower limit limit processing values Du1_ca22, Dv1_ca22, Dw1_ca22 before being corrected by the second correction amounts Du2_h22, Dv2_h22, Dw2_h22. This also applies to the later described 30 ,

At S227, the excess correction unit modulates 552 the phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21 such that the first correction amount for correcting the stationary phase is 0, and calculates the first correction amounts Du1_h22, Dv1_h22, Dw1_h22.

When the stationary phase in the second system 102 is the U phase, the first correction amounts Du1_h22, Dv1_h22, Dw1_h22 are expressed by formulas (26-1), (26-2) and (26-3), respectively. Du1_h22 = 0 (26-1) Dv1_h22 = Dv1_h21 - Du1_h21 (26-2) Dw1_h22 = Dw1_h21 - Du1_h21 (26-3)

When the stationary phase in the second system 102 is the V phase, the first correction amounts Du1_h22, Dv1_h22, Dw1_h22 are expressed by formulas (27-1), (27-2) and (27-3), respectively. Du1_h22 = Du1_h21 - Dv1_h21 (27-1) Dv1_h22 = 0 (27-2) Dw1_h22 = Dw1_h21 - Dv1_h21 (27-3)

When the stationary phase in the second system 102 is the W phase, the first correction amounts Du1_h22, Dv1_h22, Dw1_h22 are expressed by formulas (28-1), (28-2) and (28-3), respectively. Du1_h22 = Du1_h21 - Dw1_h21 (28-1) Dv1_h22 = Dv1_h21 - Dw1_h21 (28-2) Dw1_h22 = 0 (28-3)

The first correction amounts Du1_h22, Dv1_h22, Dw1_h22 are in 29 shown.

At S228, the excess correction unit corrects 552 the second upper-lower limit limit processing values Du2_ca22, Dv2_ca22, Dw2_ca22 by the first correction amounts Du1_h22, Dv1_h22, Dw1_h22 to give second excess correction values Du2_ca23, Dv2_ca23, Dw2_ca23. The second excess correction values Du2_ca23, Dv2_ca23, Dw2_ca23 are expressed by formulas (29-1), (29-2) and (29-3), respectively. Du2_ca23 = Du2_ca22 + Du1_h22 (29-1) Dv2_ca23 = Dv2_ca22 + Dv1_h22 (29-2) Dw2_ca23 = Dw2_ca22 + Dw1_h22 (29-3)

The second excess correction values Du2_ca23, Dv2_ca23, Dw2_ca23 are as in 30A and 30B shown.

In the present embodiment, the excess correction values Du1_ca23, Dv1_ca23, Dw1_ca23, Du2_ca23, Dv2_ca23, Dw2_ca23 are applied to the drive circuit 35 is output as the duty command values Du1, Dv1, Dw1, Du2, Dv2, Dw2.

In the present embodiment, the first inverter 10 and the second inverter 20 the high potential side switching elements 11 to 13 . 21 to 23 and the low potential side switching elements 14 to 16 . 24 to 26 which are pairwise for the respective phases. The current detection units 18 . 28 are between the low potential side switching elements 14 to 16 . 24 to 26 and the mass connected. Thus, the shunt resistors can be suitably used as the current detection elements 181 to 183 . 281 to 283 be used.

The excess correction unit 552 compares the all-phase-on period P1 in which the low potential side switching elements 14 to 16 of three-phase ons, with the two-phase on-period P2, in which the low-potential side switching elements 14 to 16 of two-phases, and changes the zero-point voltage such that the current detection can be performed in the longer period. Furthermore, compare the excess correction unit 552 the all-phase-on period P3 in which the low potential side switching elements 24 to 26 of three-phase ons, with the two-phase on-period P4 in which the low potential side switching elements 24 to 26 of two-phases, and changes the zero-point voltage such that the current detection can be performed in the longer period. Thus, it is possible to improve the voltage utilization rate while the current detection by the current detection units 18 . 28 , which are provided on the low potential side, is made possible. Further, a similar effect to that of the first embodiment is achieved. In the present embodiment, the lower limit values RI2, RL3 and the upper limit values RH2, RH3 correspond to the limitation value.

THIRD EMBODIMENT

31 and 32 show a third embodiment of the present disclosure. As in 31 is shown, the control unit is different 42 of the third embodiment of those of the first and second embodiments in that the control unit 42 a current correction value calculation unit 56 and a current correction unit 57 in addition to the three-phase-to-two-phase conversion unit 51 , to the control device 52 , to the voltage limiting unit 53 , to the two-phase-to-three-phase conversion unit 54 and the modulation calculation unit 55 having.

In the surplus correction processing, in the first system 101 Duty ratios that are equivalent to the first excess amounts Du1_h20, Dv1_h20, Dw1_h20 are subtracted and duty ratios equivalent to the second correction amounts Du2_h22, Dv2_h22, Dw2_h22 according to second excess amounts Du2_h20, Dv2_h20, Dv2_h20 are added. Further, in the second system 102 Duty ratios which are equivalent to the second excess amounts Du2_h20, Dv2_h20, Dw2_h20 are subtracted and duty ratios equivalent to the first correction amounts Du1_h22, Dv1_h22, Dw1_h22 according to the first excess amounts Du1_h20, Dv1_h20, Dv1_h20 are added. In the present embodiment, currents are estimated according to the duty ratios to be changed by the surplus correction processing to correct the current detection values Iu1, Iv1, Iw1, Iu2, Iv2, Iw2.

As in 32 has the current correction value calculation unit 56 subtractor 561 . 564 , Voltage conversion units 562 . 565 and power-estimating units 563 . 566 , 32 shows an example where the calculation of the second embodiment by the excess correction unit 552 is performed.

The first subtractor 561 subtracts the first excess amount Du1_h20 from the second U-phase correction amount Du2_h22 to calculate a first duty ratio change value ΔDu1. Similarly, the first subtractor subtracts 561 the first excess amount Dv1_h20 from the second V-phase correction amount Dv2_h22 for calculating a first duty ratio change value ΔDv1, and subtracts the first excess amount Dw1_h20 from the second W-phase correction amount Dw2_h22 to calculate a first duty ratio change value ΔDw1. The first duty ratio change values ΔDu1, ΔDv1, ΔDw1 may be used as changed amounts by which the duty ratios of the first duty ratio conversion values Du1_c, Dv1_c, Dw1_c are changed by the excess correction processing.

The first voltage conversion unit 562 multiplies each of the first duty ratio change values ΔDu1, ΔDv1, ΔDw1 given by the first subtractor 561 with (Vb / 100) for calculating first voltage change values ΔVu1, ΔVv1, ΔVw1 by converting the duty cycles are obtained in tensions. The first electricity estimation unit 563 estimates currents according to the first voltage change values ΔVu1, ΔVv1, ΔVw1 for calculating first current correction values CurrU1_h, CurrV1_h, CurrW1_h.

The second subtractor 564 subtracts the second excess amount Du2_h20 from the first U-phase correction amount Du1_h22 to calculate a second duty ratio change value ΔDu2. Similarly, the second subtractor subtracts 564 the second excess amount Dv2_h20 from the first V-phase correction amount Dv1_h22 for calculating a second duty ratio change value ΔDv2 and subtracts the second excess amount Dw2_h20 from the first W-phase correction amount Dw1_h22 to calculate a second duty ratio change value ΔDw2. The second duty ratio change values ΔDu2, ΔDv2, ΔDw2 may be used as changed amounts by which the duty ratios of the second duty ratio conversion values Du2_c, Dv2_c, Dw2_c are changed by the excess correction processing.

The second voltage conversion unit 565 multiplies each of the second duty-cycle change values ΔDu2, ΔDv2, ΔDw2 given by the second subtractor 564 with (Vb / 100) for calculating second voltage change values ΔVu2, ΔVv2, ΔVw2, which are obtained by converting the duty ratios into voltages. The second electricity estimation unit 566 estimates current values according to the second voltage change values ΔVu2, ΔVv2, ΔVw2 for calculating second current correction values CurrU2_h, CurrV2_h, CurrW2_h.

Further, also in a case where the calculation of the first embodiment in the excess correction unit 552 is to be performed, the first current correction values CurrU1_h, CurrV1_h, CurrW1_h are calculated on the basis of the second correction amounts Du2_h11, Dv2_h11, Dw2_h11 and the first excess amounts Du_h10, Dv1_h10, Dw1_h10. Further, the second current correction values CurrU2_h, CurrV2_h, CurrW2_h may be calculated on the basis of the first correction amounts Du1_h11, Dv1_h11, Dw1_h11 and the second excess amounts Du2_h10, Dv2_h10, Dw2_h10.

As in 31 is shown corrects the current correction unit 57 U1 current detection value Iu1 by current correction value CurrU1_h, corrects V1 current detection value Iv1 by current correction value CurrV1_h, and corrects W1 current detection value Iw1 by current correction value CurrW1_h. Further, the current correction unit corrects 57 the U2 current detection value Iu2 by the current correction value CurrU2_h, corrects the V2 current detection value Iv2 by the current correction value CurrV2_h, and corrects the W2 current detection value Iw2 by the current correction value CurrW2_h. In the present embodiment, the respective current correction values CurrU1_h, CurrV1_h, CurrW1_h, CurrU2_h, CurrV2_h, CurrW2_h are respectively subtracted from the current detection values Iu1, Iv1, Iw1, Iu2, Iv2, Iw2. The current correction calculation in the current correction unit 57 is not limited to subtraction, but may be any form of calculation. The three-phase-to-two-phase conversion unit 51 performs the three-to-two-phase conversion using the current detection values Iu1, Iv1, Iw1, Iu2, Iv2, Iw2 corrected by the current correction values CurrU1_h, CurrV1_h, CurrW1_h, CurrU2_h, CurrV2_h, CurrW2_h.

The control unit 42 also has the current correction value calculation unit 56 and the current correction unit 57 , The current correction value calculation unit 56 calculates the current correction values CurrU1_h, CurrV1_h, CurrW1_h, CurrU2_h, CurrV2_h, CurrW2_h according to streams generated by the surplus correction processing. The current correction unit 57 corrects the current detection values Iu1, Iv1, Iw1, Iu2, Iv2, Iw2 on the basis of the current correction values CurrU1_h, CurrV1_h, CurrW1_h, CurrU2_h, CurrV2_h, CurrW2_h. This allows more appropriate calculation of voltage command values Vu1 *, Vv1 *, Vw1 *, Vu2 *, Vv2 *, Vw2 *. Further, effects similar to those of the above embodiments are achieved.

FOURTH EMBODIMENT

33 shows a fourth embodiment of the present disclosure. As in 33 is shown has a control unit 43 In the present embodiment, the three-phase-to-two-phase conversion unit 51 , a sum-difference conversion unit 61 , a control device 62 , a system conversion unit 63 , the voltage limiting unit 53 , the two-phase-to-three-phase conversion unit 54 , the modulation calculation unit 55 , an excess determination unit 65 and the same. The sum difference conversion unit 61 converts the d-axis current detection values Id1, Id2 and the q-axis current detection values Iq1, Iq2 into sums and differences. In particular, the sum-difference conversion unit calculates 61 a d-axis current sum Id1 + Id2, a d-axis current difference Id1 - Id2, a q-axis current sum Iq1 + Iq2, and a q-axis current difference Iq1 - Iq2. As in the third embodiment, as the d-axis current detection values Id1, Id2 and the q-axis current detection values Iq1, Iq2, values based on the current detection values Iu1, Iv1, Iw1, Iu2, Iv2, Iw2 may be used by the current correction values CurrU1_h, CurrV1_h, CurrW1_h, CurrU2_h, CurrV2_h, CurrW2_h.

The control device 62 includes a d-axis sum controller 621 , a d-axis difference control device 622 , a q-axis sum controller 623 and a q-axis difference control device 624 , The d-axis sum controller 621 calculates a d-axis voltage sum command value Vd + * by PI calculation or the like on the basis of the d-axis current sum command value Id + * and the d-axis current sum Id1 + Id2. The d-axis difference control device 622 calculates a d-axis voltage difference command value Vd- * by PI calculation or the like on the basis of the d-axis current difference command value Id- * and the d-axis current difference Id1 - Id2. The q-axis sum controller 623 calculates a q-axis voltage sum command value Vq + * by PI calculation or the like on the basis of the q-axis current sum command value Iq + * and the q-axis current sum Iq1 + Iq2. The q-axis difference control device 624 calculates a q-axis voltage difference command value Vq- * by PI calculation or the like on the basis of the q-axis current difference command value Iq- * and the q-axis current difference Iq1 - Iq2. In the present embodiment, the current difference command values Id- *, Iq- * are 0.

The system conversion unit 63 converts the voltage sum command values Vd + *, Vq + * and the voltage difference command values Vd- *, Vq- * into the first pre-limit d-axis voltage command value Vd1 * _a, the first pre-limit q-axis voltage command value Vq1 * _a, the second pre-limit d -Axis voltage command value Vd2 * _a and the second pre-limit q-axis voltage command value Vq2 * _a. Further, the voltage control processing, the surplus correction processing, and the like based on the first pre-limit d-axis voltage command value Vd1 * _a, the first pre-limit q-axis voltage command value Vq1 * _a, the second pre-limit d-axis voltage command value Vd2 * _a and the second pre-limit q-axis voltage command value Vq2 * _a, similar to those of the above embodiments. While any one of the surplus correction processing of the first embodiment or that of the second embodiment may be used, the description is made on the assumption that the surplus correction processing of the second embodiment is executed.

The excess determination unit 65 determines whether the excess correction processing is executed. When at least one of the excess amounts Du1_h20, Dv1_h20, Dw1_h20, Du2_h20, Dv2_h20, Dw2_h20 is not 0, it is determined that the excess correction processing is being executed. Further, when all of the excess amounts Du1_h20, Dv1_h20, Dw1_h20, Du2_h20, Dv2_h20, Dw2_h20 are 0, it is determined that the excess correction is not performed.

Whether the surplus correction processing is carried out may be performed on the basis of the phase conversion amounts Du1_h21, Dv1_h21, Dw1_h21, Du2_h21, Dv2_h21, Dw2_h21 or the correction amounts Du1_h22, Dv1_h22, Dw1_h22, Du2_h22, Dv2_h22, Dw2_h22 instead of the excess amounts Du1_h20, Dv1_h20, Dw1_h20, Du2_h20, Dv2_h20, Dw2_h20 be determined. In the case of the surplus correction processing of the first embodiment, the determination may be made in a similar manner as above.

The excess determination unit 65 may determine that the excess correction is performed when voltages appearing on the winding sets 81 . 82 are greater than a voltage determination threshold. The voltages connected to the winding sets 81 . 82 voltage command values may be applied in the respective calculation processings of the voltage command values Vd1 * a, Vq1 * a, Vd2 * a, Vq2 * a and the like pre-limit by the voltage limiting unit 53 his or her actual voltages may actually be on the winding sets 81 . 82 issue. Further, the excess determination unit determines 65 in that the excess correction is carried out when a rotation speed of the motor 80 is greater than a rotational speed determination limit. The determination result is sent to the d-axis difference controller 622 and the q-axis difference control means 624 output. If it is determined that the excess correction is executed, the difference control devices decrease 622 . 624 the control response. It should be noted that turning off the control of the differential control devices 622 . 624 is also included in the concept of reducing the response.

The first voltage command values Vu1 *, Vv1 *, Vw1 * and the second voltage conversion values Vu2 *, Vv2 *, Vw2 * are determined using the sum controllers 621 . 623 for controlling a sum of currents flowing in the first winding set 81 and the second winding set 82 flow, and using the difference control devices 622 . 624 for controlling a difference between current in the first winding set 81 flows, and current flowing in the second winding set 82 flows, calculated. When the excess correction processing is executed, the decrease Differential control devices 622 . 624 the response compared with when the excess correction processing is not performed.

In the present embodiment, a command value is calculated by controlling the sum and difference, thereby reducing reduction of influences of temperature change, variation between elements, and the like. Further, when the excess correction processing is executed, the differential control response is suppressed to avoid a weak state of the differential control at the time of excess correction, thereby making it possible to adequately reduce torque ripple. Further, effects similar to those of the above embodiments are achieved.

OTHER EMBODIMENTS

(I) Value corresponding to a first voltage command, value corresponding to a second voltage command

In the embodiments, the first zero-point voltage change value corresponds to the value corresponding to a first voltage command, and the second zero-point voltage change value corresponds to the value corresponding to a second voltage command. In another embodiment, each of the value corresponding to a first voltage command and the value corresponding to a second voltage command is not limited to the zero point voltage change value, but may itself be a voltage command value. That is, the surplus correction processing may be performed by using a duty command conversion value before duty ratio conversion. Further, each of the value corresponding to a first voltage command and the value corresponding to a second voltage command may be a value other than the zero point voltage change value calculated based on a voltage command value such as a duty conversion value. Further, the value used for the surplus correction processing is not limited to one value in the three-phase coordinate system, but may be a value in another coordinate system.

(II) Current detection unit

In the second embodiment, the current detection unit is provided between the low potential side switching element and the ground. In another embodiment, the current sensing element located on the low potential side may be any element that can detect current, such as a Hall element instead of the shunt resistor. Further, the current detection element may be disposed at any position where a phase current can be detected, such as on the high potential side of the high potential side switching element. Further, it is desirable to set the limit value according to the current detection element and the position where the current detection element is arranged.

In the above embodiments, each of the first voltage command value and the second voltage command value is calculated by the current feedback control and the current control based on the current detection value, respectively. In another embodiment, each of the first voltage command value and the second voltage command value may be calculated by not using the current detection value but by performing feedforward control of, for example, an electrical angle, speed, or the like, for example. In this case, the current detection can be omitted.

(III) excess correction unit

In the above embodiments, the surplus correction unit executes the surplus correction processing for the first zero point voltage change value and the second zero point voltage change value, which are values obtained by changing the zero point voltage. In another embodiment, the excess correction unit may perform the excess correction processing without changing the zero point voltage.

(IV) Voltage limiting unit

In the above embodiments, when the bias limiting voltage vector is larger than the amplitude limiting value, the q-axis component for limiting the voltage command value is changed so that the voltage command value becomes the amplitude limiting value. In another embodiment, to be no greater than the amplitude limiting value, the voltage command value may be limited by any method such as controlling both the d-axis component and the x-axis component, instead of changing the q-axis component.

(V) Electric rotary machine

In the above embodiments, the winding sets of the rotary electric machine are arranged with phases offset by 30 °. In a further embodiment, the Phase difference between the sets of windings is not limited to 30 °, but may be any number of degrees. Further, the line phase difference is not limited to 30 ° and may be any degree number other than 0 °. The rotary electric machine is used for the electric power steering apparatus. In another embodiment, the rotary electric machine may be applied to an on-board device other than the electric power steering device, or may be applied to a non-on-board device. Further, the rotary electric machine is not limited to the motor, but may be a generator or a so-called motor generator having combined functions of an electric motor and a generator. Hitherto, the present disclosure is not limited to any of the embodiments, and may be implemented in a variety of forms within a scope that does not depart from the spirit of the disclosure.

It should be noted that a flowchart or the processing of the flowchart in the present application includes portions (also referred to as steps) each of which is represented as S101, for example. Furthermore, each section can be divided into several subsections, while multiple sections can be combined into a single section. Further, each of the sections thus configured may be referred to as a device, module or means.

While the present disclosure has been described with respect to embodiments thereof, it will be understood that the disclosure is not limited to the embodiments and constructions. The present disclosure is intended to cover various modifications and equivalent arrangements. Further, in addition to the various combinations and configurations, other combinations and configurations, including more, less or a single element, are also within the spirit and scope of the present disclosure.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• JP 2014-121189A [0003]

Claims (9)

Power converter for converting electrical power of a three-phase rotary electric machine ( 80 ) including a first winding set ( 81 ) and a second winding set ( 82 ), the power converter comprising: a first inverter ( 10 ) corresponding to the first winding set; a second inverter ( 20 ) corresponding to the second winding set; and a control unit ( 41 . 42 . 43 ) including a command calculation unit ( 52 to 54 . 62 . 63 ) which calculates a first voltage command value with respect to a voltage to be applied to the first winding set and a second voltage command value with respect to a voltage to be applied to the second winding set, and an excess correcting unit ( 552 ) which corrects a value corresponding to a first voltage command corresponding to the first voltage command value and corrects a value corresponding to the second voltage command value corresponding to a second voltage command, wherein: if one of the value corresponding to a first voltage command and the value corresponding to a second voltage command corresponds to a second voltage command value Exceeds a threshold value that is set in accordance with a voltage that can be output, the excess correction unit performs excess correction processing for correcting the other of the value corresponding to a first voltage command and the value corresponding to a second voltage command according to an excess amount above the threshold value. A power converter according to claim 1, wherein: the surplus correction unit executes the surplus correction processing for the value corresponding to a first voltage command and the value corresponding to a second voltage command whose zero-point voltage is changed. Power converter according to claim 2, further comprising: a current detection unit ( 17 . 18 . 27 . 28 ) detecting a current passing through each phase of the first winding set and the second winding set, wherein: the command calculating unit calculates the first voltage command value and the second voltage command value based on a current detection value detected by the current detection unit. A power converter according to claim 3, wherein: each of the first inverter and the second inverter has a high potential side switching element ( 11 to 13 . 21 to 23 ) and a low potential side switching element ( 14 to 16 . 24 to 26 ) providing a pair corresponding to each phase; and the current detection unit ( 18 . 28 ) is disposed between the low potential side switching element and a ground. A power converter according to claim 4, wherein: the surplus correction unit compares an all-phase-on period in which the low potential side switching element of each phase turns on, with a two-phase on period in which the low potential side switching element of each of two-phase turns on; and the surplus correction unit changes the zero-point voltage to detect current for one of the all-phase-on period and the two-phase-on period longer than the other of the all-phase-on period and the two-phase -One-period is. Power converter according to one of claims 3 to 5, wherein: the control unit ( 42 ) further includes: a current correction value calculation unit ( 56 ) which calculates a current correction value in accordance with a current generated by the surplus correction processing; and a current correction unit ( 57 ) which corrects the current detection value based on the current correction value. A power converter according to any one of claims 1 to 6, wherein: the first voltage command value and the second voltage command value are determined using a sum control device ( 621 . 623 ) and a difference control device ( 622 . 624 ) be calculated; the sum controller controls a sum of a current flowing in the first winding set and a current flowing in the second winding set; the difference control means controls a difference between the current flowing in the first winding set and the current flowing in the second winding set; and when the excess correction unit executes the surplus correction processing, the difference control means sets lower responsiveness than when the excess correction unit does not execute the excess correction processing. Power converter according to one of claims 1 to 7, wherein: the first voltage command value and the second voltage command value are limited by a predetermined amplitude limitation value to be corrected according to the surplus amount. A power converter according to any one of claims 1 to 8, wherein: the electric rotary machine for an electric power steering device ( 5 ) is used; and the rotary electric machine, a steering operation of a steering component ( 91 ) supported by a driver according to an output torque.

Images