DE102016205187A1 - Integrated circuit cooling using embedded Peltier microvias in a substrate - Google Patents

Abstract

A package of semiconductor devices and a method of manufacturing the same include a semiconductor substrate including a plurality of embedded thermocouples. The embedded thermocouples may be located in trenches and extend partially into the substrate from the handling side of the substrate. An n-bar and a p-bar are electrically connected by means of a conductive contact plate so that they each form the partially embedded thermocouples. A series circuit layer electrically connects the plurality of thermocouples on the handling side. A power source supplies electrical power to the series circuit layer and allows current to flow through the plurality of series-connected thermocouples. A heat sink is positioned adjacent the connected thermocouples for dissipating heat from the device side to the heat sink by means of the thermocouples.

Description

BACKGROUND

The present disclosure relates to a semiconductor structure and a method for semiconductor fabrication. Integrated circuits (ICs) can generate heat in a semiconductor package. Heat within the semiconductor package may have undesirable consequences in the semiconductor package, for example detrimental effects on the health of devices within the IC and failure of components. Cooling techniques for the IC may include a heat sink or other cooling mechanisms that require power from the IC and the semiconductor package. Three-dimensional integrated circuits are particularly prone to unwanted heat buildup within the unit or package.

SUMMARY

According to one embodiment of the invention, a package of semiconductor devices includes a plurality of thermocouples embedded in a semiconductor substrate. The thermocouples each include thermo bars positioned opposite each other in each one of a plurality of trenches in the substrate. Each of the trenches defines an opening on a handling side of the substrate opposite a unit side of the substrate. The rods extend partially from the handling side of the substrate into the substrate, and the opposing rods are n- or p-type materials, respectively. A thermally conductive insulating layer is located along a perimeter of the trenches and along outer sides of the bars. A conductive plate electrically connects the n and p rods. A series circuit layer electrically connects the plurality of thermocouples on the handling side of the substrate so as to be supplied with voltage through the series circuit layer. A heat sink is positioned adjacent the thermocouples for dissipating heat from the device side of the substrate to the heat sink by means of the thermocouples.

According to another embodiment of the invention, a method of fabricating a semiconductor substrate includes forming trenches that extend partially into the substrate from a handling side of a substrate facing a unit side of the substrate. The trenches define an opening on the handling side of the substrate for each of the trenches. A thermally conductive insulating layer is deposited along a perimeter of the trenches and positioned along outer sides of the bars. N-bars and P-bars are formed opposite to each other and on opposite sides of each of the trenches so as to form thermocouples. A conductive plate is formed for electrically connecting the n and p rods. A series circuit layer is formed, which electrically connects the plurality of thermocouples so as to be supplied with voltage through the series circuit layer. A heat sink is positioned adjacent to the thermocouples to dissipate heat from the device side of the substrate to the heat sink by means of the thermocouples.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

These and other objects, features and advantages of the present invention will become more apparent from the following detailed description of illustrative embodiments thereof, taken in conjunction with the accompanying drawings. The various features of the drawings are not to scale as the illustrations are illustrative and are intended to assist one of ordinary skill in the art, as well as the detailed description, in understanding the invention. In the drawings:

is 1 10 is a cross-sectional side view of a substrate having a device level / layer, wherein the substrate includes a series of thermocouples and the substrate communicates with a heat sink, according to an embodiment of the disclosure;

is 2 12 is a cross-sectional side view of a substrate having a device level layer, a trench, and silicon vias, according to an embodiment of the disclosure;

is 3 10 is a cross-sectional side view of a substrate having a device level / layer and silicon vias, according to an embodiment of the disclosure;

is 4 a cross-sectional side view of the in 3 illustrated substrate having a trench;

is 5 a cross-sectional side view of the in 4 illustrated substrate having a lining over the trench;

is 6 a cross-sectional side view of the substrate of 5 having a barrier / seed layer;

is 7 a cross-sectional side view of the substrate of 6 in which a rod is formed in the trench;

is 8th a cross-sectional side view of the substrate of 7 in which another rod is formed in the trench;

is 9 a cross-sectional side view of the substrate of 8th in which conductive elements are formed in the trench and on the handling side of the substrate;

is 10 a cross-sectional side view of the substrate of 9 as a final structure;

is 11 a cross-sectional side view of a similar substrate as in 2 10, having a buried junction region, according to an embodiment of the disclosure;

is 12 a cross-sectional side view of a substrate forming a buried joint region;

is 13 a cross-sectional side view of the substrate of 12 having silicon vias in the substrate;

is 14 a cross-sectional side view of the substrate of 13 with the substrate turned over;

is 15 a cross-sectional side view of the substrate of 14 in which thermo bars are formed in the substrate and connected to the buried connection region;

is 16 a cross-sectional side view of a package of integrated circuits according to an embodiment of the disclosure, a similar substrate as in 1 and 10 shown substrate which is connected to another substrate;

is 17 a cross-sectional side view of in 16 illustrated package having a heat sink; and

is 18 a cross-sectional side view of a package of integrated circuits according to an embodiment of the present disclosure, similar to those in 17 illustrated package includes a heat sink on a substrate, but without Siliziumdurchkontaktierungen in the substrate, and includes an external power / voltage source.

DETAILED DESCRIPTION

With reference to 1 herein is a semiconductor substrate 10 according to one embodiment of the disclosure discussed. One side of the substrate 10 includes a unit layer or plane 14 (also referred to as the active device side) and the opposite side of the substrate 10 is with a heat sink 20 connected. thermocouples 30 each include a trench from the handling side (the heat sink side) of the substrate 10 has been created from. The thermocouples 30 include a conductive cooling plate 34 , which may for example consist of a metal, such as copper or tungsten, etc., and in the embodiment of 1 is embodied as a copper cooling plate. An isolation layer 38 surrounds the thermocouples 30 that is, the insulating layer extends along a circumference of the trench. The thermocouples 30 include a rod 42 from a n-thermal material and a rod 44 from a p-type thermal material in the trench passing through the conductive contact plate 34 are separated for heat transfer. The n- and p-thermo materials may be deposited in the trenches. The rods of the n- and p-material consist of thermo materials such as bismuth telluride, lead telluride and other materials. An area of the trench that lies between the n-thermostab 42 and the p-thermostab 44 and over the conductive plate 34 can be defined, optionally with a filler material 52 be filled. A series circuit layer 56 electrically connects the thermocouples on the handling side of the substrate and allows a current flow, for example, a current flow of plus 46 after minus 48 , The series circuit layer 56 is between the trenches and the heat sink 20 positioned and along the length of the substrate so that it connects the thermocouples on the handling (trench opening) side of the substrate.

In the 1 illustrated embodiment of the present disclosure thereby describes an integrated circuit having a cooling technique, the thermocouples 30 includes thermostats in trenches that extend partially into the substrate 10 extend and are connected in series within the substrate with a direct or buried connection. For example, the trench may extend from the handling side of the substrate to a shallow depth. Alternatively, the trench may extend into the substrate until it approaches the unit side or unit level in the substrate. Preferably, the trench does not penetrate into the unit plane of the substrate. An exemplary depth of the trench may include a shallow trench, which may receive the elements of the thermal bars, as in the present disclosure, to a trench depth that approximates or adjoins the active layer.

The majority of the trenches may be by way of a conductive path, the series circuit layer 56 which is formed on the handling side of the unit, as in 1 shown, be connected in series and be connected to an appropriate voltage source (power source) for active cooling. The thermocouples may communicate with a heat sink on the handling side of the substrate (as in FIG 16 and 17 shown).

The unit layer 14 of the substrate may be connected to the other substrates within an IC package (in 16 and 17 shown). Fasteners such as a ball grid or joints may be used for electrical connections within an IC package, for example, from the device level in the IC package. The method and structure of the present disclosure utilizing the thermocouples and electrical current flow utilizes a thermoelectric effect to transfer heat from the device layer 14 of the substrate to the heat sink 20 which communicates with a handling side (a unit layer opposite side) of the substrate.

With reference to 2 In one embodiment according to the present disclosure, it is similar to a substrate 100 the in 1 shown substrate, and similar elements have the same reference numerals. The substrate 100 includes a unit level or layer 14 , joints 104 are connected to the device layer and are at conductive levels 108 in the active layer 14 in connection. The connection points 104 consist of an electrically conductive material. vias 112 (ie silicon vias (TSVs)) connect the active layer 14 with the connection layer 56 (in 2 partially shown) on a handling side 116 of the substrate 100 , The ditch 30 includes an insulation layer 38 along the opposite sides of the trench 30 extending between the handling side 116 of the substrate 100 and the tie layer 56 extends. The insulating layer is also deposited along the sidewalls of the vias, as in FIG 2 shown.

A material of a n-thermo bar 120 is on one side of the trench 30 deposited and may have n-bismuth telluride (Bi2 Te3). A material of a p-thermo bar 124 is in the ditch 30 on a side of the trench opposite the n-bar 30 deposited. The p-rod may have p-bismuth telluride (Bi2 Te3). A trench layer 128 is located between the n-rod and the p-rod and is at the bottom of the trench 30 positioned. The trench layer 128 may for example consist of copper or tungsten, which are electrically conductive and thermally conductive.

With reference to 3 to 10 In the following, a process flow for manufacturing a semiconductor device according to an embodiment of the disclosure will be discussed. Similar elements in the in 1 and 2 illustrated embodiments have the same reference numerals. With reference to 3 includes a substrate 200 vias 112 that the handling side 116 of the substrate with the active layer 14 connect. Initially there is an oxide layer 38 on the back of the wafer.

With reference to 4 becomes a ditch 210 in the substrate 200 etched. With reference to 5 becomes a lining 214 along the circumference of the trench 210 formed, which can be selectively deposited. The lining may be made of a material that has good thermal conductivity but is electrically insulating. With reference to 6 becomes a barrier / seed layer 218 over the lining 214 along the handling side of the substrate and along the circumference of the trench 210 deposited. The barrier / seed layer can be made of materials such as titanium (Ti), ruthenium (Ru) or titanium nitride (TiN), which also have good thermal conductivity.

With reference to 7 becomes a photoresist layer 222 above the handling side 116 of the substrate 200 deposited. Lithography or reactive ion etching may be used to form a trench in the photoresist. A n-rod 230 is formed on one side of the trench. The n-rod may consist of an n-type thermal material, eg of n-bismuth telluride (Bi2 Te3). With reference to 8th the photoresist has been partially removed, and a p-rod 234 is formed on the side opposite the n-rod side of the trench. The p-rod may consist of a p-thermo material, for example of p-bismuth telluride (Bi2 Te3).

With reference to 9 becomes a photoresist layer 222 (as etch stop layer) to protect the n and p thermo bars. The photoresist layer 222 becomes for depositing a conductive layer 238 on the in 9 etched away. The conductive layer 238 For example, it can be made of copper or tungsten, which are electrically conductive, allowing a current to pass between the thermostats. With reference to 10 are the photoresist 238 and the barrier / seed layer 218 partially removed, for example by etching, and the final substrate 250 with the thermocouple 254 is shown.

1 represents several trenches that are in 10 (and below in 16 and 17 ) being represented. The present disclosure thereby describes an integrated circuit comprising a Cooling technology that includes thermocouples having Thermostäbe that extend partially into the substrate and are connected in series within the substrate with a direct or buried connection. The majority of (in 1 shown) thermocouples can by means of a conduction path, which is formed on the handling side of the unit, as in 1 shown, be connected in series and be connected for active cooling with a suitable voltage source. The thermocouples and rods may communicate with a heat sink on the handling side of the substrate.

With reference to 11 Another embodiment according to the present disclosure includes a substrate 300 , the n- or p-thermostats 304 . 308 includes. Both thermostats can be made of any of the known thermo materials (eg Bi2 Te3). A buried connection area 312 may include an implanted metal in the substrate. The buried connection area 312 stands with the bars 304 . 308 in connection.

With reference to 12 to 15 will be a process flow to manufacture the in 11 represented substrate 300 discussed. With reference to 12 becomes a photoresist layer 320 over a part of an active page 324 of the substrate except over a region of a region of the substrate for an implanted conductor 330 for forming a buried connection 340 corresponds to (in 15 shown). With reference to 13 can be the active level 14 on the active side 324 of the substrate can be formed and TSVs 112 in the substrate 300 be formed.

With reference to 14 becomes the substrate 300 shown turned around, so that the active level 14 located in the drawing below. With reference to 15 become the bars 304 . 308 from the handling side 116 of the substrate 300 formed from, and the substrate 300 it is the same as the one in 11 shown. The substrate 300 includes n and p rods 304 . 308 , The buried connection 340 is inside the substrate 300 been trained and joins the bars 304 . 308 ,

The voltage applied to the free ends of two different conductive materials results in a flow of current sequentially through a series of thermocouples and two semiconductors. The current flows through the electrical series circuit on the handling side (or back) of the substrate through the n-type thermo-bar to the conductive plate, to the p-type thermo-bar, and then to the heat sink. Because the thermocouples are connected in series (or chained), the current flows through all the thermocouples connected in series. Peltier cooling causes heat to be absorbed from the environment of the conductive cooling plate and the heat absorbed to the other end of the substrate, i. to the heat sink, is transported. When current is forced through the unit (the substrate as shown in the figures), the electrons pick up energy at one end, while those at the other end release energy. Therefore, in an uninterrupted flow of current, heat is continuously received at one end and released at another end.

With reference to 16 includes an IC pack 400 according to an embodiment of the present disclosure, similar elements as previously illustrated embodiments having the same reference numerals. The IC pack 400 includes a second substrate 404 , The second substrate 404 is using solder balls 408 with a substrate 350 connected the elements of in 10 as a substrate 250 contains the present disclosure. The substrate 350 includes an active page 14 and a handling side 116 , The trenches 412 of the substrate 400 resemble the in 1 and 2 pictured, the top as a ditch 30 have been described, and the in 10 shown thermocouple 254 of the substrate 250 , In the IC pack 400 from 16 are the substrate 350 and its vias using the solder balls 408 and the conductive junctions 104 with the second substrate 404 connected. With reference to 17 will be the ic pack 400 (using the solder balls 408 ) with other substrates 460 shown connected, and a heat sink 470 is about the additional substrates 460 and the substrate 350 positioned. The heat sink 470 is using a thermal interlayer material 474 (Thermal interface material, TIM) connected to the heat transfer 478 from the substrate 350 and its trenches 412 to the heat sink 470 improved.

With reference to 18 shows a further embodiment of an IC package 500 according to the present disclosure, elements similar to those in 16 and 17 shown pack with the same reference numerals for the same elements. The IC pack 500 includes a substrate 550 and ditches 412 , in the 16 and 17 being represented. In the 16 and 17 illustrated TSVs 112 are in the substrate 550 been removed. Separate wiring (not shown) for current flow through the substrate and rods in the trenches may be employed.

A heat sink 504 is over the trenches 412 of the substrate 550 positioned. The heat sink 504 is similar to the one in 17 shown heatsink 470 in structure and function, the heat sink 504 however, has a number of fins 508 for improving heat dissipation. The substrate 550 and the trenches are from an electrical circuit 512 powered by the handling side of the substrate without using TSVs. The substrate 550 is with a second substrate 404 connected, as in 18 shown.

In general, in accordance with embodiments of the present disclosure, a package of semiconductor devices and a method of manufacturing the same include embedded thermocouples in a semiconductor substrate. The thermocouples may include trenches that extend partially into the substrate, with the n and p rods extending into the trenches. A thermally conductive insulating layer may be deposited in the trenches. The insulation lining may be made of a material which has a high thermal conductivity but is electrically insulating. The n and p thermocouples are electrically connected by means of a contact plate or a conductive plate so that they each form the partially embedded thermocouples. A series circuit layer electrically connects the plurality of thermocouples on the handling side of the substrate. A current source supplies electrical power to the series circuit layer and supplies current flowing through the plurality of series-connected thermocouples. A heat sink is positioned adjacent the bonded thermocouples and dissipates heat from the device side of the substrate.

The embodiments of the present disclosure do not require moving components or cooling devices, such as a liquid pump, that can be used to cool three-dimensional ICs. The trenches increase the surface contact with the substrate so that heat transfer to the heat sink unit is increased, so that cooling of the IC package is enhanced. The thermo-bars do not occupy the area of the substrate for the unit-level (or device-layer) side of the substrate, thus allowing the most efficient use of the unit level.

The descriptions of the various embodiments of the present invention have been presented by way of illustration, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, the practical application or technical improvement over the technologies available on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims (15)

Package of semiconductor devices comprising a plurality of thermocouples embedded in a semiconductor substrate, the thermocouples each having thermocouples positioned opposite each other and extending into the substrate from a handling side of a substrate facing a unit side of the substrate; the bars extend partially from the handling side of the substrate into the substrate, the opposing bars being a corresponding n-type and p-type; a thermally conductive insulating layer along a perimeter of the trenches and along outer sides of the bars; a conductive plate electrically connecting the n and p rods; a series circuit layer electrically connecting the plurality of thermocouples on the handling side of the substrate so as to be supplied with voltage through the series circuit layer; and a heat sink positioned to dissipate heat from the device side of the substrate to the heat sink by means of the thermocouples adjacent the thermocouples. The unit of claim 1, further comprising: a current source for supplying the series circuit layer with electric current so that the electric current flows through the plurality of thermocouples. The unit of claim 1, wherein the power source is electrically connected to the series circuit layer via silicon vias. The unit of claim 1, wherein the power source has a voltage source connected to the series circuit layer without using silicon vias. The unit of claim 1, wherein the conductive plate separates the n and p rods, defining a bottom of each of the trenches opposite the openings of the trenches on the handling side of the substrate. The unit of claim 1, wherein the opposed rods of the thermocouples are positioned in respective ones of a plurality of trenches in the substrate, each of the trenches defining an opening on a handling side of the substrate. The unit of claim 1, further comprising: a filler material deposited in each of the trenches between the n and p rods. The unit of claim 1, wherein the heat sink is a copper heat sink with fins. The unit of claim 1, wherein the series circuit layer is positioned between the thermocouples and the heat sink. The unit of claim 1, further comprising: a current source for supplying the series circuit layer with electric current so that the electric current through the plurality of thermocouples flows from each of the p-type rods through the conductive plate to the n-type rods and through the series of thermocouples. A method of fabricating a semiconductor substrate, comprising: Forming an n-bar and a p-bar opposed to each other and partially extending into the semiconductor substrate from a handling side of a substrate opposite to a unit side of the semiconductor substrate; Forming a conductive plate electrically connecting each pair of the n and p rods so as to form each of a plurality of thermocouples; Forming a series circuit layer electrically connecting the plurality of thermocouples to be supplied with voltage through the series circuit layer; and Positioning a heat sink adjacent to the thermocouples to dissipate heat from the device side of the substrate to the heat sink using the thermocouples. The method of claim 11, further comprising: Connecting a current source to supply the series circuit layer with electric current so that the electric current flows through the plurality of thermocouples. The method of claim 11, further comprising: Forming silicon vias in the substrate connected to the series circuit layer; and connecting the silicon vias to the power source. The method of claim 11, further comprising: Forming trenches extending partially from the handling side of the substrate into the substrate, the trenches defining an opening on the handling side of the substrate for each of the trenches; Depositing a thermally conductive insulating layer along a circumference of the trenches; Positioning the opposing n and p rods of the thermocouples in each of the plurality of trenches on opposite sides of each of the trenches; and Positioning the conductive plate electrically connecting each pair of the n and p rods so along a bottom of each of the trenches that each of the plurality of thermocouples is formed. The method of claim 11, wherein the current source includes a voltage source connected to the series circuit layer without using silicon vias. and or wherein the conductive plate connects the N-bars and the P-bars and defines a bottom of each of the trenches opposite the openings of the trenches on the handling side of the substrate, and or Depositing a filling material in the trenches between the n and p rods, and or wherein the heat sink is a copper heat sink with fins, and or wherein the series connection layer is positioned between the thermocouples and the heat sink, and or the method further comprising: Connecting a current source for supplying electrical power to the series circuit layer such that the electrical current through the plurality of thermocouples flows from each of the p-type rods through the conductive plate to the n-type rods and through the series of thermocouples.

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