DE102016124380A1 - Semiconductor device and method for manufacturing a semiconductor device - Google Patents

Abstract

A semiconductor device (1) is provided, comprising a semiconductor body (2) having a first semiconductor layer (3) and a second semiconductor layer (4), a first main surface (2A) and a second main surface (2B) opposite the first main surface (2A) first main surface (2A) is formed by a surface of the first semiconductor layer (3) and the second main surface (2B) is formed by a surface of the second semiconductor layer (4), at least one side surface (2C, 2D) having the first main surface (2A) the second main surface (2B), wherein the semiconductor body (2) has a roughening on the first main surface (2A), a metallic protective layer (7) comprising the second main surface (2B) and the at least one side surface (2C, 2D) at least partially covered, anda metallic start layer (8) disposed between the semiconductor body (2) and the metallic protective layer (7), the metallic protective layer (7) is applied directly and uninterrupted to the metal starting layer (8). Furthermore, a method for producing such a semiconductor device (1) is given.

Description

The invention relates to a semiconductor component and to a method for producing a semiconductor component.

Semiconductor components are possible which have a metallic encapsulation for the protection of their semiconductor body. If the encapsulation already partially dissipates in the course of the manufacturing process, then the finished semiconductor component is not adequately protected against moisture, for example.

An object to be solved in the present case is to specify a mechanically stable semiconductor component. Furthermore, a method for producing such a semiconductor device is specified.

In accordance with at least one embodiment, the semiconductor component comprises a semiconductor body having a first semiconductor layer and a second semiconductor layer. Furthermore, the semiconductor body has a first main area and a second main area opposite the first main area, wherein in particular the first main area is formed by a surface of the first semiconductor layer and the second main area is formed by a surface of the second semiconductor layer. In particular, the first main surface and the second main surface define the semiconductor body in a vertical direction.

Furthermore, the semiconductor body preferably has at least one side surface which connects the first main surface to the second main surface. In particular, the semiconductor body has a plurality of side surfaces. This is the case, for example, with a cuboid semiconductor chip. The at least one side surface is preferably arranged largely transversely to the first and second main surfaces. "Transverse" means that a normal vector of the side surface is not parallel to a normal vector of the first and / or second major surface. Preferably, the at least one side surface bounds the semiconductor body in a lateral direction. The lateral direction is transverse, in particular perpendicular, to the vertical direction.

The first semiconductor layer may have a first conductivity and the second semiconductor layer may have a second conductivity. Preferably, the first semiconductor layer is an n-type layer. Furthermore, the second semiconductor layer is, in particular, a p-conducting layer. The semiconductor body may have further semiconductor layers between the first and second semiconductor layers.

Preferably, the first main surface of a growth substrate at least partially, in particular completely, freed. The first and second semiconductor layers can be produced in layers successively on a growth substrate by means of an epitaxy process, which is then at least partially removed after the production of the semiconductor body, so that the first main surface or a surface of the first semiconductor layer is at least partially exposed. In particular, the direction in which the second semiconductor layer is grown on the first semiconductor layer denotes the vertical direction. As a rule, the first main surface has traces of the removal process, so that it is possible to draw conclusions about the original presence of a growth substrate. By detaching the growth substrate, the first main surface can already be provided with a roughening. In addition, the first main surface or a surface of the first semiconductor layer can be roughened in an additional step. Thus, the semiconductor body preferably has a roughening on the first main surface.

Furthermore, the semiconductor component may have a metallic protective layer. A "metallic protective layer" is to be understood as a protective layer which is formed from a metal or a metal compound and is distinguished by at least one of the following properties: high electrical conductivity, which decreases with increasing temperature; high thermal conductivity, ductility (ductility), metallic gloss (mirror gloss). Preferably, the second main surface and the at least one side surface are at least partially covered by the metallic protective layer. A "cover" means in particular that the metallic protective layer forms a predominantly closed surface which extends parallel to the second main surface and the first side surface. Advantageously, the semiconductor body is encapsulated by the metallic protective layer. Preferably, the second major surface is at least 80%, preferably at least 90%, covered by the metallic protective layer.

In a preferred embodiment, the protective layer extends from the second main surface to at least one side surface of the first semiconductor layer. In this case, side surfaces of the second semiconductor layer can be completely covered by the protective layer. Furthermore, at least one side surface of the semiconductor component is preferably formed in regions by a surface of the metallic protective layer. In particular, a plurality of side surfaces of the semiconductor device are formed in regions by surfaces of the metallic protective layer. The Semiconductor component is thus limited in the lateral direction by the protective layer partially.

Furthermore, the semiconductor component preferably comprises a metallic seed layer, which is arranged between the semiconductor body and the metallic protective layer, the metallic protective layer being applied directly to the metallic starting layer. Between the starting layer and the protective layer, therefore, preferably no further layer is arranged. Furthermore, the metallic protective layer is applied to the metallic starting layer advantageously without interruption. In particular, there are no voids between the starting layer and the protective layer, which cavities can form, for example, in the course of production by partial detachment of the starting layer.

The inventors have found that, in particular by wet-chemical treatment of the semiconductor body with an etchant, for example KOH, on the first main surface, as is the case, for example, when the semiconductor body is roughened on the first main surface, delamination may occur at the start layer. The cause of this is attributed to a too thin or insufficiently dense starting layer, which allows the penetration of etchant, which can penetrate to the protective layer. Due to the penetration of the etchant and the delamination caused thereby, voids or gaps may form between the semiconductor body and the starting layer as well as between the starting layer and the protective layer. These can be up to 300 nm wide. As a result, moisture can penetrate into the finished semiconductor device and damage it. To solve the problem, the inventors suggest a more stable starting layer. This can effectively prevent at least the formation of voids or gaps between the starting layer and the protective layer.

In accordance with at least one embodiment of the semiconductor component, the starting metal layer consists of a single layer. In particular, the metallic starting layer is produced from a single material. In this case, the starting layer preferably has a thickness of at least 100 nm, more preferably of 500 nm. The starting layer is advantageously made thicker than in an alternative embodiment and thus has a higher stability.

According to a further embodiment, the metallic starting layer comprises a first layer and a second layer, wherein the first and the second layer differ from one another by their material and / or their production process. The metallic starting layer can consist exclusively of the first and second layers. If the starting layer is formed in multiple layers, the individual layers can be made thinner than in the case of a single-layer starting layer. Preferably, the second layer is made thicker than the first layer. For example, the first layer may be formed with a thickness of at most 200 nm, while the second layer is formed with a thickness between 100 nm and 1000 nm. In the case of a multilayer starting layer, the total thickness is preferably at least 500 nm.

The second layer is preferably that layer of the starting layer adjacent to the protective layer. Suitable materials for the second layer are, in particular, materials which, in the case of the abovementioned wet-chemical treatment of the semiconductor body, exhibit a similar interaction with an etchant used as the protective layer. Suitable materials are, for example, Au, Pt, Rh or W. In particular, the second layer may be a galvanic or vapor-deposited layer.

Furthermore, the first or only layer can contain at least one of the materials Au, Ti or Pt or consist of one of these materials. In particular, the first layer is a sputtered layer.

In accordance with at least one embodiment, the metallic protective layer contains at least one of the materials nickel or copper or consists of one of these materials. Furthermore, the protective layer may have a thickness of between 5 μm and 50 μm inclusive, for example between 5 μm and 30 μm inclusive, approximately between 5 μm and 15 μm inclusive.

In accordance with at least one embodiment, the semiconductor component has at least one gap between the semiconductor body and the starting layer, which extends from the first main area along the side area in the direction of the second main area. This can have a width of up to 300 nm. Such a gap between the semiconductor body and the starting layer may arise despite a more stable starting layer. If the protective layer is also arranged without gaps on the starting layer, this can be regarded as an indication that the starting layer withstands the further penetration of the etchant towards the protective layer and is therefore sufficiently stable.

In accordance with at least one embodiment, the semiconductor component in the present case is an optoelectronic component. In this case, the semiconductor body preferably has an active zone which is used for radiation generation or for Radiation detection is suitable. In particular, the active zone is a pn transition zone. The active zone may be formed as a layer or as a layer sequence of several layers. For example, during operation of the semiconductor device, the active zone emits electromagnetic radiation, for example in the visible, ultraviolet or infrared spectral range. Alternatively, during operation of the semiconductor device, the active region may absorb electromagnetic radiation and convert it into electrical signals or electrical energy. The active zone is in particular arranged between the first semiconductor layer and the second semiconductor layer.

For the layers of the semiconductor body are preferably based on nitride compound semiconductors materials. "Based on nitride compound semiconductors" in the present context means that at least one layer of the semiconductor body comprises a nitride III / V compound semiconductor material, preferably Al _n Ga _m In _{1 nm} N, where 0 ≦ n ≦ 1, 0 ≦ m ≤ 1 and n + m ≤ 1. This material does not necessarily have to have a mathematically exact composition according to the above formula. Rather, it may comprise one or more dopants as well as additional constituents which do not substantially alter the characteristic physical properties of the Al _n Ga _m In _1-nm N material. For the sake of simplicity, however, the above formula contains only the essential constituents of the crystal lattice (Al, Ga, In, N), even if these may be partially replaced by small amounts of other substances.

The roughened first main surface preferably forms a radiation passage area of the semiconductor component. Advantageously, the radiation extraction or radiation coupling efficiency can be increased by the roughening against a smooth surface.

In accordance with at least one embodiment of the semiconductor component, the semiconductor body has at least one recess which extends from the second main area in the direction of the first main area and which ends in the first semiconductor layer. The recess is completely surrounded by the semiconductor body in lateral directions, for example. The semiconductor body may have a plurality of such recesses. Preferably, the metallic protective layer is arranged in the at least one recess. As a result, a plated-through hole can be formed, which serves for electrically contacting the first semiconductor layer from the side of the second main surface.

In accordance with at least one embodiment, the semiconductor component has on the side of the second main surface a first connection contact for electrical contacting of the first semiconductor layer and a second connection contact for electrical contacting of the second semiconductor layer. In this case, the first connection contact with the metallic protective layer may be electrically connected. Furthermore, the second terminal contact may be electrically insulated from the metallic protective layer and extend through it in the vertical direction. For the electrical insulation, in particular, an insulation layer is provided between the second terminal contact and the metallic protective layer.

In accordance with at least one embodiment, the semiconductor component has an integrally formed carrier body, on which the semiconductor body is arranged. In the vertical direction, the metallic protective layer is preferably arranged between the semiconductor body and the carrier body. In particular, the first and the second connection contact extend from the semiconductor body through the carrier body through to an outer surface of the carrier body. The outer surface is preferably arranged on a side of the carrier body facing away from the second main surface. The connection contacts are preferably completely enclosed by the carrier body in lateral directions.

The carrier body may be formed, for example, by a casting process. In particular, the carrier body is made of a castable plastic, such as a polymer such as resin, epoxy or silicone. Advantageously, the plastic material of the carrier body can be protected by the metallic protective layer, which is arranged between the semiconductor body and the carrier body, from the electromagnetic radiation of the semiconductor body, which leads, for example, to accelerated aging of the carrier body. A casting process is generally understood to mean a process by means of which a molding composition is preferably configured under pressure in accordance with a predetermined shape and, if necessary, cured. In particular, the term "casting method" includes molding, film assisted molding, injection molding, transfer molding, and compression molding.

• - Bereitstellen eines Halbleiterkörpers mit
  • - einer ersten Halbleiterschicht und einer zweiten Halbleiterschicht,
  • - einer ersten Hauptfläche und einer der ersten gegenüberliegenden zweiten Hauptfläche, wobei die erste Hauptfläche durch eine Oberfläche der ersten Halbleiterschicht und die zweite Hauptfläche durch eine Oberfläche der zweiten Halbleiterschicht gebildet wird,
  • - mindestens einer Seitenfläche, welche die erste Hauptfläche mit der zweiten Hauptfläche verbindet,
• - Ausbilden einer metallischen Startschicht auf der zweiten Hauptfläche und der mindestens einen Seitenfläche zumindest bereichsweise,
• - direktes Aufbringen einer metallischen Schutzschicht auf die metallische Startschicht, und
• - Bearbeitung des Halbleiterkörpers mittels eines Ätzmittels, so dass dieser an der ersten Hauptfläche mit einer Aufrauung versehen wird.

In accordance with at least one embodiment of a method for producing a semiconductor component, the latter has the following steps:

• - Providing a semiconductor body with
  • a first semiconductor layer and a second semiconductor layer,
  • a first major surface and one of the first opposing second major surface, wherein the first main surface is formed by a surface of the first semiconductor layer and the second main surface is formed by a surface of the second semiconductor layer,
  • at least one side surface connecting the first main surface to the second main surface,
• Forming a metallic starting layer on the second main surface and the at least one side surface at least in regions,
• - Direct application of a metallic protective layer on the metallic starting layer, and
• - Processing of the semiconductor body by means of an etchant, so that it is provided on the first main surface with a roughening.

The etchant used may penetrate into a region between the semiconductor body and the metal starting layer and form a gap which extends from the first main surface in the direction of the second main surface. Advantageously, however, the metallic starting layer is designed such that it can largely prevent further penetration of the etchant to the metallic protective layer, so that no further gap is formed between the metallic starting layer and the metallic protective layer. Thus, the protective layer is arranged without interruption on the starting layer.

According to at least one embodiment of the method, the first or only layer of the starting metallic layer is sputtered on. Furthermore, the second layer of the metallic starting layer can be applied to the first layer by means of a coating method, preferably by means of a galvanic coating method. However, it is also possible that the second layer is vapor-deposited.

In accordance with at least one embodiment of the method, the metallic protective layer is also applied to the metallic starting layer by means of a coating method, preferably by means of a galvanic coating method.

In addition, the connection contacts are preferably applied to the semiconductor body by means of a coating method, preferably by means of a galvanic coating method.

For producing a plurality of semiconductor components, a wafer composite may be provided which has a semiconductor layer sequence comprising a first and a second semiconductor layer, a plurality of first connection contacts, a plurality of second connection contacts and at least one or a plurality of contiguous metallic starting layers and metallic protective layers. The wafer composite may include a plurality of isolation trenches along which the wafer composite is separable into a plurality of semiconductor devices. A complete penetration of the semiconductor layer sequence through the separation trenches is not necessary. Instead, the separating trenches can extend through the second semiconductor layer and the active layer into the first semiconductor layer and end there. The first semiconductor layer can be partially removed during the roughening, so that separate semiconductor body or semiconductor components are formed. Alternatively, it is also possible for the isolation trenches to extend through the entire wafer composite in the vertical direction, so that separate semiconductor bodies or semiconductor components are already formed by the formation of the isolation trenches.

In accordance with at least one embodiment of a method for producing one or a plurality of the semiconductor components described here, a carrier body composite is formed on the wafer composite. To form the carrier body composite, a material suitable for this purpose is applied to the wafer composite such that the separation trenches and intermediate regions between the connection contacts are at least partially or completely filled up. In a subsequent method step, the wafer composite and the carrier body composite are separated along the separation trenches into a plurality of semiconductor components such that the semiconductor components each have a semiconductor body, a metal starting layer, a metallic protective layer and a carrier body, wherein in the carrier body a first terminal contact and a second Connection contact are embedded.

The method described above is particularly suitable for the production of one or a plurality of the semiconductor components described here. Therefore, features described in connection with the semiconductor device can also be used for the method and vice versa.

Further advantages, preferred embodiments and further developments of the method and of the semiconductor component will become apparent from the following in connection with FIGS 1 to 7B explained embodiments.

• 1 bis 3 verschiedene Ausführungsbeispiele eines Halbleiterbauelements in schematischen Schnittansichten,
• 4 ein Ausführungsbeispiel eines alternativen Halbleiterbauelements in einer schematischen Schnittansicht,
• 5A eine Rasterelektronenmikroskop-(REM-)Aufnahme eines alternativen Halbleiterbauelements und 5B eine Rasterelektronenmikroskop-(REM-)Aufnahme eines bevorzugten Halbleiterbauelements,
• 6A und 6B ein Zwischenstadium eines Verfahrens zur Herstellung beziehungsweise eines Halbleiterbauelements gemäß einem Ausführungsbeispiel in einer schematischen Draufsicht (6A) und einer Schnittansicht (6B), und
• 7A und 7B ein weiteres Zwischenstadium eines Verfahrens zur Herstellung beziehungsweise eines Halbleiterbauelements gemäß einem Ausführungsbeispiel in einer schematischen Draufsicht (7A) und einer Schnittansicht (7B).

Show it:

• 1 to 3 various embodiments of a semiconductor device in schematic sectional views,
• 4 an embodiment of an alternative semiconductor device in a schematic sectional view,
• 5A a scanning electron microscope (SEM) image of an alternative semiconductor device and 5B a scanning electron microscope (SEM) image of a preferred semiconductor device,
• 6A and 6B an intermediate stage of a method for the production or a semiconductor component according to an embodiment in a schematic plan view ( 6A ) and a sectional view ( 6B ), and
• 7A and 7B 1 is a further intermediate stage of a method for the production or a semiconductor component according to an exemplary embodiment in a schematic plan view (FIG. 7A ) and a sectional view ( 7B ).

1 shows a first embodiment of a semiconductor device described here 1 , Preferably, the semiconductor device is 1 to an opto-electronic semiconductor device. The semiconductor device 1 comprises a semiconductor body 2 with a first semiconductor layer 3 and a second semiconductor layer 4 , Furthermore, the semiconductor body 2 a first main area 2A and one of the first major surfaces 2A opposite second major surface 2 B on, being the first major surface 2A through a surface of the first semiconductor layer 3 and the second major surface 2 B through a surface of the second semiconductor layer 4 is formed. In addition, the semiconductor body 2 several side surfaces 2C . 2D on which the first major surface 2A with the second main surface 2 B connect. In particular, limit the first major area 2A and the second major surface 2 B the semiconductor body 2 in a vertical direction V while the side surfaces 2C . 2D the semiconductor body 2 in lateral direction L limit. The lateral direction L runs transversely, in particular perpendicular, to the vertical direction V ,

Between the first semiconductor layer 3 and the second semiconductor layer 4 has the semiconductor body 2 an active zone 5 on, which is preferably provided for generating radiation. In particular, the active zone 5 a pn transition zone. The active zone 5 can be formed as a layer or as a layer sequence of multiple layers. For example, the active zone emits 5 during operation of the semiconductor device 1 electromagnetic radiation, for example in the visible, ultraviolet or infrared spectral range. In particular, the electromagnetic radiation is predominantly on the first main surface 2A from the semiconductor device 1 decoupled.

Preferably, the semiconductor body 2 at the first main area 2A from a growth substrate 3A (compare to this 6B and 7B ) at least partially, in particular completely, freed. Advantageously, the semiconductor body 2 at the first major surface 2A a roughening up. This is due to the first major surface 2A a plurality of structural elements 6 which advantageously improve the radiation extraction efficiency. In particular, the structural elements 6 are arranged irregularly, that is to say that their arrangement does not follow a periodic pattern. Furthermore, the structural elements can 6 in their size, that is, in their height and / or width, differ from each other, wherein the height of a maximum extent in the vertical direction V and the width of a maximum extent in the lateral direction L equivalent.

Furthermore, the semiconductor component comprises 1 a metallic protective layer 7 , which is the second main area 2 B and the side surfaces 2C . 2D of the semiconductor body 2 at least partially covered. In this case, the protective layer extends 7 from the second major surface 2 B over side surfaces of the second semiconductor layer 4 out to side surfaces of the first semiconductor layer 3 , Furthermore, side surfaces 1A . 1B of the semiconductor device 1 partially by surfaces of the metallic protective layer 7 educated. Advantageously, the metallic protective layer forms 7 an encapsulation of the semiconductor body 2 and protects it from damage.

Furthermore, the semiconductor component comprises 1 a metallic starting layer 8th between the semiconductor body 2 and the metallic protective layer 7 is arranged, wherein the metallic protective layer 7 on the metallic starting layer 8th applied directly and without interruption. Between the start layer 8th and the protective layer 7 Thus, preferably no further layer is arranged. Furthermore, the metallic protective layer 7 on the metallic starting layer 8th applied with interruption without interruption. So there are between the start layer 8th and the protective layer 7 in particular, no cavities or gaps, for example, in the course of production by partial detachment of the starting layer 8th can form.

In this context, on the 4 . 5A and 5B directed. 4 shows an alternative semiconductor device 1 that compared to the in 1 shown semiconductor device a less densely formed starting layer 8th having. This is formed in a single layer with a thickness of, for example, less than 100 nm. As a result, occur in the course of manufacture at the starting layer 8th by penetration of etchant delaminations, which occur both between the semiconductor body 2 and the starting layer 8th as well as between the start layer 8th and the protective layer 7 to cavities 9 or columns 9 to lead. These can be up to 300 nm wide, with the width B a maximum extension of the gap 9 in lateral direction L designated. Because of the columns 9 For example, moisture may be introduced into the finished semiconductor device 1 invade and damage this.

5A shows a section of the cross section of an alternative semiconductor device in a SEM micrograph. The semiconductor device has a first and a second gap 9 on, extending from the first major surface 2A in the direction of the second main surface 2 B extend. The first gap 9 in the area of the second main area 2 B is better recognizable than in the area of the first main area 2A , located between the semiconductor body 2 and the starting layer 8th , The second gap 9 is located between the start layer 8th and the protective layer 7 ,

5B shows a section of the cross section of a semiconductor device according to a preferred embodiment in an SEM image. The second gap 9, which in the alternative in 5A shown semiconductor device between the starting layer 8th and the protective layer 7 occurs, is no longer available here. On the other hand, the first gap 9 that is between the semiconductor body 2 and the starting layer 8th is still occurring. This can be considered as an indication that the starting layer 8th the further penetration of etchant to the protective layer 7 withstand and thus is sufficiently stable.

At the in 1 illustrated embodiment, the semiconductor device 1 neither a first gap nor a second gap. The starting layer 8th is formed sufficiently stable, in particular the formation of a second gap between the starting layer 8th and the protective layer 7 to prevent. The starting layer 8th is at the in 1 illustrated embodiment formed in two layers. It points to a semiconductor body 2 facing side, a first layer 8A and on one of the protective layers 7 facing side, a second layer 8B on. The first shift 8A and the second layer 8B may differ from one another by their material and / or their manufacturing process. For example, the first layer 8A sputtered while the second layer 8B on the first layer 8A is applied galvanically. Suitable materials for the first layer 8A are for example Au, Ti or Pt. Suitable materials for the second layer 8B For example, Au, Pt, Rh or W.

Preferably, the second layer 8B thicker than the first layer 8A , For example, the first layer 8A may have a thickness D1 of at most 200 nm, while the second layer having a thickness D2 is formed between 100 nm and 1000 nm. Preferably, in a multilayer starting layer 8th the total thickness is at least 500 nm. The thickness of a layer denotes its maximum extent perpendicular to a main plane of extension of the layer. For example, the starting layer indicates 8th a main extension plane parallel to the second major surface 2 B is arranged. The fat D the starting layer 8th is determined by its maximum extent in the vertical direction V , The starting layer 8th has further main extension planes parallel to the side surfaces 2C . 2D are arranged. The fat D the starting layer 8th is then determined by its maximum extent in the direction of the surface normal of the side surfaces 2C, 2D. In particular, the thickness of the starting layer remains 8th on the side surfaces 2C . 2D compared to their thickness on the second major surface 2 B essentially, that is within the scope of the usual manufacturing tolerances, constant.

The metallic protective layer 7 At least one of the materials comprises nickel or copper or consists of one of these materials. At the metallic protective layer 7 it is in particular a galvanic layer. Furthermore, the protective layer 7 have a thickness D3 of between 5 μm and 50 μm inclusive, for example between 5 μm and 30 μm inclusive, approximately between 5 μm and 15 μm inclusive.

The semiconductor device 1 points to the side of the second main surface 2 B a first connection contact 10 for electrically contacting the first semiconductor layer 3 and a second terminal contact 11 for electrically contacting the second semiconductor layer 4 on. In this case, the first connection contact 10 with the metallic protective layer 7 be electrically connected. Furthermore, the semiconductor body 2 have at least one recess extending from the second major surface 2 B in the direction of the first main surface 2A extends and in the first semiconductor layer 3 ends (compare this 6A ). Preferably, the metallic protective layer extends 7 into the recess and forms a via, which is used for electrical contacting of the first semiconductor layer 3 from the side of the second main surface 2 B her serves. Furthermore, the second connection contact 11 in the vertical direction through the protective layer 7 extend through and between them by a between the protective layer 7 and the connection contact 11 arranged insulation layer 12 be electrically isolated. The insulation layer 12 may be formed of an electrically insulating material such as silicon oxide and / or silicon nitride.

Furthermore, the semiconductor device 1 an integrally formed carrier body 13 on, on which the semiconductor body 2 is arranged. In the vertical direction V is between the semiconductor body 2 and the carrier body 13 the metallic protective layer 7 arranged. The first and the second connection contact 10 . 11 extend from the semiconductor body 2 through the carrier body 13 through to an outer surface 13A of the carrier body 13 on one of the second main surface 2 B opposite side of the carrier body 13 is arranged. The connection contacts 10 . 11 become of the carrier body 13 in lateral directions L completely enclosed.

The semiconductor device 1 may be between the semiconductor body 2 and the start layer 8th have further layers. For example, a connection layer 14 be provided directly to the second semiconductor layer 4 borders. The connection layer is preferred 14 formed of an electrically conductive and highly reflective material. For example, the connection layer 14 an electrically conductive mirror layer. For example, the connection layer 14 Ag contain or consist of. However, it is also possible that the connection layer 14 is formed from a transparent conductive oxide (transparent conductive oxides, in short "TCO") such as zinc oxide.

Further, adjacent to the terminal layer 14 a current spreading layer 15 be arranged. The current spreading layer 15 can be formed as a layer stack of several metal layers. In particular, the current spreading layer 15 Metals such as platinum, gold and / or titanium have.

In addition, between the start layer 8th and the semiconductor body 2 a passivation layer 16 be provided. The passivation layer 16 can thereby the semiconductor body 2 , the connection layer 14 and the current spreading layer 15 partially, in particular completely cover.

In 2 is another embodiment of a semiconductor device 1 represented by the in 1 shown semiconductor device only by the metallic starting layer 8th different. The metallic starting layer 8th is at the in 2 illustrated embodiment of a single layer. In other words, the starting metallic layer exists 8th from a single layer. The metallic starting layer 8th is preferably formed from a single material. For example, the starting layer 8th contain one of the materials Au, Ti or Pt or consist of one of these materials. Preferably, the starting layer 8th a thickness D of at least 100 nm, more preferably of 500 nm. The starter layer is an advantage 8th thicker than in the alternative embodiment and thus has a higher stability. In particular, it is the starting layer 8th around a sputtered layer.

In 3 is another embodiment of a semiconductor device 1 represented by the in 1 shown differs in that it is between the semiconductor body 2 and the starting layer 8th at least one gap 9 which extends from the first major surface 2A along the side surface 2C, 2D in the direction of the second major surface 2 B extends. The gap 9 can be a width B of up to 300 nm. Such a gap 9 between the semiconductor body 2 and the starting layer 8th can despite stable start layer 8th arise. Because the protective layer 7 at the same time without a gap on the start layer 8th is arranged, is the starting layer 8th However, sufficiently stable trained.

The 6A and 6B illustrate an intermediate stage of a method of manufacturing or a semiconductor device described herein. 6A shows the unfinished semiconductor device 1 in plan view of the second main surface 2 B of the semiconductor body 2 , 6B shows a cross section of the unfinished semiconductor device 1 along in FIG 6A represented line AA '.

As in the 6A and 6B can be seen, the semiconductor body 2 several recesses 17 on. The recesses 17 can each be from the second major surface 2 B in the direction of the first main surface 2A extend and in the first semiconductor layer 3 end up. The recesses 17 become in lateral directions L completely from the semiconductor body 2 surround. In the recesses 17 becomes the metallic protective layer 7 arranged. Furthermore, the passivation layer becomes 16 such on the semiconductor body 2 applied to these in lateral directions L between the semiconductor body 2 and the metallic protective layer 7 located. In particular, the semiconductor body becomes 2 in the area of the active zone 5 from the passivation layer 16 covered. On the other hand, the passivation layer indicates 16 at the bottom of the recess 17 preferably an opening so that the metallic protective layer 7 in direct contact with the first semiconductor layer 3 stands.

The 7A and 7B illustrate another intermediate stage of a method for manufacturing or a semiconductor device described herein. 7A shows the unfinished semiconductor device 1 in plan view of the second main surface 2 B of the semiconductor body 2 , 7B shows a cross section of the unfinished semiconductor device 1 along the in 7A represented line BB '.

On the semiconductor body 2 are already the metallic starting layer 8th and the metallic protective layer 7 educated. The starting layer 8th can by sputtering on the passivation layer 16 be applied. The metallic protective layer 7 can by means of a galvanic coating process on the starting layer 8th be applied. After forming the metallic protective layer 7 can this with at least one opening 18 be provided. In the finished semiconductor device 1 is in this opening 18 the second connection contact 11 arranged (compare 1 to 3 ).

In a further method step (not shown), the semiconductor body 2 at the first main area 2A roughened, reducing the structural elements 6 (see 1 to 3 ) be formed. In particular, the surface of the first semiconductor layer becomes 3 structured by wet-chemical treatment using an etchant such as KOH.

The invention is not limited by the description with reference to the embodiments. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

1

Semiconductor device

1A, 1B

side surface

2

Semiconductor body

2A

first main area

2 B

second main surface

2C, 2D

side surface

3

first semiconductor layer

3A

growth substrate

4

second semiconductor layer

5

active zone

6

structural element

7

metallic protective layer

8th

metallic starting layer

8A

first layer of the metallic starting layer

8B

second layer of the metallic starting layer

9

Cavity, gap

10

first connection contact

11

second connection contact

12

insulation layer

13

support body

13A

outer surface

14

connection layer

15

Current spreading layer

16

passivation

17

recess

18

opening

B

width

D, D1, D2

Thickness, total thickness

V

vertical direction

L

lateral direction

Claims (15)

Semiconductor component (1) comprising - A semiconductor body (2) with a first semiconductor layer (3) and a second semiconductor layer (4), a first major surface (2A) and a second major surface (2B) opposite the first major surface (2A), the first major surface (2A) passing through a surface of the first semiconductor layer (3) and the second major surface (2B) through a surface of the second Semiconductor layer (4) is formed, at least one side surface (2C, 2D) connecting the first main surface (2A) to the second main surface (2B), wherein the semiconductor body (2) has a roughening on the first main surface (2A), - A metallic protective layer (7), the at least partially covering the second main surface (2B) and the at least one side surface (2C, 2D), and - A metallic starting layer (8), the - Between the semiconductor body (2) and the metallic protective layer (7) is arranged, wherein the metallic protective layer (7) on the metallic starting layer (8) is applied directly and without interruption. A semiconductor device (1) according to the preceding claim, wherein the starting metallic layer (8) consists of a single layer having a thickness (D) of at least 500 nm. Semiconductor device according to Claim 1 wherein the starting metallic layer (8) comprises a first layer (8A) and a second layer (8B), wherein the first and second layers (8A, 8B) differ from one another by their material and / or their manufacturing process. Semiconductor component (1) according to the preceding claim, wherein the second layer (8B) contains at least one of the materials Au, Pt, Rh or W or consists of one of these materials. Semiconductor component (1) according to Claim 3 or 4 wherein the second layer (8B) is a galvanic or vapor deposited layer. Semiconductor component (1) according to one of Claims 2 to 5 in which the first or only layer (8A, 8) contains at least one of the materials Au, Ti or Pt or consists of one of these materials. Semiconductor component (1) according to one of Claims 2 to 6 wherein the first or only layer (8A, 8) is a sputtered layer. Semiconductor component (1) according to one of the preceding claims, wherein the metallic protective layer (7) contains at least one of the materials nickel or copper or consists of one of these materials. Semiconductor component (1) according to one of the preceding claims, wherein the metallic protective layer (7) extends from the second main surface (2B) to at least one side surface (2C, 2D) of the first semiconductor layer (3). Semiconductor component (1) according to one of the preceding claims, comprising between the semiconductor body (2) and the starting layer (8) at least one gap (9) extending from the first major surface (2A) along the side surface (2C, 2D) in the direction the second major surface (2B) extends. Semiconductor component (1) according to one of the preceding claims, wherein the semiconductor body (2) has at least one recess (17) which extends from the second main surface (2B) in the direction of the first main surface (2A) and which in the first semiconductor layer (3 ), wherein in the recess (17), the metallic protective layer (7) is arranged. Semiconductor component (1) according to one of the preceding claims, which has on the side of the second main surface (2B) a first connection contact (10) for electrical contacting of the first semiconductor layer (3) and a second connection contact (11) for electrical contacting of the second semiconductor layer (4 ), wherein the first connection contact (10) is electrically conductively connected to the metallic protective layer (7). Semiconductor component (1) according to the preceding claim, which has an integrally formed carrier body (13) on which the semiconductor body (2) is arranged, wherein the first and the second connection contact (10, 11) extend through the carrier body (13) up to an outer surface (13A) of the carrier body (13) extend. Method for producing a semiconductor component (1) according to one of the preceding claims, comprising the following steps: - Providing a semiconductor body (2) with a first semiconductor layer (3) and a second semiconductor layer (4), a first major surface (2A) and a second major surface (2B) opposite the first major surface (2A), the first major surface (2A) passing through a surface of the first semiconductor layer (3) and the second major surface (2B) through a surface of the second Semiconductor layer (4) is formed, at least one side surface (2C, 2D) which connects the first main surface (2A) to the second main surface (2B), Forming a metallic starting layer (8) on the second main surface (2B) and the at least one side surface (2C, 2D) at least in regions, - Direct application of a metallic protective layer (7) on the metallic starting layer (8), and - Processing of the semiconductor body (2) by means of an etchant, so that it is provided on the first main surface (2A) with a roughening. Method according to the preceding claim, wherein the etchant penetrates into a region between the semiconductor body (2) and the starting metal layer (8) and forms a gap (9) extending from the first main surface (2A) towards the second main surface (2B ).

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