DE102016118932B3 - DC buck converter - Google Patents

Abstract

The invention relates to a method for DC-DC converter control with a voltage input (Vin) and a voltage output (Vout) according to a constant-on or constant-off-time method, which has at least one switch (S1) for converting the voltage and wherein the times the periodic opening and closing of the switch (S1) by means of a switching signal (SS1). depend on the potential profile at its voltage output (Vout). The duration (TE) of the on-time (TE) is constant in the case of a constant-on-time method or the duration (TA) of the off-time (TA) in the case of a constant-off-time method. The potential of an internal voltage signal (Vi) whose potential depends on the output voltage at the voltage output (Vout) is detected by a comparator (COMP) and compared with a reference voltage (Ref). This generates a comparator output signal (Cs). The time in which the comparator output signal (Cs) is in the state ("ON") is extended to a minimum time for generating the switching signal (SS1) in the case of a constant on-time method. The time in which the comparator output signal (Cs) is in the state ("OFF") is extended to a minimum time for generating the switching signal (SS1) in the case of a constant-off-time method. An offset voltage (Voff) is generated in response to the switching signal (SS1) between the potential at the voltage output (Vout) and the internal voltage signal (Vi) to produce this internal voltage signal (Vi).

Description

introduction

The invention relates to a DC buck converter and is also applicable to other architectures in which the ON time or OFF duration of a switch is constant and the other variable is regulated as a function of the potential at a voltage output. In the invention, the basic construction is a DC-DC converter comprising a constant-on-time regulator. The off-time is adjusted in this type of voltage regulator and readjusted by a control loop in the way, so that the desired output voltage at the voltage output (V _out ) sets the DC-DC converter. The on-time to which the switch (S ₁ ) is turned on, that is closed, is constant. Hence the English name Constant-On-Time-Regulator. Of course, this principle of the prior art can also be used for voltage regulators with a constant off-time and a controlled on-time. The corresponding designation is Constant-Off-Time-Regulator. Although the following description of the invention describes a DC-DC voltage regulator having a basic structure including a constant on-time voltage regulator for convenience of description, the invention relates to both types of voltage regulators. Voltage regulators with constant off-time are therefore also included in the invention. Such voltage regulators are also referred to as pulse-frequency controllers or pulse-frequency converters or PFM controllers.

Such a voltage regulator of the prior art is in 1 shown. The input voltage at the voltage input (V _in ) of the voltage regulator is periodically electrically connected to an intermediate node (Z ₁ ) by a first switch (S ₁ ) in response to a switching signal (SS ₁ ) or disconnected from this intermediate node (Z ₁ ). This happens with a time switching period (T _p ). During the duration of a time period (T _p ), the first switch (S ₁ ) is closed for the duration of an on-time (T _E ) and open for the duration of an off-time (T _A ). The time sum of on-time (T _E ) and off-time (T _A ) results in neglecting the switching edges, the switching period (T _P ). The skilled person is apparent that the use of semiconductor switches such as MOS transistors, as the first switch (S ₁ ) is particularly advantageous. From the intermediate node (Z ₁ ) flows a coil current (I _L ) through a choke coil (L ₁ ), which connects the intermediate node (Z ₁ ) to the voltage output (V _out ). A storage capacity (C ₁ ) stabilizes the voltage at the voltage output (V _out ). This storage capacity (C ₁ ) is connected to a first terminal via a resistor (R _ESR ) to the voltage output (V _out ). The second terminal of the storage capacitor (C ₁ ) is connected to a reference potential. The resistor (R _ESR ) is required for circuit stability. This resistor (R _ESR ) from the prior art leads to a superimposed triangular signal, which is superimposed on the temporal potential curve at the voltage output (V _out ). Here is an example of the US 8,698,469 B1 directed. The voltage at the voltage output (V _out ) is in the prior art equal to the internal voltage signal (V _i ), which will be separated according to the invention from this. A comparator (COMP) compares this internal voltage signal (V _i ) with a reference voltage (Ref) and forms the associated comparator output signal (C _s ), which is preferably value-discrete with typically two possible output states. A pulse extension unit (PV) forms a pulse with a minimum time length on its output signal, the switching signal (SS ₁ ) from an edge that is either rising or falling (depending on the voltage regulator type). By this minimum time length, the constant on-time (T _E ) in the case of a constant-on-time controller, or the constant off-time (T _A ) is set in the case of an alternative constant-off-time controller.

Although the simplest method thus consists of a measurement of the output voltage as the manipulated variable of the voltage regulator and a readjustment of the off-time (constant on-time regulator), a problem is the resistance (R _ESR ) (ESR = equivalent series resistance = equivalent Series resistor) before the storage capacitor (C ₁ ) capacitor, because otherwise the system has no information about the electrical coil current (I _L ) through the choke coil (L ₁ ). The function of the ESR resistor (R _ESR ) is to optimize the control behavior.

• 1. Auf der Ausgangsspannung am Spannungsausgang (V_out) entsteht ein dem konstanten Spannungspegel überlagertes periodisches Dreieckssignal, das durch den über den Widerstand (R_ESR) abfallenden Lade- und Entladestrom der Speicherkapazität (C₁) hervorgerufen wird. Dieses Dreieckssignal entsteht aufgrund der durch die Drosselspule erzwungenen Stromkonstanz und der Integration durch die Speicherkapazität (C₁). Bei einer Zustandsänderung des Schaltsignals (SS₁) von „AN“ nach „AUS“ und umgekehrt wechselt auch die Steigung dieses überlagerten Dreieckssignals.
• 2. Der Widerstand (R_ESR) ist zunächst der parasitische Zuleitungswiderstand der Speicherkapazität (C₁), der relativ undefiniert ist. Daher wird oft ein überdimensionierter zusätzlicher ESR-Widerstand (R_ESR) in Serie zum Kondensator eingebaut. Um den Ausgangswiderstand des Systems gering zu halten, werden kleine Widerstandswerte bevorzugt. Ein 20mOhm Widerstand (R_ESR) ist aber erfahrungsgemäß relativ teuer.

This use of the resistor (R _ESR ), as is common in the art, has two disadvantages:

• 1. On the output voltage at the voltage output (V _out ) results in a constant voltage level superimposed periodic triangular signal, which is caused by the across the resistor (R _ESR ) falling charge and discharge current of the storage capacity (C ₁ ). This triangular signal is due to the forced by the choke coil current constancy and integration by the storage capacity (C ₁ ). When the switching signal (SS ₁ ) changes from "ON" to "OFF" and vice versa, the slope of this superimposed triangular signal also changes.
• 2. The resistance (R _ESR ) is initially the parasitic lead resistance of the storage capacitance (C ₁ ), which is relatively undefined. Therefore, an oversized additional ESR resistor (R _ESR ) is often installed in series with the capacitor. To keep the output resistance of the system low, small values of resistance are preferred. However, experience has shown that a 20mOhm resistor (R _ESR ) is relatively expensive.

From the US 2013 0 099 761 A1 A method for controlling a switched-mode power supply (SMPS) is already known, which bypasses the resistor (R _ESR ) and comprises the following steps: The output signal of the switched-mode power supply is regulated by a first control signal and a second control signal. A current ramp signal is generated according to the first control signal and the second control signal. This current ramp signal is converted to a voltage ramp signal by a resistor module. The first control signal and the second control signal are in response to the voltage ramp signal and in response to a feedback signal from the output of the switching power supply according to the method of US 2013 0 099 761 A1 readjusted. In this case, the resistance module comprises a feedback circuit, which comprises a voltage divider with two resistors. The voltage ramp signal is obtained by changing the resistance values of the two resistors in accordance with US 2013 0 099 761 A1 customized. At the same time reveals the US 2013 0 099 761 A1 a corresponding device.

The technical teaching of US 2013 0 099 761 A1 however, only allows operation in one quadrant. This in turn means that the device can only be operated in Constant-Off or Constant-On-Time mode. The device of US 2013 0 099 761 A1 is therefore either unable to deliver a 100% duty cycle or deliver a 0% duty cycle. The generated current ramp of the US 2013 0 099 761 A1 always has a sign. Their mean value is therefore different from 0A. (Please refer 6A and 6b of the US 2013 0 099 761 A1 ) This results in accordance with the technical teaching of US 2013 0 099 761 A1 a deviating from 0A mean and thus a non - vanishing control error (disadvantage of the 1 US 2013 0 099 761 A1 ). Furthermore, the included in the 7 of the US 2013 0 099 761 A1 proposed ramp generator an operational amplifier, which always has an offset, which also leads to a control error (disadvantage of the 2 US 2013 0 099 761 A1 ). By using the operational amplifier is in the US 2013 0 099 761 A1 proposed ramp generator slowly (disadvantage 3 of US 2013 0 099 761 A1 ). Thus, the regulation in the US 2013 0 099 761 A1 proposed only limited dynamics. The required accuracy leads to an increase in the area required for integration into a microelectronic circuit (disadvantage 4 of the US 2013 0 099 761 A1 ). The required speed must be compensated by an increased current consumption. In addition, the mentioned voltage divider (resistors with reference symbols R1 and R2 of the US 2013 0 099 761 A1 ) is also occupied with parasitic capacitances that significantly disrupt the control principle and slow down the controller massively (disadvantage of the 5 US 2013 0 099 761 A1 ). Therefore, for example, the ideal curve of the curves in the 6A and 6B of the US 2013 0 099 761 A1 not reached in reality. It was therefore recognized that the technical teaching of US 2013 0 099 761 A1 would lead to an integrated circuit with a larger chip area and an increased power consumption.

From the IEEE publication by C.C. CHUANG et. al. "A Buck Converter Using Accurate Synthetic Ripple Hysteresis Control Scheme" IEEE PEDS 2011, Singapore, 5-8-December 2011 (hereafter referred to as IEEE publication for short) is also known as a DC-DC converter with current-mode control. In whose 7 a synthetic ripple voltage generating circuit is disclosed which, on the one hand, the switching voltage at the voltage source side terminal of the throttle (reference L of the 7 IEEE Publication) via a voltage divider (reference R _id and R ₀ of 7 the IEEE publication) and, on the other hand, the output voltage (reference V _out of 7 IEEE Publication) and in an operational amplifier (reference numeral A _id der 7 the IEEE publication) compares and with the output signal a switching transistor for connecting and disconnecting a power source (reference I _b of 7 IEEE publication). The aim of this circuit is to control the occurring control hysteresis such voltage regulator. Together with a Umladekapazität (reference character C _SRM the 7 IEEE Publication) is by connecting and disconnecting the power source, the desired voltage ripple on the internal measuring node (reference V _sense of 7 the IEEE publication). This circuit has the disadvantage of requiring a direct tapping of the output side, which requires the use of high voltage circuitry, for example, when controlling voltages such as are required in automobiles. Again 11 According to the IEEE publication, the ripple generated in this way is not used to obtain the output voltage free of the ESR-related sawtooth-shaped signals, but exclusively for hysteresis optimization. The technique disclosed in the IEEE publication therefore does not solve the problem, but rather the problem to be solved remains (see 11 IEEE publication). Incidentally, the ESR problem is not mentioned in the text of the IEEE publication. It is also, as already mentioned, to a current-mode control and not a constant-on-time regulator. The operational amplifier circuit used (see 8th IEEE publication) is relatively slow and power consuming and therefore requires too much chip area.

Also in the synopsis solve both the IEEE publication as well as the US 2013 0 099 761 A1 the problem is not because both fonts require the use of an operational amplifier. The US 2013 0 099 761 A1 requires this for the generation of the current ramp (reference I _ramp the US 2013 0 099 761 A1 ). The IEEE publication requires this (reference number (A _id ) of the IEEE publication in their 7 ) to the output voltage of the half-bridge with the voltage behind the choke (reference L and DCR of the IEEE publication in their 7 ) to compare.

Object of the invention

The aim is to eliminate the output ripple and the additional ESR resistor (R _ESR ) without the disadvantages of the prior art (eg the five disadvantages of the US 2013 0 099 761 A1 and from the IEEE publication). The ESR resistor (R _ESR ) would otherwise interfere with its dispersion or the control would be too slow and too large. The need for the minimum resistance (R _ESR ) of the external storage capacity (C ₁ ) is to be eliminated, whereby ceramic capacitors can be used. In addition, a sufficient control speed must be made possible.

This object is achieved by a method according to claim 1.

Description of the invention

A basic idea of the invention is similar to that in the US 2013 0 099 761 A1 From the prior art, the ESR resistor (R _ESR ) operatively installed at another point in the control circuit and so to avoid the superimposed triangular signal on the potential of the voltage output (V _out ) by the charging and discharging of the storage capacity (C ₁ ).

From the US 8,698,469 B1 a method is known whose idea is to emulate the ESR resistance by means of suitable filter algorithms by means of a complicated digitized calculation method and to measure the output voltage and to digitize it for the calculation by means of an ADC. Here, the reference value is changed. However, the device according to the invention can be made substantially more compact without the reference value, according to the invention a reference voltage (Ref), is changed.

The invention relates to a method and a corresponding device for controlling a DC-DC converter according to a constant-on-time method or alternatively according to a constant-off-time method. The method comprises a plurality of steps, which are typically carried out in a time-parallel or quasi-parallel manner in any order and fast sequence cyclically. As a first step, the device according to the invention comprises the periodically recurring closing and opening of a first switch (S ₁ ) between a voltage input (V _in ) and an intermediate node (Z ₁ ). This opening and closing of the first switch (S ₁ ) is controlled by means of a preferably discrete-value, time-continuous or time-discrete switching signal (SS ₁ ) with a switching period (T _P ). The switching period (TP) is in a on-time (T _E ), in which the switching signal (SS ₁ ) is on and the first switch (S ₁ ) is closed, and a subsequent off-time (T _A ), in the switch signal (SS ₁ ) is off and the first switch (S ₁ ) is open, split. The duration (T _E ) of the on-time (T _E ) is constant in the case of a constant on-time controller. In contrast, instead, the duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time regulator.

As a second step, the inventive method comprises the smoothing of the output current (I _out ), which flows out of the voltage output (V _out ), by means of a choke coil (L ₁ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ). A further step concerns the storage and / or the delivery of a charge quantity from the voltage output (V _out ) into or out of a storage capacity (C ₁ ). From the electrical potential, an internal voltage signal (V _i ) is generated whose voltage or at least its value depends on the potential at the voltage output (V _out ). This is done according to the invention by a capacitive / resistive voltage divider (C _i1 , C _i2 , R ₁ , R ₂ ) of a first capacitor (C _i1 ), a second capacitor (C _i2 ), a first voltage divider resistor (R ₁ ) and a second voltage divider resistor (R ₂ ). The use of voltage divider resistors (R ₁ , R ₂ ) is indeed from the US 2013 0 099 761 A1 known. The use of a parallel capacitive voltage divider is not previously known, since the control method of US 2013 0 099 761 A1 with a sawtooth-shaped current (reference Iramp der US 2013 0 099 761 A1 ) is working. Such a capacitive voltage divider would therefore lead to a deformation of the time course of the ramp. A capacitive coating of the internal voltage signal (V _i ) is in the technical teaching of US 2013 0 099 761 A1 just for that reason avoided. According to the invention, it has now been recognized that it makes sense to have such a capacitive voltage divider (C _i1 , C _i2 ) parallel to the ohmic voltage divider (R ₁ , R ₂ ) in contrast to US 2013 0 099 761 A1 be provided to readjust fast transients on the output voltage (V _out ) can. The use of this capacitive voltage divider is thus an essential step to disadvantage 5 of US 2013 0 099 761 A1 to fix. However, this has the consequence that the generation of the sawtooth-shaped voltage signal for ripple emulation no longer, as in the US 2013 0 099 761 A1 by a sawtooth current (reference Iramp der US 2013 0 099 761 A1 ) like in the US 2013 0 099 761 A1 can be done, but must be solved differently. A further inventive concept is therefore to use a current ramp generation known for example from the IEEE publication for a control loop in a switched mode power supply, the capacitive voltage divider (C _i1 , C _i2 ) assuming the role of integration capacity (reference number C _{SRM of} the IEEE publication) , Only through the use of this capacitive voltage divider instead of a simple integration capacity (reference number C _{SRM of} the IEEE publication) and the other method of the IEEE publication for generating the voltage ripple on the internal voltage signal (Vi) in combination with that of US 2013 0 099 761 A1 known ripple emulation method is the disadvantage of the 5 US 2013 0 099 761 A1 eliminated. A measuring device now detects the potential of the internal voltage signal thus generated (V _i), or its value. A comparator compares the value of the internal voltage signal (V _i ) with a threshold value (Ref). In the case of a voltage value, for example, a comparator (COMP) can compare the potential on the internal voltage line (V _i ) with a reference voltage (Ref) as the reference value. The comparison device or the comparator (COMP) generates as a result signal a comparator output signal (C _s ), which may have the value "on" or "off". Although one could already control the first switch (S ₁ ) with this signal. But then it would come to very short pulses, which would thus have a very broad signal spectrum and are generally not desirable for reasons of electromagnetic compatibility. Therefore, in a further step, the time in which the comparator output signal (Cs) is in the "on" state is extended to a minimum time by a pulse extension unit (PV). In this case, the pulse extension unit (PV) generates the switching signal (SS ₁ ), which controls the first switch (S ₁ ). This switching signal (SS ₁ ) is also preferably a discrete-value signal with two states, of which a first "ON" state closes the first switch (S ₁ ) and the second "OFF" state closes the first switch (S ₁ ) opens.

Now, in the method according to the invention by an additional device (I ₁ , I _s ), the above-mentioned triangular signal as voltage triangular signal or value triangular signal to the internal voltage signal (V _i ) is added, which emulates the effect of the resistor (R _ESR ). As a result, the generation of this superimposed triangular signal on the output voltage of the voltage output (V _out ) as in the US 2013 0 099 761 A1 avoided. The generation of a temporal voltage triangle signal in the temporal potential curve or the generation of a time value triangle signal in the temporal value curve of the internal voltage signal (V _i ) is thus carried out by adding this additional voltage triangular signal or value triangular signal time-synchronous to the opening and / or closing of the first switch (S ₁ ). In this case, said voltage divider (C _i1 , C _i2 ) serves as integration capacity for the controllable constant current sources (I ₁ , I _s ) for generating said voltage triangular signal or value triangular signal.

In contrast to the prior art and in particular in contrast to US 2013 0 099 761 A1 However, the node of this internal voltage signal (V _i ), which is connected in parallel to said capacitive voltage divider (C _i1 , C _i2 ) for generating the superimposed triangle signal but now additionally by a controllable constant current source (I _S ) with a constant during the charging process charged electrical current or discharged with a constant during the discharge electric current. The polarity of the electrical output current of the constant current source (I _S ) depends on the value of the switching signal (SS ₁ ), which controls the first switch (S ₁ ) from. By means of this controllable constant current source (I _s ), the effect of the superimposed triangular signal on the temporal potential curve at the voltage output (V _out ) now on the internal voltage signal (V _i ) is now decisive in comparison with FIG US 2013 0 099 761 A1 Simplified way emulated so that the internal voltage signal now in contrast to the potential curve at the voltage output (V _out ) has a very precise superimposed triangular signal in addition. Here, a very easily realizable, very compact switchable constant current source (I _s ) of a few electrical components in combination with a charging capacitance, the capacitor (C _i ), instead of the operational amplifier circuit of US 2013 0 099 761 A1 can be used, since instead of a current ramp now a rectangular current signal can be used, this solution according to the invention in all essential points of the solution US 2013 0 099 761 A1 technically and economically much superior.

In another embodiment of the invention, the method comprises generating an output current (I _Buf ) of a buffer circuit (Buf) for generating the internal voltage signal (V _i ). As before, this is again proportional to the voltage at the voltage output (V _out ). The generation of the output current (I _Buf ) is preferably carried out by this buffer circuit (Buf), which has an output resistance (R _a ). _Thereby flows an output current (I _Buf ) from the buffer circuit (Buf) in the accounts of the internal voltage signal (V _i ), of this output resistance (R _a ) of the buffer circuit (Buf) and the voltage difference between the potential at the output of the buffer circuit (Buf ) and the potential of the internal voltage signal (V _i ). This output current (I _Buf) of the buffer circuit (BUF) is loaded, a capacitor (C _i) or discharged. Thus, the voltage across this capacitor (C _i ) low-pass filtered and multiplied by a predetermined by the buffer circuit (Buf) factor of the output voltage at the voltage output (V _out ). In order to emulate the superimposed triangular signal at the potential of the voltage output (V _out ), the capacitor (C _i ) is briefly charged or discharged in this variant of the invention by means of the output current of a controllable bipolar constant current source (I _s ). Their polarity depends in this example on the switching signal (SS ₁ ). In order to avoid a continuous increase or decrease of the potential of the internal voltage signal and to obtain the signal quality of the output signal, which is useful for the typical use in motor vehicles, the time average of the current sum in the nodes of the internal voltage signal (V _i ) flowing in currents and the outflowing from this node currents in averaging in the steady state to a voltage change across the capacitor (C _i ) lead, which may not be more than 200μV. Of course, with a corresponding reduction in quality, larger values such as 400μV, 800μV or even 1.6V can be allowed. Conversely, the quality can be increased if the circuit is designed so that the variations are kept smaller than 100μV or even smaller than 50μV.

In a further embodiment of the invention, the potential of the internal voltage signal (V _i ) whose potential depends here also on the output voltage at the voltage output (V _out ) is compared by a comparator (COMP) with a reference voltage (Ref). The comparator (COMP) generates as a result of comparison the comparator output signal (C _s ), which depending on the result of the comparison may have the value "on" or "off", that is to say preferably a discrete-value binary signal. As before, a pulse extension unit (PV) extends the time in which the comparator output signal (C _s ) in the state "on" in the case of a constant on-time controller or in the state in the case of a constant-off-time controller. Off "is at a minimum time and generates the switching signal (SS ₁ ). In this case, a buffer circuit (Buf) generates an output current (I _Buf ) into the node of the internal voltage signal (V _i ) generated therewith. The internal voltage signal (V _i ) is proportional to the potential of the voltage output (V _out ) with respect to the reference potential except for the superimposed triangular signal described below. This base curve of the internal voltage signal (V _i ) forms a first voltage signal component of the internal voltage signal (V _i ). The buffer circuit (Buf) has an output resistance (R _a ) which is different from zero. Through this output resistance (R _a ), the internal voltage signal (V _i ) may be at a different potential than the output of the buffer circuit (Buf). This output current (I _Buf ) of the buffer circuit (Buf) is now used in this embodiment of the invention for charging a capacitor (C _i ). As a result, a potential of the internal voltage signal (V _i ) sets, which first substantially corresponds to the potential of the output of the buffer circuit (Buf) as the first voltage signal component of the internal voltage signal (V _i ).

This first voltage signal component (V _i ) has the said base profile. Typically, the buffer circuit (BUF) is designed so that the potential of its ideal resistance-free output of the buffer circuit (BUF), which excludes output resistance (R _a), directly proportional to the potential of the output voltage (V _out). In order to emulate the triangular signal at the output voltage (V _out ), a controllable constant current source (I _s ) of a first constant current source (I _s1 ) and a second constant current source (I _s2 ) additionally charges and discharges this capacitor (C _i ) by means of its output current and thus generates an additional falling or rising voltage ramp on the internal voltage signal (V _i ) as the second voltage signal component. The controllable first constant _{current source} (I _s1 ) is switched on and off depending on the switching signal (SS ₁ ), which also controls the first switch (S ₁ ) at the same time. In this variant of the invention, the capacitor (C _i ) is simultaneously charged or discharged by the second constant current source (I _s2 ) by means of its output current, the polarity of which also depends on the switching signal (SS ₁ ). Here, too, care must be taken that the mean value of the current sum of the currents flowing into the nodes of the internal voltage signal (V _i ) and the currents flowing out of this node leads to a voltage change at the capacitor (C _i ) when the steady-state averaging occurs, again not more than 200μV. The above with regard to this limit also applies here.

In a variant of the invention derived therefrom, the output current of the first controllable constant current source (I _s1 ), which is switched on and off depending on the switching signal (SS ₁ ), charges the capacitor (C _i ). The output current of the second controllable constant current source (I _s2 ), which is now switched on depending on the switching signal (SS ₁ ) only when the first constant current source (I _s1 ) is turned off, charges the capacitor (C _i ) and thus generates a third voltage signal component. It may also happen, for example, that both constant current sources (IS ₁ , IS ₂ ) are temporarily switched off at the same time.

Alternatively, it may be provided in another embodiment of the invention to charge or discharge the capacitor (C _i ) by means of the output current of a controllable constant current source (I _s ) whose polarity depends on the switching signal (SS ₁ ).

In another embodiment of the invention, a measuring current, preferably as output current (I _buff ) of said buffer circuit (Buf), in dependence on the output voltage at the voltage output (V _out ) is used to generate an internal voltage signal (V _i ) proportional to the Voltage at the voltage output (V _out ) is. The measuring current flows at least virtually through the output resistance (R _a ). The measuring current (I _Buf ) is thus generated by a sub-device, namely the buffer circuit (Buf), which has a small-signal output resistance (R _a ). With this _measurement current, namely the output current (I _Buf ) of the buffer circuit (Buf), one or more capacitors (C _i1 , C _i2 ) are now charged or discharged. According to the invention, these capacitors (C _i1 , C _i2 ) are additionally charged or discharged by means of the output current of a controllable constant current source (I _s ), the polarity of which depends on the switching signal (SS ₁ ), in order to generate the triangular signal on the potential curve of the voltage output (V _out ). , as it occurs in the prior art, pretend.

In addition to the previously described embodiments of the device and the method as a down converter, the invention can also be carried out as an up-converter.

The inventive method for controlling a DC-DC converter, which again has a voltage input (V _in ) and a voltage output (V _out ), can again as before according to a constant-on-time method with a constant on-time (T _E ) or alternatively be performed according to the constant-off-time method with a constant off-time (T _A ). The following steps can be performed in parallel or sequentially, preferably in quick succession in any order. A first step in this case relates to the smoothing of the input current (I _in ), which flows into the voltage input (V _in ), by means of a choke coil (L ₁ ) between an intermediate node (Z ₁ ) and the voltage input (Vin). A further step comprises the periodic, recurrent closing and opening of a first switch (S ₁ ) between this intermediate node (Z ₁ ) and a reference potential by means of a switching signal (SS ₁ ). The switching signal (SS ₁ ) again has a first state ("ON") and a second state ("OFF") and a switching period (T _P ). The switching period (T _P ) is again in an on-time (T _E ), in which the switching signal (SS ₁ ) in the first state ("ON") and the switch (S ₁ ) is closed, and a subsequent output Time (T _A ), in which the switching signal (SS ₁ ) in the second state ("OFF") and the switch (S ₁ ) is open, divided. The duration (T _E ) of the on-time (T _E ) is constant in the case of a constant-on-time method. The duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time method. A further step relates to the closing of a second switch (S ₂ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ) when the potential difference between the voltage output (V _out ) and the intermediate node (Z ₁ ) minus a voltage offset is a first And opening of the second switch (S ₂ ) when the potential difference between the voltage output (V _out ) and the intermediate node (Z ₁ ) less the voltage offset has a second sign opposite to the first sign. It is obvious to a person skilled in the art that it is particularly preferable to use a diode as the second switch (S ₂ ). This typically has a slip voltage from which the diode opens and lets current through. In the case of a diode as a second switch (S ₂ ), this lock voltage represents the voltage offset described here. Finally, the method comprises the storage and / or the discharge of a charge amount from the voltage output (V _out ) into one or more storage capacities (C ₁ ) into or out of these. Detecting the potential of an internal voltage signal (V _i ) whose potential depends on the output voltage at the voltage output (V _out ) versus a reference potential also belongs to the method. Typically, the detection is performed by an input of a comparator (COMP). This compares the potential at its input with a reference voltage (Ref) and generates a comparator output signal (C _s ) which, depending on the result of the comparison, may have a first state ("ON") or a second state ("OFF"). In the case of a constant-on-time method, a further step comprises extending a time in which the Comparator output signal (C _s ) in the first state ("ON") is at a minimum time for generating the switching signal (SS ₁ ) by a pulse extension unit (PV). Alternatively, in the case of a constant-off-time method, the method comprises extending a time in which the comparator output signal (C _s ) is in the second state ("OFF") to a minimum time for generating the switching signal (SS ₁ ) a pulse extension unit (PV).

In a first embodiment as Aufwärtswandelverfahren, the method is characterized in that it is the periodic generation of a temporal overlay signal, in particular a triangular signal, with the temporal switching period (T _p ) in the temporal potential curve of the internal voltage signal (V _i ) by adding an additional beat signal, in particular a triangular signal, time-synchronized to open and / or close the first switch (S ₁ ).

In contrast to the prior art, however, the node of this internal voltage signal (V _i ), which is connected to a capacitor (C _i ) for generating the superimposed triangle signal now but in addition by a controllable constant current source (I _S ) with a time constant electric charging current the constant current source (I _S ) is charged or discharged with a time constant electric discharge current of the constant current source (I _S ) whose polarity depends on the value of the switching signal (SS ₁ ), which controls the first switch (S ₁ ). The effect of the superimposed triangular wave on the temporal potential profile at the voltage output (V _out) is now on the internal voltage signal (V _i) by this controllable constant current source (I _s) is emulated such that the internal voltage signal is now in contrast to the potential profile at the voltage output (V _out) has a superimposed triangular signal in addition. Again, a very easily realizable, very compact switchable constant current source (I _s ) of a few electrical components in combination with a charging capacitance, the capacitor (C _i ), instead of the operational amplifier circuit of US 2013 0 099 761 A1 can be used, since instead of a current ramp now a rectangular current signal can be used, this solution according to the invention in all essential points of the solution US 2013 0 099 761 A1 technically and economically much superior.

In a second embodiment as Aufwärtswandelverfahren, the method is characterized by the periodic generation of a temporal beat signal, in particular a triangular signal, with the temporal switching period (T _p ) in the time course of the internal voltage signal (V _i ) by adding a suitable additional beat signal, in particular a triangular signal , time-synchronized to open and / or close the first switch (S ₁ ).

In a third embodiment as an up- _conversion method, the method is characterized by the generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) through this buffer circuit (Buf), which has an output resistance (R _a ) owns. The potential of the internal voltage signal (V _i ) is the voltage sum of a first voltage signal component and a second voltage signal component. The first voltage component is proportional to the voltage at the voltage output (V _out ). The _{step-up method} in this third embodiment comprises charging one or more capacitors (C _i1 , C _i2 ) with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component and charging the one or more capacitors (C _i1 , C _i2 ) by means of the output current of a controllable constant current source (Is), whose polarity depends on the switching signal (SS ₁ ), for generating the second voltage signal component.

In a fourth embodiment as an up- _conversion method, the method is characterized by the generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf), which has an output resistance (R _a ) owns. The potential of the internal voltage signal (V _i ) is the voltage sum of a first voltage signal component and a second voltage signal component and a third voltage signal component. The first voltage signal component is proportional to the voltage at the voltage output (V _out ). In this fourth embodiment, the _{boosting method} further comprises charging one or more capacitors (C _i1 , C _i2 ) with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component and charging the one or more capacitors (C _i1 , C _i2) off by means of the output current of a first controllable constant current source (I _S1) for generating said second voltage signal component, which depends (from the switching signal SS ₁₎ and is turned off and the charging of the or the capacitors (C _i1, C _i2) using the Output current of a third controllable constant current source (I _s3 ) for generating the third voltage signal component whose polarity depends on the switching signal (SS ₁ );

In a fifth embodiment as an up- _conversion method, the method is characterized by the generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf), which has an output resistance (R _a ) owns. The potential of the internal voltage signal (V _i ) is the voltage sum of the first voltage signal component and a second voltage signal component and a third voltage signal component. The first voltage signal component is proportional to the voltage at the voltage output (V _out ). The upconversion method in this fifth embodiment further comprises charging one or more capacitors (C _i1 , C _i2 ) with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component and charging the one or more capacitors (C _i1 , C _i2 ) by means of the output current of a first controllable constant current source (I _s1 ) for generating the second voltage signal component which is switched on and off depending on the switching signal (SS ₁ ) and the charging of the capacitor or capacitors (C _i1 , C _i2 ) by means of the output current a second controllable constant current source (I _s2 ) for generating the third voltage signal component which is switched on as a function of the switching signal (SS ₁ ) only when the first constant current source (I _s1 ) is switched off. Both constant current sources (I _S1 , I _S2 ) can be temporarily switched off at the same time.

In a sixth embodiment as an up- _conversion method, the method is characterized by the generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf), which has an output resistance (R _a ) owns. The potential of the internal voltage signal (V _i ) is the voltage sum of the first voltage signal component and a second voltage signal component. The first voltage signal component is proportional to the voltage at the voltage output (V _out ). The up- _{conversion method} further comprises, in this sixth embodiment, charging one or more capacitors (C _i1 , C _i2 ) with the output current (I _Buf ) of the buffer circuit (Buf) to generate the first voltage signal component and charging the one or more capacitors (C _i1 , C _i2 ) by means of the output current of a controllable constant current source (I _s ) whose polarity depends on the switching signal (SS ₁ ), for generating the second voltage signal component.

In a seventh embodiment as an up- _conversion method, the method is characterized by generating a _measurement current (I _Buf ) which is proportional to the voltage at the voltage output (V _out ) by means of a sub-device (Buf) having a small-signal output resistance (R _a ). In this seventh embodiment, the _{step-up method} further comprises charging one or more capacitors (C _i1 , C _i2 ) with the measuring current (I _Buf ) of the sub-device (Buf) to generate a first voltage signal component of the internal voltage signal (V _i ) and charging the or the capacitors (C _i1 , C _i2 ) by means of the output current of a controllable constant current source (I _s ) whose polarity depends on the switching signal (SS ₁ ), for generating a second voltage signal component of the internal voltage signal (V _i ).

In an eighth form as a step-up method, the method is characterized by the generation of an offset voltage (V _off ) in response to the switching signal (SS ₁ ) between the potential at the voltage output (V _out ) and the internal voltage signal (V _i ) to produce that internal voltage signal (V _i ).

Opposite the US 2013 0 099 761 A1 For example, the technical solution according to the invention described above has significant and significant economic and technical advantages.

In the technical teaching of US 2013 0 099 761 A1 is a ramp current (reference Iramp the US 2013 0 099 761 A1 ) to simulate the effect of the ripples. In order to produce this ramp precisely, the construction is carried out according to the technical teaching of US 2013 0 099 761 A1 based on an operational amplifier

By contrast, the switchable constant current sources proposed above are very simple to implement and, due to their simple construction, have a much smaller time constant than that in the US Pat US 2013 0 099 761 A1 proposed construction based on an operational amplifier. The US 2013 0 099 761 A1 suggests a said, difficult to implement current ramp (reference Iramp the US 2013 0 099 761 A1 ) in front. In addition, the inventive construction proposed here is in contrast to US 2013 0 099 761 A1 able to perform a two-quadrant control. As a result, the regulation proposed here with respect to the operational amplifier based solution of US 2013 0 099 761 A1 offset-free. Overall, the required chip area is smaller in the control method proposed here than in the method of US 2013 0 099 761 A1 and the power consumption in circuits according to the method proposed here is lower than in circuits according to the US 2013 0 099 761 A1 , The Indian US 2013 0 099 761 A1 proposed operational amplifier (reference AMP of US 2013 0 099 761 A1 ) typically consumes electrical current on the order of a few milliamps to meet precision and speed requirements corresponding to the technical solution presented here. The hie proposed inventive technical solution, however, comes out with a few μA. It is therefore an advantage in several orders of magnitude of the solution proposed here according to the invention towards the solution of US 2013 0 099 761 A1 , The precise realization of the constant current sources proposed here (I ₁ , I _s ) to internal capacitances (C _i ) is much easier to implement than the OP circuit of US 2013 0 099 761 A1 and that in the US 2013 099 761 A1 proposed methods.

The one of us in the 4 and 7 proposed constructions are in contrast to the construction of US 2013 0 099 761 A1 completely offset-free, since the coupling is done by the coupling capacitance C _k , which does not allow transmission of DC values.

• 1. Die Abbildung der Rampe des virtuellen ESRs erfolgt in beiden Schaltphasen (Anzeit und Auszeit)
• 2. Eine Überwachung/Auswertung vom Schaltausgang her ist nicht notwendig. Damit entfällt die Notwendigkeit einer chipflächenintensiven Hochvoltschaltungstechnik mit Hochvolt-Transistoren.
• 3. Es ist kein Operationsverstärker notwendig, welcher eine Strom-Rampe an seinem Ausgang ausgeben muss, was stromintensiv und schaltfrequenzbegrenzend wäre.
• 4. Es sind keine zusätzlichen externen Komponenten nötig. Die vorgeschlagene Lösung ist vollintegrierbar.

These advantages over the prior art can be summarized as follows:

• 1. The virtual ESR ramp is mapped in both switching phases (time-out and time-out)
• 2. Monitoring / evaluation from the switching output is not necessary. This eliminates the need for a chip-intensive high-voltage circuit technology with high-voltage transistors.
• 3. There is no need for an operational amplifier, which must output a current ramp at its output, which would be power-intensive and switching frequency limiting.
• 4. No additional external components are needed. The proposed solution is fully integrated.

The phrase mentioned in the claims periodic recurrent closing and opening a first switch should be interpreted in the sense of this document so that it is not a closing or opening at the same time intervals, but only a temporally recurring. In the stable control state with stable boundary conditions, however, a periodic opening and closing occurs. For example, during a load change, this temporal periodicity with a period that is constant over time is abandoned.

The invention is based on the 2 to 7 explained. The 2 and 5 however, they are not claimed. For the extent claimed, the claims are relevant in case of doubt.

Description of the figures

1 shows a voltage regulator according to the prior art

2 shows the unclaimed basic principle of the invention for a buck converter by simulating a triangular signal on the temporal potential curve of the output voltage (V _out ) by inserting a controlled offset voltage source (V _off ) between the internal voltage signal (V _i ) and voltage output (V _out ).

3 shows the claimed generation of the superimposed triangle signal for a buck converter by decoupling the internal voltage signal (V _i ) from the voltage output (V _out ) by means of the buffer circuit (Buf) having an output resistance (R _a ) and simultaneously supplying a pulsed current in synchronism with the switching of the first switch (S ₁ ) from a controllable constant current source (Is, I ₁ ).

4 shows a claimed variant of 4 for a down-converter, where only the displacement currents are fed in here.

5 shows the unclaimed basic principle of the invention for an up-converter by simulating a triangular signal on the temporal potential curve of the output voltage (V _out ) by inserting a controlled offset voltage source (V _off ) between internal voltage signal (V _i ) and voltage output (V _out ).

6 shows the claimed generation of the superimposed triangular signal for a boost converter by decoupling the internal voltage signal (V _i ) from the voltage output (V _out ) by means of the buffer circuit (Buf) having an output resistance (R _a ) and simultaneously supplying a pulsed current in synchronism with the switching of the first switch (S ₁ ) from a controllable constant current source (I _S , I ₁ ).

7 shows a claimed variant of 4 for a boost converter, where only the shift currents are fed in here.

8th shows an exemplary constant current source

Fig. 2

2 shows the unclaimed basic principle of the invention. The circuit largely corresponds to the 1 , An additional offset voltage source (V _off ), the voltage of which depends on the state of the switching signal (SS ₁ ), provides a voltage offset between the electrical potential of the voltage output (V _out ) and the potential of the internal voltage signal (V _i ). It has been recognized that this voltage offset (V _off ) has the same stabilizing effect as the ESR resistor (R _ESR ) without generating the parasitic superimposed triangular wave signal at the voltage output (V _out ) itself as in the prior art. The exact configuration of this offset voltage source (V _off ) is the subject of the developments of the invention. According to the invention, in addition to the prior art, a delay unit (Δt) is provided which delays the switching signal (SS ₁ ) to the delayed switching signal (SS _v ) by the switching behavior of the first switch delayed due to the size of the first or second switch (S1, S2) (S1) and / or the second switch (S ₂ ) for the regulation to take into account. As a result, the generation of the ripples on the internal voltage signal (V _i ) is optimized in terms of time. Preferably, the delay unit is implemented as a series connection of an RC low-pass filter and a comparator or Schmidt trigger.

Fig. 3

3 shows a more concrete version of the invention 2 , The buffer circuit (Buf) reproduces at its output the potential at the voltage output (V _out ) detected by the voltage divider (R ₁ , R ₂ ) and reduced by the voltage divider factor. In this case, the buffer circuit (Buf) has an output resistance (R _a ). A capacitor (C _i ) is charged or discharged by the output current (I _Buf ) of the buffer circuit (Buf) depending on the sign of the output current (I _Buf ) of the buffer circuit (Buf). The output of the buffer circuit (Buf) and the connected terminal of the capacitor (C _i ) thereby form the already described internal voltage signal (V _i ). The other terminal of the capacitor (C _i ) is connected to a reference potential.

In contrast to the prior art, however, the node of this internal voltage signal (V _i ) is now additionally charged by a controllable constant current source (I _S ) with a time constant in the charging phases electric charging current or discharged with a time constant in the discharge phases electric discharge. For this purpose, the polarity of the output current of the constant current source (I _S ) depends on the value of the switching signal (SS ₁ ) which controls the first switch (S ₁ ). By means of this constant controllable constant current source (I _s ), the effect of the superimposed triangular signal on the temporal potential curve at the voltage output (V _out ) is now emulated on the internal voltage signal (V _i ), so that the internal voltage signal now in contrast to the potential curve at the voltage output (V _out ) additionally has a superimposed triangular signal. This is an essential step according to the invention. One possibility for realizing the bipolar controlled constant current source (I _s ) is the combination of a non-controllable constant current source (I ₁ ) with a controllable constant _{current source} (I _s2 ) which can be switched as a function of the switching signal (SS ₁ ) instead of the bipolar controlled constant _{current source} (I _s ). , which then supplies only one of the constant current source (I ₁ ) opposite current polarity at twice the current amount. Instead, it is also conceivable to replace the non-controllable constant-current source (I ₁ ) by a first switchable constant-current source (I _S1 ) and inverse-positive to the second switchable controllable constant current source (I _s2 ) instead of the bipolar, controlled constant current source (I _s ) as a function of Switching signal (SS ₁ ) to operate. Of course, other current source configurations of one or more current sources are conceivable which, as a result, feed a cumulative charging current which is constant in the charging phases into the nodes of the internal voltage signal (V _i ) as a function of the switching signal (SS ₁ ) take the discharge phases constant Sumententladestrom from the node of the internal voltage signal (V _i ).

Fig. 4

4 shows a further embodiment of the invention. In this case, the capacitor (C _i ) becomes the 3 split into two capacitors (C _i1 , C _i2 ), which are each connected to a terminal with a small signal ground. The first capacitor (C _i1 ) is connected to a first terminal with the internal voltage signal (C _i ) and the second terminal with the voltage output (V _out ), which can be regarded as a small signal ground.

The second capacitor (C _i2 ) is connected to a first terminal also to the internal voltage signal (C _i ) and to the second terminal having a reference potential. The feed of the additional, superimposed triangular signal is now not directly by the constant current sources (I ₁ , I _s ) as in 3 but now by means of the displacement current via a coupling capacitance (C _k ), thus the constant current sources (I ₁ , I _s ) with respect to the DC voltage from the internal voltage signal (V _i ) is electrically isolated. The coupling capacitance (C _k ) preferably has a series resistor (R _s ), so that switching transients of the constant current sources (I ₁ , I _s ) can not penetrate to the internal voltage signal (Vi) and thus could disturb the control. In order to define the DC voltage level on the side of the constant current sources (I ₁ , I _s ), in the example of FIG 4 an operating point setting by a working point voltage divider (R ₃ , R ₄ ) from a first operating point resistor (R ₃ ) and a second operating point resistor (R ₄ ) provided by way of example. The resistances of the operating point voltage divider (R ₃ , R ₄ ) also ensure that in the event of a faulty adaptation of the current values of the two constant current sources (I ₁ , I _s ) in the form of slightly different current values with preferably the same target current values, the output voltage at the voltage output (V _out ) does not change. This configuration is offset-free, which is a particular advantage.

Instead of a non-switched constant current source (I ₁ ) in combination with a controllable constant current source (I _s ), which is turned on and off, to generate a charging and discharging current in response to the switching signal (SS ₁ ) for charging and discharging the coupling capacitance (C _k ), other implementations of a bipolar current source are conceivable. Instead, it is also conceivable, for example, to replace the non-controllable constant current source (I ₁ ) by a first switchable constant current source (I _S1 ) and inverse-positive to the second switchable controllable constant current source (I _s2 ) instead of the bipolar, controlled constant current source (I _s ) in dependence to operate from the switching signal (SS ₁ ). Of course, other current source configurations of one or more current sources are conceivable which, as a result, feed a cumulative charging current which is constant in the charging phases into the nodes of the internal voltage signal (V _i ) as a function of the switching signal (SS ₁ ) take the discharge phases constant Sumententladestrom from the node of the internal voltage signal (V _i ).

Fig. 5

5 shows the unclaimed basic principle of the invention for a boost converter. The input current (I _in) flows into the voltage input (V _in) is determined by the choke coil (L ₁₎ extending between the voltage input (V _in) and intermediate node (Z ₁₎ is smoothed. Here, the coil current (I _L ) is equal to the input current (I _in ). A second switch (S ₂ ), which is typically a diode, connects this intermediate node (Z ₁ ) to the voltage output (V _out ) when the voltage difference across this diode is poled in the flux direction and whose magnitude is above the threshold voltage of the diode. A storage capacity (C ₁ ) is charged or discharged depending on the load on the voltage output (V _out ) and the size of the coil current (I _L ). As before, in the case of a buck converter, the potential of the voltage output is again detected relative to a reference potential. As in the case of the down converter 2 is again created by an inventive additional offset voltage source (V _off ), the voltage of the state of the switching signal (SS ₁ ), a voltage offset between the electrical potential of the voltage output (V _out ) and the potential of the internal voltage signal (V _i ). According to the invention, it was also recognized here that this voltage offset (V _off ) has the same stabilizing effect as an ESR resistor (R _ESR ) according to the prior art without the parasitic superimposed triangular signal temporal potential profile at the voltage output (V _out ) itself as in the state to produce the technology. The further embodiment of this offset voltage source (V _off ) is the subject of further developments of the invention.

Fig. 6

6 shows an improved, now inventive version of 5 , The buffer circuit (Buf) reproduces at its output the potential at the voltage output (V _out ) detected by the voltage divider (R ₁ , R ₂ ) and reduced by the voltage divider factor. In this case, the buffer circuit (Buf) has an output resistance (R _a ). The capacitive voltage divider (C _i1 , C _i2 ) is charged or discharged by the output current (I _Buf ) of the buffer circuit (Buf) depending on the sign of the output current (I _Buf ) of the buffer circuit (Buf). The output of the buffer circuit (Buf) and the connected center tap of the capacitive voltage divider (C _i1 , C _i2 ) thereby form the already described internal voltage signal (V _i ). The other terminal of the second capacitor (C _i2 ) is connected to a reference potential. The other terminal of the first capacitor (C _i1 ) is connected to the voltage output (V _out ).

In contrast to the prior art, however, the node of this internal voltage signal (V _i ) is now additionally charged or discharged by a controllable constant current source (I _S ) whose polarity is equal to the value of the switching signal (SS ₁ ) connecting the first switch (S ₁ ) controls, depends. Whether the node of this internal Voltage signal (V _i ) is charged or discharged by the controllable constant current source (I _S ) thus depends on the value of the switching signal (SS ₁ ). The effect of the superimposed triangular wave on the temporal potential profile at the voltage output (V _out) is now on the internal voltage signal (V _i) by this controllable constant current source (I _s) is emulated such that the internal voltage signal is now in contrast to the potential profile at the voltage output (V _out) has a superimposed triangular signal in addition. This is an essential step according to the invention. One way to realize the bipolar controlled constant current source (I _s ) is the combination of a non-controlled constant current source (I ₁ ) with a switchable controllable constant current source (I _s ), which then provides only one of the non-controlled constant current source opposite current polarity at twice the current amount ,

Fig. 7

7 shows a further embodiment of the invention. The first capacitor (C _i1 ) of the capacitive voltage divider (C _i1 , C _i2 ) is connected with a first terminal to the internal voltage signal (V _i ) and the second terminal to the voltage output (V _out ), which can be regarded as a small signal ground ,

The second capacitor (C _i2 ) of the capacitive voltage divider (C _i1 , C _i2 ) is connected to a first terminal also to the internal voltage signal (V _i ) and to the second terminal having a reference potential. The feeding of the additional, superimposed triangular signal is now not directly by the current sources (I ₁ , I _s ) as in 6 but now by means of the displacement current via a coupling capacitance (C _k ), thus the constant current sources (I ₁ , I _s ) with respect to the DC voltage from the internal voltage signal (V _i ) is electrically isolated. The coupling capacitance (C _k ) preferably has a series resistor (R _s ), so that switching transients of the constant current sources (I ₁ , I _s ) can not penetrate to the internal voltage signal (Vi) and thus could disturb the control. In order to define the DC voltage level on the side of the constant current sources (I ₁ , I _s ), in the example of FIG 7 an operating point setting by a working point voltage divider (R ₃ , R ₄ ) from a first operating point resistor (R ₃ ) and a second operating point resistor (R ₄ ) provided by way of example. The resistances of the operating point voltage divider (R ₃ , R ₄ ) also ensure that in the event of a faulty adaptation of the current values of the two constant current sources (I ₁ , I _s ) in the form of slightly different current values with preferably the same target current values, the output voltage at the voltage output (V _out ) does not change. This configuration is offset-free, which is a particular advantage.

Instead of a non-switched constant current source (I ₁ ) in combination with a controllable constant current source (I _s ), which is turned on and off, to generate a charging and discharging current in response to the switching signal (SS ₁ ) for charging and discharging the coupling capacitance (C _k ), other implementations of a bipolar current source are conceivable. Instead, it is also conceivable, for example, to replace the non-controllable constant current source (I ₁ ) by a first switchable constant current source (I _S1 ) and inverse-positive to the second switchable controllable constant current source (I _s2 ) instead of the bipolar, controlled constant current source (I _s ) in dependence to operate from the switching signal (SS ₁ ). Of course, other current source configurations of one or more current sources are conceivable which, as a result, feed a cumulative charging current which is constant in the charging phases into the nodes of the internal voltage signal (V _i ) as a function of the switching signal (SS ₁ ) take the discharge phases constant Sumententladestrom from the node of the internal voltage signal (V _i ).

Fig. 8

8th shows an exemplary controllable constant current source. An exemplary first transistor (T ₁ ) is connected to its control terminal (gate) with a reference voltage and with a contact (source) to a supply voltage. As a result, the current (I) is adjusted by the power source. An exemplary second transistor (T ₂ ) serves in this example as a switching transistor, which is directly controlled by the switching signal (SS ₁ ) or alternatively by the inverted switching signal.

LIST OF REFERENCE NUMBERS

• ADC

  Analog to digital converter

  Buf

  buffer circuit

  C ₁

  Storage capacity. This can also be a plurality of storage capacities, which are connected directly or indirectly to one terminal to the voltage output (V _out ) and are connected to a reference potential with the other voltage output.

  C _i

  capacitor

  C _i1

  first capacitor. The first capacitor forms with the second capacitor (C _i2 ) a capacitive voltage divider parallel to the ohmic voltage divider (R ₁ , R ₂ ) from the first voltage divider resistor (R ₁ ) and the second voltage divider resistor (R ₂ ). By means of this capacitive voltage divider, the potential of the internal voltage signal (V _i ) can quickly follow voltage jumps in the output voltage at the voltage output (V _out ).

  C _i2

  second capacitor

  C _k

  coupling capacitance

  C _s

  comparator

  COMP

  comparator

  .delta.t

  Delay unit. The delay unit delays the switching signal (SS ₁ ) to the delayed switching signal (SS _v ) to the delayed due to the size of the first or second switch (S1, S2) switching behavior of the first switch (S1) and / or the second switch (S ₂ ) to be considered for the scheme. As a result, the generation of the ripples on the internal voltage signal (V _i ) is optimized in terms of time. Preferably, the delay unit is implemented as a series connection of an RC low-pass filter and a comparator or Schmidt trigger.

  I ₁

  non-controllable constant current source. This supplies a temporally constant electric current. It is preferably combined with a switchable bipolar current source.

  I _in

  input current

  I _L

  Coil current through the choke coil (L ₁ )

  I _buf

  Output current of the buffer circuit (Buf)

  I _out

  output current

  I _R

  Voltage divider current through the first voltage divider resistor (R ₁ ) and the second voltage divider resistor (R ₂ ) of the voltage divider (R ₁ , R ₂ )

  I _s

  controllable constant current source. The controllability refers to the switching of the polarity of the temporally magnitude constant output current of the constant current source. The current source thus behaves in the times between the switching as a constant current source.

  I _s1

  first controllable constant current source. The controllability refers to the switching on or off of a constant in the switch-on phase electrical output current of the constant current source. The current source thus behaves like a constant current source in the times between the circuits.

  I _s2

  second controllable constant current source. The controllability refers to the switching on or off of a constant in the switch-on phase electrical output current of the constant current source. The current source thus behaves like a constant current source in the times between the circuits.

  I _s3

  third controllable constant current source. The controllability refers to the switching of the polarity of the temporally magnitude constant output current of the constant current source. The current source thus behaves in the times between the switching as a constant current source.

  L ₁

  inductor

  NB

  unclaimed

  PV

  Pulse lengthening unit

  R ₁

  first voltage divider resistor

  R ₂

  second voltage divider resistor

  R ₃

  first bias resistor

  R ₄

  second working point resistance

  R _a

  Output resistance of the buffer circuit (Buf)

  R _s

  dropping resistor

  Ref

  reference voltage

  R _ESR

  Resistor for the stability of the control loop in the prior art, which is connected in series to the storage capacity (C ₁ ).

  S ₁

  first switch between the voltage input (V _in ) and the intermediate node (Z ₁ )

  S ₂

  second switch between the intermediate node (Z ₁ ) and the voltage output (V _out )

  SS ₁

  Switching signal with a switching period T _P

  SS _v

  delayed switching signal

  T _A

  Off time

  T _E

  One-time

  T _P

  Switching period; Where T _P = T _A + T _E.

  V _i

  internal voltage signal

  V _in

  voltage input

  V _off

  voltage offset

  V _out

  voltage output

  Z ₁

  between nodes

Claims (5)

Method for controlling a DC-DC converter with a voltage input (V _in ) and a voltage output (V _out ) according to a constant-on-time method or the constant-off-time method comprising the steps a. Periodic recurrent closing and opening of a first switch (S ₁ ) between the voltage input (V _in ) and an intermediate node (Z ₁ ) by means of a switching signal (SS ₁ ) having a first state ("ON") and a second state ("OFF"). ) and with a switching period (T _P ), wherein the switching period (T _P ) in a on-time (T _E ), in which the switching signal (SS ₁ ) in the first state ("ON") and the switch (S ₁ ), and a subsequent off-time (T _A ) in which the switching signal (SS ₁ ) is in the second state ("OFF") and the switch (S ₁ ) is open, divided and wherein the duration (T _E ) of the on-time (T _E ) in the case of a constant-on-time method is constant or the duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time method; b. Smoothing the output current (I _out ), which flows out of the voltage output (V _out ), by smoothing a current component (I _L ) of this output current (I _out ) by means of a choke coil (L ₁ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ); c. Storing and / or delivering a charge amount from the voltage output (V _out ) into or _{out of} one or more storage capacities (C ₁ ); d. Detecting the potential of an internal voltage signal (V _i ) whose potential depends on the output voltage at the voltage output (V _out ) versus a reference potential, by a comparator (COMP) and comparing it with a reference voltage (Ref) to produce a comparator output signal (C _s ), which may have a first state ("ON") or a second state ("OFF") depending on the result of the comparison; e. Extending a time in which the comparator output signal (C _s ) is in the first state ("ON") to a minimum time to generate the switching signal (SS ₁ ) by a pulse extension unit (PV) or, alternatively, to extend a time in which the comparator output signal (C _s ) in the second state ("OFF") is at a minimum time for generating the switching signal (SS ₁ ) by a pulse extension unit (PV); f. possibly generating a delayed switching signal (SS _v ) from the switching signal (SS ₁ ); G. periodic generation of a temporal heterodyne signal, in particular of a triangular signal, with the temporal switching period (T _p ) in the temporal potential curve of the internal voltage signal (V _i ) by adding an additional heterodyne signal, in particular a triangular signal, synchronously with the opening and / or closing of the first switch (S1 ); H. Generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf) having an output resistance (R _a ), the potential of the internal voltage signal (V _i ) the voltage sum of a first voltage signal component and a second voltage signal component is and wherein the first voltage component is proportional to the voltage at the voltage output (V _out ); i. Charging a first capacitor (C _i1 ) and a second capacitor (C _i2 ) forming a capacitive voltage divider (C _i1 , C _i2 ) between the voltage output (Vout) and the reference potential and whose voltage divider tap the node of the internal voltage signal (V _i ) is, with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component; j. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of one in the controllable constant current source (I _s ) for generating the second voltage signal component; k. wherein the polarity of the output current of the constant current source (I _s ) is controlled by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ) and the amount of the output current of the constant current source (I _s ) is constant. Method for controlling a DC-DC converter with a voltage input (V _in ) and a voltage output (V _out ) according to a constant-on-time method or the constant-off-time method comprising the steps a. Periodic recurrent closing and opening of a first switch (S ₁ ) between the voltage input (V _in ) and an intermediate node (Z ₁ ) by means of a switching signal (SS ₁ ) having a first state ("ON") and a second state ("OFF"). ) and with a switching period (T _P ), wherein the switching period (T _P ) in a on-time (T _E ), in which the switching signal (SS ₁ ) in the first state ("ON") and the switch (S ₁ ), and a subsequent off-time (T _A ) in which the switching signal (SS ₁ ) is in the second state ("OFF") and the switch (S ₁ ) is open, and wherein the duration (T _E ) the on-time (T _E ) is constant in the case of a constant-on-time method or the duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time method; b. Smoothing the output current (I _out ), which flows out of the voltage output (V _out ), by smoothing a current component (I _L ) of this output current (I _out ) by means of a choke coil (L ₁ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ); c. Storing and / or delivering a charge amount from the voltage output (V _out ) into or _{out of} one or more storage capacities (C ₁ ); d. Detecting the potential of an internal voltage signal (V _i ) whose potential depends on the output voltage at the voltage output (V _out ) to a reference potential, by a comparator (COMP) and comparing with a reference voltage (Ref) to produce a comparator output signal (C _s ) which may have a first state ("ON") or a second state ("OFF") depending on the result of the comparison; e. Extending a time in which the comparator output signal (C _s ) is in the first state ("ON") to a minimum time to generate the switching signal (SS ₁ ) by a pulse extension unit (PV) or, alternatively, to extend a time in which the comparator output signal (C _s ) in the second state ("OFF") is at a minimum time for generating the switching signal (SS ₁ ) by a pulse extension unit (PV); f. possibly generating a delayed switching signal (SS _v ) from the switching signal (SS ₁ ); G. periodic generation of a temporal heterodyne signal, in particular of a triangular signal, with the temporal switching period (T _p ) in the temporal potential curve of the internal voltage signal (V _i ) by adding an additional heterodyne signal, in particular a triangular signal, synchronously with the opening and / or closing of the first switch (S1 ); H. Generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf) having an output resistance (R _a ), the potential of the internal voltage signal (V _i ) the voltage sum of a first voltage signal component and a second voltage signal component and a third voltage signal component is and wherein the first voltage signal component is proportional to the voltage at the voltage output (V _out ), i. Charging a first capacitor (C _i1 ) and a second capacitor (C _i2 ) forming a capacitive voltage divider (C _i1 , C _i2 ) between the voltage output (Vout) and the reference potential and whose voltage divider tap the node of the internal voltage signal (V _i ) is, with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component; j. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of one in the controllable constant current source (I _s ) for generating the second voltage signal component; i. wherein the first controllable constant current source (I _s1 ) by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ) is switched on and off and delivers a temporally constant output current in the on state; k. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of a second controllable constant current source (I _s2 ) for generating the third voltage signal component, ii. wherein the polarity of the output current of the second controllable constant current source (I _s2 ) is controlled by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ), and iii. wherein the magnitude of the output current of the second controllable constant current source (I _s2) between polarity reversals of the output current of the second controllable constant current source (I _s2) is constant over time; Method for controlling a DC-DC converter with a voltage input (V _in ) and a voltage output (V _out ) according to a constant-on-time method or the constant-off-time method comprising the steps a. Periodic recurrent closing and opening of a first switch (S ₁ ) between the voltage input (V _in ) and an intermediate node (Z ₁ ) by means of a switching signal (SS ₁ ) having a first state ("ON") and a second state ("OFF"). ) and with a switching period (T _P ), wherein the switching period (T _P ) in a on-time (T _E ), in which the switching signal (SS ₁ ) in the first state ("ON") and the switch (S ₁ ), and a subsequent off-time (T _A ) in which the switching signal (SS ₁ ) is in the second state ("OFF") and the switch (S ₁ ) is open, and wherein the duration (T _E ) the on-time (T _E ) is constant in the case of a constant-on-time method or the duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time method; b. Smoothing the output current (I _out ), which flows out of the voltage output (V _out ), by smoothing a current component (I _L ) of this output current (I _out ) by means of a choke coil (L ₁ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ); c. Storing and / or delivering a charge amount from the voltage output (V _out ) into or _{out of} one or more storage capacities (C ₁ ); d. Detecting the potential of an internal voltage signal (V _i ) whose potential depends on the output voltage at the voltage output (V _out ) versus a reference potential, by a comparator (COMP) and comparing it with a reference voltage (Ref) to produce a comparator output signal (C _s ), which may have a first state ("ON") or a second state ("OFF") depending on the result of the comparison; e. Extending a time in which the comparator output signal (C _s ) is in the first state ("ON") to a minimum time to generate the switching signal (SS ₁ ) by a pulse extension unit (PV) or, alternatively, to extend a time in which the comparator output signal (C _s ) in the second state ("OFF") is at a minimum time for generating the switching signal (SS ₁ ) by a pulse extension unit (PV); f. possibly generating a delayed switching signal (SS _v ) from the switching signal (SS ₁ ); G. periodic generation of a temporal heterodyne signal, in particular of a triangular signal, with the temporal switching period (T _p ) in the temporal potential curve of the internal voltage signal (V _i ) by adding an additional heterodyne signal, in particular a triangular signal, synchronously with the opening and / or closing of the first switch (S1 ); H. Generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf) having an output resistance (R _a ), the potential of the internal voltage signal (V _i ) the voltage sum of the first voltage signal component and a second voltage signal component and a third voltage signal component is and wherein the first voltage signal component is proportional to the voltage at the voltage output (V _out ), i. Charging a first capacitor (C _i1 ) and a second capacitor (C _i2 ) forming a capacitive voltage divider (C _i1 , C _i2 ) between the voltage output (Vout) and the reference potential and whose voltage divider tap the node of the internal voltage signal (V _i ) is, with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component; j. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of one in the controllable constant current source (I _s ) for generating the second voltage signal component; iv. wherein the first controllable constant current source (I _s1 ) by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ) is switched on and off and delivers a temporally constant output current in the on state; k. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of a second controllable constant current source (I _s2 ) for generating the third voltage signal component, v. wherein the second controllable current source (I _s2 ) is turned on by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ) only when the first constant current source (I _s1 ) is turned off, and vi. wherein the second controllable current source (I _s2 ) delivers a time-constant output current in the switched-on state and l. wherein both constant current sources (I _S1 , I _S2 ) can be temporarily switched off at the same time. Method for controlling a DC-DC converter with a voltage input (V _in ) and a voltage output (V _out ) according to a constant-on-time method or the constant-off-time method comprising the steps a. Periodic recurrent closing and opening of a first switch (S ₁ ) between the voltage input (V _in ) and an intermediate node (Z ₁ ) by means of a switching signal (SS ₁ ) having a first state ("ON") and a second state ("OFF"). ) and with a switching period (T _P ), wherein the switching period (T _P ) in a on-time (T _E ), in which the switching signal (SS ₁ ) in the first state ("ON") and the switch (S ₁ ), and a subsequent off-time (T _A ) in which the switching signal (SS ₁ ) is in the second state ("OFF") and the switch (S ₁ ) is open, and wherein the duration (T _E ) the on-time (T _E ) is constant in the case of a constant-on-time method or the duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time method; b. Smoothing the output current (I _out ), which flows out of the voltage output (V _out ), by smoothing a current component (I _L ) of this output current (I _out ) by means of a choke coil (L ₁ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ); c. Storing and / or delivering a charge amount from the voltage output (V _out ) into or _{out of} one or more storage capacities (C ₁ ); d. Detecting the potential of an internal voltage signal (V _i ) whose potential depends on the output voltage at the voltage output (V _out ) versus a reference potential, by a comparator (COMP) and comparing it with a reference voltage (Ref) to produce a comparator output signal (C _s ), which may have a first state ("ON") or a second state ("OFF") depending on the result of the comparison; e. Extending a time in which the comparator output signal (C _s ) is in the first state ("ON") to a minimum time to generate the switching signal (SS ₁ ) by a pulse extension unit (PV) or, alternatively, to extend a time in which the comparator output signal (C _s ) in the second state ("OFF") is at a minimum time for generating the switching signal (SS ₁ ) by a pulse extension unit (PV); f. possibly generating a delayed switching signal (SS _v ) from the switching signal (SS ₁ ); G. periodic generation of a temporal heterodyne signal, in particular of a triangular signal, with the temporal switching period (T _p ) in the temporal potential curve of the internal voltage signal (V _i ) by adding an additional heterodyne signal, in particular a triangular signal, synchronously with the opening and / or closing of the first switch (S1 ); H. Generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf) having an output resistance (R _a ), the potential of the internal voltage signal (V _i ) the voltage sum of the first voltage signal component and a second voltage signal component is and wherein the first voltage signal component is proportional to the voltage at the voltage output (V _out ); i. Charging a first capacitor (C _i1 ) and a second capacitor (C _i2 ), which form a capacitive voltage divider (C _i1 , C _i2 ) between the voltage output (Vout) and the reference potential and their Voltage divider _tap the node of the internal voltage signal (V _i ) is, with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component; j. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of one in the controllable constant current source (I _s ) for generating the second voltage signal component; i. wherein the polarity of the output current of the controllable constant current source (I _s ) is controlled by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ), and ii. wherein the amount of the output current of the controllable constant current source (I _s ) between polarity changes of the output current of the controllable constant current source (I _s ) is constant over time. Method for controlling a DC-DC converter with a voltage input (V _in ) and a voltage output (V _out ) according to a constant-on-time method or the constant-off-time method comprising the steps a. Periodic recurrent closing and opening of a first switch (S ₁ ) between the voltage input (V _in ) and an intermediate node (Z ₁ ) by means of a switching signal (SS ₁ ) having a first state ("ON") and a second state ("OFF"). ) and with a switching period (T _P ), wherein the switching period (T _P ) in a on-time (T _E ), in which the switching signal (SS ₁ ) in the first state ("ON") and the switch (S ₁ ), and a subsequent off-time (T _A ) in which the switching signal (SS ₁ ) is in the second state ("OFF") and the switch (S ₁ ) is open, and wherein the duration (T _E ) the on-time (T _E ) is constant in the case of a constant-on-time method or the duration (T _A ) of the off-time (T _A ) is constant in the case of a constant-off-time method; b. Smoothing the output current (I _out ), which flows out of the voltage output (V _out ), by smoothing a current component (I _L ) of this output current (I _out ) by means of a choke coil (L ₁ ) between the intermediate node (Z ₁ ) and the voltage output (V _out ); c. Storing and / or delivering a charge amount from the voltage output (V _out ) into or _{out of} one or more storage capacities (C ₁ ); d. Detecting the potential of an internal voltage signal (V _i ) whose potential depends on the output voltage at the voltage output (V _out ) versus a reference potential, by a comparator (COMP) and comparing it with a reference voltage (Ref) to produce a comparator output signal (C _s ), which may have a first state ("ON") or a second state ("OFF") depending on the result of the comparison; e. Extending a time in which the comparator output signal (C _s ) is in the first state ("ON") to a minimum time to generate the switching signal (SS ₁ ) by a pulse extension unit (PV) or, alternatively, to extend a time in which the comparator output signal (C _s ) in the second state ("OFF") is at a minimum time for generating the switching signal (SS ₁ ) by a pulse extension unit (PV); f. possibly generating a delayed switching signal (SS _v ) from the switching signal (SS ₁ ); G. periodic generation of a temporal heterodyne signal, in particular of a triangular signal, with the temporal switching period (T _p ) in the temporal potential curve of the internal voltage signal (V _i ) by adding an additional heterodyne signal, in particular a triangular signal, synchronously with the opening and / or closing of the first switch (S1 ); H. Generation of an output current (I _Buf ) of a buffer circuit (Buf) for generating a first voltage signal component of the internal voltage signal (V _i ) by this buffer circuit (Buf) having an output resistance (R _a ), the potential of the internal voltage signal (V _i ) the voltage sum of the first voltage signal component and a second voltage signal component is and wherein the first voltage signal component is proportional to the voltage at the voltage output (V _out ); i. Charging one or more capacitors (C _i1 , C _i2 ) with the output current (I _Buf ) of the buffer circuit (Buf) to produce the first voltage signal component; j. Generating a _measurement current (I _Buf ) which is proportional to the voltage at the voltage output (V _out ) by means of a sub-device (Buf) having a small-signal output resistance (R _a ); k. Charging a first capacitor (C _i1 ) and a second capacitor (C _i2 ) forming a capacitive voltage divider (C _i1 , C _i2 ) between the voltage output (Vout) and the reference potential and whose voltage divider tap the node of the internal voltage signal (V _i ) is, with the output current (I _Buf ) of the buffer circuit (Buf) for generating the first voltage signal component; l. Charging the first capacitor (C _i1 ) and the second capacitor (C _i2 ) by means of the output current of one in the controllable constant current source (I _s ) for generating the second voltage signal component, i. wherein the polarity of the output current of the controllable constant current source (I _s ) is controlled by the switching signal (SS ₁ ) or the delayed switching signal (SS _v ), and ii. wherein the amount of the output current of the controllable constant current source (I _s ) between polarity changes of the output current of the controllable constant current source (I _s ) is constant over time.

Images