DE102014103433B4 - DIGITAL-ANALOG CONVERTER - Google Patents

Abstract

A digital-to-analog converter (350) for a current mode converter (100), comprising: a voltage-to-current converter (333); a first converter circuit (320), which comprises a first sub-DAC and is designed to do so generate a constant and continuous-time signal during a switching cycle; and a second converter circuit (330) configured to generate a signal that changes continuously over the switching cycle, the second converter circuit (330) comprising a second partial DAC (331) configured to generate a discrete value signal and one Waveform generation circuit coupled to the second sub-DAC (331), the waveform generation circuit being adapted to convert the discrete value signal into the continuously changing signal, the waveform generation circuit being a switch (11) of the current mode Transducer (100) includes a simulated element (332) and a capacitor (334), the simulated element (332) being coupled to an output of the first converter circuit (320), the capacitor (334) comprising a first electrode and a second electrode, which first electrode with a node between the second partial DAC (331) and an input of the voltage-current converter (333) ppelt, an output of the voltage-current converter (333) is coupled to an output of the first converter circuit (320), and the second electrode is coupled to a ground potential, and wherein at an output of the digital-to-analog converter (350) a voltage is provided which is tapped at a node between the first converter circuit (320) and the simulated element (320).

Description

FIELD OF THE INVENTION

The present disclosure relates to a digital-to-analog converter.

BACKGROUND

Power supply and voltage regulation for devices such as A central processing unit, analog / RF subsystems, a memory, systems-on-chip or peripheral loads is becoming a major challenge due to the higher demands on computer, control and communication platforms. In recent years, there has been an increasing need for power supply and power converters that offer high dynamic parameters. An important challenge for power supplies is to enable them to respond quickly to strong load and power fluctuations. For this purpose, a current mode control method can be used in which a current feedback circuit is provided in addition to a voltage feedback circuit or as the only feedback circuit.

The object of the present invention is to provide an improved digital-to-analog converter for a feedback circuit in a current-controlled power converter. The object is achieved by a device having the features of claim 1.

The publication US 2010/0134083 A1 describes an analog-to-digital (A / D) converter comprising: a ramp signal generator having a ramp signal output and a clock input; a delay line having a plurality of delay elements; a delay line controller configured to activate the delay line and to cause a signal to pass through the delay line when a ramp signal (vramp (t)) at the ramp signal output first of all a first of an A / D input signal on an A / D Intersects input and from a reference signal at a reference signal input; and deactivate the delay line and sample an output signal of the delay line when the ramp signal intersects a second one of the A / D input signal and the reference signal; and an edge steepness calibration module, which is coupled to the ramp generator, wherein the calibration module is configured to set the edge steepness of the signal at the ramp signal output.

The publication US 2011/0280353 A1 describes an adaptive out-of-phase synchronization clock generator circuit and a method for generating a out-of-phase synchronization clock. The adaptive phase-shifted synchronization clock generator circuit includes: a current source that generates a current flowing through a node to generate a node voltage on the node; an inversely proportional voltage generator coupled to the node to generate a voltage that is inversely proportional to the node voltage; a ramp generator that receives a synchronization input signal and generates a ramp signal; a comparator that compares the inversely proportional voltage with the ramp signal; and a pulse generator for generating a clock signal according to an output of the comparator.

The publication US 2012/0176824 A1 describes a digital control circuit for use with a switching power supply that receives an input signal at a first input node and a control signal at a second input node and provides an output signal at a second input node and that provides an output signal at a first output node and a current signal at a second output node. The digital control circuit generates a programmable current reference signal based on a difference between the output signal and a voltage reference signal, calculates a time at which the current signal substantially corresponds to the programmable current reference signal, and generates the control signal based on the calculated time.

The publication CN 102 882 375 A. describes a switching power supply with an output port configured to supply a load, a control signal generator having an input and an output configured to provide a first control signal; a first switch configured to receive the first control signal and regulate the voltage at the output port; and a ramp signal generator comprising an input and an output, the input configured to receive the control signal and the output configured to provide a current signal that simulates an output signal at the output port, and wherein the output of the ramp signal generator further includes is coupled to the input of the means for generating the control signal.

The publication US 7,772,810 B2 describes a fully digital DC / DC automatic up / down converter circuit that converts an input voltage into a based on a switching process Converts output voltage with a predetermined value. The switching process includes switching process cycles with at least one switching process phase. The converter is controlled by a digital controller with a look-up table that stores a variety of data. The digital controller uses certain data from the plurality of data related to an actually switched mode of operation to continuously set the start and end of a shift.

The publication "A new, continuous-time model for current-mode control" by R. B. Ridley in IEEE Transactions on Power Electronics, Vol. 6, No. 2, 1991, pages 271-280 - ISSN 1941-0107, describes a new current mode control model that combines the accuracy of the modeling of sample data with the simplicity of pole-zero representation. All small-signal characteristics of current mode control are predicted, including high-frequency subharmonic vibrations that can occur even at duty cycles less than 0.5. The best representation for the function of the transfer from control to output is represented as the third order. Model predictions are confirmed by measurements on a buck converter.

The publication “Digital Control of Single-Inductor Dual-Output DC-DC Converters in Continuous-Conduction Mode” by D. Trevisan et al. in IEEE 36th Power Electronics Specialists Conference, 2005, pages 2612-2622 - ISBN 978-0-7803-9033-1, describes the use of digital control for non-isolated single-inductor dual-output step-down DC-DC converters in continuous -Conduction Mode (CCM). Precise and independent control of each output requires a sophisticated digital control architecture to minimize cross-regulation problems. The control used includes separate regulation of the common mode and differential mode output voltages. In addition, the variable gain of the differential mode controller and a non-linear evaluation of the common mode voltage were examined in order to improve the dynamic behavior of the system under different load conditions. Experimental investigations were carried out with discrete components, whereby the digital control was implemented in a field programmable gate array (FPGA).

The publication US 2005/0007087 A1 describes constant on-time control for a step-down converter that uses two symmetrical ramps. The ramps can be generated artificially or by sensing the voltage across a sense resistor in the output. The ramp can also be generated by detecting the voltage across the "ON" resistance of the low-side FET in the switching regulator. With a modified output voltage one of the ramps is superimposed and with a modified reference voltage the other ramps are superimposed. The modified output voltage and the modified reference voltage are compared to determine when to start the buck converter on time. The double ramps reduce the sensitivity to noise. The ON time is stopped in response to the charging of a capacitor with the input voltage of the regulator. An offset can also be generated which represents the difference between the average output voltage and the reference voltage. The offset is used to create a modified reference to compensate for the offset.

Figure list

• 1 zeigt ein schematisches Blockschaltbild eines nicht zur Erfindung gehörigen digital gesteuerten Strommodus-Leistungswandlers nach der Offenbarung.
• 2a-2c zeigen beispielhafte Ausgangssignale von Digital-Analog-Wandlern nach der Offenbarung.
• 3 zeigt ein schematisches Blockschaltbild eines nicht zur Erfindung gehörigen Digital-Analog-Wandlers für einen digital gesteuerten Strommodus-Wandler nach der Offenbarung.
• 4 zeigt ein schematisches Blockschaltbild eines erfindungsgemäßen Digital-Analog-Wandlers für einen digital gesteuerten Strommodus-Wandler nach der Offenbarung.
• 5 zeigt ein Ablaufdiagramm eines beispielhaften nicht zur Erfindung gehörigen Verfahrens zum digitalen Steuern eines Strommodus-Leistungswandlers nach der Offenbarung.

The accompanying drawings are provided to provide a better understanding of the disclosure and are incorporated in and constitute a part of this specification. The drawings show embodiments and together with the description serve to explain the principles of the disclosure. Other variations and many of the envisaged advantages of embodiments will become apparent as they become more fully understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to one another. The same reference numerals designate similar parts.

• 1 shows a schematic block diagram of a digitally controlled current mode power converter not according to the invention according to the disclosure.
• 2a-2c show exemplary output signals from digital-to-analog converters according to the disclosure.
• 3rd shows a schematic block diagram of a digital-to-analog converter not belonging to the invention for a digitally controlled current mode converter according to the disclosure.
• 4th shows a schematic block diagram of a digital-to-analog converter according to the invention for a digitally controlled current mode converter according to the disclosure.
• 5 FIG. 12 shows a flow diagram of an exemplary method for digitally controlling a current mode power converter according to the disclosure.

DETAILED DESCRIPTION

The aspects and embodiments will now be described with reference to the drawings, wherein like reference numerals are generally used to designate the same elements throughout. In the following description, numerous specific details are set forth for purposes of illustration to provide a thorough understanding of one or more aspects of the disclosure. However, it is obvious to a person skilled in the art that one or more aspects of the embodiments can be carried out with a lower degree of specific details. In other instances, known structures and elements are shown in schematic form to simplify the description of one or more aspects of the disclosure. It should be understood that other embodiments may be used and structural or logical changes may be made without departing from the scope of the disclosure. It should also be noted that the drawings are not to scale or not necessarily to scale.

Furthermore, disclosed features or aspects can be combined with one or more other features or aspects of the other implementations, as may be desired and advantageous for a given or special application. The terms "coupled" and "connected", along with derivatives thereof, can be used. It should be noted that these terms can be used to indicate that two elements are interacting or interacting with one another, regardless of whether they are in direct physical or electrical contact or not. The following detailed description, therefore, should not be taken as a limitation, and the scope of the present disclosure is defined by the appended claims.

The following disclosure relates to a power converter. It should be noted that different types of power converters can be used, e.g. DC-DC power converter circuits, such as step-down converter circuits, step-up converters or step-down / step-up converter circuits, DC-AC converter circuits or AC-DC converter circuits.

Current controlled power converters, e.g. DC-DC converters, compare a characteristic, such as the coil current, with a threshold signal, e.g. a threshold current emitted by a control circuit. The power converter can include a set of transistors. He can e.g. a first switch, e.g. an n-MOS transistor, a second switch, e.g. a p-MOS transistor, a coil and an output capacitor included. When the threshold is reached, the first transistor switch is turned off and the second transistor switch is turned on (in the example of a step-up converter). Before reaching the threshold, the coil current increases, and after reaching the threshold, the first and second switches reconfigure the circuit and the coil current decreases.

1 shows a schematic block diagram of a digitally controlled current mode power converter according to the disclosure. The power converter 100 in 1 includes a power converter level 10th which can be implemented as an up-converter stage, as in 1 is shown. The power converter stage 10th includes a first switch 11 , a second switch 12th , a coil 13 and an output capacitor 14 . A battery voltage V _B can be connected to one end of the coil 13 be applied, and an output voltage V ₀ can at an output of the power converter stage 10th be preserved. The power converter 100 also includes a digital-to-analog converter 20th , which comprises an input and an output and is designed to receive a digital nominal current signal at the input and to output an analog nominal current signal at the output. The digital-to-analog converter can have a width of 8 bits, for example.

The power converter 100 further includes an edge compensation circuit 30th , which comprises a first input and an output, the first input having the output of the digital-to-analog converter 20th is coupled to receive the desired analog current signal therefrom and the edge compensation circuit 30th is designed to output an edge-compensated analog nominal current signal at the output. The edge compensation circuit 30th serves the purpose of preventing subharmonic oscillation at half the switching frequency by generating a threshold current value which is slightly reduced over the switching cycle. The current threshold is first determined from the output voltage using a digital loop filter V ₀ calculated by converting the analog output voltage V ₀ into a digital value in the analog-to-digital converter 40 and then calculating the current threshold in the digital compensator 50 , which is provided, for example, as a PID (proportional-integral-derivative) controller. Then the digital-to-analog converter generates 20th a constant current threshold in each switching cycle. With the edge compensation circuit 30th then subharmonic oscillations can be avoided.

The power converter 100 also includes a comparator 60 which comprises a first input, a second input and an output, the first input having the power converter stage 10th is coupled to an analog actual To receive current signal from this, the second input with the output of the edge compensation circuit 30th is coupled and the comparator 60 is designed to output a specific signal when a value of the analog actual current signal is equal to a value of the edge-compensated analog target current signal.

The specific signal can go to a controller 70 are delivered, which can be implemented in the form of a finite state machine (FSM). The controller 70 can also be configured to control signals for the first and second switches 11 and 12th to produce and deliver.

The power converter 100 also includes a timer 80 , which can be implemented as an ultra-coarse digital pulse width modulator (DPWM). The timer 80 provides a control signal to the digital compensator 50 and a switching frequency to the controller 70 . The timer can also be used to set a minimum on-time or a minimum off-time of one of the switches in the converter stage 10th ensure.

The power converter 100 may further comprise a voltage control loop, which is a further comparator 90 which includes the analog output voltage V ₀ receives and compares this with a target voltage. An output signal in the form of a PFM (pulse frequency modulation) signal can go to an input of the controller 70 to be delivered. However, the voltage control loop is only optional and can be omitted.

2a shows an exemplary output signal of a digital-to-analog converter without edge compensation. The output signal is a piecewise constant signal, ie a sample and hold version of a discrete time signal. A desired output signal of the digital-to-analog converter is in 2 B shown. It consists of the piecewise constant component as in 2a and a continuous time ramp component. Edge compensation is possible with an output signal like this, thus avoiding subharmonic oscillation. 2c shows a variant of 2 B , the continuous time ramp being added only in a selectable subinterval of the switching cycle. This can be useful if, for example, a strong ramp is required. In an alternative implementation, the continuous ramp can be replaced with another continuous waveform, such as a cubic or exponential waveform.

3rd shows a schematic block diagram of a digital-to-analog converter for a power converter according to the disclosure. In the block diagram in 3rd are only part of a power converter and a converter stage, like the one in 1 shown, shown. In the 3rd Circuit shown includes a power converter stage 10th who have a first switch 11 , a second switch 12th and an inductor 13 includes. The power converter stage 10th further includes an output capacitor (not shown). The first switch 11 can be formed from an n-MOS transistor, and the second switch 12th can be formed from a p-MOS transistor. A battery voltage V _b can be connected to one end of the inductor 13 be created.

The circuit in 3rd also includes a digital-to-analog converter (DAC) 20th (first part DAC), an edge compensation circuit 30th and a comparator 40 . Furthermore, the power converter in 3rd include other components that in 1 are shown and which are not shown here for the sake of simplicity. The DAC 20th , the edge compensation circuit 30th and the comparator 40 can be done in the same way as in 1 shown to be connected to these other components.

The edge compensation circuit 30th includes an input and an output, the input connected to the output of the DAC 20th is coupled to receive the desired analog current signal therefrom, and wherein the output is connected to a first input of the comparator 40 is coupled. The edge compensation circuit 30th is designed to generate an edge-compensated analog target current signal and to supply the edge-compensated analog target current signal to the output. The edge compensation circuit 30th includes a power source 31 (second part DAC), a first switch 32 , a capacitor 34 and a second switch 35 . The first switch 32 performs the function of a simulated device of the first switch 11 the power converter stage 10th out, which means the first switch 11 the power converter stage 10th and the first switch 32 the edge compensation circuit 30th have a predetermined ratio of resistance values. In addition, the control electrodes are the two switches 11 and 32 coupled with one and the same signal. The first switch 32 is also between the DAC 20th and coupled to the crowd. The first switch 32 may include a transistor, but may also include a resistor that holds the current of the DAC 20th converted into a tension. The condenser 34 includes a first port and a second port, the first port having a node between the DAC 20th and the first switch 32 is coupled and the second connection to the power source 31 is coupled. The edge compensation circuit 30th further includes a second switch 35 which functions as a reset switch which is opened during the switching period and which is closed when the end of the switching period is reached by the capacitor 34 unloaded so that a new ramp can be generated at the beginning of the following switching period. The DAC generates at the beginning of each switching period 20th an analog target current from a digital target current and injects a current I ₁ in the first (replica) switch 32 . Then a combined effect of the power source is used 31 and the capacitor 34 for subtracting a ramp signal from the voltage across the first switch 32 is measured or dissipated, and for supplying the resulting signal to the output of the edge compensation circuit 30th . The strength or height of the ramp can depend on the power source 31 are controlled as a customizable power source 31 can be designed. In particular, the power source 31 also be designed in the form of a digital-to-analog converter (DAC) (second partial DAC), which in this case has a width of 2 or 3 bits. In an alternative embodiment, neither the switching transistor 11 still its replica transistor 32 used for current measurement. Instead, dedicated measuring devices such as measuring resistors are used.

Assuming that a stream I ₁ from the DAC 20th through the first switch 32 flows to ground, the first switch 32 has a resistor R, the capacitor 34 has a capacitance C and the current source 31 a stream I ₂ then the voltage across the capacitor develops 34 like 1 / C × I ₂ × t and that of the output of the edge compensation circuit 30th supplied output voltage develops like R (I ₁ - I ₂ ) - 1 / C × I ₂ × t.

The power source 31 can also be operated so that the ramp is added later in this switching cycle, ie not from the beginning. Such an example is in the timing diagram in 2c shown. In one embodiment, the edge is activated before a roughly determined time instance of the equality of the analog target current and the actual current.

4th shows a schematic block diagram of a digital-to-analog converter 350 for a power converter according to the revelation. The digital-to-analog converter 350 in 4th is to be understood in the same way as the power converter in 1 , with some elements in 4th are not shown. The digital-to-analog converter 350 in 4th includes a power converter level 10th who have a first switch 11 , a second switch 12th and an inductor 13 comprises, the output capacitor is not shown. The digital-to-analog converter 350 in 4th also includes a DAC 320 (first part DAC) and an edge compensation circuit 330 . The power converter also includes a comparator 340 . The edge compensation circuit 330 includes a power source 331 (second part DAC), a simulated element, for example a first switch 332 , a voltage-current converter 333 , a capacitor 334 , a second switch 335 and a third switch 336 . The DAC 320 is with the DAC 20th in 3rd comparable, and it injects a current into the first switch 332 that as a replica device with respect to the first switch 11 the power converter stage 10th acts. The first switch can also be used here 11 include a transistor or resistor to the current of the DAC 320 to convert into a tension. Then through a combined effect between the power source 331 , the capacitor 334 and the voltage-current converter 333 generates a current ramp that leads to the analog current as provided by the DAC 320 can be delivered, added or subtracted from this. The second switch 335 serves to reset the circuit at the end of a switching cycle. The third switch 336 disables the power source 331 during this reset phase. The resulting current I _DAC - I _RAMP generates a voltage drop across the simulated device 332 leading to a first input of the comparator 340 is supplied with the coil current through the inductance 13 the power converter stage 10th flows to a second input of the comparator 340 is delivered. Once the two in the comparator 340 input signals are the same, an output signal is generated and sent to the controller 70 delivered with a closing of the first switch 11 responds.

5 shows a flowchart of a method for digitally controlling a current mode power converter. The procedure 400 in 5 includes providing a power converter level at 410 , the conversion of a digital target current signal into an analog target current signal 420 and converting the target analog current signal into an edge compensated target analog current signal 430 . The method further includes comparing a parameter representative of an actual analog current signal obtained from the power converter stage with a parameter representative of the edge compensated analog target current signal 440 and generating a signal when a value of the actual analog current signal is equal to a value of the edge compensated desired analog current signal 450 . The digital target current signal can be derived from a measurement of an output voltage of the power converter stage.

The parameter that is representative of an analog actual current signal can be the analog actual current signal itself or a voltage that is representative of the analog actual current signal and the parameter that is representative of the edge-compensated analog target current signal. can be the edge-compensated analog target current signal itself or a voltage that is representative of the edge-compensated target current signal.

According to one embodiment of the method, converting the analog desired current signal into an edge-compensated analog desired signal comprises reducing or increasing a value of the analog desired current signal. In particular, it involves generating a ramp current signal, e.g. can be done by charging a capacitor using a power source. The current source can be implemented as an adaptable current source, in particular in the form of a digital-to-analog converter.

Although the disclosure has been shown and described with reference to one or more implementations, changes and / or modifications may be made to the examples shown without departing from the spirit and scope of the appended claims. In particular with regard to the various functions performed by the components or structures (arrangements, devices, circuits, systems, etc.) described above, unless expressly stated otherwise, the terms (including a reference to a “means”) must: may be used to describe such components to correspond to any other component or structure that performs the specified function of the described component (e.g., is functionally equivalent), even if it is of the disclosed structure that performs the function in the exemplary implementations presented here of Revelation are not structurally equivalent.

Claims (1)

A digital-to-analog converter (350) for a current mode converter (100) comprising: a voltage-to-current converter (333); a first converter circuit (320) comprising a first sub-DAC and configured to generate a signal that is constant and continuous over a switching cycle; and a second converter circuit (330) configured to generate a signal that changes continuously over the switching cycle, wherein the second converter circuit (330) includes a second sub-DAC (331) configured to generate a discrete value signal and a waveform generation circuit coupled to the second sub-DAC (331), wherein the waveform generating circuit is configured to convert the discrete value signal into the continuously changing signal, wherein the waveform generating circuit comprises an element (332) simulating a switch (11) of the current mode converter (100) and a capacitor (334), wherein the simulated element (332) is coupled to an output of the first converter circuit (320), wherein the capacitor (334) comprises a first electrode and a second electrode, wherein the first electrode is coupled to a node between the second partial DAC (331) and an input of the voltage-current converter (333), an output of the voltage-current converter (333) to an output of the first converter circuit (320) and the second electrode is coupled to a ground potential, and wherein a voltage is provided at an output of the digital-to-analog converter (350), which voltage is connected to a node between the first converter circuit (320) and the simulated element (320) is tapped.

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