DE102016115579A1 - Fanglayer substrate stacking technique for improving RF device performance - Google Patents

Abstract

Some embodiments of the present disclosure are directed to an apparatus. The device comprises a substrate which comprises a silicon layer arranged above an insulating layer. The substrate includes a transistor device region and a radio frequency (RF) region. A coupling structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handling substrate is disposed over an upper surface of the coupling structure. A trapping layer separates the coupling structure and the handling substrate.

Description

REFERENCE TO RELATED APPLICATION

The present application claims priority over US Provisional Application No. 62 / 243,442, filed Oct. 19, 2015, the contents of which are fully incorporated by reference.

GENERAL PRIOR ART

Integrated circuits are formed on semiconductor substrates and packaged to form so-called chips or microchips. Traditionally, integrated circuits are formed on bulk semiconductor substrates comprising semiconductor material such as silicon. Semiconductor-on-insulator (SOI) substrates have come up as an alternative in recent years. SOI substrates comprise a thin layer of active semiconductor (eg, silicon) that is separated from an underlying handling substrate by a layer of insulating material. The layer of insulating material electrically isolates the thin layer of active semiconductor from the handling substrate, thereby reducing current leakage of devices formed within the thin layer of active semiconductor. The thin layer of active semiconductor also provides other benefits such as faster switching times and lower operating voltages, which has resulted in SOI substrates being widely used to make high volume radio frequency (RF) systems such as RF switches.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It should be noted that, according to industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1A FIG. 12 illustrates a cross-sectional view of some embodiments of a device according to some aspects of the present disclosure. FIG.

1B illustrates an enlarged cross-sectional view of a portion of 1A according to some embodiments.

The 2 to 13 Figure 12 illustrates some embodiments of cross-sectional views illustrating a method of forming an IC at various stages of fabrication.

14 FIG. 12 illustrates a flowchart of some embodiments of a method of forming a device according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. Of course these are just examples and should not be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features so that the first and second features can not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

Further, spatially relative terms such as "below," "below," "below," "above," "upper," and the like may be used herein to facilitate discussion of the relationship of an element or feature to one or more other elements or to describe features as illustrated in the figures. The spatially relative terms, in addition to the orientation shown in the figures, are intended to encompass different orientations of the device in use or operation of the device. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

RF semiconductor devices, typically fabricated on semiconductor on insulator (SOI) substrates, operate at high frequencies and generate RF signals. For these RF devices, the SOI substrates typically include a high resistance handle substrate, an insulating layer over the handle substrate, and a semiconductor layer disposed over the insulating layer. The high-resistance handling substrate has a low doping concentration and may, for example, have a resistance in the range of 2 kiloohm centimeters (kΩ-cm) to 8 kΩ-cm. The high resistance of the handling substrate can improve the high frequency (RF) performance of the RF devices in some respects, but one judgment in the present disclosure resides in the fact that the high resistance handling substrate can still be a source of eddy currents when carriers are removed from the high impedance grid Handling substrate are freed by the RF signals. These eddy currents, which may have high frequencies, are a source of noise in the final chip. In particular, these eddy currents may result in device crosstalk and / or non-linear signal distortion.

In order to prevent such crosstalk and non-linear signal distortion, the present disclosure proposes to fabricate the RF devices on an SOI substrate comprising a handle substrate, a layer of insulating material, and an active semiconductor layer. However, instead of leaving the existing handling substrate in the final device, the manufacturing process removes the handling substrate from the bottom of the insulating layer prior to the final packaging of the device so that the handling substrate is no longer present and no longer acts as a source of eddy currents.

With reference to 1A FIG. 12 is a cross-sectional view of some embodiments of a device. FIG 100 illustrated in accordance with the present disclosure. The device 100 includes a first substrate 106 , a coupling structure 112 that over the first substrate 106 is arranged, and a second substrate 122 that over the coupling structure 112 is arranged. The first substrate 106 includes an insulating layer 110 and an active semiconductor layer 108 ; and the coupling structure 112 includes several metal layers (eg 114a - 114e ), which are inside a dielectric structure 116 are arranged. One or more active components, such as metal oxide semiconductor field effect transistors (MOSFETs) 111 are in or over a transistor zone 102 of the first substrate 106 arranged and one or more passive components such as inductor 128 , Capacitor 130 and / or resistance 131 are over an RF region 104 of the first substrate 106 arranged. A substrate via (TSV) 118 extends vertically through the semiconductor layer 108 and through the insulating layer 110 , The TSV 118 couples a metal layer (eg 114a . 114b . 114c , ...) electrically with a contact point 120 on a lower surface of the insulating layer 110 , An area of the contact point 120 can through a packaging or molding layer 121 remain exposed, thereby allowing the device 100 is attached to a printed circuit board or other chip via solder bumps, wire leads, etc., so that the circuit board or other chip is electrically connected to active and / or passive components on the device 100 can be coupled.

In particular, the first substrate 106 an absence of a handling substrate under the insulating layer 110 on and therefore is the contact point 120 in some embodiments, in direct contact with the bottom surface of the insulating layer 110 , It will be more apparent below with reference to the 2 to 13 the device 100 for example, can be made by a process in which the first substrate 106 Initially, an SOI wafer is the semiconductor layer 108 , Insulating layer 110 and a handling substrate under the insulating layer 110 includes. In the final device, such as in 1A however, the underlying handling substrate has been removed to prevent the underlying handling substrate from acting as an eddy current source during device operation. As the insulating layer 110 insulating (and therefore not susceptible to eddy currents), removal of the underlying handling substrate eliminates a source of problematic eddy currents from the bottom of the first substrate 106 , Therefore, the device can 100 have less crosstalk and less distortion than conventional devices.

To the reduced thickness and structural rigidity of the first substrate 106 due to the removal of the underlying handling substrate and to provide sufficient thickness to adequately fill a package and provide structural support during manufacture is a handling substrate 124 over an upper surface 112u the coupling structure 112 arranged. An optional but advantageous trapping layer 126 can the coupling structure 112 from the handling substrate 124 separate. The catch layer 126 is configured to trap carriers caused by RF components (eg, inductor 128 and / or capacitor 130 ) to generate eddy currents in the handling substrate 124 to limit. As an example, a case is used in which the inductor 128 and / or the capacitor 130 individually or jointly generate an RF signal in the handling substrate 124 to a certain extent can excite carriers when an appropriate bias voltage is applied. The catch layer 126 is configured to capture these carriers to limit corresponding eddy currents. The catch layer 126 may manifest as doped or undoped polysilicon or as an amorphous silicon layer in some embodiments. The catch layer 126 can with the handling substrate 124 meet at an interface, which in some cases has peaks and valleys, in other cases is substantially planar or in other cases generally roughened.

1B shows some embodiments where the trapping layer 126 made of polysilicon and multiple grain boundaries 132 having. The grain boundaries 132 are dislocations or mistakes where the atoms of the trapping layer 126 within the crystal lattice in the wrong place or misaligned. The grain boundaries 132 act as recombination centers configured to capture carriers (e.g., carriers from the handling substrate 124 ). Once the carriers are trapped within the recombination centers, their lifetime is reduced. Therefore, by trapping carriers within the grain boundaries 132 the catch layer 126 the accumulation of carriers along a lower surface of the handling substrate 124 essentially reduces eddy currents, crosstalk and nonlinear distortion during device operation 100 weakens.

In some embodiments, an interface between the handle substrate 124 and the catch layer 126 a series of surveys 134 and depressions 136 that can form a sawtooth profile. The surveys 134 and depressions 136 facilitate smaller grain sizes and therefore facilitate more grain boundaries near the top surface of the handling substrate 124 , Therefore, most carriers are at the grain boundaries 132 trapped to mitigate and / or prevent eddy currents. The surveys 134 and / or depressions 136 may be triangular, pyramidal or conical, among others. In some embodiments, the bumps 134 a height h in the range of about 10 nm to about 1 μm as measured from the base of an adjacent well (or a more remote well) and in some embodiments about 0.5 μm. The surveys 134 may also have a width w in the range of about 10 nm to about 10 microns and in some embodiments be about 1 micron. In other embodiments, the elevations 134 as illustrated, ends in a peak rather than being flattened and / or may be rounded. Instead of ending up in a tip as illustrated, the wells can 136 be flat or rounded in other embodiments. In some embodiments, adjacent protrusions may have the same heights and / or widths to one another (adjacent recesses may also have the same depths and / or widths to each other), but in other embodiments, protrusions may also have different heights and / or different widths to each other (and recesses can have different depths and / or widths). In some cases, the bumps and / or pits follow a random distribution of heights and / or widths, follow a Gaussian distribution of heights and / or widths, or follow a different distribution.

Advantageously, the integration of the handling substrate 124 above the coupling structure 112 increased structural rigidity to prevent the absence of a handling substrate under the insulating layer 110 compensate. It also reduces the catch layer 126 advantageously eddy currents as a potential source of noise in the handling substrate 124 and, although optional, is advantageous for many applications.

With reference to the 2 to 13 For example, a series of cross-sectional views together illustrate a method of making a device according to some embodiments.

2 FIG. 12 illustrates a cross-sectional view of some embodiments of providing an SOI substrate. FIG 106 ' , As illustrated by 2 is the SOI substrate 106 ' a semiconductor on insulator (SOI) substrate comprising a handle substrate 202 , an insulating layer 110 that over the handling substrate 202 is arranged, and a semiconductor layer 108 that over the insulating layer 110 is arranged comprises. In many cases, the SOI substrate 106 ' take the form of a wafer-like wafer. For example, such a wafer may have a diameter of 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm) or 125 mm (4.9 inches); 150 mm (5.9 inches, commonly referred to as "6 inches"); 200 mm (7.9 inches, commonly referred to as "8 inches"); 300 mm (11.8 inches, commonly referred to as "12 inches"); or 450 mm (17.7 inches, commonly referred to as "18 inches"); exhibit.

The handling substrate 202 may have a thickness sufficient to the SOI substrate 106 ' to provide sufficient structural stiffness to withstand semiconductor processing operations. In some embodiments, the handling substrate 202 For example, a thickness in the range of about 200 microns to about 1000 microns and is about 700 microns in some embodiments. In embodiments, the handling substrate 202 a low resistivity silicon handling substrate having a resistance of between several ohm-cm and several tens of ohm-cm, and in some embodiments, between 8 ohm-cm and 12 ohm-cm. In alternative embodiments, the handling substrate 202 be a high resistance silicon handling substrate with a resistance between several hundred and several thousand ohm-cm, and in some embodiments, between 2 kΩ-cm to 8 kΩ-cm. Although either a high-resistance or low-resistance silicon substrate may be used, it is advantageous to use low-resistance silicon substrates because low-resistance silicon substrates are cheap and greater resistivity is not significant Offers advantages, since the handling substrate 202 is removed in this manufacturing process. Other handling substrates such as sapphire substrates may also be used.

In some embodiments, the insulating layer 110 have a thickness ranging from less than one micron to several microns, which is sufficient to provide potential separation between the handling substrate 202 and the semiconductor layer 108 provide. In some embodiments, the insulating layer 110 Be silica, which has a dielectric constant of about 3.9. In other embodiments, the insulating layer 110 a low-k dielectric. Non-limiting examples of low κ dielectric include, but are not limited to: fluorine doped silica, carbon doped silica, porous silica, porous carbon doped silica, spin on organic polymeric dielectrics, and / or spin on silicon based polymeric dielectric.

In some embodiments, the semiconductor layer is 108 a layer of pure silicon which has a monocrystalline lattice structure and may be intrinsic (e.g., undoped) or a doped p-type or n-type. The semiconductor layer 108 In some embodiments, it may have a thickness in the range of several microns down to about one nanometer. The semiconductor layer 108 may also be a semiconductor compound made up of elements of two or more different groups of the periodic table. The elements may be binary alloys (two elements, eg GaAs), ternary alloys (three elements, eg InGaAs or AlGaAs) or quad alloys (four elements, eg AlInGaP). The semiconductor layer 108 For example, doped regions, epitaxial layers, insulating layers formed in or on the semiconductor layer may include photoresist layers formed in or on the semiconductor layer and / or conductive layers formed in or on the semiconductor layer.

In 3 become active components like MOSFETs 111 and / or other field effect transistors (FETs) in or over a transistor zone 102 the semiconductor layer 108 educated. A shallow trench isolation (STI) region 117 is formed, in the insulating material, an island of the material of the semiconductor layer 108 surrounds. A gate electrode 123 is formed sidewall spacers 125 are on opposite side walls of the gate electrode 123 formed and source / drain regions 119 are on opposite sides of the sidewall spacers 125 educated. A gate dielectric 127 separates the gate electrode 123 from a channel region in the semiconductor layer which includes the source / drain regions 119 separates. In some embodiments, the gate electrode comprises 123 Polysilicon or metal, the sidewall spacers 125 include silicon nitride and the gate dielectric 127 includes silicon dioxide or high-k dielectric. Although not illustrated, the transistors can 111 Other forms such as finFET devices, bipolar transistors, floating gate transistors, etc. assume. A resistance 131 made of polysilicon, for example 135 can be made and of the semiconductor layer 108 by means of the gate dielectric and / or another dielectric 129 can be isolated in the RF region 104 be formed. A dielectric layer 133 extends over upper surfaces of the gate electrodes 123 and source / drain regions 119 , The dielectric layer 133 may comprise a low κ dielectric or silicon dioxide.

In 4 become the source / drain contacts 150 formed to make an ohmic connection to the source / drain regions 119 through the dielectric layer 133 provide, and gate contacts 152 are formed to make an ohmic connection to upper surfaces of the gate electrodes 123 provided. In some embodiments, the source / drain contacts 150 and / or gate contacts 152 For example, copper, tungsten, aluminum, gold, titanium or titanium nitride include. In addition, a substrate via (TSV) 118 educated. The illustrated TSV 118 extends down through the dielectric layer 133 , through the semiconductor layer 108 and through the insulating layer 110 , In other embodiments, the TSV may 118 also down partially or completely through the handling substrate 202 extend. The TSV 118 can be made of, for example, copper, tungsten, aluminum, gold, titanium or titanium nitride, and can be made of the same or different material as the source / drain contacts 150 and / or the gate contacts 152 , The TSV 118 is typically formed by a separate photomask and / or separate etching from the source / drain contacts and / or gate contacts.

As illustrated by 5 becomes a coupling structure 112 over the SOI substrate 106 ' educated. The coupling structure 112 is formed by forming a first dielectric layer 154 such as a low κ dielectric layer, nitride or silicon dioxide dielectric layer, and then forming one or more photoresist masks over the first dielectric layer 154 educated. An etching is performed on an existing photoresist mask to form trench openings and / or via openings in the first dielectric layer 154 to build. Then, metal is deposited around the openings in the first dielectric layer 154 to fill, creating vias and / or metal lines 156 formed according to a metal 1 layer become. In some embodiments, copper is used to surround the openings in the first dielectric layer 154 to fill such that vias and metal-1 lines are made of copper. In embodiments where copper is used, the openings are typically lined with a diffusion barrier layer, then a copper seed layer is formed over the diffusion barrier layer and an electroplating process is used to build copper and fill the openings. The diffusion barrier layer typically has high electrical conductivity to maintain good electronic contact while maintaining a sufficiently low copper diffusion capability to sufficiently chemically isolate these copper conductor films from underlying structures. Cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride and titanium nitride are some non-limiting examples of materials that can be used for the diffusion barrier layer. After the metal has been grown to fill the openings, a chemical mechanical planarization (CMP) operation is performed around the first metal layer and the first dielectric at the plane 154a to planarize. Then, a second dielectric layer 158 formed openings are in the second dielectric layer 158 formed and metal is deposited to vias and metal 2 wires 160 to build. Additional dielectric and metal layers are formed in this manner until the coupling structure 112 is formed. As illustrated in 5 can the coupling structure 112 an RF component such as inductor 128 and / or capacitor 130 include that over an RF region 104 of the SOI substrate 106 ' is formed.

In 6 becomes a second handling substrate 124 ' as a massive silicon wafer provided. The second handling substrate 124 ' may have a thickness which is between 300 microns and 1000 microns and in some embodiments is about 700 microns. In some embodiments, the second handle substrate 124 ' have a resistivity greater than that of the handling substrate 202 , In some embodiments, the second handle substrate may be 124 ' For example, a resistivity of between several hundred and several thousand ohm-cm, and in some embodiments between 2 kΩ-cm to 8 kΩ-cm, may help to reduce eddy currents in the final device. In some cases, the second handling substrate is 124 ' for structural support and therefore may have an absence of device features and an absence of coupling features in some embodiments. In many cases, the second handling substrate 124 ' take the form of a wafer-like wafer. For example, such a wafer may have a diameter of 1 inch (25 mm); 2 inches (51 mm); 3 inches (76 mm); 4 inches (100 mm); 5 inches (130 mm) or 125 mm (4.9 inches); 150 mm (5.9 inches, commonly referred to as "6 inches"); 200 mm (7.9 inches, commonly referred to as "8 inches"); 300 mm (11.8 inches, commonly referred to as "12 inches"); or 450 mm (17.7 inches, commonly referred to as "18 inches");exhibit; and often has the same diameter as the SOI substrate 106 ' on.

In 7 becomes an upper surface of the second handling substrate 124 ' etched to surveys 134 and depressions 136 to build. The surveys 134 and depressions 136 are made by first using a photomask (not shown) to define a pattern on the top surface and then the top surface an etchant 702 is exposed to rough the top surface with projections and depressions. In other embodiments, the second handle substrate 124 ' be damaged by the upper surface of the second handling substrate 124 ' is mechanically damaged (eg, micro scratching, abrasive blasting, etc.) or by performing sputtering, deposition, or self-assembling monolayer. In some embodiments, the protrusions and depressions include sawtooth-shaped protrusions and corresponding recesses, wherein protrusions and depressions of the individual "teeth" are spaced at equal intervals or at random intervals. In other embodiments, the protrusions and depressions include randomly shaped protrusions having different grid directions and geometries. In some embodiments, the etchant 702 a dry etchant (eg, a plasma etchant, an RIE etchant, etc.) or a wet etchant (eg, hydrofluoric acid).

In 8th becomes a catch layer 126 but the surveys 134 and depressions 136 formed such that an interface between the trapping layer 126 and the second handling substrate 124 ' will be produced. Therefore, a second substrate 122 intended. In some embodiments, the capture layer 126 be a polycrystalline silicon layer. In other embodiments, the capture layer 126 comprising amorphous silicon comprising a dopant species. In various embodiments, the dopant species may include argon (Ar), carbon (C), and / or germanium (Ge). The area 802 the capture layer furthest from the second handle substrate 124 ' In some cases, using CMP, for example, can be planarized to make it more suitable for bonding.

In 9 become the SOI substrate 106 ' and the coupling structure 112 to the second substrate 122 bonded. This bonding can take one of many forms, such as fusion bonding or epoxide bonding. In some embodiments, an oxide may be over the bottom surface of the trap layer prior to bonding 126 be formed and the oxide on the lower surface of the trapping layer 126 can then contact the upper surface of the coupling structure 112 be bonded by performing an annealing process.

In 10 becomes the handling substrate 202 away. In some embodiments, a two-step process is used to manipulate the handling substrate 202 to remove. During a first stage, a grinding process is used to thin the handling substrate, for example by a first distance d1. The grinding process may use a surface which is reasonably abrasive and therefore by the distance d1 of the handling substrate 202 sand down quite quickly. After the grinding process is completed, such as determined by a predetermined time or by making measurements indicating that the predetermined distance d1 has been removed; a chemical mechanical planarization (CMP) operation is performed to obtain a second residual amount d2 of the handling substrate 202 to remove. The CMP operation typically uses a polishing pad that is less abrasive than when sanding, providing a smoother, more uniform surface than when sanding. The CMP operation may end, for example, after a predetermined time has elapsed, or when measurements indicate that the handling substrate 202 was completely removed. It will be appreciated that in some embodiments, an amount of thinned handling substrate 202 on the lower surface of the insulating layer 110 will be left.

11 shows the structure of 10 after CMP has run. In the example of 11 becomes the lower section of the TSV 118 exposed.

In 12 became a contact point 120 in direct contact with the lower section of the TSV 118 educated. The contact point 120 In some embodiments, it is in direct contact with the bottom of the insulating layer 110 , The contact point 120 For example, it can be made of copper, tungsten, aluminum, gold, titanium or titanium nitride. In some embodiments, the pad becomes 120 by forming a metal layer on the lower surface of the insulating layer 110 and then patterning the metal layer, for example, using a photolithography mask and performing etching of the metal layer with the existing photolithography mask. It should be noted that 12 according to several different TSVs 118 . 118a . 118b and corresponding contact points 120 . 120a . 120b shows, to highlight a few examples. The TSV 118 extends between metal 1 layer, dielectric layer 133 , Semiconductor layer 108 and insulating layer 110 ; while the second TSV 118a from a lower surface of the resistor 131 through the dielectric 129 , the semiconductor layer 108 and insulating layer 110 extends. A third TSV 118b extends from the metal 2-line through the second dielectric layer 158 , the first dielectric layer 154 , the dielectric layer 133 , through the semiconductor layer 108 and through the insulating layer 110 ,

After forming the contact points 120 For example, the structure, which is often still in the form of a wafer-like wafer, can be optionally bonded to other substrates to make a 3D IC, and can be cut or scored into individual die or integrated circuits. Then it will be in 13 a packaging layer 121 formed around a lower surface of the insulating layer 110 cover. The packaging layer 121 may extend along sidewalls of the device about an upper surface of the second handle substrate 122 cover. The packaging layer 121 For example, it may be made of ceramic or a polymeric material and may protect the device from environmental extremes, corrosion, dirt, dust, water vapor, etc.

14 FIG. 12 illustrates a flowchart of some embodiments of a method. FIG 1400 for manufacturing a device according to some aspects of this disclosure. Although the disclosed method 1400 is illustrated and described below as a series of acts or events, it is to be understood that the illustrated order of such acts or events should not be construed as limiting. For example, some acts apart from those illustrated and / or described herein may take place in a different order and / or concurrently with other acts or events. In addition, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and / or phases. Even though 14 for clarity in terms of 2 to 13 It is obvious that the structures used in the 2 to 13 are disclosed, not on the method of 14 are limited but instead can stand alone as structures independent of the process. Although the procedure of 14 in terms of the 2 to 13 It is obvious that the procedure is not limited to those in the 2 to 13 disclosed structures is limited, but instead independent of those in the 2 to 13 revealed structures can stand on their own.

at 1402 an SOI substrate is provided. The first substrate includes a first handle substrate, an insulating layer disposed over the first handle substrate, and a semiconductor layer disposed over the insulating layer. Therefore, can 1402 for example 2 correspond.

at 1404 For example, a coupling structure is formed over the SOI substrate. The coupling structure comprises a plurality of metal layers arranged within a dielectric structure. Therefore, can 1404 for example 5 correspond.

at 1406 a second substrate is bonded to an upper surface of the coupling structure. In some embodiments, the second substrate includes a second handle substrate and a trap layer. In some such embodiments, after bonding, the capture layer is disposed between the second handle substrate and the top surface of the coupling structure. Therefore, can 1406 for example 9 correspond.

at 1408 For example, the first handling substrate is removed to expose a bottom surface of the insulating layer after the second substrate has been bonded to the top surface of the coupling structure. Therefore, can 1408 for example 10 correspond.

at 1410 For example, a pad is formed in direct contact with the lower surface of the insulating layer after the first handling substrate is removed. A substrate via (TSV) extends vertically through the insulating layer and the semiconductor layer and electrically couples the pad to a metal layer of the coupling structure. Therefore, can 1410 for example 12 correspond.

Therefore, as noted above, some embodiments of the present disclosure are directed to an apparatus. The device comprises a substrate which comprises a silicon layer arranged above an insulating layer. The substrate includes a transistor device region and a radio frequency (RF) region. A coupling structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handling substrate is disposed over an upper surface of the coupling structure. A trapping layer separates the coupling structure and the handling substrate.

Other embodiments relate to a method. In the method, a first substrate is provided. The first substrate includes a first handle substrate, an insulating layer disposed over the first handle substrate, and a semiconductor layer disposed over the insulating layer. A coupling structure is formed over the substrate. The coupling structure comprises a plurality of metal layers arranged within a dielectric structure. A second substrate comprising a second handle substrate and a trap layer is bonded to an upper surface of the coupling structure. After bonding, the trap layer is disposed between the second handle substrate and the top surface of the coupling structure. The second handling substrate is then removed to expose a bottom surface of the insulating layer.

Still other embodiments relate to a method. In this method, an SOI substrate is provided. The SOI substrate includes a first handle substrate, an insulating layer disposed over the first handle substrate, and a silicon layer disposed over the insulating layer. The SOI substrate includes a transistor device region and a radio frequency (RF) region that are laterally spaced apart. A coupling structure is formed over the SOI substrate. The coupling structure comprises a plurality of metal layers arranged within a dielectric structure. A second substrate comprising a trap layer and a second handle substrate made of silicon is bonded to an upper surface of the coupling structure. After bonding, the trap layer separates the second handle substrate from the top surface of the coupling structure. The first handling substrate is then removed to expose a bottom surface of the insulating layer; and a pad is formed in direct contact with a lower surface of the insulating layer. A substrate via (TSV) extends vertically through the silicon layer and through the insulating layer.

The foregoing describes features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. It should be apparent to one skilled in the art that he may readily use the present disclosure as a basis to design or modify other processes and structures to accomplish the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims (20)

Apparatus comprising: a substrate including a semiconductor layer disposed over an insulating layer, the substrate including a transistor device region and a radio frequency (RF) region; a coupling structure disposed over the substrate and including a plurality of metal layers disposed within a dielectric structure; a handling substrate disposed over an upper surface of the coupling structure; and a trap layer separating the coupling structure and the handling substrate. The device of claim 1, further comprising: a pad disposed in direct physical contact with a bottom surface of the insulating layer of the substrate; and a substrate via extending vertically through the semiconductor layer and the insulating layer and electrically coupling the pad to a metal layer of the coupling structure. The device of claim 1 or 2, wherein the handling substrate comprises a silicon substrate and the capture layer comprises a polysilicon layer that meets the silicon substrate at a non-planar interface. The device of claim 3, wherein the non-planar interface comprises a series of protrusions extending downwardly into the trap layer from the silicon substrate. The device of claim 1, wherein the RF region comprises an RF device disposed in the coupling structure and configured to transmit an RF signal, wherein the capture layer is configured to capture carriers caused by the RF signal be energized to limit eddy currents in the handling substrate. The device of any one of the preceding claims, further comprising: a packaging layer covering a bottom surface of the insulating layer and extending along sidewalls of the device to cover an upper surface of the handling substrate. Method, comprising: Providing a first substrate comprising a first handle substrate, an insulating layer disposed over the first handle substrate, and a semiconductor layer disposed over the insulating layer; Forming a coupling structure over the substrate, the coupling structure comprising a plurality of metal layers disposed within a dielectric structure; Bonding a second substrate comprising a second handle substrate and a trap layer to an upper surface of the coupling structure, wherein the trap layer is disposed after bonding between the second handle substrate and the upper surface of the coupling structure; and after bonding, removing the second handle substrate to expose a bottom surface of the insulating layer. The method of claim 7, further comprising: after removing the second handle substrate, forming a pad in direct physical contact with a bottom surface of the insulating layer of the first substrate, wherein a substrate via (TSV) extends vertically through the semiconductor layer and the insulating layer and electrically couples the pad to a metal layer of the coupling structure , A method according to claim 7 or 8, wherein the first and second handling substrates have different ohmic resistances. The method of any one of claims 7 to 9, wherein the first handling substrate has a resistance between 8 ohm-cm and 12 ohm-cm. Method according to one of claims 7 to 10, wherein the first handling substrate has a first ohmic resistance and the second handling substrate has a second ohmic resistance and the second ohmic resistance is greater by a factor of ten or more than the first ohmic resistance. Method according to one of claims 7 to 11, wherein the second handling substrate comprises a silicon substrate and the trapping layer comprises an amorphous silicon layer. The method of claim 7, wherein the second handling substrate comprises a silicon substrate and the capture layer comprises a polysilicon layer that meets the silicon substrate at a non-planar interface. The method of claim 13, wherein the non-planar interface comprises a series of protrusions extending downwardly from the silicon substrate into the trapping layer. The method of claim 13 or 14, wherein the non-planar interface is formed by forming a photomask over a surface of the silicon substrate and etching the surface of the silicon substrate to form a series of protrusions and depressions, and the trap layer directly over the series of protrusions and depressions is formed. The method of claim 7, wherein a radio frequency (RF) device is disposed in the coupling structure and configured to transmit an RF signal, wherein the capture layer is configured to capture carriers excited by the RF signal To limit eddy currents in the second handling substrate. Method, comprising: Providing a semiconductor on insulator (SOI) substrate comprising a first silicon handle substrate, an insulating layer disposed over the first handle substrate, and a silicon layer disposed over the insulating layer, the SOI substrate comprising a transistor device region and a semiconductor device Radio frequency (RF) region, which are laterally spaced from each other; Forming a coupling structure over the SOI substrate, the coupling structure comprising a plurality of metal layers disposed within a dielectric structure; Bonding a second substrate comprising a trap layer and a second handle substrate made of silicon to an upper surface of the coupling structure, wherein after the bonding, the trap layer separates the second handle substrate from the upper surface of the coupling structure; after bonding, removing the first handle substrate to expose a bottom surface of the insulating layer; and Forming a pad in direct contact with a bottom surface of the insulating layer, wherein a substrate via (TSV) extends vertically through the silicon layer and through the insulating layer to contact the pad. The method of claim 17, wherein the first handle substrate has an ohmic resistance smaller than that of the second handle substrate. The method of claim 17 or 18, further comprising: Forming a gate dielectric on an upper surface of the transistor device region of the silicon layer; Forming a gate electrode over the gate dielectric, wherein at least one of the metal layers is coupled to the gate electrode. The method of claim 19, wherein the TSV electrically couples the pad to the at least one of the metal layers.

Images