DE102016115579B4 - Capture layer substrate stacking technique to improve performance for RF devices - Google Patents

Abstract

A device comprising: a substrate (106) comprising a semiconductor layer (108) disposed over an insulating layer (110), said substrate (106) comprising a transistor device region (102) and a radio frequency (RF) region (104); an interconnect (112) disposed over the substrate (106) and including a plurality of metal layers (114) disposed within a dielectric structure (116); a handle substrate (124) disposed over a top surface of the interconnect (112); a trap layer (126) separating the interconnect (112) and the handle substrate (124); a pad (120) disposed in direct physical contact with a bottom surface of the insulating layer (110) of the substrate (106); and a substrate via (118) extending vertically through the semiconductor layer (108) and the insulating layer (110) and electrically coupling the pad (120) to a metal layer (114) of the interconnect (112).

Description

BACKGROUND ART

Integrated circuits are formed and packaged on semiconductor substrates to form so-called chips or microchips. Traditionally, integrated circuits are formed on bulk semiconductor substrates that include semiconductor material such as silicon. In recent years, semiconductor-on-insulator (SOI) substrates have emerged as an alternative. SOI substrates have a thin layer of active semiconductor (e.g., silicon) that is separated from an underlying handle substrate by a layer of insulating material. The layer of insulating material electrically isolates the thin active semiconductor layer from the handle substrate, thereby reducing current leakage from devices formed within the thin active semiconductor layer. The thin layer of active semiconductor also provides other benefits such as faster switching times and lower operating voltages that have led to SOI substrates being widely used for high volume fabrication of radio frequency (RF) systems such as RF switches.

Prior art relating to the subject matter of the invention can be found, for example, in U.S. 2012/0 161310 A1 .

The invention provides an apparatus according to claim 1, a method according to claim 6 and a method according to claim 15. Refinements are given in the dependent claims.

character list

• 1A veranschaulicht eine Querschnittansicht von einigen Ausführungsformen einer Vorrichtung gemäß einigen Aspekten der vorliegenden Offenbarung.
• 1B veranschaulicht eine vergrößerte Querschnittansicht eines Abschnitts von 1A gemäß einigen Ausführungsformen.
• Die 2 bis 13 veranschaulichen einige Ausführungsformen von Querschnittansichten, die ein Verfahren zum Bilden eines IC bei verschiedenen Stufen der Herstellung zeigen.
• 14 veranschaulicht ein Ablaufdiagramm von einigen Ausführungsformen eines Verfahrens zum Bilden einer Vorrichtung gemäß einigen Ausführungsformen.

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

• 1A FIG. 12 illustrates a cross-sectional view of some embodiments of an apparatus according to some aspects of the present disclosure.
• 1B FIG. 12 illustrates an enlarged cross-sectional view of a portion of FIG 1A according to some embodiments.
• the 2 until 13 10 illustrate some embodiments of cross-sectional views showing a method of forming an IC at various stages of manufacture.
• 14 FIG. 11 illustrates a flow chart of some embodiments of a method of forming a device according to some embodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features may be formed between the first and second features , so that the first and second features cannot be in direct contact. In addition, the present disclosure may repeat reference numerals and/or indicia throughout the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and/or configurations.

Further, for ease of discussion, spatially relative terms such as "below," "below," "lower," "above," "upper," and the like may be used herein to indicate the relationship of an element or feature to another element(s). or to describe features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation of the device in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relative descriptors used herein similarly interpreted accordingly.

RF semiconductor devices, typically fabricated on semiconductor-on-insulator (SOI) substrates, operate at high frequencies and generate RF signals. For these RF devices, the SOI substrates typically include a high resistance handle substrate, an insulating layer over the handle substrate, and a semiconductor layer overlying the insulating layer. The high resistance handle substrate has a low doping concentration and may have a resistivity ranging from 2 kiloohm-centimeters (kΩ-cm) to 8 kΩ-cm, for example point. The high resistance of the handle substrate can improve the radio frequency (RF) performance of the RF devices in some respects, but a judgment in the present disclosure lies in the fact that the high resistance handle substrate can still be a source of eddy currents when carrier be freed from the grid of the high impedance handle substrate by the RF signals. These eddy currents, which can have high frequencies, are a source of noise in the final chip. In particular, these eddy currents can lead to device crosstalk and/or non-linear signal distortion.

In order to prevent such crosstalk and non-linear signal distortion, the present disclosure proposes to fabricate the RF devices on an SOI substrate that includes a handle substrate, a layer of insulating material, and an active semiconductor layer. However, rather than leaving the existing handle substrate in the final device, the manufacturing process removes the handle substrate from the underside of the insulating layer prior to final packaging of the device, such that the handle substrate is no longer present and no longer acts as a source of eddy currents.

With reference to 1A Illustrated is a cross-sectional view of some embodiments of an apparatus 100 according to the present disclosure. The device 100 includes a first substrate 106 , an interconnect 112 disposed over the first substrate 106 , and a second substrate 122 disposed over the interconnect 112 . The first substrate 106 comprises an insulating layer 110 and an active semiconductor layer 108; and coupling structure 112 includes multiple metal layers (e.g., 114a-114e) disposed within dielectric structure 116 . One or more active components such as metal oxide semiconductor field effect transistors (MOSFETs) 111 are disposed in or over a transistor region 102 of the first substrate 106 and one or more passive components such as inductor 128, capacitor 130 and/or resistor 131 are over an RF region 104 of the first substrate 106 arranged. A substrate via (TSV) 118 extends vertically through the semiconductor layer 108 and through the insulating layer 110. The TSV 118 electrically couples a metal layer (e.g., 114a, 114b, 114c, ...) to a pad 120 on a bottom surface of the Insulating layer 110. A surface of pad 120 may be left exposed by a packaging or molding layer 121, allowing device 100 to be attached to a circuit board or other chip via solder bumps, wire bonds, etc. such that the circuit board or other chip may be electrically coupled to active and/or passive components on device 100 .

In particular, the first substrate 106 has an absence of a handle substrate under the insulating layer 110 and therefore, in some embodiments, the pad 120 is in direct contact with the bottom surface of the insulating layer 110. It will become more apparent below that with reference to FIGS 2 until 13 For example, device 100 may be fabricated by a process where first substrate 106 is initially an SOI wafer comprising semiconductor layer 108, insulating layer 110, and a handle substrate beneath insulating layer 110. In the final device, such as that shown in 1A 1, however, the underlying handle substrate has been removed to prevent the underlying handle substrate from acting as an eddy current source during device operation. Because insulating layer 110 is insulating (and therefore not susceptible to eddy currents), removal of the underlying handle substrate eliminates a source of problematic eddy currents from the underside of first substrate 106. Therefore, device 100 may exhibit less crosstalk and less distortion than conventional devices.

To compensate for the reduced thickness and structural rigidity of the first substrate 106 due to the removal of the underlying handle substrate and to provide sufficient thickness to adequately fill out a package and provide structural support during manufacture, a handle substrate 124 is disposed over a top surface 112u of the interconnect 112. An optional but beneficial trap layer 126 may separate the interconnect 112 from the handle substrate 124 . The trapping layer 126 is configured to trap carriers excited by RF components (e.g., inductor 128 and/or capacitor 130) to limit eddy currents in the handle substrate 124. As an example, consider a case where the inductor 128 and/or the capacitor 130 individually or collectively generate an RF signal that can excite carriers in the handle substrate 124 to some extent when an appropriate bias is applied. The trapping layer 126 is configured to trap these carriers to limit corresponding eddy currents. The trap layer 126 may manifest as doped or undoped polysilicon or an amorphous silicon layer in some embodiments. The trap layer 126 may meet the handle substrate 124 at an interface that in some cases has peaks and valleys, in other cases is substantially planar, or in other cases is generally roughened.

1B FIG. 12 shows some embodiments where the trap layer 126 is made of polysilicon and has multiple grain boundaries 132. FIG. The grain boundaries 132 are dislocations or faults where the atoms of the trap layer 126 are misplaced or misaligned within the crystal lattice. The grain boundaries 132 act as recombination centers configured to capture carriers (e.g., carriers from the handling substrate 124). Once the carriers are trapped within the recombination centers, their lifespan is reduced. Therefore, by trapping carriers within the grain boundaries 132 of the trapping layer 126, carrier accumulation along a bottom surface of the handle substrate 124 is substantially reduced, which mitigates eddy currents, crosstalk, and nonlinear distortion during operation of the device 100.

In some embodiments, an interface between the handle substrate 124 and the capture layer 126 includes a series of peaks 134 and valleys 136 that may form a sawtooth profile. The peaks 134 and valleys 136 facilitate smaller grain sizes and therefore facilitate more grain boundaries near the top surface of the handle substrate 124. Therefore, most carriers are trapped at the grain boundaries 132 to mitigate and/or prevent eddy currents. The elevations 134 and/or indentations 136 may be triangular, pyramidal, or conical in shape, among others. In some embodiments, the bumps 134 may have a height h ranging from about 10 nm to about 1 μm as measured from the base of an adjacent depression (or a more distant depression), and in some embodiments about 0.5 μm. The bumps 134 can also have a width w in the range of about 10 nm to about 10 μm and can be about 1 μm in some embodiments. In other embodiments, the bumps 134 may be tipped as illustrated rather than being flattened and/or may be rounded. Rather than terminating in a peak as illustrated, in other embodiments the indentations 136 may be flat or rounded. In some embodiments, adjacent ridges may have the same heights and/or widths as one another (adjacent troughs may also have the same depths and/or widths as one another), but ridges may also have different heights and/or different widths from one another (and troughs may have different depths and/or widths). In some cases, the peaks and/or valleys follow a random distribution of heights and/or widths, follow a Gaussian distribution of heights and/or widths, or follow some other distribution.

Advantageously, the incorporation of the handle substrate 124 over the interconnect structure 112 provides increased structural rigidity to compensate for the absence of a handle substrate under the insulating layer 110 . In addition, the trapping layer 126 advantageously reduces eddy currents as a potential source of noise in the handle substrate 124 and, although optional, is beneficial for many applications.

Referring to the 2 until 13 10 is a series of cross-sectional views collectively depicting a method of fabricating a device according to some embodiments.

2 FIG. 11 illustrates a cross-sectional view of some embodiments of providing an SOI substrate 106'. As illustrated by 2 the SOI substrate 106' is a semiconductor-on-insulator (SOI) substrate comprising a handle substrate 202, an insulating layer 110 disposed over the handle substrate 202, and a semiconductor layer 108 disposed over the insulating layer 110, includes. In many cases, the SOI substrate 106' may take the form of a disk-like wafer. Such a wafer may be, for example, 1 inch (25 mm) in diameter; 2 inches (51mm); 3 inches (76mm); 4 inches (100mm); 5 inches (130mm) or 125mm (4.9 inches); 150 mm (5.9 in, commonly referred to as "6 in"); 200 mm (7.9 in, commonly referred to as "8 in"); 300 mm (11.8 in, commonly referred to as "12 in"); or 450 mm (17.7 in, commonly referred to as "18 in"); exhibit.

The handle substrate 202 may have a thickness sufficient to provide the SOI substrate 106' with sufficient structural rigidity to withstand semiconductor processing operations. For example, in some embodiments, the handle substrate 202 has a thickness in the range of about 200 μm to about 1000 μm, and is about 700 μm in some embodiments. In embodiments, handle substrate 202 may be a low resistivity silicon handle substrate having a resistivity between several ohm-cm and tens of ohm-cm, and in some embodiments between 8 ohm-cm and 12 ohm-cm. In alternative embodiments, the handle substrate 202 may be a high-resistance silicon handle substrate with a resistivity between several hundred and several thousand ohm-cm, and in some embodiments between 2 kΩ-cm to 8 kΩ-cm. Although either a high-resistance or low-resistance silicon substrate may be used , it is advantageous to use low-resistance silicon substrates because low-resistance silicon substrates are cheap and have a larger specific resistance does not offer any significant advantages since the handle substrate 202 is removed in this manufacturing process. Other handle substrates such as sapphire substrates can also be used.

In some embodiments, the insulating layer 110 may have a thickness ranging from less than one micron to several microns, which is sufficient to provide electrical isolation between the handle substrate 202 and the semiconductor layer 108 . In some embodiments, insulating layer 110 may be silicon dioxide, which has a dielectric constant of about 3.9. In other embodiments, the insulating layer 110 may be a low-κ dielectric. Non-limiting examples of low-κ dielectric include, but are not limited to: fluorine-doped silica, carbon-doped silica, porous silica, porous carbon-doped silica, spin-on organic polymeric dielectrics, and/or spin-on silicon-based polymeric dielectric.

In some embodiments, the semiconductor layer 108 is a layer of pure silicon, which may have a monocrystalline lattice structure and may be intrinsic (eg, undoped) or doped p-type or n-type. Semiconductor layer 108 may have a thickness ranging from several micrometers down to about one nanometer in some embodiments. The semiconductor layer 108 may also be a compound semiconductor made of elements from two or more different groups of the periodic table. The elements can form binary alloys (two elements, e.g. GaAs), ternary alloys (three elements, e.g. InGaAs or AlGaAs) or quaternary alloys (four elements, e.g. AlInGaP). The semiconductor layer 108 may include doped regions, epitaxial layers, insulating layers formed in or on the semiconductor layer, photoresist layers formed in or on the semiconductor layer, and/or conductive layers formed in or on the semiconductor layer.

In 3 Active components such as MOSFETS 111 and/or other field effect transistors (FETs) are formed in or over a transistor region 102 of the semiconductor layer 108 . A shallow trench isolation (STI) region 117 is formed in which insulating material surrounds an island of the semiconductor layer 108 material. A gate electrode 123 is formed, sidewall spacers 125 are formed on opposite sidewalls of the gate electrode 123 , and source/drain regions 119 are formed on opposite sides of the sidewall spacers 125 . A gate dielectric 127 separates the gate electrode 123 from a channel region in the semiconductor layer separating the source/drain regions 119 . In some embodiments, gate electrode 123 comprises polysilicon or metal, sidewall spacers 125 comprises silicon nitride, and gate dielectric 127 comprises silicon dioxide or high-κ dielectric. Although not illustrated, transistors 111 may take other forms such as finFET devices, bipolar transistors, floating gate transistors, and so on. A resistor 131 , which can be made of polysilicon 135 , for example, and isolated from the semiconductor layer 108 by the gate dielectric and/or other dielectric 129 , can be formed in the RF region 104 . A dielectric layer 133 extends over top surfaces of gate electrodes 123 and source/drain regions 119. Dielectric layer 133 may comprise a low-κ dielectric or silicon dioxide.

In 4 For example, source/drain contacts 150 are formed to provide ohmic connection to source/drain regions 119 through dielectric layer 133, and gate contacts 152 are formed to provide ohmic connection to upper surfaces of gate electrodes 123. FIG. In some embodiments, source/drain contacts 150 and/or gate contacts 152 may comprise copper, tungsten, aluminum, gold, titanium, or titanium nitride, for example. A substrate via (TSV) 118 is also formed. The illustrated TSV 118 extends down through the dielectric layer 133, through the semiconductor layer 108, and through the insulating layer 110. In other embodiments, the TSV 118 may also extend down partially or fully through the handle substrate 202. The TSV 118 can be made of copper, tungsten, aluminum, gold, titanium, or titanium nitride, for example, and can be made of the same or different material than the source/drain contacts 150 and/or the gate contacts 152. The TSV 118 is typically formed by a separate photomask and/or etch is formed opposite the source/drain contacts and/or gate contacts.

As illustrated by 5 An interconnect 112 is formed over the SOI substrate 106'. The interconnect 112 is formed by forming a first dielectric layer 154, such as a low-κ dielectric layer, nitride, or silicon dioxide dielectric layer, and then forming one or more photoresist masks over the first dielectric layer 154. FIG. With an existing photoresist mask, an etch is performed around trench openings and/or via openings in the first dielectric layer 154 to form. Metal is then deposited to fill the openings in the first dielectric layer 154, forming vias and/or metal lines 156 corresponding to a metal i-layer. In some embodiments, copper is used to fill the openings in the first dielectric layer 154 such that vias and metal 1 lines are made of copper. In embodiments where copper is used, the openings are typically lined with a diffusion barrier layer, then a copper seed layer is formed over the diffusion barrier layer, and an electroplating process is used to build up copper and fill the openings. The diffusion barrier layer typically has a high electrical conductivity to maintain good electronic contact while maintaining a sufficiently low copper diffusivity to adequately chemically isolate these copper conductor films from underlying structures. Cobalt, ruthenium, tantalum, tantalum nitride, indium oxide, tungsten nitride, and titanium nitride are some non-limiting examples of materials that can be used for the diffusion barrier layer. After the metal is grown to fill the openings, a chemical mechanical planarization (CMP) operation is performed to planarize the first metal layer and first dielectric at level 154a. A second dielectric layer 158 is then formed, openings are formed in the second dielectric layer 158 and metal is deposited to form vias and metal-2 lines 160 . Additional dielectric and metal layers are formed in this manner until interconnect 112 is formed. As illustrated in 5 For example, the coupling structure 112 may include an RF component such as inductor 128 and/or capacitor 130 formed over an RF region 104 of the SOI substrate 106'.

In 6 a second handle substrate 124' such as a bulk silicon wafer is provided. The second handle substrate 124' may have a thickness ranging from 300 μm to 1000 μm, and in some embodiments is approximately 700 μm. In some embodiments, the second handle substrate 124' may have a resistivity that is greater than that of the handle substrate 202. For example, in some embodiments, the second handle substrate 124' may have a resistivity that is between several hundred and several thousand ohm-cm and in some embodiments is between 2 kΩ-cm to 8 kΩ-cm, which may help reduce eddy currents in the final device. In some cases, the second handle substrate 124' is intended for structural support and may therefore have an absence of device features and an absence of interconnect features in some embodiments. In many cases, the second handle substrate 124' may take the form of a disk-like wafer. Such a wafer may be, for example, 1 inch (25 mm) in diameter; 2 inches (51mm); 3 inches (76mm); 4 inches (100mm); 5 inches (130mm) or 125mm (4.9 inches); 150 mm (5.9 in, commonly referred to as "6 in"); 200 mm (7.9 in, commonly referred to as "8 in"); 300 mm (11.8 in, commonly referred to as "12 in"); or 450 mm (17.7 inches, commonly referred to as "18 inches");exhibit; and often has the same diameter as the SOI substrate 106'.

In 7 For example, a top surface of the second handle substrate 124' is etched to form bumps 134 and valleys 136. FIG. The bumps 134 and valleys 136 are fabricated by first using a photomask (not shown) to define a pattern on the top surface and then exposing the top surface to an etchant 702 to roughen the top surface with bumps and valleys close. In other embodiments, the second handle substrate 124' may be damaged by mechanically damaging the top surface of the second handle substrate 124' (e.g., micro-scratching, abrasive blasting, etc.) or by performing sputtering, deposition, or self-assembling monolayer. In some embodiments, the peaks and valleys comprise sawtooth-shaped projections and corresponding valleys, with peaks and valleys of the individual "teeth" being spaced at equal or random intervals. In other embodiments, the peaks and valleys comprise randomly shaped protrusions that have different lattice orientations and geometries. In some embodiments, the etchant 702 may comprise a dry etchant (e.g., a plasma etchant, an RIE etchant, etc.) or a wet etchant (e.g., hydrofluoric acid).

In 8th a trap layer 126 is formed over the peaks 134 and valleys 136 such that an interface is established between the trap layer 126 and the second handle substrate 124'. Therefore, a second substrate 122 is provided. In some embodiments, the trap layer 126 may be a polycrystalline silicon layer. In other embodiments, the trap layer 126 may comprise amorphous silicon that includes a dopant species. In various embodiments, the dopant species may include argon (Ar), carbon (C), and/or germanium (Ge). The surface 802 of the capture layer, that is farthest from the second handle substrate 124' may in some cases be planarized using, for example, CMP to make it more suitable for bonding.

In 9 the SOI substrate 106 ′ and the coupling structure 112 are bonded to the second substrate 122 . This bonding can take one of many forms, such as fusion bonding or epoxy bonding. In some embodiments, an oxide may be formed over the bottom surface of trap layer 126 prior to bonding, and the oxide on the bottom surface of trap layer 126 may then be bonded to the top surface of interconnect 112 by performing an anneal process.

In 10 the handle substrate 202 is removed. In some embodiments, a two-step process is used to remove handle substrate 202 . During a first stage, a grinding process is used to thin the handle substrate, for example, by a first distance d1. The grinding process may use a surface that is reasonably abrasive and therefore grinds down the handle substrate 202 distance d1 quite quickly. After the grinding process is completed, such as as determined by a predetermined time or by taking measurements indicating that the predetermined distance d1 has been removed; a chemical mechanical planarization (CMP) operation is performed to remove a second residual amount d2 of the handle substrate 202. FIG. The CMP operation typically uses a polishing pad that is less abrasive than grinding, thereby providing a smoother, more uniform surface than grinding. For example, the CMP operation may end after a predetermined time has elapsed or when measurements indicate that the handle substrate 202 has been completely removed. It is apparent that in some embodiments an amount of thinned handle substrate 202 is left on the bottom surface of insulating layer 110 .

11 shows the structure of 10 after CMP runs. In the example of 11 the lower section of TSV 118 is exposed.

In 12 a pad 120 in direct contact with the lower portion of the TSV 118 was formed. Pad 120 is in direct contact with the underside of insulating layer 110 in some embodiments. Pad 120 may be made of copper, tungsten, aluminum, gold, titanium, or titanium nitride, for example. In some embodiments, pad 120 is formed by forming a metal layer on the bottom surface of insulating layer 110 and then patterning the metal layer using, for example, a photolithographic mask and performing etching of the metal layer with the existing photolithographic mask. It should be noted that 12 12 shows several different TSVs 118, 118a, 118b and corresponding pads 120, 120a, 120b, respectively, to highlight some examples. TSV 118 extends between metal i-layer, dielectric layer 133, semiconductor layer 108 and insulating layer 110; while the second TSV 118a extends from a lower surface of the resistor 131 through the dielectric 129, the semiconductor layer 108 and the insulating layer 110. FIG. A third TSV 118b extends from the metal-2 line, through second dielectric layer 158, first dielectric layer 154, dielectric layer 133, through semiconductor layer 108, and through insulating layer 110.

After forming the pads 120, the structure, which is often still in the form of a disc-like wafer, can optionally be bonded to other substrates to create a 3D IC, and can be cut or scribed into individual dies or integrated circuits. Then in 13 a packaging layer 121 is formed to cover a lower surface of the insulating layer 110 . The packaging layer 121 may extend along sidewalls of the device to cover a top surface of the second handle substrate 122 . The packaging layer 121 can be made of ceramic or a polymeric material, for example, and can protect the device from environmental extremes, corrosive action, dirt, dust, water vapor, and so on.

14 FIG. 14 illustrates a flow chart of some embodiments of a method 1400 for manufacturing a device according to some aspects of this disclosure. Although the disclosed method 1400 is illustrated and described below as a series of acts or events, it is understood that the illustrated order of such acts or events should not be construed in a limiting manner. For example, some acts may occur in a different order and/or concurrently with other acts or events apart from those illustrated and/or described herein. Additionally, not all illustrated acts may be required to implement one or more aspects or embodiments of the description herein. Further, one or more of the acts presented herein may be performed in one or more separate acts and/or phases. Even though 14 to overview ality in relation to the 2 until 13 is described, it is evident that the structures in the 2 until 13 are disclosed, not to the method of 14 are limited, but instead can stand alone as structures independent of the process. Although the procedure of 14 in relation to the 2 until 13 is described, it is obvious that the method is not related to those in the 2 until 13 disclosed structures is limited, but instead independent of the in the 2 until 13 disclosed structures can stand alone.

At 1402, an SOI substrate is provided. The first substrate includes a first handle substrate, an insulating layer disposed over the first handle substrate, and a semiconductor layer disposed over the insulating layer. Therefore, 1402, for example 2 correspond.

At 1404, an interconnect is formed over the SOI substrate. The coupling structure includes multiple metal layers disposed within a dielectric structure. Therefore, 1404, for example 5 correspond.

At 1406, a second substrate is bonded to a top surface of the interconnect. In some embodiments, the second substrate includes a second handle substrate and a capture layer. In some such embodiments, after bonding, the tether layer is disposed between the second handle substrate and the top surface of the interconnect. Therefore, 1406, for example 9 correspond.

At 1408, the first handle substrate is removed to expose a bottom surface of the insulating layer after the second substrate is bonded to the top surface of the interconnect. Therefore, 1408, for example 10 correspond.

At 1410, a pad is formed in direct contact with the bottom surface of the insulating layer after the first handle substrate is removed. A substrate via (TSV) extends vertically through the insulating layer and the semiconductor layer and electrically couples the pad to a metal layer of the interconnect. Therefore, 1410, for example 12 correspond.

Claims (18)

Device comprising: a substrate (106) comprising a semiconductor layer (108) disposed over an insulating layer (110), the substrate (106) comprising a transistor device region (102) and a radio frequency (RF) region (104); a coupling structure (112) disposed over the substrate (106) and comprising a plurality of metal layers (114) disposed within a dielectric structure (116); a handle substrate (124) disposed over a top surface of the interconnect (112); a trap layer (126) separating the interconnect (112) and the handle substrate (124); a pad (120) disposed in direct physical contact with a bottom surface of the insulating layer (110) of the substrate (106); and a substrate via (118) extending vertically through the semiconductor layer (108) and the insulating layer (110) and electrically coupling the pad (120) to a metal layer (114) of the interconnect (112). device after claim 1 wherein the handle substrate (124) comprises a silicon substrate and the trap layer (126) comprises a polysilicon layer meeting the silicon substrate at a non-planar interface. device after claim 2 , wherein the non-planar interface comprises a series of bumps extending down from the silicon substrate into the trap layer (126). The device of any preceding claim, wherein the radio frequency (RF) region (104) comprises an RF device disposed in the interconnect (112) and configured to transmit an RF signal, the capture layer (126) configured to trap carriers excited by the RF signal to limit eddy currents in the handle substrate (124). The device of any preceding claim, further comprising: a packaging layer (121) covering a bottom surface of the insulating layer (110) and extending along sidewalls of the device to cover a top surface of the handle substrate (124). A method comprising: providing a first substrate (106) comprising a first handle substrate (202), an insulating layer (110) disposed over the first handle substrate (202), and a semiconductor layer (108) disposed over the insulating layer (110) includes; forming an interconnection structure (112) over the first substrate (106), the interconnection structure (112) including a plurality of metal layers (114) disposed within a dielectric structure (116) includes; Bonding a second substrate (122) comprising a second handle substrate (124) and a trap layer (126) to an upper surface of the interconnect (112), the trap layer (126) after bonding between the second handle substrate (124) and the upper surface of the coupling structure (112); after bonding, removing the first handle substrate (202) to expose a bottom surface of the insulating layer (110); and after removing the first handle substrate (202), forming a pad (120) in direct physical contact with a bottom surface of the insulating layer (110) of the first substrate (106) with a substrate via, TSV, (118) extending vertically through extending the semiconductor layer (108) and the insulating layer (110) and electrically coupling the pad (120) to a metal layer (114) of the interconnect (112). procedure after claim 6 , wherein the first (202) and the second (124) handle substrate have different ohmic resistances. Procedure according to one of Claims 6 or 7 wherein the first handle substrate (202) has a resistance between 8 ohm-cm and 12 ohm-cm. Procedure according to one of Claims 6 until 8th , wherein the first handle substrate (202) has a first ohmic resistance and the second handle substrate (124) has a second ohmic resistance and the second ohmic resistance is greater than the first ohmic resistance by a factor of ten or more. Procedure according to one of Claims 6 until 9 wherein the second handle substrate (124) comprises a silicon substrate and the trap layer (126) comprises an amorphous silicon layer. Procedure according to one of Claims 6 until 9 wherein the second handle substrate (124) comprises a silicon substrate and the trap layer (126) comprises a polysilicon layer meeting the silicon substrate at a non-planar interface. procedure after claim 11 , wherein the non-planar interface comprises a series of bumps extending down from the silicon substrate into the trap layer (126). procedure after claim 11 or 12 wherein the non-planar interface is formed by forming a photomask over a surface of the silicon substrate and etching the surface of the silicon substrate to form a series of peaks and valleys, and the trap layer (126) is formed directly over the series of peaks and valleys. Procedure according to one of Claims 6 until 13 wherein a radio frequency (RF) device is disposed in the coupling structure (112) and configured to transmit an RF signal, wherein the capture layer (126) is configured to capture carriers excited by the RF signal to prevent eddy currents in the second handle substrate (124). Method comprising: providing a semiconductor-on-insulator (SOI) substrate (106) comprising a first handle substrate (202) of silicon, an insulating layer (110) disposed over the first handle substrate (202), and an insulating layer ( 110) arranged silicon layer (108), said SOI substrate (106) comprising a transistor device region (102) and a radio frequency (RF) region (104) laterally spaced from each other; forming an interconnect (112) over the SOI substrate (106), the interconnect (112) comprising a plurality of metal layers (114) disposed within a dielectric structure (116); Bonding a second substrate (122) comprising a trap layer (126) and a second handle substrate (124) made of silicon to a top surface of the interconnect (112), the trap layer (126) after bonding the second separating the handle substrate (124) from the top surface of the interconnect structure (112); after bonding, removing the first handle substrate (202) to expose a bottom surface of the insulating layer (110); and forming a pad (120) in direct contact with a bottom surface of the insulating layer (110), with a substrate via (TSV, 118) extending vertically through the silicon layer (108) and through the insulating layer (110) to form the pad (120) to contact. procedure after claim 15 , wherein the first handle substrate (202) has an ohmic resistance which is smaller than that of the second handle substrate (124). procedure after claim 15 or 16 , further comprising: forming a gate dielectric on a top surface of the transistor device region (102) of the silicon layer (108); forming a gate electrode over the gate dielectric, coupling at least one of the metal layers to the gate electrode. procedure after Claim 17 wherein the substrate via (TSV, 118) electrically couples the pad (120) to the at least one of the metal layers.

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