DE102016114804A1 - Semiconductor device and method for its manufacture - Google Patents

Abstract

A semiconductor device includes a semiconductor substrate, a radiation sensing region, at least one isolation structure, and a doped passivation layer. The radiation sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims the benefit of US Provisional Application Serial No. 62 / 243,904 filed Oct. 20, 2015, which is incorporated herein by reference.

GENERAL PRIOR ART

An image sensor is a sensor that detects and transmits the information that constitutes an image. Complementary metal oxide semiconductor (CMOS) image sensors (CIS) are used in various applications such as digital camera or mobile phone camera applications. These devices use an array of pixels in a substrate that includes photodiodes and transistors that can absorb radiation projected toward the substrate and convert the detected radiation into electrical signals.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure will be best understood from the following detailed description when read with the accompanying figures. It should be noted that, according to industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

1 FIG. 10 is a flowchart of a method of forming a semiconductor device according to some embodiments of the present disclosure.

The 2A to 2F FIG. 15 are cross-sectional views of a semiconductor device at multiple intermediate stages of a formation process according to some embodiments of the present disclosure. FIG.

3 FIG. 10 is a sectional view of a semiconductor device according to some embodiments of the present disclosure. FIG.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments or examples to implement different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. Of course these are just examples and should not be limiting. For example, forming a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional functions may be formed between the first and second features so that the first and second features can not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

Further, spatially relative terms such as "below," "below," "below," "above," "upper," and the like may be used herein to facilitate discussion of the relationship of an element or feature to one or more other elements or to describe features as illustrated in the figures. The spatially relative terms, in addition to the orientation shown in the figures, are intended to encompass different orientations of the device in use or operation of the device. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatial relative descriptors used herein may be interpreted accordingly.

1 is a flowchart of a method 100 for forming a semiconductor device according to some embodiments of the present disclosure. The 2A to 2F FIG. 15 are cross-sectional views of a semiconductor device. FIG 200 at several intermediate stages of a formation process according to some embodiments of the present disclosure. However, it will be appreciated that additional steps may be implemented before, during, and after the method, and that some of the steps described may be replaced or eliminated for other embodiments of the method. The semiconductor device 200 and the procedure 100 for its manufacture will be described in common with reference to various figures.

With reference to 1 and 2A the procedure begins 100 with block 102 by forming a radiation sensing region 220 inside a front 212 a semiconductor substrate 210 , The semiconductor substrate 210 has the front 212 and a back 214 on. The front 212 can also be referred to as the front surface and the back 214 can also be referred to as the back surface. In some embodiments of the present disclosure, the completed semiconductor device may be a photosensitive device such as an image sensor device. at The finished semiconductor device is the back side 214 of the semiconductor substrate 210 designed to receive the incoming light. Therefore, the finished semiconductor device may be referred to as an illuminated backside image sensor, such as a Back Surface Illuminated (BSI) Complementary Metal Oxide Semiconductor (CIS) Image Sensor.

The semiconductor substrate 210 is made of a semiconductor material, such as silicon. In some embodiments, the semiconductor substrate 210 a silicon substrate doped with P-type impurities such as boron, in which case the semiconductor substrate 210 is a P substrate. Alternatively, the semiconductor substrate 210 another suitable semiconductor material. For example, the semiconductor substrate 210 a silicon substrate doped with N type dopants such as phosphorus, arsenic or antimony, in which case the semiconductor substrate 210 is an N-substrate. The semiconductor substrate 210 may include other elemental semiconductors such as germanium and diamond. The semiconductor substrate 210 may optionally comprise a compound semiconductor and / or an alloy semiconductor. Furthermore, the semiconductor substrate 210 an epitaxial layer (epi-layer) may be stretched for performance improvement and may include a silicon-on-insulator (SOI) structure.

Radiation sensing region 220 may be doped regions comprising the first dopants in the semiconductor substrate 210 by a method such as diffusion or ion implantation on the semiconductor substrate 210 be formed. Specifically, the semiconductor substrate becomes 210 with the first dopants from the front 212 implanted to the radiation-sensing region 220 to build. In some embodiments, the radiation sensing region may be 220 by performing a plurality of ion implantation processes on the semiconductor substrate 210 through the front 212 be formed. Radiation sensing region 220 is formed by multiple implant processes using different dopants, implant doses, and implant energies. The implant processes may also use different masks having different structures and aperture sizes. For example, N + implant, Array N well implant, and Deep Array N well implant can be performed.

Herein, the ion implantation process implants the semiconductor substrate 210 with first dopants having an opposite doping polarity as the semiconductor substrate 210 exhibit. In some embodiments, where the semiconductor substrate 210 is a P-type substrate, becomes the radiation-detecting region 220 doped with N-type dopants, for example. In some embodiments, where the semiconductor substrate 210 is an N-substrate, becomes the radiation-detecting region 220 doped with P-type dopants.

In 2A is the radiation sensing region 220 next to or near the front 212 of the semiconductor substrate 210 educated. In alternative embodiments, depending on the design needs and manufacturing requirements, the radiation sensing region may 220 further away from the front 212 be formed. The location or location of the radiation sensing region 220 can be adjusted by tuning an implantation energy level of the implantation process used to detect the radiation sensing region 220 to build. In some embodiments, a higher implant energy level results in a deeper implant, meaning that the radiation sensing region 220 further away from the front 212 is formed. Similarly, a lower implant energy level will cause the radiation sensing region 220 closer to the front 212 is formed.

2 B illustrates forming a connection structure 230 and a buffer layer 240 , In some embodiments, the connection structure becomes 230 over the front 212 of the semiconductor substrate 210 educated. The connection structure 230 comprises a number of patterned dielectric layers and conductive layers provided with various doped features, circuits and an input / output of the radiation sensing region 220 couple. The connection structure 230 includes an interlayer dielectric (ILD) and a multilayer interconnect (MLI) structure. The MLI structure includes contacts, vias and metal lines. For the purpose of illustration is in 2 a number of conductive lines 232 and vias / contacts 234 shown. It is understood that the conductive wires 232 and vias / contacts 234 are exemplary. The actual positioning and configuration of the conductive lines 232 and vias / contacts 234 can vary depending on design needs and manufacturing concerns.

In some embodiments, the MLI structure may include conductive materials such as aluminum, aluminum / silicon / copper alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, or combinations thereof, referred to as aluminum interconnect structures. Other fabrication techniques for forming the aluminum interconnect structure may include photolithography processing and etching to pattern the conductive materials for a vertical interconnect (via and contact) and horizontal interconnect (conductive line). Alternatively you can Copper multilayer interconnect structures can be used to form the metal structures. The copper multilayer interconnect structures may include copper, copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polysilicon, metal silicide, or combinations thereof. The copper multilayer interconnect structures may be formed by a technique including chemical vapor deposition (CVD), sputtering, plating or other suitable processes.

The buffer layer 240 is on the connection structure 230 educated. In some embodiments of the present disclosure, the buffer layer comprises 240 a dielectric such as silicon oxide. Alternatively, the buffer layer 240 optionally comprising silicon nitride. The buffer layer 240 is formed by CVD, physical vapor deposition (PVD) or other suitable techniques. The buffer layer 240 is planarized to form a smooth surface by a chemical mechanical polishing (CMP) process.

In some embodiments of the present disclosure, a carrier substrate then becomes 250 with the buffer layer 240 Bonded so that the processing of the back 214 of the semiconductor substrate 210 can be done. The carrier substrate 250 gets to the buffer layer 240 bonded by molecular forces. The carrier substrate 250 may be the semiconductor substrate 210 be similar and includes a silicon material. Alternatively, the carrier substrate 250 optionally comprise a glass substrate. The carrier substrate 250 provides protection for the various features on the front 212 of the semiconductor substrate 210 are formed. The carrier substrate 250 also provides mechanical strength and support for processing the backside 214 of the semiconductor substrate 210 which will be described below. An annealing process can be optionally performed to improve the bonding strength. The buffer layer 240 represents a potential separation between the connection structure 230 on the semiconductor substrate 210 and the carrier substrate 250 ready.

Thereafter, a thinning process (also referred to as a thinning process) may optionally be performed to form the semiconductor substrate 210 from the back 214 such thinning that the distance between the radiation sensing region 220 and the back 214 of the thinned semiconductor substrate 210 is reduced. In some embodiments, the thinning process includes a CMP process. The thinning process may also include a diamond wash process, a grinding process, or other suitable techniques. In some embodiments, the thinning process will continue until the radiation sensing region is reached 220 executed. Alternatively, in some embodiments, a reinforced and thin semiconductor substrate 210 which provides mechanical strength and support for the previous process, such as forming the connection structure 230 or the deposition of the buffer layer 140 In this case, the thinning process may be omitted.

2C illustrates forming a patterned hardmask layer 260 over the back 214 of the semiconductor substrate 210 , The structured hard mask layer 260 can be achieved by first forming a hard mask material over the backside 214 using a deposition process such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The hardmask material is then patterned in a photolithography process that can incorporate a photoresist material (not illustrated) and various exposure, development, firing, stripping, and etching processes. As a result, the patterned hard mask layer becomes 260 with openings 262 formed in it.

It is now referred to 1 and 2C , The procedure 100 goes to block 104 by forming at least one trench 270 in the back 212 of the semiconductor substrate 210 continued. The openings 262 the structured hardmask layer 260 continue into the semiconductor substrate 210 etched to the trenches 270 for example, using a dry etching process. This is the structured hard mask layer 260 as a protective mask during the etching process. In some embodiments of the present disclosure, the trenches extend 270 from the back 214 Radiation sensing region 220 and the radiation sensing region 220 , so the radiation-detecting region 220 divided into several regions.

In 2C is a cross-sectional area of the trench 270 adjacent to the back 214 of the semiconductor substrate 210 larger than a cross-sectional area of the trench 270 adjacent to the front 212 of the semiconductor substrate 210e , The trenches 270 have in the figure trapezoidal shapes with inclined side walls 272 and a bottom edge 274 However, various embodiments of the present disclosure are not limited in this regard. In alternative embodiments, the trenches 270 have approximately rectangular shapes, triangular shapes or other suitable shapes. In some embodiments, a cross section of the trenches narrows 270 from the back 214 Radiation sensing region 220 , Herein, at least one of the trench faces 270 a depth ranging from about 0.25 microns to about 4 microns.

It is now referred to 1 and 2D , After forming the trenches 270 becomes the structured hardmask layer 260 away. As shown in 2D are the back side 214 of the semiconductor substrate 210 and the side wall 272 and the bottom edge 274 of the trench 270 uncovered. That is, in some embodiments of the present disclosure, the back surface of the semiconductor substrate is 210 exposed for the next implant step.

It is now referred to 1 and 2E , The procedure 100 walk to step 106 by implanting second dopants from the backside 214 in the semiconductor substrate 210 progressed to a passivation layer 280 to build. In some embodiments of the present disclosure, the implantation process is performed without using a mask and the second dopants become the entire backside 214 of the semiconductor substrate 210 implanted.

Specifically, some of the second dopants will pass through the sloped sidewall 272 and the bottom edge 274 the trenches 270 implanted to the first sections 282 the passivation layer 280 to form, with the first sections 282 the passivation layer 280 the trenches 270 correspond. The other of the second dopants are through the backside 212 of the semiconductor substrate 210 implanted to second sections 284 the passivation layer 280 to form, with the second sections 284 the passivation layer 280 a flat profile as in the back surface of the semiconductor substrate 210 can have. The first paragraph 282 and the second section 284 the passivation layer 280 are formed simultaneously and continuously.

In some embodiments of the present disclosure, the trenches 270 with the inclined side walls 272 receive the second dopant well, when the implant process is performed in a direction to the back surface of the semiconductor substrate 210 is vertical. In some embodiments, the implantation process may be performed at a tilt angle while the sidewalls 272 the trenches 270 are respectively inclined to receive the second dopant well. However, various embodiments of the present disclosure are not limited in this regard, and a plasma diffusion process involving plasma immersion ion implantation may also be adopted and the passivation layer 280 may be formed on vertical sidewalls of the trenches (not shown) when the trenches have rectangular shapes.

Since implanting to form the passivation layer 280 from the back 214 is performed, implantation damage may occur at the radiation sensing region 220 in the semiconductor substrate 210 which occurs in a front side implantation process can be eliminated. Here is the dopant polarity of the passivation layer 280 the doping polarity of the radiation detecting region 220 opposed. That is, the second dopants of the passivation layer 280 have an opposite type to the first dopants of the radiation sensing region 220 on.

Herein may be the location or location of the passivation layer 280 adjusted by tuning an implantation energy level of the implant process. For example, a lower implant energy level causes the radiation sensing region 220 closer to the sloping side wall 272 and the bottom edge 274 the trenches 270 and the back 214 of the semiconductor substrate 210 is. Through the process, the passivation layer can 280 with the inclined sidewall 272 and the bottom edge 274 the trenches 270 and the back 214 of the semiconductor substrate 210 get connected. Alternatively, a higher implant energy level results in a deeper implant, meaning that the passivation layer 280 further away from the sloping sidewall 272 and the bottom edge 274 the trenches 270 and the back 214 of the semiconductor substrate 210 is formed. Through the process, the passivation layer can 280 from the inclined sidewall 272 and the bottom edge 274 the trenches 270 and the back 214 of the semiconductor substrate 210 be separated.

In some embodiments of the present disclosure, implanting may achieve a doping depth in a range of about 10 nanometers to about 2.5 micrometers and a dosage range in a range of about 1E11 ions / cm ² to about 1E13 ions / cm ² . As a result of implanting, the passivation layer becomes 280 around the trenches 270 and the back 214 of the semiconductor substrate 210 formed around.

Processes (such as etching processes) that are used around the trenches 270 can form into errors (such as free bonds) on the surfaces of the trenches 270 (like the side walls 272 ) result. These errors can be physical errors or electrical errors and could trap carriers such as electrons. The trapped carriers can generate leakage. Leakage is problematic for semiconductor devices such as photosensitive devices. With a sufficient amount of leakage current, radiation-detecting regions (which are not yet formed at this stage of manufacturing) may erroneously detect "light" even when the semiconductor device is placed in an optically dark environment. In other words, the semiconductor device may end up with "light" if it should not (because there really is no light). In this situation, the leakage current can be referred to as "dark current". Dark currents are formed by electrical crosstalk and cause a deterioration in the performance of the semiconductor device. Therefore, the dark currents are undesirable.

Here the passivation layer seals 280 essentially these errors on the surfaces of the trenches 270 , The sealed faults can not move around freely and are therefore much less likely to cause leakage. As such, the passivation layer assists 280 thereby eliminating the dark current and therefore reducing electrical crosstalk.

With reference now to 2F become the trenches 270 filled with a dielectric, according to trench isolation features 290 to build. The trench isolation features 290 are deposited by depositing a dielectric (such as an oxide material or a nitride material) from the backside 214 in the trenches 270 and thereafter by removing the portions of the dielectric outside of the trenches 270 formed by a chemical mechanical polishing (CMP) process. In some embodiments, the trench isolation features 290 from high-k dielectric material such as Al ₂ O ₃ , ZrO ₂ , barium strontium titanate (BST), lead zirconate titanate (PZT), ZrSiO ₂ , HfSiO ₂ , HfSiON, TaO ₂ or the like.

Herein, the trench isolation features define 290 multiple radiation sensing regions 222 in the radiation sensing region 220 , Radiation sensing regions 222 are capable of detecting or detecting radiation waves passing through the back 214 of the semiconductor substrate 210 to the radiation sensing regions 222 be projected. Radiation sensing regions 222 may be capable of detecting or detecting radiation having specific wavelengths that may correspond to light of different colors. In some embodiments, the radiation sensing regions comprise 222 a photodiode. In other embodiments, the radiation sensing regions may be 222 other types of photodiodes, photogates, reset transistors, source follower transistors or transfer transistors. For the sake of simplicity, the structural details are the radiation sensing regions 222 not illustrated.

In some embodiments of the present disclosure, a semiconductor device 200 obtained. The semiconductor device 200 includes the semiconductor substrate 210 , the radiation-sensing region 220 , the ditches 270 , the passivation layer 280 and the trench isolation features 290 , Radiation sensing region 220 will be adjacent to the front 212 educated. The trenches 270 have inclined side walls 272 and a bottom edge 274 on, with the trenches 270 from the back 214 Radiation sensing region 220 extend. The passivation layer 280 is adjacent to the back 214 of the semiconductor substrate 210 and the sloping sidewalls 272 and the bottom edge 274 of the trench 270 formed, wherein the passivation layer 280 the ditch 270 equivalent. The trench isolation features 290 are in the trenches 270 educated. The trench isolation features 290 define multiple radiation-sensing regions 222 the radiation sensing region 220 , The passivation layer 280 can with the trench isolation features 290 be connected.

In the present embodiments of the present disclosure, the distance is between one of the radiation sensing regions 222 the radiation sensing region 220 and the trench isolation features 290 reduced because the trench isolation features 290 after forming the passivation layer 280 be formed. Despite the reduced distance, the radiation sensing regions have 222 in the semiconductor device 200 a large size and can therefore improve the full-well capacity (FWC).

In some embodiments, the semiconductor device comprises 200 continue the connection structure 230 , the buffer layer 240 and the carrier substrate 250 , The connection structure 230 is on the front 212 of the semiconductor substrate 210 educated. The buffer layer 240 is on the connection structure 230 educated. The carrier substrate 250 is at the buffer layer 250 bonded. The function and detail configuration have been previously illustrated and will not be repeated here.

3 Fig. 10 is a sectional view of a semiconductor device 200 in accordance with some embodiments of the present disclosure. The present embodiments are the embodiments of 2F similar but at least one of the differences between the present embodiments and the embodiments of FIG 2F is that a back deep trench isolation (BDTI) structure is adopted in the present embodiments. As shown in the figure, at least one of the trench isolation feature extends 290 from the back 214 Radiation sensing region 220 and penetrates through the radiation-sensing region 220 , so the radiation-detecting region 220 into the multiple radiation sensing regions 222 is shared.

The manufacturing process of the semiconductor device 200 The present embodiment is substantially the same as that of the embodiments of FIG 2F and the difference is that the trenches 270 are formed deeper than those of the previous embodiments, by the radiation detecting region 220 penetrate (refer to 2C ). The passivation layer 280 and the trench isolation features 290 which are subsequently formed have shapes that correspond to the deeper trenches 270 such that the trench isolation features 290 the radiation sensing regions 222 define. In support of some embodiments of the present disclosure, the passivation layer 280 at the bottom 274 of the trench 270 is formed, the front 212 achieve such that the semiconductor substrate 210 and the radiation sensing region 220 divided into several separate parts in the cross-sectional view. In some other embodiments, the trenches 270 be extended and the front 212 reach and the passivation layer 280 Can on the side walls 272 but not at the bottom 274 of the trench 270 to be formed.

Other details of the present embodiments are substantially the same as in the embodiments of FIG 2F and therefore will not be repeated herein.

In the embodiments of the present disclosure, the passivation layer is formed on the sidewall and bottom edges of the trench isolation features and the back surface of the substrate. Despite the process, no additional mask is required to form the passivation layer. Since the implantation for forming the passivation layer is performed from the back side, the implantation damage to the substrate can be eliminated. In addition, the radiation-detecting regions have a large size to obtain the full-well capacity. The deep trench isolation feature semiconductor device may also be fabricated by the methods of the present embodiments.

According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, a radiation sensing region, at least one isolation structure, and a doped passivation layer. The radiation sensing region is present in the semiconductor substrate. The isolation structure is present in the semiconductor substrate and adjacent to the radiation sensing region. The doped passivation layer at least partially surrounds the isolation structure in a substantially conformal manner.

According to some embodiments of the present disclosure, a semiconductor substrate, a radiation sensing region, at least one dielectric, and a doped passivation layer. The semiconductor substrate has at least one trench in it. The radiation sensing region is present in the semiconductor substrate. The dielectric is present in the trench of the semiconductor substrate. The doped passivation layer is present at least in at least one side wall of the trench and at least substantially corresponds thereto.

According to some embodiments of the present disclosure, a method of forming a semiconductor device includes forming at least one radiation-detecting region in a semiconductor substrate; forming at least one trench in a backside of the semiconductor substrate and adjacent to the radiation sensing region; and implanting a first dopant into the semiconductor substrate from the backside of the semiconductor substrate after forming the trench.

The foregoing describes features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. It should be apparent to one skilled in the art that he may readily use the present disclosure as a basis to design or modify other processes and structures to accomplish the same purposes and / or achieve the same advantages of the embodiments introduced herein. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the present disclosure.

Claims (20)

A semiconductor device, comprising: a semiconductor substrate; a radiation-detecting region present in the semiconductor substrate; and at least one isolation structure present in the semiconductor substrate and adjacent to the radiation sensing region; and a doped passivation layer at least partially surrounding the isolation structure in a substantially conformal manner. The semiconductor device according to claim 1, wherein the semiconductor substrate has a front side and a back side, and the radiation detecting region is adapted to detect a radiation wave entering the semiconductor substrate through the back side of the semiconductor substrate, and the insulating structure extends from the back surface of the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor substrate has a front side and a back side, the radiation detecting region is adapted to detect a radiation wave entering the semiconductor substrate through the back side of the semiconductor substrate, and the doped passivation layer is at least partially in the back side of the semiconductor substrate Semiconductor substrate is present. Semiconductor device according to one of the preceding claims, wherein the doped passivation layer substantially corresponds to the back side of the semiconductor substrate. The semiconductor device of claim 1, wherein the radiation sensing region comprises a first type of dopant and the doped passivation layer comprises a second dopant and the second type of dopant is opposite to the first type of dopant. A semiconductor device according to any one of the preceding claims, wherein the insulation structure comprises a deep trench isolation structure. The semiconductor device according to claim 1, wherein the semiconductor substrate has a front side and a back side, the radiation-detecting region is adapted to detect a radiation wave entering the semiconductor substrate through the back side of the semiconductor substrate, and a cross-sectional area of the insulation structure adjacent to the back side of the semiconductor substrate Semiconductor substrate is larger than a cross-sectional area of the insulating structure adjacent to the front side of the semiconductor substrate. A semiconductor device, comprising: a semiconductor substrate having at least one trench therein; a radiation-detecting region present in the semiconductor substrate; at least one dielectric present in the trench of the semiconductor substrate; and a doped passivation layer which is present at least in at least one side wall of the trench and this at least substantially corresponds. The semiconductor device of claim 8, further comprising: a connection structure provided on a front side of the semiconductor substrate, wherein the trench extends from a back side of the semiconductor substrate. A semiconductor device according to claim 8 or 9, further comprising: a connection structure provided on a front side of the semiconductor substrate, wherein the doped passivation layer is at least partially present in a back side of the semiconductor substrate. The semiconductor device of claim 10, wherein the doped passivation layer substantially corresponds to the backside of the semiconductor substrate. The semiconductor device of claim 8, wherein the radiation-detecting region comprises at least one of an N-type dopant and a P-type dopant, and the doped passivation layer comprises the other of the N-type dopant and the P-type dopant. A semiconductor device according to any one of claims 8 to 12, wherein the doped passivation layer is present at least in a lower edge of the trench and at least substantially corresponds thereto. A semiconductor device according to any one of claims 8 to 13, wherein the radiation sensing region is surrounded by the dielectric and the doped passivation layer is present between the radiation sensing region and the dielectric. A semiconductor device according to any one of claims 8 to 14, further comprising: a connection structure provided on a front side of the semiconductor substrate, wherein the doped passivation layer or the trench reaches the front side of the semiconductor substrate. A semiconductor device according to any one of claims 8 to 15, further comprising: a connection structure provided on a front side of the semiconductor substrate, wherein the trench narrows from a back side of the semiconductor substrate to the radiation detecting region. A method of forming a semiconductor device, comprising: Forming at least one radiation-detecting region in a semiconductor substrate; Forming at least one trench in a back side of the semiconductor substrate and adjacent to the radiation sensing region; and Implanting a first dopant into the semiconductor substrate from the backside of the semiconductor substrate after forming the trench. The method of claim 17, further comprising: filling the trench with a dielectric. The method of claim 17 or 18, wherein forming the radiation sensing region comprises: implanting a second dopant into the semiconductor substrate from a front side of the semiconductor substrate Semiconductor substrate, wherein the first dopant is of an opposite type to the second dopant type. The method of any one of claims 17 to 19, further comprising: Forming a connection structure on a front side of the substrate.

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