DE102016015712A1 - Half bridge circuit and clip wire pack - Google Patents

Abstract

A half-bridge circuit (100) comprising an input terminal (102) for providing an electrical input, an output terminal (104) for providing an electrical output to a load to be connected to the output terminal (104), a switch (106), and a diode (108) between the input terminal (102) and the output terminal (104); and a voltage limiting inductor (110) disposed between the switch (106) and the diode (108) and configured to limit a voltage upon switching of the switch.

Description

Background of the invention

Field of the invention

The present invention relates to a half-bridge circuit, a method of operating a half-bridge circuit and a package.

Description of the Prior Art

A buck converter is a DC / DC power converter that decouples a voltage from its input (supply) to its output (load) while the current is being boosted. It typically includes at least two semiconductors (one diode and one transistor, although modern down-converters often replace the diode with a second transistor used for synchronous rectification) and at least one energy storage element (such as a capacitor, coil, or the two in combination ). To reduce voltage ripple, capacitors constructed from capacitors (sometimes in combination with coils) may be added to an output (load side filter) and input (supply side filter) of such a converter.

The requirement profile of high performance synchronous buck converters requires high conversion efficiency over the entire load range. To achieve this, various measures must be taken to achieve proper behavior. As one of the requirements for adequate efficiency, the FETs must be switched as fast as possible. However, extremely fast switching can lead to voltage overshoot that may be outside the safe operating range of the device, i. H. the device can enter an avalanche.

Summary of the invention

There may be a need for a half-bridge circuit and package with adequate performance and high reliability during operation.

According to an embodiment, there is provided a half-bridge circuit having an input terminal for providing an electrical input (such as an input voltage), an output terminal for providing an electrical output (such as an output current) (for example, a load to be connected to the output terminal) Switch and a diode between the input terminal and the output terminal and a Spannungsbegrenzungsinduktivität that between the switch and the diode designed (in particular dimensioned) and arranged, and is configured to limit a voltage when switching the switch (in particular when switching the switch of a "On" state to an "off" state).

According to another embodiment, there is provided a method of operating a half-bridge circuit, the method comprising providing an electrical input to an input terminal, generating an electrical output by a switch and a diode between the input terminal and an output terminal to which a load is connected, and Limiting a voltage occurring when the switch is switched by a voltage limiting inductance, which is arranged between the switch and the diode.

According to yet another embodiment, a package is provided that includes a gripping clip and a wire, wherein the wire is connected to the clip (in particular, connected to an upper major surface of the clip).

According to a particular aspect of embodiments, a voltage limiting inductance between a switch and a diode of a half-bridge circuit is designed such that in the event that the switch is rapidly switched during operation of the half-bridge circuit (particularly when the switch is turned off) a voltage overshoot occurs State of the art brings the switch to its or even about its breakdown voltage can be kept sufficiently small, so that the functionality of the half-bridge circuit is not disturbed. In particular, the design may be such that the voltage overshoot when switching the switch can be kept so small that it always remains reliably below the breakdown voltage. More specifically, the design of the voltage limiting inductance may be such that the overshoot voltage is reliably limited below the breakdown voltage and at the same time does not unduly limit a performance of the half-bridge circuit.

In accordance with another aspect of embodiments, an electrically conductive clip used in the prior art to directly electrically contact a semiconductor die on a submount, such as a leadframe, may be directly connected to one or more electrically conductive wires, which may be one associated surface portion of the clip within an electronic element, for example with a semiconductor chip of a corresponding package, can electrically couple. Thus, the functionality of a clip may be extended to contribute to bond wire-based electrical coupling in addition to the direct, electrical coupling function of the clip. Such an architecture allows space to be saved and provides a high degree of flexibility for a circuit designer.

Description of further embodiments

In the context of the present application, the term "voltage limiting inductance" may refer in particular to an inductance which is spatially arranged directly between the switch and the diode. Such a voltage-limiting inductance may be a lumped element or a correspondingly and intentionally defined and designed parasitic inductance in the mentioned spatial region.

In the context of the present application, the term "clip" may in particular denote a solid, electrically conductive structure (in particular constructed of copper), which may be embodied as a sheet (for example bent and / or structured) and for contacting a surface of a sheet Semiconductor chips can be configured from above. A clip-bonding technology is an alternative to a wire bond between a semiconductor chip and a terminal through a solid metal bridge (especially a copper bridge). Such a clip may be connected to the semiconductor chip by soldering using solder paste. A clip may be a three-dimensional curved structure capable of covering an upper major surface of a semiconductor chip with a first surface portion of the clip and a surface portion of a carrier (eg, a chip carrier such as a leadframe on which the semiconductor chip mounted) on which the clip is simultaneously supported. Assembled with the carrier and the semiconductor chip, the clip presses from above onto the semiconductor chip. A clip may include an upper plate portion, a lower connecting portion, and a vertical transition portion therebetween.

In the following, further embodiments of the half-bridge circuit, the method and the pack will be explained.

In one embodiment, the switch is configured as a transistor switch, in particular as a field effect transistor switch. Such a transistor switch can form a high-side switch.

In one embodiment, the diode is configured as a transistor diode, in particular as a field effect transistor diode. Such a transistor diode can form a low-side switch.

In one embodiment, the voltage limiting inductance is arranged between a source terminal of the transistor switch and a drain terminal of the transistor diode. This position of the voltage limiting inductance has been found to be highly effective in reducing overshoot in half-bridge down converter designs. With a properly positioned voltage limiting inductance, it is possible to generate feedback using a source inductance to reduce gate current.

In one embodiment, the voltage limiting inductance has an inductance value that is large enough that the voltage when the switch is switched remains below a breakdown voltage of the switch. In one embodiment, this voltage may be limited to less than 30V, in particular it is limited to not more than 25V. By doing this, it can be prevented that the voltage at the switch reaches or even exceeds the breakdown voltage, which may deteriorate the half-bridge circuit.

In one embodiment, the voltage-limiting inductance has an inductance value of at least 50 pH, in particular of at least 80 pH, more particularly of at least 100 pH. When the voltage limiting inductance is a parasitic inductance rather than a lumped element, a connection between the source terminal of the switch and the drain terminal of the diode may be defined to achieve the mentioned values of inductance. For example, this can be achieved by configuring the connection between the source terminal of the switch and the drain terminal of the diode through a clip.

In one embodiment, the half-bridge includes a loop between the input terminal and the output terminal and including both the switch and the diode. Proper design of this loop has proven to be an effective measure for suppressing voltage overshoot during switching of the half-bridge.

In one embodiment, an inductance value of the voltage limiting inductance is at least 20%, in particular in a range between 20% and 70%, of a loop inductance of the loop. A percentage of approximately 20% has been found to be particularly effective for sufficiently reducing voltage overshoot during switching. A percentage of below 70% has been found to be particularly advantageous because then a slight reduction in the conversion efficiency of the half-bridge caused by the voltage limiting inductance can be kept very small.

In one embodiment, an inductance value of a gate inductance of the transistor switch is below 1 nH, in particular it is not more than 500 pH. While a relatively high voltage limiting inductance has been found to be beneficial in suppressing overshoot, this effect can be further enhanced by simultaneously keeping the gate inductance of the switch sufficiently low.

In one embodiment, the half-bridge circuit is configured to bypass the voltage-limiting inductance under a particular condition or operating state of the half-bridge circuit. For example, such a bypass may occur when the switch is switched from an "off" state to an "on" state, in which case overshoot problems as compared to switching the switch from an "on" state to a "on" state. Out of "condition are less severe. Another opportunity for enabling bypass is the event of detecting that a value of electrical current in the half-bridge circuit is below a predefined threshold, in particular below 20A. As mentioned above, the insertion of the voltage limiting inductance may slightly degrade the conversion efficiency of the half-bridge. In order to limit this slight reduction in efficiency to cases where the presence of a sufficiently high voltage limiting inductance is necessary (especially in a high current range), the voltage limiting inductance can be removed from the current flow path if overshoot protection is not necessary or not desired ( especially in a region of low current).

In one embodiment, the half-bridge circuit is configured as a semiconductor package. In the context of the present application, the term "package" may in particular designate at least one at least partially encapsulated or surface-mounted semiconductor chip having at least one external, electrical contact (such as a pad, for example). The semiconductor chip may include at least one integrated circuit element (eg, a diode or a transistor) in a surface portion thereof. The semiconductor chip may be a bare die, or it may already be packed or encapsulated. Such a semiconductor chip may be embedded in or surface-mounted on the interior of the encapsulant.

In one embodiment, the switch and diode belong to a common package. In particular, the switch and the diode can be mounted on the same mounting base, in particular on the same leadframe. It is also possible that the switch and the diode are electrically connected to each other by a bridging clip.

In one embodiment, the half-bridge circuit is configured as a buck converter circuit. In addition to a half-bridge circuit (which may have alternately connected transistors), a converter circuit may additionally have one or more further electronic elements (in particular at least one additional passive electronic element).

In one embodiment, the half-bridge circuit further includes a clip configured to couple the switch to the diode. Such a clip may be constructed from a metallic sheet such as a copper sheet. Clip coupling rather than just bond wires coupling has proven to be a powerful mechanism for adjusting the voltage limiting inductance to provide overshoot protection.

In one embodiment, at least a portion of the voltage limiting inductor forms at least a portion of the clip. The clip may have further sections, however, a particular clip section may define the value of the voltage limiting inductance by forming a bridge from the source terminal of the switch to the drain terminal of the diode. As an alternative to a clip section or to the entire clip, it is possible for the voltage limiting inductance to be formed by one or more wires.

In one embodiment, the switch is configured as a first semiconductor chip, the diode is configured as a second semiconductor chip, and the clip covers at least a portion of the first semiconductor chip and the second semiconductor chip. A semiconductor die may be a die (such as a piece of silicon) having an active region in which one or more integrated circuit elements (such as a transistor or a diode) may be monolithic.

In one embodiment, the half-bridge circuit further comprises at least one wire having a gap between the clip and a Semiconductor chip, in particular a driver of the half-bridge circuit, bridged. Thus, the combination of one or more bond wires and one or more clips provides powerful circuitry to a circuit designer for shaping the voltage limiting inductance and other circuit characteristics.

In one embodiment, the clip comprises a first section, in particular a plate-like section, which carries a load current, and comprises a second section, in particular a finger-like section, which is electrically connected to the first section but does not conduct the load current during operation of the half-bridge circuit , In other words, a main area of the clip may be arranged so that the main flow can flow over the main area. Apart from that, a finger of the clip may be arranged and dimensioned to prevent it from carrying a significant amount of the load current. For example, only one gate charge current may be allowed to flow across the finger portion. It is possible that such a finger portion is not at a source potential of the switch.

In one embodiment, the half-bridge circuit further includes an energy-dissipating ohmic resistor in series with the switch. Such an energy dissipating ohmic resistor can be used with the switch and with the diode as in 10 be connected (see reference number Ross_Q1). Such an energy dissipating ohmic resistor can dissipate excess energy that occurs during switching, and thus can contribute to limiting overshoots in voltage.

In one embodiment, the half-bridge circuit further includes a load-suppressing ohmic resistor in parallel with the switch. Such a load-suppressing ohmic resistor can be connected to the switch and to the diode as in 10 be connected (see reference R_chan). Such a charge suppressing ohmic resistor can slow the switching and therefore also contribute to limiting overshoot. In one embodiment, this resistor is not a physical element, but is created by slightly holding the MOSFET channel open to allow current flow. For example, a charge suppressing ohmic resistance path may be provided.

In one embodiment, the half-bridge circuit is configured such that when the switch is turned "on" and the switch "off", the voltage limiting inductance is always within a current flow path. Such an embodiment is in 5 and may be suitable for a design incorporating MOSFETs with a low breakdown voltage.

In another embodiment, the half-bridge circuit is configured such that when the switch is "on", the voltage limiting inductor is outside a current flow path and when the switch is "off", the voltage limiting inductance is within the current flow path. Such an embodiment is in 6 and may be suitable where maximum power is desired because this embodiment in the less critical "switch on" configuration allows the half-bridge circuit to operate without the influence of the voltage limiting inductance.

In one embodiment, the voltage limiting inductor is configured as an inductive feedback element configured to limit a gate current of the switch in the event of a rapidly changing electrical current in the half-bridge circuit. Based on this principle, a voltage overshoot can be effectively suppressed, particularly when the switch is turned off. This can lead to a more reliable half-bridge circuit.

In an embodiment, the package with the wire-on-clip configuration further comprises at least one semiconductor chip. The latter semiconductor chip can be electrically coupled to the clip via the wire. A certain end of the wire may be set on an upper major surface of the clip, whereas the other end of the wire may be fixed on a pad of the semiconductor chip.

In one embodiment, at least one further semiconductor die is electrically coupled (i.e., without wire) to the clip. Thus, the package may include a plurality of semiconductor chips, a certain portion of which may be coupled directly to the clip, while another portion thereof may be indirectly coupled to the clip via the wire. Direct coupling between the clip and the semiconductor chip can be achieved by soldering.

In one embodiment, the wire is a bonding wire. Thus, wirebond clip hybrid coupling in a semiconductor package can be achieved. This increases the freedom of design of a circuit designer.

In one embodiment, the clip comprises a plate-like section and at least one finger section formed integrally with the plate-like section. Therefore, a purely geometric design can be different Clip sections are assigned different functions. For example, the fact that an electrical current preferably flows along a path of low ohmic resistance may be used to define low-current and low-current portions of the clip.

In one embodiment, the at least one finger section is an overhanging structure. Such an overhanging structure may either hang freely in a cantilever manner with respect to a mounting base (such as a leadframe) or may be supported by a support member (such as a support post) to prevent unwanted flexing of the overhanging finger (e.g. Connecting a bonding wire with the finger a force is applied).

In one embodiment, the package comprises a carrier, in particular a leadframe, on which the clip is mounted. The carrier may form a mounting base on which the one or more semiconductor chips are mounted. The clip and the at least one wire are disposed on the semiconductor chips and provide electrical contact from an upper surface side.

In one embodiment, at least a portion of the clip is covered with a coating, particularly a coating comprising at least one of the group consisting of silver, gold, palladium, nickel and nickel-phosphorus. Usually, a clip can be made of copper. Copper, however, tends to oxidize on a surface. Therefore, to make a reliable electrical connection to a wire, it may be necessary to clean or chemically treat an oxidized top surface of the clip prior to wire bonding to remove the surface layer of copper oxide. However, when the copper clip is covered with a coating (or any other coating) that does not tend to oxidize (a condition that is met for the examples of coating materials given above), wire bonding may be applied to such a coating directly and without pretreatment be executed.

In an embodiment, the wire comprises at least one of the group consisting of silver, aluminum, gold, and copper. However, other materials are possible.

In one embodiment, the wire comprises at least one of the group consisting of a ball, a wedge and a band. A ball and a wedge may define end portions of a bonding wire. Apart from a thread-like bonding wire shaped like a yarn, it is also possible to implement a ribbon-type bonding wire constructed of a flat strip of electrically conductive material.

In one embodiment, the package is configured as one of the group consisting of a DC / DC conversion package (such as a buck converter) and a motor drive package. For example, a half-bridge may be provided with a driver for motor control.

The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings, in which like parts or elements are denoted by like reference characters.

Brief description of the drawings

The accompanying drawings, which are included to provide a more thorough understanding of embodiments of the invention and which form a part of the specification, illustrate embodiments of the invention.

In the drawings:

1 FIG. 12 illustrates a circuit diagram of a buck converter with a half-bridge according to one embodiment. FIG.

2 FIG. 12 is a diagram illustrating a conversion efficiency of a prior art half-bridge and a half-bridge according to an embodiment in accordance with a current. FIG.

3 1 is a diagram illustrating a maximum voltage of different transistors of a half-bridge according to one embodiment, depending on a current.

4 1 illustrates, in accordance with one embodiment, a three-dimensional view of a pack of a down converter having a half-bridge incorporating a bond wire-bonded clip.

illustrate 5 and 6 In one embodiment, plan views of packages of a buck converter with a half bridge incorporating a bond wire connected clip.

7 and 8th illustrate schematics of a buck converter with a half-bridge.

9 FIG. 15 is a diagram showing a maximum voltage of different transistors of the half-bridge according to FIG 7 and 8th illustrated.

10 FIG. 12 illustrates a circuit diagram of a buck converter with a half-bridge and including elements (in particular R_chan, Ross_Q1) which are used in the half-bridge circuit according to FIG 1 can be implemented.

11 is a diagram showing a maximum voltage and an efficiency of the half-bridge according to 10 depending on a resistance value illustrated.

12 FIG. 15 is a diagram showing a maximum voltage of different transistors of the half-bridge according to FIG 10 depending on a current illustrated.

13 is a diagram showing an efficiency of the half-bridge according to 10 depending on a current illustrated.

14 FIG. 15 is a diagram showing a maximum voltage of the switch transistor of the half-bridge according to FIG 10 depending on a current and illustrated in different configurations.

15 FIG. 12 illustrates, in accordance with one embodiment, a plan view of a pack of a down converter having a half bridge incorporating a bond wire connected clip. FIG.

Detailed description of embodiments

The illustration in the drawing is schematic and not to scale.

An embodiment of the invention implements an inductive feedback element in an integrated power stage that can reduce gate current in the event of a rapid change in current over time. In particular, in combination with a low-inductance gate circuit, this can limit the maximum source-drain voltage (VDS) across the switch to a desired value. Thus, a major point of an embodiment is to actively make a source inductance, for example, by one or more additional terminals (eg, an additional finger of a clip, correspondingly adapted bond wires in the case of wire bonding, etc.). Generating a suitable source inductance can also be done on the clip itself to generate the necessary voltage drop. Also wire bonding from gate to source pad or to a leadframe may be possible to realize the described technical functions.

According to embodiments, a multiple finger clip design is implemented to bring the potential from the drain terminal of the diode to the surface of the switch (the length of a corresponding cut defines the inductance value of the voltage limiting inductance). Such an additional clip finger may be in mechanical contact with a passivated surface (to allow wire bonding on the clip). The clip finger may be soldered to the die in an associated land area (isolated from the source terminal of the FET), and a connection to the gate driver (phase wire) may be made by wire bonding on the chip surface. In particular, the source inductance can be realized by the clip, but the connection from the drain of the inverted low-side FET can be made by wire bonding.

Particularly advantageous is a design in which the source inductance is a quarter or more of the Gesamtschleifeninduktivität.

In one embodiment, the effect on power up and power off may be disconnected if a bootstrap capacitor is connected to the switch. It is possible to design different source inductance values for turn-on and turn-off.

In one embodiment, it is possible to provide source feedback for both junctions, where both the capacitor and the gate driver are interconnected to produce the inductive effect. In another embodiment, such feedback is provided only for the turn-off phase. In yet another configuration, feedback is enabled only for power up (in such an embodiment, a driver may be directly connected to the FET).

It may be advantageous to have a fast gate loop, i. H. to have a low gate loop inductance for a faster response. In this context, it is possible that an NMOS of the output stage of the high-side driver may be integrated into the switch. It may also be advantageous to provide a power stage with integrated NMOS in the high-side switch together with the source feedback loop design described above.

Since the feedback is only needed for higher currents (for example, at I ≥ 20 A), in a particular embodiment, it can be bypassed at lower currents to achieve optimum efficiency.

According to one embodiment, a dual port power stage may be provided, wherein the driver determines the current and uses the appropriate port based on the result to optimize low load and peak efficiency.

Before describing embodiments of the invention, based on 1 to 6 . 15 In further details, some difficulties in prior art half-bridge downconverters as explained by the inventors of the present invention are explained. Then, an improved or optimized package design will be described thereafter to reduce or minimize overshoot in buck converters in accordance with embodiments of the invention.

One difficulty with half-bridge downconverters is that fast switching can cause voltage overshoots. This is especially critical for the high side switch: when the field effect transistor (FET) is turned on, the energy stored in the magnetic field of the power loop will keep the current flowing, which will charge the output capacitance of the FET. In a circuit of the prior art, there is no effective bypass element that could absorb the energy. When the magnetic energy (roughly given as EM = L · I ^2/2, where L is the inductance and I is current) EM is greater than the energy Ec of the output capacitor can store (EC = C · V DS ^2/2, where C is the capacitance), the voltage can reach the breakdown voltage. Since the inductance can not be reduced to zero and load current values tend to go up, avalanche cases may be unavoidable for highly efficient down-converters.

Embodiments of the invention provide a solution that effectively reduces the voltage spikes of integrated buck converters (power stages) while maintaining the conversion efficiency at a high level.

7 and 8th illustrate schematics 200 a buck converter with a half bridge.

Between an inlet 202 and an outlet 204 is an arrangement of a transistor switch 206 and a transistor diode 208 provided. An inlet capacity 214 , a loop inductance 210 and an outlet capacity 212 are also available. As 8th can be removed, the part of the circuit diagram acts 200 on the left as an AC loop, whereas the part of the circuit diagram 200 on the right side acts as a DC loop.

7 and 8th thus show a circuit diagram 200 in that the two field-effect transistors Q1 and Q2 are connected in a half-bridge configuration. As soon as Q1 in the schematic 200 according to 7 is switched off, it corresponds to the simplified circuit diagram 200 from 8th ,

9 is a diagram 900 , which measures a maximum voltage VDS of different transistors of the half-bridge 7 and 8th illustrated. Along an abscissa 902 the current is shown. Along an ordinate 904 the maximum voltage is shown. Thus shows 9 in that in the given example the simulated maximum voltage across Q1 reaches the breakdown voltage at approximately a load current value of 28A.

It can be assumed that the output current value Iout is positive, Q1 is an ideal switch (i.e., the switching time is zero), and that the capacitance Coss_Q1 of Q1 is derived from the loop inductance L_loop, i. H. a power source is charged.

The energy EL stored in the loop inductance L_loop is: EL = 1/2 L_loop Iout ²

Once Q1 is turned off, the system moves to its new equilibrium. It is a damped, nonlinear resonant circuit, and the energy is converted into capacitive energy EC, ie into the capacitance Coss_Q1 of Q1: EC = ^{VDS, max} ₀ ∫UdQ = ^{VDS, max} ₀ ∫Coss_Q1 UdU

In the latter equation, U is the stress and Q is the charge. VDS, max is reached when EL is completely converted to EC, ie EC = EL. If the energy EL is too large, an avalanche will be generated in Q1. If the system were linear, the overshoot would be as follows: VDS, max = √ (L_loop / Coss_Q1) Iout

10 illustrates a circuit diagram 200 a buck converter with a half bridge. Several elements of the circuit diagram 200 (in particular R_chan and / or Ross_Q1) can also be used in a half-bridge circuit 100 be implemented according to an embodiment of the invention. Preferably, R_chan is executed as the channel resistance, ie, the FET is intentionally not properly turned off.

Strategies for a repeated avalanche in the circuit diagram 200 from 10 To avoid implemented high-side switches Q1, are explained below.

One particular measure that can be taken to reduce overshoot is the reduction in loop inductance L_loop. However, this is possible only to a limited extent due to other circuit design limitations. A very low inductance can lead to a large charging current, so that the current in the first capacitor can be greater than 100 A.

Another measure that can be taken to reduce the overshoot is to increase the capacity of the switch C_oss_Q1. One way to achieve this is to use a larger die. However, if the die gets too big, it may not fit in the pack. In addition, this approach brings with it extra volume. In addition, this can negatively impact peak efficiency, but can improve full load.

Yet another approach to reducing the overshoot voltage is to insert a series resistor Ross_Q1 to dissipate the energy.

Another approach for reducing the overshoot voltage is to insert a shunt resistor R_chan (preferably made as a channel resistor) or a current path to reduce the charging of the capacitance of the switch Coss_Q1. This keeps the channel open or opens again. It reduces the gate driver power for higher currents and reduces the threshold voltage to a slow turn off. It is also possible to implement a zener diode between gate and drain.

While the above-mentioned approaches (particularly, the implementation of the above-described series resistor and / or the above-described parallel resistor) for limiting the overshoot voltage can be advantageously implemented according to embodiments of the invention, these approaches are limited to a certain extent, so there is still room for improvement Overshoot suppression is present.

According to one embodiment, and as described in further detail below, it is possible to effectively reduce the overshoot voltage by providing feedback using a source inductance to reduce gate current (particularly, when a small gate loop is used). Inductance is implemented).

Reducing the loop inductance is limited by the physical dimensions and assembly constraints during the assembly process. A higher output capacitance Coss_Q1 helps, but 60 A without avalanche in the 7 and 8th would have to be quadrupled, with negative effects on compactness, low load and peak efficiency.

Inserting a resistor in series with a portion of the output capacitance reduces overshoot, but is of limited effect. In the example given, a value of about 1 ohm shows a limited improvement (see below 12 ). Compared with a design with Ross_Q1 = 0 ohms, the area without avalanche can be increased from 22 A to 30 A.

The disadvantage for the efficiency is about 0.2%.

11 is a diagram 1100 , the maximum voltage and the efficiency of the half-bridge according to 10 depending on a resistance value illustrated. Along an abscissa 1102 the value of the resistance Ross Q1 is shown. Along an ordinate 904 the maximum voltage is shown. Along an ordinate 1104 the efficiency is shown.

12 is a diagram 1200 , the maximum voltage of different transistors of the half-bridge according to 10 depending on a current illustrated. Along an abscissa 902 the current is shown. Along an ordinate 904 the maximum voltage is shown.

11 and 12 show a reduction in overshoot by inserting a resistor Ross_Q1 in series with a portion of the output capacitance.

13 is a diagram 1300 , the efficiency of the half-bridge according to 10 depending on a current illustrated. Along an abscissa 902 the current is shown. Along an ordinate 1104 the efficiency is shown.

14 is a diagram 1400 , which is a maximum voltage of the switch transistor of the half-bridge according to 10 depending on a current and illustrated in different configurations. Along an abscissa 902 the current is shown. Along an ordinate 904 the maximum voltage is shown.

A parallel path to the output capacitance may be formed by the channel open is held to pass a portion of the energy. In most cases, the gate driver power is reduced, either in the driver itself or by inserting a gate resistor in series, which may be integrated into the FET or the driver. This will extend the time during which the channel can conduct electricity. A disadvantage of this approach is that it significantly increases losses over the entire load range (see 13 and 14 ).

13 and 14 show an increase in resistance in the gate driver of 0.25 ohms to higher values. The higher the resistance, the lower the voltage overshoot, but with the disadvantage of lower efficiency. The dashed line in 13 refers to a smart driver that adjusts the drive strength based on available current information (for example, from an integrated current sense structure), so that it is the best possible solution to keep the voltage below the rated breakdown voltage of the FET of 25V.

Integration of a Zener diode increases complexity, but reduces voltage overshoot. A lower threshold voltage acts much like the weaker gate driver.

Thus, there is room for improvement in reliability and efficiency of a half-bridge circuit. In the following, corresponding improvements will be described which are provided by embodiments of the invention.

1 Fig. 12 illustrates a circuit diagram of a buck converter with a half-bridge circuit 100 according to an embodiment.

The buck converter closes the in 1 shown half-bridge circuit 100 one. The half-bridge circuit 100 includes an input port 102 for providing an electrical voltage as an electrical input, more precisely an electrical DC input voltage. This electrical DC input voltage is through the half-bridge circuit 100 to convert into a DC electrical output, wherein the electrical output has a larger current and a lower voltage than the electrical input. At an output terminal 104 one is connected to the output terminal 104 to be connected load (not shown) an output current provided as an electrical output. The load may be any electrical circuit or element that is through the half-bridge circuit 100 generated, electrical output picks up or used.

A switch 106 and a diode 108 are between the input terminal 102 and the output terminal 104 connected. Directly between the switch 106 and the diode 108 is a voltage limiting inductance 110 arranged. The voltage limiting inductance 110 is configured to limit a voltage value when switching the switch 106 occurs. Especially if the switch 106 is switched from an "on" state to an "off" state, an overshoot voltage can be generated, which in the prior art is a breakdown voltage of the switch 100 forming transistor Q1 can exceed. This can be the half-bridge circuit 100 to damage.

As mentioned, the switch 106 configured as transistor Q1, and thus may be referred to as a field effect transistor switch. As mentioned, the diode is 108 configured as another transistor Q2 and can thus be referred to as a field effect transistor diode. The voltage limiting inductance 110 is between a source port 112 of the transistor switch 106 and a drain connection 114 the transistor diode 108 arranged. Both the switch 106 as well as the diode 108 are inside a loop 116 between the input terminal 102 and the output terminal 104 connected. The voltage limiting inductance 110 has an inductance value that is large enough to be the maximum voltage when switching the switch 106 to limit to about 25V. For this purpose, the voltage limiting inductance 110 set to have an inductance value of about 100 pH. Preferably, the inductance value is the voltage limiting inductance 110 at least 20% of a loop inductance 130 the loop 116 , Furthermore, an inductance value of a gate inductance 118 of the transistor switch 106 even only 300 pH. As 1 can be taken, is the Spannungsbegrenzungsinduktivität 110 as an inductive feedback element configured to limit a gate current of the switch 106 in the case of a rapidly changing electric current in the half-bridge circuit 100 is configured.

As an alternative to the in 1 shown configuration, the half-bridge circuit 100 upon detecting that a value of an electric current in the half-bridge circuit 100 is below a predefined threshold, in particular below 20 A, for selectively bypassing the voltage limiting inductance 110 be configured. This has the advantage that the voltage limiting inductance 110 showing the conversion efficiency of the half-bridge circuit 100 slightly reduced, under conditions where it is not necessary (for example, at a relatively low load current), inactive or can be deactivated. This combines both a reliable protection against one Overshoot voltage as well as against an unnecessary reduction of the power.

Although in 1 not shown, it is possible that the half-bridge circuit 100 from 1 Furthermore, an energy dissipating ohmic resistance (see reference numeral 170 in 10 ) in series with the switch 106 includes, in a way, as in 10 shown is arranged. Additionally or alternatively, the half-bridge circuit 100 a charge suppressing ohmic resistor (see reference numeral 172 in 10 ) parallel to the switch 106 include, in a way, as in 10 shown is arranged. Each of these additional resistors 170 . 172 can further reduce voltage overshoot when switching the switch 106 occurs.

The input voltage of the half-bridge circuit 100 will have an input capacity 140 (see also reference numeral C_IN) delivered. The gate terminal of the switch 106 is with a pad 142 connected with "GH" (Gate high). A driver (see reference numeral 400 in 4 ) can with the pad 142 be connected. Another pad 144 labeled "Phase" is electrical with the voltage limiting inductance 110 , the drain connection 114 the diode 108 and an output inductance 146 (the latter being used to store or buffer energy).

To voltage overshoot during "off" switching of the switch 106 below the breakdown voltage of the switch 106 or to the voltage overshoot at the diode 108 during "on" switching of the switch 106 below the breakdown voltage of the diode 108 to hold, generates the half-bridge circuit 100 according to 1 a feedback using the source inductance.

In one embodiment, the loop inductance is 130 (L_loop) is not a lumped element, as in the circuit diagram of 1 shown (alternatively, however, it may be embodied as a lumped element). In contrast, it can be found in the in 1 embodiment shown over the entire loop 116 be distributed. In particular, there is also an inductance contribution between Q1 and Q2, ie the voltage limiting inductance 110 , as in 1 shown.

In the case of a transient there is a voltage drop proportional to the change in current I over time (i.e., dl / dt), which can reduce or even stop the gate current from flowing until the end of the commutation phase. If designed accordingly, the channel will remain conductive at a fairly high VDS, still guaranteeing fast turn off.

For the given example, a value of the voltage limiting inductance 110 of 100 pH, keep the overshoot below 25V (cf. 3 ). The effect on conversion efficiency is significantly smaller (the reduction is only 0.1%, cf. 2 ) than any other available solution (see in particular the description of 10 ). Even the overshoot in the transistor diode 108 (Q2) can be reduced from 21V to about 18V (see 3 ). This allows the breakdown voltage of the FETs to be reduced, which in turn improves electrical parameters such as on-resistance.

1 thus shows a half-bridge circuit 100 with a source inductance. For the embodiment shown, a value of the voltage limiting inductance 110 of 100 pH keep the overshoot below 25V.

If the gate circuit is fast enough, the voltage will adjust to approximately: VDS, max = Vin + L_loop / Ls V_plateau

In the latter equation, Vin is the one at the input port 102 provided input voltage, and V_plateau is a plateau voltage.

For conversion of an input of 12V to a lower output voltage using transistors having a nominal breakdown voltage of 25V or 30V, the source inductance can be adjusted to be preferably about one quarter of the loop inductance. In a particular implementation, this corresponds to a value of the voltage limiting inductance 110 of about 100 pH.

The gate loop inductance 118 should be very low, because the half-bridge circuit 100 within a short time of, for example, less than 1 ns. In addition, a hybrid solution is possible, for example the use of an integrated CMOS in Q1.

For a further improved efficiency, it is even possible to use the source inductance (ie the voltage limiting inductance 110 ) for a light to medium load (for example by a separate tap or a pad in a driver circuit). Furthermore, the value of the resistor Ross_Q1 of the switch 106 be reduced.

If a particular circuit design with a necessary value Ls of the source Inductance is incompatible, a lower plateau voltage V_plateau, ie a lower threshold voltage can be used.

2 shows a diagram 250 , the efficiency of a half-bridge according to the prior art and the half-bridge 100 illustrated in accordance with an embodiment depending on a current. Along an abscissa 252 the current is shown. Along an ordinate 254 the efficiency is shown. Thus shows 2 the effect on efficiency for Ls = 100 pH compared with no source feedback. As 2 is the efficiency reduction due to the provision of the voltage limiting inductance 110 with an inductance value of Ls = 100 pH extremely small.

3 is a diagram 300 , which is a maximum voltage of the different transistors Q1, Q2 of the half-bridge 100 illustrated in accordance with an embodiment depending on a current. Along an abscissa 252 the current is shown. Along an ordinate 302 the maximum voltage is shown. 3 therefore shows an overshoot in both FETs Q1 and Q2, ie at the switch 106 as well as the diode 108 , As 3 can be taken, is the efficiency protection due to the provision of Spannungsbegrenzungsinduktivität 110 remarkable with an inductance value of Ls = 100 pH.

4 illustrates, according to one embodiment, a three-dimensional view of a package 150 a buck converter with a half-bridge circuit 100 using a bond wire-bonded clip (see Bonding Wire 154 , Clip 152 ). 4 is a simple design sketch showing a solution with source feedback.

Before describing the functionality of the pack 150 with regard to the half-bridge circuit 100 according to 1 becomes a very advantageous feature of the package design according to 4 described. The skilled person understands that the described package design, in particular the clip design, can advantageously be implemented in very different applications (for example also for a motor drive).

The semiconductor package 150 Includes a metallic clip 152 and a bonding wire 154 , The bonding wire 154 is by wire bonding directly to the clip 152 connected.

Furthermore, the semiconductor package includes 150 three semiconductor chips, ie the transistor switch 106 , the transistor diode 108 (in 4 barely visible, as they are under the clip 152 located) and a driver 400 , The semiconductor chips regarding the switch 106 and the diode 108 are by soldering electrically with the clip 152 coupled. The semiconductor chip regarding the driver 400 is however indirectly over the bonding wire 154 electrically with the clip 152 coupled. In other words, the bonding wire bridges 154 a gap between the clip 152 and a pad of the driver 400 , as in 4 shown. In particular, the clip includes 152 a plate-like section 160 and a finger section 162 that with the, plate-like section 160 is integrally formed. The bonding wire 154 is with the finger section 162 coupled (only a small gate charging current, but no large load current, leading). In contrast, the plate-like section leads 160 the big load current. The finger section 162 does not stand with the source connection 112 of the switch 106 in contact, ie is not at source potential. The load current flows substantially along the plate-like section 160 and forms a bridge between the switch 106 and the diode 108 (which are designed as separate chips).

The semiconductor chips (see reference numeral 106 . 108 . 400 ) are on a carrier 176 (such as a leadframe) mounted. Also the clip 152 is on the carrier 176 but extends vertically beyond the upper major surfaces of the semiconductor chips.

Prior art clips are formed of copper material which tends to oxidize. This is not a problem in the prior art. In the clip 152 However, according to the described embodiment of the invention, an electrically insulating oxide layer on the copper clip 152 be removed before the bonding wire 154 is connected to ensure an adequate electrical connection. Alternatively, at least that is part of the surface of the clip 152 on which the bonding wire 154 is covered with a coating or coating which does not suffer from surface oxidation (for example, a coating of silver, gold, palladium, nickel or nickel-phosphorus). This allows a reliable electrical coupling to be achieved with the described wire-on-clip architecture.

The bonding wire 154 For example, it may comprise silver, aluminum, gold or copper and may be shaped as a thread or ribbon.

On the half-bridge functionality of the package 150 from 4 Coming back, it is at the switch 106 and the diode 108 around separate semiconductor chips, but they belong to the common package 150 from 4 ,

How out 4 can be taken, is the clip 152 for direct coupling of the switch 106 with the diode 108 configured while the plate-like section 160 , Very advantageous is the voltage limiting inductance 110 through the clip 152 educated. This allows a flexible design and adaptation of the value of the voltage limiting inductance 110 by a corresponding shaping and dimensioning of the clip 152 , The half-bridge circuit 100 further includes the bonding wire 154 which can also be referred to as a gate-return (phase) wire, since it connects to the pad 144 (Phase) coupled with the clip 152 a bridge between the switch 106 and the diode 108 in terms of the driver 400 forming. The plate-like section 160 carries a substantial part of a load current. The finger-like section 162 is integral with the plate-like section 160 formed and therefore electrically connected thereto, but during operation substantially no load current. The clip 152 reaches a low-resistance connection between the mentioned electronic elements. 4 further shows another bonding wire 402 , which can be referred to as a gate wire and to provide a connection to the pad 142 ("GH") and for electrical bridging between the switch 106 and the driver 400 is configured.

The wire-on-clip architecture according to 4 provides improved packaging performance based on increased maximum clip size with low manufacturing and assembly costs. In the application shown, it performs the task of connecting the gate IC directly to the clip 152 can be connected. More generally, the described wire-on-clip architecture is particularly suitable for all types of multi-chip modules or packages. The wire-on-clip architecture is particularly powerful in combination with a special clip coating (eg Ag, Au, Pd, Ni and / or NiP) as described above. It can be made with different wire materials (for example Ag, Al, Au and / or Cu). Wire processes that may be performed in conjunction with the wire-on-clip architecture include ball machining, wedge machining, and / or tape configuration. Such a wire-on-clip architecture can be universally used for many different applications, such as DC / DC conversion and motor drive. Based on such a wire-on-clip concept, efficiency may be improved within DC / DC or motor applications due to reduced or optimized package / board loop inductance.

In order to design a 100 pH voltage limiting inductance, an additional connection is possible to reduce the drain potential of the diode transistor Q2 (in FIG 4 through the clip 152 hidden, inverted) to the smaller high side switch transistor Q1. The clip 152 may be soldered to an associated pad or only in mechanical contact with a passivated surface. The design of the pack 150 according to 4 allows a sufficiently high value of the voltage limiting inductance 110 to obtain.

5 illustrates, according to one embodiment, a plan view of a package 150 a buck converter with a half bridge 100 holding a bond wire-linked clip 152 includes.

5 shows an exemplary implementation of the above-described source inductance feedback. The voltage limiting inductance 110 is active for both the switch-on and switch-off process. The buck converter according to the package 150 from 5 is thus configured so that when the switch is "on" 106 and when the switch is "off" 106 the voltage limiting inductance 110 always located within a stream flow path.

For "on" switching, the current path leads from the "phase" terminal over the connected bonding wire 154 on the clip 152 , from there to the counter 106 , continue over the bonding wire 402 on the driver 400 and from there via another bonding wire 500 to the connection "boat". For turning off the current loop through the bonding wire 402 , a wire, the driver 400 directly with the clip 152 connects, and the clip connection with the chip 106 educated. This clip connection forms the required source inductance 110 out.

6 illustrates, according to one embodiment, a plan view of a package 150 a buck converter with a half bridge 100 holding a bond wire-linked clip 152 includes.

In contrast to the pack 150 according to 5 is the pack 150 according to 6 configured so that when the switch turns "on" 106 the voltage limiting inductance 110 is located outside of a current flow path and "off" the switch 106 the voltage limiting inductance 110 located within the stream flow path. Thus shows 6 another implementation of the source inductance feedback. The source inductance is active only for turn-on, not turn-off. For "on" and "off" switching, the current paths are according to 6 differently. For "on" switching: from "phase" connection via a connected bonding wire 600 on the switch 106 , continue over the bonding wire 402 on the driver 400 and from there over the other bonding wire 500 to the connection "boat". For the "off" switch: along a loop between the switch 106 , the clip 152 , the bonding wire 154 on the driver 400 and the bonding wire 402 ,

15 illustrates, according to one embodiment, a plan view of a package 150 a buck converter with a half bridge 100 holding a bond wire-linked clip 152 includes.

According to 15 it is the finger section 162 around an overhanging structure. Such an overhanging structure may be cantilevered in cantilever mode or supported by a support member (not shown). Thus, the wireframe clip architecture described above may be combined with a particular process flow (e.g., the overhanging wire configuration shown).

It should be noted that the term "comprising" does not exclude other elements or features and that the "one" and its declinations do not preclude the plural. It is also possible to combine elements which are described in connection with different embodiments. It should also be noted that reference numbers are not to be considered as limiting the scope of the claims. Moreover, the scope of the present application should not be limited to the particular embodiments of the process, machine, method of manufacture, subject matter, means, methods, and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, methods of manufacture, subject matter compositions, means, methods or steps.

Claims (12)

Pack ( 150 ), comprising: • a clip ( 152 ); and • a wire ( 154 ); • where the wire ( 154 ) with the clip ( 152 ), the clip ( 152 ) a plate-like section ( 160 ) and at least one finger section ( 162 ) integral with the plate-like section ( 160 ) is trained. Pack ( 150 ) according to claim 1, further comprising at least one semiconductor chip ( 106 . 108 . 400 ). Pack ( 150 ) according to claim 2, wherein at least one of the at least one semiconductor chip ( 106 . 108 . 400 ) over the wire ( 154 ) directly electrically with the clip ( 152 ) is coupled. Pack ( 150 ) according to claim 2 or 3, wherein at least one other semiconductor chip ( 106 . 108 . 400 ) directly electrically with the clip ( 152 ) is coupled. Pack ( 150 ) according to any one of claims 1 to 4, wherein the wire ( 154 ) around a bonding wire ( 154 ). Pack ( 150 ) according to claim 1 to 5, wherein it is in the at least one finger section ( 162 ) is an overhanging structure. Pack ( 150 ) according to any one of claims 1 to 6, comprising a carrier ( 176 ), in particular a leadframe on which the clip ( 152 ) is mounted. Pack ( 150 ) according to one of claims 1 to 7, wherein at least a part of a surface of the clip ( 152 ) is covered with a coating, in particular a coating comprising at least one of the group consisting of silver, gold, palladium, nickel and nickel-phosphorus. Pack ( 150 ) according to one of claims 1 to 8, wherein the wire ( 154 ) comprises at least one material selected from the group consisting of silver, aluminum, gold and copper. Pack ( 150 ) according to one of claims 1 to 9, wherein the wire ( 154 ) at least one of the group consisting of a thread and a band. Pack ( 150 ) according to one of claims 1 to 10, configured as one of the group consisting of a DC / DC conversion package ( 150 ) and a motor drive pack ( 150 ). Pack ( 150 ) according to one of claims 1 to 11, comprising a half-bridge circuit ( 100 ) comprising: an input terminal ( 102 ) for providing an electrical input; • an output connector ( 104 ) for providing an electrical output to one of the output terminals ( 104 ) load to be connected; • a switch ( 106 ) and a diode ( 108 ) between the input terminal ( 102 ) and the output terminal ( 104 ); and a voltage limiting inductance ( 110 ) between the switch ( 106 ) and the diode ( 108 ) and for limiting a voltage when switching the switch ( 106 ) is configured.

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