DE102014105462B4 - SEMICONDUCTOR POWER COMPONENT WITH A HEAT SINK AND METHOD OF MANUFACTURING - Google Patents

Abstract

A semiconductor device (300) comprising: a lead frame (110) having a mounting surface (112) and a second side (114) opposite the mounting surface (112); a metal block (120) having a first surface (121) facing the lead frame (110) and a second face (122) facing away from the leadframe (110), the metal block (120) having a thickness, measured between the first (121) and second (122) faces, equal to or greater than 1.5 times the thickness of the lead frame (110) and wherein an area of the first face (121) is equal to or greater than 4Tm (Tm + Fc0.5) + Fc, where Tm is the thickness of the metal block (120 ) , measured between the first (121) and second (122) faces, and Fc is an area of a first face of a semiconductor power die (130) bonded to the second face (122) of the metal block (120);wherein the semiconductor power die (130) arranged over the second surface (122) of the metal block (120). net and electrically connected to the metal block (120) and the leadframe (110);an encapsulation body (310) encapsulating the leadframe (110), the metal block (120) and the semiconductor power die (130), the second side (114 ) the lead frame (110) is exposed under the semiconductor power die (120) on the encapsulation body (310); anda contact clip (320) having a first face (321) connected to a second face of the semiconductor power die (130) opposite the first face of the semiconductor power die (130).

Description

This invention relates to the technique of packaging, and more particularly to the technique of encapsulating a semiconductor power chip.

The manufacturers of power semiconductor components are relentlessly striving to increase the performance of their products while reducing the costs of their manufacture. A cost-intensive area in the production of power semiconductor components is the encapsulation (packaging) of the semiconductor power chip. The performance of a power semiconductor component depends on the heat dissipation capacity of the package. It is desirable to have packaging processes that provide high thermal robustness at low cost. the US 2008/029 860 A1 discloses a semiconductor device having a semiconductor chip, a heat spreader and a chip carrier, the heat spreader being arranged between the semiconductor chip and the chip carrier. Comparable semiconductor devices are in DE 10 2008 008 920 A1 that and that US 2008/0 164 589 A1 and the DE 10 2005 054 872 A1 disclosed.

An object on which the invention is based can be seen in creating a semiconductor component with good thermal properties. Furthermore, a method for producing such a component is to be specified.

The problem is solved by the features of the independent claims. Embodiments and developments are the subject of the dependent claims.

According to one embodiment of a semiconductor component, the semiconductor component comprises an electrically conductive carrier with a mounting surface, a metal block and a semiconductor power chip. The metal block has a first surface facing the carrier and a second surface facing away from the electrically conductive carrier. The semiconductor power chip is arranged over the second surface of the metal block.

According to one embodiment of a semiconductor package, the semiconductor package comprises a lead frame with a thickness T1, a metal block and a semiconductor power chip. The metal block is mounted on the lead frame. The metal block has a thickness Tm, where Tm is at least 1.5 times T1. The semiconductor power chip is mounted on the metal block.

According to one embodiment of a method for producing a semiconductor component, the method comprises the bonding of a semiconductor power chip to a metal block and the bonding of the metal block to an electrically conductive carrier.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and viewing the accompanying drawings.

• 1 veranschaulicht schematisch eine Querschnittsansicht eines nicht erfindungsgemäßen Leistungshalbleiterbauelements.
• 2 veranschaulicht schematisch eine Draufsicht eines nicht erfindungsgemäßen Leistungshalbleiterbauelements.
• 3 veranschaulicht schematisch eine Querschnittsansicht eines beispielhaften Leistungshalbleiterbauelements entlang der Linie A-A in 5, wobei des Weiteren die stationäre Wärmeleistungsdissipation veranschaulicht ist.
• 4 veranschaulicht schematisch eine Querschnittsansicht eines beispielhaften Leistungshalbleiterbauelements entlang der Linie A-A in 5, wobei des Weiteren die dynamische Wärmeleistungsdissipation veranschaulicht ist.
• 5 veranschaulicht schematisch eine Draufsicht eines beispielhaften Leistungshalbleiterbauelements.
• 6 veranschaulicht ein grundlegendes Schaltbild eines Halbbrücken-Leistungshalbleiterbauelements.
• 7A-7G veranschaulichen schematisch Querschnittsansichten eines beispielhaften Prozesses eines Verfahrens zum Verkapseln eines Halbleiterleistungschips.

The accompanying drawings serve the purpose of making the embodiments easier to understand. The drawings illustrate embodiments and together with the description serve to explain the principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily understood from the following detailed description. The elements of the drawings are not necessarily to scale relative to one another. The same reference numbers designate corresponding or similar parts.

• 1 schematically illustrates a cross-sectional view of a power semiconductor component not according to the invention.
• 2 schematically illustrates a top view of a power semiconductor component not according to the invention.
• 3 FIG. 11 schematically illustrates a cross-sectional view of an exemplary power semiconductor device along line AA in FIG 5 , wherein the stationary thermal power dissipation is further illustrated.
• 4th FIG. 11 schematically illustrates a cross-sectional view of an exemplary power semiconductor device along line AA in FIG 5 , further illustrating the dynamic thermal power dissipation.
• 5 schematically illustrates a top view of an exemplary power semiconductor device.
• 6th Figure 3 illustrates a basic circuit diagram of a half-bridge power semiconductor device.
• 7A-7G schematically illustrate cross-sectional views of an exemplary process of a method for encapsulating a semiconductor power chip.

In the following description, reference is made to the accompanying drawings, in which there is shown by way of illustration specific embodiments of how the invention may be practiced. In this context, directional terms such as “up”, “down”, “front”, “back”, “upper”, “lower” etc. are used Used with reference to the orientation of the figure (s) described. Because components of embodiments can be positioned in a number of different orientations, the directional terms are used for purposes of illustration only and are in no way limiting. It goes without saying that other embodiments can also be used and that structural or logical changes can be made without departing from the concept of the present invention. The following detailed description is therefore not to be understood in a restrictive sense.

It goes without saying that the features of the various exemplary embodiments described in the present text can be combined with one another, unless expressly stated otherwise.

For the purposes of this specification, the terms “coupled” and / or “connected” do not generally mean that elements must be directly coupled or connected to one another. There may be intermediate elements between the "coupled" or "connected" elements. Without being limited to this meaning, the terms “coupled” and / or “connected” can also be understood in the sense that they optionally disclose an embodiment in which the elements are directly coupled or connected to one another without any intermediate elements between the "coupled" or "connected" elements are present.

In the present text, components are described that contain a semiconductor power chip. In particular, one or more semiconductor power chips with a vertical structure can be involved; that is, the semiconductor power chips can be manufactured so that electric currents can flow in a direction perpendicular to the main surfaces of the semiconductor power chips. A semiconductor power chip with a vertical structure has electrodes on its two main surfaces, that is, on its upper side and its lower side. In various other embodiments, semiconductor power chips with a horizontal structure may be involved. A semiconductor power chip with a horizontal structure has electrodes only on a single surface, that is, on its upper side.

The semiconductor power chip can be made of special semiconductor material, such as Si, SiC, SiGe, GaAs, GaN, AlGaN, InGaAs, InAlAs, etc., and can further contain inorganic and / or organic materials that are not semiconductors. The semiconductor power chips can be of different types and can be manufactured by different technologies.

Furthermore, the electronic components described in the present text can optionally contain one or more integrated logic circuits for controlling the semiconductor power chip. The integrated logic circuit can contain one or more control circuits for controlling the semiconductor power chip. The integrated logic circuit can be, for example, a microcontroller which contains, for example, memory circuits, level shifters, etc.

The semiconductor power chip may have electrodes (chip islands) that enable electrical contact to be made with the integrated circuits contained in the semiconductor power chip. The electrodes can contain one or more metal layers which are applied to the semiconductor material of the semiconductor power chips. The metal layers can be produced with any desired geometric shape and any desired material composition. The metal layers can, for example, be in the form of a layer or a contact pad that covers one area. For example, any desired metal capable of forming a solder bond or diffusion solder bond, for example Cu, Ni, NiSn, Au, Ag, Pt, Pd, In, Sn, and an alloy of one or more of these metals, to be used as the material. The metal layers need not be homogeneous or consist of only a single material; that is, different compositions and concentrations of the materials contained in the metal layers are possible.

Semiconductor power chips can be used as power MISFETs (Metal Insulator Semiconductor Field Effect Transistors), Power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), HEMTs (High Electron Mobility Transistor), power bipolar transistors or power diodes, such as a PIN diode or a Schottky diode. For example, in vertical components, the source contact electrode and the gate contact electrode of a power MISFET or a power MOSFET or a HEMT can be on one main surface, while the drain contact electrode of the power MISFET or power MOSFET or HEMT is on the other main surface can be arranged. However, the semiconductor power chips that are considered in the present text, for example HEMTs, can also be horizontal components, in which the electrodes are only arranged on the top.

The semiconductor power chip is mounted over an electrically conductive carrier. In various embodiments, the electrically conductive carrier can be a metal plate or foil, such as, for example, a chip contact island (chip pad) of a leadframe. The metal plate or foil can consist of any metal or any metal alloy, for example copper or copper alloy. In other embodiments, the electrically conductive chip carrier can consist of plastic or ceramic. For example, the electrically conductive chip carrier can comprise a layer of plastic that is coated with a metal layer. For example, such a chip carrier can be a single-layer circuit board or a multi-layer circuit board. In other embodiments, the component carrier can comprise a plate made of ceramic which is coated with a metal layer, for example a metal-bonded ceramic substrate. For example, the electrically conductive carrier can be a DCB (Direct Copper Bonded) ceramic substrate.

The semiconductor power chip can be at least partially embedded in or surrounded by at least one electrically insulating material. The electrically insulating material forms an encapsulation body. The encapsulation body can comprise or consist of a potting material. Various techniques can be used to form the encapsulation body from the potting material, for example die casting, injection molding, powder fusion processes, or resin infusion molding. Furthermore, the encapsulation body can have the shape of a piece of a layer, for example a piece of foil, which is laminated onto the semiconductor power chip and the electrically conductive carrier. The encapsulation body can form part of the peripheral edge of the package, i.e. it can at least partially define the shape of the semiconductor component or limit its circumference.

The electrically insulating material can comprise or consist of a thermosetting material or a thermoplastic material. A thermosetting material can be made on the basis of an epoxy resin, for example. A thermoplastic material can, for example, comprise one or more materials from the group consisting of polyetherimide (PEI), polyethersulfone (PES), polyphenylene sulfide (PPS) or polyamideimide (PAI). Thermoplastic materials melt when pressure and heat are applied during molding or lamination and harden (reversibly) with cooling and releasing pressure.

The electrically insulating material that forms the encapsulation body can comprise or consist of a polymer material. The electrically insulating material can comprise at least one of the following: a filled or unfilled potting material, a filled or unfilled thermoplastic material, a filled or unfilled thermosetting material, a filled or unfilled laminate, a fiber reinforced laminate, a fiber reinforced polymer laminate and a fiber reinforced polymer laminate with filler particles .

In some embodiments, the electrically insulating material can be a laminate, for example a polymer film. Heat and pressure can be applied for a period of time appropriate to adhere the polymer sheet to the underlying structure. During lamination, the electrically insulating film is flowable (i.e. it is in a plastic state), with the result that gaps between the semiconductor power chips and / or other topological structures on the chip carriers are filled with the polymer material of the electrically insulating film. The electrically insulating film can comprise or consist of any suitable thermoplastic or thermosetting material. In one embodiment, the insulating film can comprise or consist of a prepreg (short for “pre-impregnated fibers”), for example a combination of a fiber mat, for example glass or carbon fibers, and a resin, for example a thermosetting or thermoplastic material. Prepreg materials are known to the person skilled in the art and are generally used for the production of printed circuit boards.

A metal block can be arranged between the electrically conductive carrier and the semiconductor power chip. The metal block can be mechanically, thermally and, for example, electrically connected to the semiconductor power chip. The metal block can consist of any metal or any metal alloy, in particular of metals with a high thermal conductivity and / or a high thermal capacity. For example, the metal block can comprise or consist of copper or a copper alloy. The metal block can consist of full metal material. The metal block can enable both an effective static heat dissipation and an effective dynamic heat dissipation of heat power losses of the semiconductor power chip with a high heat power loss area density.

A connecting element, such as a contact clip (contact clip), can be electrically and mechanically connected to a load electrode of the semiconductor power chip, which is on a surface surface of the semiconductor power chip is arranged, which is opposite to the surface where the semiconductor power chip is connected to the metal block. The connecting element can also be of a type other than a contact clip (a contact clip). It can also be implemented by one or more ribbons or one or more bond wires, for example.

A variety of different types of electronic components can be configured to use a metal block as described herein, or can be fabricated by the techniques described herein. For example, an electronic component according to the disclosure may represent, for example, a power supply, a DC-to-DC converter (DC-DC converter), an AC-to-DC converter (AC-DC converter), a power amplifier, and many other power components.

In various embodiments, an electronic component disclosed herein may include power cascode circuits, for example based on a HEMT, for example. Such cascode circuits are referred to by those skilled in the art as a HEMT cascode. HEMTs, in particular HEMT cascodes, can be based on GaN, AlGaN, InGaAs and InAlAs, for example. For example, they can be used as switching components, AC-DC converters (AC-DC converters), power amplifiers, RF circuits, etc.

Power semiconductor components which are equipped with a metal block, as described in the present text, can contain a power SiC MOSFET or a power SiC diode as a semiconductor power chip. Similar to HEMTs, SiC MOSFETs and SiC diodes are small in size with high thermal power losses at the same time. Furthermore, half-bridge circuits that contain a high-side transistor and a low-side transistor can use a metal block, as described in the present text. Half-bridge circuits can be used, for example, as alternating current to direct current converters (AC-DC converters) or direct current to direct current converters (DC-DC converters).

In general, DC-DC converters can be used to convert a DC input voltage, which is provided by a battery or an accumulator, into a DC output voltage that is adapted to the requirements of the downstream electronic circuits. For example, a DC-DC converter described herein can be a buck converter or buck converter. AC-DC converters can be used to convert an AC input voltage, for example provided by a high-voltage AC power network, into a DC output voltage that is adapted to the requirements of the downstream electronic circuits.

In general, any power device that includes a semiconductor power chip with a high thermal power loss and a comparatively small footprint for dissipating the thermal power can benefit from the disclosure herein. For example, semiconductor power chips that have a thermal power loss during operation of at least 1 W, 3 W, 5 W, 7 W or 10 W and, for example, a base area for thermal power dissipation of equal to or less than 15 mm ² , 10 mm ² , 7 mm ² , 5 mm ² or 3 mm ² , use a metal block, as described in the present text, to improve their thermal behavior and for power dissipation during operation.

1 4 illustrates a cross-sectional view of a semiconductor component 100 not according to the invention. The semiconductor component 100 comprises an electrically conductive carrier 110, a semiconductor power chip 130 and a metal block 120 which is arranged between the electrically conductive carrier 110 and the semiconductor power chip 130.

The electrically conductive carrier 110 can consist of a flat metal plate, for example a chip contact island (chip pad) of a lead frame. For example, the electrically conductive carrier 110 can consist of a full metal material. A thickness of the electrically conductive carrier 110 is denoted by T1. For example, the thickness T1 can be equal to or greater than 0.1 mm, 0.3 mm or 0.5 mm, or the thickness T1 can be equal to or less than 0.7 mm, 0.5 mm, 0.4 mm, 0.2mm or 0.1mm.

The semiconductor power chip 130 can be, for example, a GaN-HEMT, an Si or SiC power MOSFET, or an Si or SiC power diode. The semiconductor power chip 130 can have high thermal losses during operation, for example a thermal power loss (heat dissipation) in the range between 1 W and 10 W or even more. The thermal power that is generated in the semiconductor power chip 130 during operation must be dissipated in order to avoid overheating, material deterioration, or failure of the semiconductor power chip 130. The semiconductor power chip 130 may be configured to operate at voltages above 50 V, 100 V, 300 V, 500 V or 1000 V to work. The semiconductor power chip 130 can have a thickness Tc, measured between the first surface 131 and an opposing second surface 132 of the semiconductor power chip 130, of equal to or less than 300 μm, 200 μm, 100 μm, 80 μm or 50 μm.

The metal block 120 has a first surface 121, which faces the electrically conductive carrier 110, and a second surface 122, which faces away from the electrically conductive carrier 110. The semiconductor power chip 130 is disposed over the second surface 122 of the metal block 120.

The metal block 120 has a thickness indicated by Tm. The thickness Tm of the metal block 120 is measured between the first surface 121 and the second surface 122 of the metal block 120. The thickness Tm may be equal to or greater than 1.5, 2.0, 3.0, 4.0 or 5.0 times the thickness T1 of the electrically conductive substrate 110. For example, the thickness Tm can be equal to or greater than 0.5 mm, 0.75 mm, 1.0 mm, 1.25 mm, or 1.5 mm.

The first surface 121 of the metal block 120 may have a surface area equal to or greater than 8.0 mm ² , 14.0 mm ² , 20.0 mm ^2, or 26.0 mm ² . The first surface 121 of the metal block 120 can be completely connected to an upper side 112 of the electrically conductive carrier 110.

The semiconductor power chip 130 has a first surface 131 that is connected to the second surface 122 of the metal block 120. The first area 131 of the semiconductor power chip 130 can, for example, be defined by the outline of an electrode or a metal coating (in 1 not shown), which is located on the first surface 131 of the semiconductor power chip 130 and faces the second surface 122 of the metal block 120. In this way, the first surface 131 of the semiconductor power chip 130 is the surface of the semiconductor power chip 130 which is connected to the second surface 122 of the metal block 120 and which, by virtue of this connection, is able to transfer heat from the semiconductor power chip 130 to the metal block 120. In many cases, the first area 131 of the semiconductor power chip 130 may correspond to the footprint of the semiconductor power chip 130, or may have a size that is the same as or nearly as large as the area of the footprint of the semiconductor power chip 130. Thus - in the sense of the present text - the first surface 131 of the semiconductor power chip 130 is that surface which brings about the heat transfer from the semiconductor power chip 130 to the first surface 121 of the metal block 120. In order to simplify the description, no distinction is made between the base area of the semiconductor power chip 130 and the first area 131 of the semiconductor power chip 130 in the following description.

As will be explained in more detail below, the efficiency of the heat dissipation through the metal block 120 depends on the dimensioning parameters of the metal block 120. In particular, the metal block 120 should enable the heat flow to expand (dilate) in a direction away from the semiconductor power chip 130. That is to say, the area of the heat transfer from the metal block 120 to the electrically conductive carrier 110 should be larger than the area of the heat transfer from the semiconductor power chip 130 to the metal block 120.

sein, wobei Fc der Flächeninhalt der ersten Fläche 131 des Halbleiterleistungschips 130 ist.For example, the area of the first surface 121 of the metal block 120 may be equal to or greater than $$\mathrm{4th}\text{Tm}\cdot \left(\text{Tm}+{\text{Fc}}^{0.5}\right)+\text{Fc}$$

where Fc is the area of the first area 131 of the semiconductor power chip 130.

The expansion of the area of heat transfer from the semiconductor power chip 130 to the metal block 120 and from the metal block 120 to the electrically conductive carrier 110 is indicated by the dashed line in FIG 1 illustrated. It should be noted that equation (1) may correspond to an implementation, for example, in which the difference between a lateral dimension Wb of the first surface 121 of the metal block 120 and a lateral dimension Wc of the first surface 131 of the semiconductor power chip 130 is at least 2Tm / 3 twice (if, by way of example and without loss of generality, rectangular or square heat transfer areas were assumed). In this and other examples, the metal block 120 can allow a geometric spread angle α of 30 degrees or more between the dashed line connecting the edges of the first surfaces 121 and 131 and a vertical direction corresponding to the main direction of heat flow.

sein.Furthermore, for example, the area of the first surface 121 of the metal block 120 may be equal to or greater than $$\text{3Tm}\cdot \left(\text{3Tm / 4}+{\text{Fc}}^{0.5}\right)+\text{Fc}$$

being.

Equation (2) may correspond, for example, to an implementation in which the difference between a lateral dimension Wb of the first surface 121 of the metal block 120 and a lateral one Dimension Wc of the first surface 131 of the semiconductor power chip 130 is at least twice the thickness Tm of the metal block 120. In this and other examples, the metal block 120 can allow a geometric spread angle α of 45 degrees or more between the dashed line connecting the edges of the first surfaces 121 and 131 and a vertical direction corresponding to the main direction of heat flow. For example, the lateral dimensions Wb of the metal block 120 can be in a range between 2 × 2 mm and 8 × 8 mm, in particular in a range between 3.5 × 3.5 mm and 6.5 × 6.5 mm.

The metal block 120 can be made of a metal or a metal alloy with a high thermal conductivity. Furthermore, the metal block 120 may be made of a metal having a high thermal capacity. For example, the metal block 120 may comprise or consist of copper or a copper alloy.

In 2 An exemplary top view of the power semiconductor device 100 is shown. For example, the semiconductor power chip 130 may have a rectangular or square shape. Likewise, the metal block 120 may have a rectangular or square shape, for example. In 2 the illustrated outline of the semiconductor power chip 130 corresponds to the outline of the first surface 131 of the semiconductor power chip 130, and the illustrated outline of the metal block 120 corresponds to the first surface 121 of the metal block 120. Thus, the illustrated outline delimits the areas of heat transfer from the semiconductor power chip 130 to the metal block 120 and from the metal block 120 to the electrically conductive support 110. As previously mentioned, the surface areas of these heat transfer areas differ considerably from one another. For example, a ratio of the area of the first area 121 of the metal block 120 to the area of the first area 131 of the semiconductor power chip 130 may be equal to or greater than 5.0, 7.0, 11.0, or 13.0.

The electrically conductive carrier 110 can also have an overall rectangular or square shape. For example, the electrically conductive carrier 110 may include protrusions 113 that protrude from the peripheral edge of the electrically conductive carrier 110. As in 2 As illustrated, the protrusions 113 may protrude from an encapsulation body 210 made of an insulating material. The encapsulation body 210 (the one shown in 1 not shown) may partially or completely embed the metal block 120 and the semiconductor power chip 130 located thereon.

3 FIG. 11 illustrates a semiconductor device 300. With regard to the electrically conductive substrate 110, the metal block 120, and the semiconductor power chip 130, the semiconductor device 300 may have the same design, specifications, and dimensions as the semiconductor device 100, for example an electrically conductive connecting element 320, which has a first surface 321, which is connected to the second surface 132 of the semiconductor power chip 130, which is opposite the first surface 131 of the semiconductor power chip 130. In 2 For example, the connection element 320 may be electrically and mechanically connected to an electrode (not shown) on the second surface 132 of the semiconductor power chip 130. The connecting element 320 may be a contact clip (contact clip) or some other means for connecting the semiconductor power chip to an external connection of a package, for example a tape or a plurality of bonding wires.

The connecting element 320 can extend in at least one lateral dimension beyond the outline of the semiconductor power chip 130, beyond the outline of the metal block 120 and, for example, beyond the outline of the electrically conductive carrier 110. The connector 320 may have a curved portion or protrusion 320a that may be connected to a contact pad (i.e., contact pad) 330. The contact pad 330 may be coplanar with the electrically conductive carrier 110. Furthermore, the contact island 330 can consist, for example, of the same material as the electrically conductive carrier 110. For example, the contact island 330 can be a connecting wire of the lead frame, of which the electrically conductive carrier 110 forms a chip contact island (i.e. a chip contact pad).

The semiconductor component 300 can furthermore comprise an electrically insulating material, for example a potting material, which forms an encapsulation body 310 (that of the encapsulation body 210 from FIG 2 is equivalent to). The encapsulation body 310 may partially or completely embed, for example, the metal block 120, for example the semiconductor power chip 130 and, for example, the connection element 320.

An underside 114 of the electrically conductive carrier 110 and an underside 334 of the contact island 330 can be exposed on the peripheral edge of the semiconductor component 300. These areas 114, 334 can form external connections of the semiconductor component 300. In this way, the underside 114 of the electrically conductive carrier 110 and the underside 334 of the contact pad 330 can be configured to be used (not shown) to be connected to the circuit board on which the semiconductor device 300 is mounted.

The semiconductor device 300 may comprise various package types, such as, for example, QFN (Quad Flat No-Lead) packages, for example with a half-etched lead frame, or other lead frame-based package types. The semiconductor component 300 can comprise a package as it is specified in the open standards of JEDEC (Joint Electron Device Engineering Council), for example a Super-SO8 package according to JEDEC MO-240, wherein the features, the dimensions of the package, the number of pins, etc., are incorporated herein by reference.

3 FIG. 12 also shows an exemplary, more detailed disclosure of the semiconductor device 100 that forms part of the semiconductor device 300. As in 3 As illustrated, a first bonding layer 340 can be arranged next to the top side 112 of the electrically conductive carrier 110 and the first surface 121 of the metal block 120, a second bonding layer 350 can be arranged next to the second surface 122 of the metal block 120 and the first surface 131 of the semiconductor power chip 130 , and a third bonding layer 360 may be arranged adjacent to the second area 132 of the semiconductor power chip 130 and the first area 321 of the connection element 320.

The bonding layers 340, 350, 360 can each form a diffusion solder bond, for example, which comprises or consists of, for example, AuSn, AgSn, CuSn, AgIn, AuIn, AuGe, CuIn, AuSi, Sn or Au. Furthermore, soft solder bonds, hard solder bonds, sintered metal bonds and / or electrically conductive adhesive bonds can be used in order to form one or more of the first, second or third bonding layers 340, 350, 360.

The first, second and / or third bonding layers 340, 350, 360 can have a high thermal conductivity and / or a small thickness. For example, the thickness of the first, second and / or third bonding layer 340, 350, 360 can be, for example, equal to or less than 10 μm, 5 μm or 2 μm. The smaller the thickness, the better the heat transport via the corresponding bonding layer 340, 350, 360.

The mode of operation of the metal block 120 with regard to its thermal effects is explained below with reference to FIG 3 and 4th explained. 3 and 4th are identical except that 3 schematically illustrates a stationary thermal power dissipation and 4th schematically illustrates a dynamic thermal power dissipation.

“Stationary thermal power dissipation” means the average thermal power that is generated in the semiconductor power chip 130 during operation. This thermal power is generated continuously in the semiconductor power chip 130 and must therefore be continuously dissipated from the semiconductor power chip 130. The arrows in 3 illustrate the main directions of the heat flow within the metal block 120, the electrically conductive carrier 110 and the connecting element 320. In the metal block 120, the main direction of the heat flow widens in a lateral direction with increasing distance from the semiconductor power chip 130 (or from the second surface 122 of the metal block 120). That is, due to the dimensional design of the metal block 120, the heat flow may expand as it traverses the metal block 120. As a result of this spatial expansion of the heat flow, a large-area heat flow interface is formed on the first surface 121 of the metal block 120. This large transition area for heat dissipation between the metal block 120 and the electrically conductive carrier 110 allows continuous and efficient heat dissipation. In other words: the metal block 120 can be viewed as a “heat flow geometry converter” which is shaped in such a way that it is adapted to the spatial properties of the heat flow expansion in solids.

According to the disclosure, it is possible to significantly reduce the thickness T1 of the electrically conductive support 110 to achieve the same steady-state thermal power dissipation as a conventional implementation without the metal block 120 Leadframe (leadframe) make up a significant proportion of the total cost of the package, the presence of the metal block 120, thanks to the possibility of reducing the thickness T1, significantly lowers the total cost of the encapsulation.

In addition, the dynamic dissipation of heat output is taken into account. “Dynamic heat power dissipation” means fluctuations in the generation of the heat power in the semiconductor power chip 130. The heat power generated in the semiconductor power chip 130 is time-variant. Time variance can be caused, for example, by the time-variant operation of the semiconductor power chip 130 or a time-variant operation of a load connected to it, or both.

The dynamic heat power dissipation is counteracted by the heat capacity of the metal block 120, which is closely coupled to the semiconductor power chips 130. The heat capacity of the metal block 120 enables a short-term heat storage capacity. The storage of heat from dynamic dissipation in the metal block 120 allows temporary cooling of the semiconductor power chip 110. In other words: the metal block 120 expands the heat capacity of the semiconductor power chip 130 by an effective heat capacity, which prevents power loss peaks from overheating the semiconductor power chip 130.

In 4th The solid arrow from the semiconductor power chip 130 into the metal block 120 illustrates the capacity of dynamic thermal power dissipation into the metal block 120. The thinner solid arrow from the semiconductor power chip 130 into the connector 320 illustrates the capacity of the dynamic thermal power dissipation into the connector 320.

The connecting element 320 may be provided with a protrusion 323 that forms a region of greater thickness, measured between the first surface 321 of the connecting element 320 and a second surface, namely the top surface 322 of the connecting element 320. The protrusion 323 also provides a heat capacity, which serves as a short-term heat storage capacity during the time-variant operation of the semiconductor power chip 130.

It can thus be determined that the metal block 120 brings about both improved stationary cooling by virtue of lateral heat flow expansion and improved short-term cooling by coupling an additional heat capacity for buffering temperature peaks caused by fluctuating heat power dissipation.

5 FIG. 14 illustrates a top view of exemplary semiconductor device 300. Line AA is a section line that intersects, for example, the sectional views of FIG 3 and 4th is equivalent to. 5 resembles 2 , and we refer to the corresponding description to avoid repetition. Also illustrated 5 the contact island (contact pad) 330, which may be arranged along at least part of a side of the encapsulation body 210. Similar to the electrically conductive carrier 110, the contact island 330 can have projections 333 which protrude from the encapsulation body 210 and are exposed in order to form external connections of the semiconductor component 300, for example. As in 5 As shown, the semiconductor power chip 130 may be electrically connected to the pad 330 through the connector 320. In order to enable high conductivity, a section 320b of increased width can be arranged between the semiconductor power chip 130 and the contact pad 330 in the connection element 320.

Furthermore, the semiconductor component 300 can comprise a further contact island (contact pad) 530. The contact pad 530 may be electrically connected to an electrode, for example the gate electrode, of the semiconductor power chip 130. For example, a bond wire (not shown) can be used for the electrical connection.

6th illustrates an exemplary circuit configuration of a power supply 600 using a high-power transistor T2 and a low-voltage transistor T1 arranged in a cascode circuit. The high-power transistor T2 can be, for example, a HEMT, for example a GaN-HEMT. The critical field of GaN is ten times larger than that of Si, making small size, high power, high voltage applications possible. Furthermore, GaN offers fast switching capabilities with a low charge. Other materials, such as SiC, also have critical fields that are significantly larger than the critical field of Si and can therefore also require extensive heat dissipation via small-area heat transfer interfaces. The low-voltage transistor T1 can, for example, be an FET, for example as a Si-MOSFET.

The transistors T1, T2 can be vertical or horizontal components. The power supply 600 may be an AC-to-DC converter, for example. The DC voltage that is provided at an output 601 can be at least 100 V, 200 V, 400 V, 600 V, etc., for example. Terminal 602 can be connected to a negative supply voltage or ground. An input voltage of, for example, 0 to 5 V at connection 603 can be used to control the gate electrode of transistor T1. The gate electrode of transistor T2 can be connected to a negative supply voltage or ground, for example. Inductances 604 may be between ground and the source of transistor T1, ground and the gate of transistor T2, the drain of transistor T1 and the source of transistor T2 and the drain of transistor T2 and the output 601 connected.

The GaN-HEMT T2 is a switch-off component ("normally-on device"). However, connecting the low voltage FET transforms T1 with the source electrode of the GaN-HEMT T2 via the cascode circuits the HEMT T2 into a switch-on transistor (English: "normally-off device").

The power supply 600 can be implemented as a double-chip component. That is, the low voltage FET T1 can be implemented in a single semiconductor power chip, and the high voltage HEMT T2 can also be implemented in a single semiconductor power chip 130 which, for example, can be encapsulated in accordance with the disclosure herein.

the 7A-7G illustrate exemplary stages of an exemplary method of manufacturing a semiconductor power device 700. The semiconductor power device 700, as shown in FIG 7G shown is similar to the semiconductor power components 100, 300, and we refer to the corresponding description in the present text in order to avoid repetition.

7A illustrates the provision of the electrically conductive carrier 110 and the contact island (contact pad) 330. As mentioned above, the electrically conductive carrier 110 and the contact island 330 can have lower and / or upper sides which are respectively coplanar with one another.

According to 7B For example, a bonding material 710 can be deposited on top 112 of the electrically conductive substrate 110. The bonding material 710 can for example comprise or consist of solder, a soft solder, a diffusion solder, a paste, a nanopaste or an electrically conductive adhesive. The bonding material 710 can be deposited on the carrier 110 in a batch process, that is to say for a plurality of semiconductor components 700 that are produced in parallel.

More specifically, the bonding material 710 can be made of, for example, a solder material for diffusion solder bonding, as mentioned above, through a paste containing metal particles dispersed in a polymer material or resin, such as α-terpineol, or other materials. Metal particles contained in a paste can consist of silver, gold, copper, tin or nickel, for example. The extensions (average diameter) of the metal particles can be, for example, smaller than 100 nm and in particular smaller than 50 nm. These pastes are also referred to as nanopastes by the person skilled in the art.

As in 7C As shown, the metal block 120 is placed on the bonding material 710 over the carrier 110. At this point in time, the semiconductor power chip 130 can already be mounted on the metal block 120, for example with the aid of a bonding layer, as described above. In particular, a diffusion solder bonding layer, which provides for a direct thermal coupling between the semiconductor power chip 130 and the metal block 120, can be used.

As in 7D As shown, a bonding material 710 is deposited on a top surface 335 of the contact island (contact pad) 330. The deposition of the bonding material 710 on the upper side 335 can also be carried out in a batch process, that is to say for a plurality of semiconductor power components 700 that are produced in parallel.

As in 7E As shown, bonding material 710 is deposited on the second surface 132 of the semiconductor power chip 130. The deposition of the bonding material 710 on the second surface 132 can also take place simultaneously with the in 7D deposition step shown can be carried out.

As in 7F can be seen, the connector 320 can be via the shown in FIGS 7D and 7E deposited bonding materials 710 are arranged. The arrangement of the connection elements 320 over a plurality of semiconductor power chips 130 and contact pads (contact pads) 330 can be carried out in a batch process.

As in 7G As shown, energy is applied to melt, sinter, or cure the bonding material 710. The energy can be applied through heat, radiation, etc. For example, heat can be applied in a furnace such as a reflow furnace. By applying energy, the bonding material 710, for example solder, metal paste or conductive adhesive, electrically and mechanically connects the top 112 of the carrier 110 to the first surface 121 of the metal block 120, and the second surface 132 of the semiconductor power chip 130 to the bottom 321 of the connecting element 320, and the upper side 335 of the contact island (contact pad) 330 with the lower side 321 on the projection 320a of the connecting element 320.

The sequential process stages, as in the 7A-7G may be performed in a different order, for example. For example, after the step of FIG 7C and before the step of 7D are bonded to the electrically conductive carrier 110. According to another variant, the semiconductor power chip 130 only needs to be on the metal block 120 in FIG 7F to be arranged, but not to be bonded to them. In this case, a single final temperature process, for example a melting step, can be sufficient to achieve all Establish bond connections in the semiconductor component 700.

Although specific embodiments have been illustrated and described in the present text, it is clear to the person skilled in the art that a large number of different alternative and / or equivalent implementations can take the place of the specific embodiments shown and described without departing from the concept of the present invention. This application is also intended to include all adaptations or variations of the embodiments specifically discussed in the present text.

Claims (15)

A semiconductor component (300) comprising: a lead frame (110) having a mounting surface (112) and a second side (114) arranged opposite the mounting surface (112); a metal block (120) having a first surface (121) facing the lead frame (110) and a second surface (122) facing away from the lead frame (110), the metal block (120) having a thickness between the first (121) and second (122) areas measured equal to or greater than 1.5 times the thickness of the lead frame (110) and where an area of the first area (121) is equal to or greater than 4Tm * (Tm + Fc ^0.5 ) + Fc, where Tm is the thickness of the metal block (120) measured between the first (121) and second (122) surfaces, and Fc is an area of a first surface of a semiconductor power chip (130) which is marked with the second surface (122) of the metal block (120) is bonded; wherein the semiconductor power chip (130) is disposed over the second surface (122) of the metal block (120) and is electrically connected to the metal block (120) and the lead frame (110); an encapsulation body (310) which embeds the lead frame (110), the metal block (120) and the semiconductor power chip (130), the second side (114) of the lead frame (110) under the semiconductor power chip (120) on the encapsulation body (310) exposed; and a contact clip (320) having a first surface (321) connected to a second surface of the semiconductor power chip (130) opposite the first surface of the semiconductor power chip (130). Semiconductor component (300) according to Claim 1 further comprising: a first bonding layer (340) mechanically and electrically connecting the mounting surface (112) of the lead frame (110) to the first surface (121) of the metal block (120). Semiconductor component (300) according to Claim 2 wherein the first bonding layer (340) is a diffusion solder layer, a soft solder layer, a sintered metal layer, a nanopaste layer or a conductive adhesive layer. The semiconductor component (300) according to any one of the preceding claims, further comprising: a second bonding layer (350) mechanically and electrically connecting the second surface (122) of the metal block (120) to a first surface of the semiconductor power chip (130). Semiconductor component (300) according to Claim 4 wherein the second bonding layer (350) is a diffusion solder layer, a soft solder layer, a sintered metal layer, a nanopaste layer or a conductive adhesive layer. The semiconductor component (300) according to any one of the preceding claims, wherein the metal block (120) has a thickness, measured between the first (121) and second (122) surfaces of the metal block (120), of equal to or greater than 0.5 mm, 0, 75 mm, 1.0 mm, 1.25 mm or 1.5 mm. Semiconductor component (300) according to one of the preceding claims, wherein an area of the first surface (121) of the metal block (120) is equal to or greater than 8.0 mm ² , 14.0 mm ² , 20.0 mm ² or 26.0 mm ² is. Semiconductor component (300) according to one of the preceding claims, wherein an area of a first area of the semiconductor power chip (130), which is connected to the second area (122) of the metal block (120), is equal to or less than 10.0 mm ² , 7, 5mm ² , 5.0mm ² , 2.5mm ^2, or 1.0mm ² . The semiconductor device (300) according to any one of the preceding claims, wherein an area of the first area (121) of the metal block (120) is equal to or greater than 3Tm * (3Tm / 4 + Fc ^0.5 ) + Fc, where Tm is the thickness of the metal block (120), measured between the first (121) and second (122) surfaces of the metal block (120), and Fc is an area of a first surface of the semiconductor power chip (130) connected to the second surface of the metal block (120) . The semiconductor component (300) according to any one of the preceding claims, wherein the semiconductor power chip (130) is a vertical semiconductor power chip. Semiconductor component (300) according to one of the preceding claims, wherein the semiconductor power chip (130) is a GaN power chip, a Si power chip or an SiC power chip. The semiconductor component (300) according to any one of the preceding claims, wherein a thermal output of the semiconductor power chip (130) is equal to or greater than 3.0 W, 5.0 W, 7.0 W or 9.0 W. Semiconductor component (300) according to one of the preceding claims, wherein the semiconductor component (300) is an AC-DC converter or a DC-DC converter. A method of manufacturing a semiconductor device (300), the method comprising: bonding a semiconductor power chip (130) to a second surface (122) of a metal block (120) and thereby electrically connecting the semiconductor power chip (130) to the metal block (120); Bonding of the metal block (120) to a mounting surface (112) of a lead frame (110), wherein a first surface (121) of the metal block (120) faces the lead frame (110) and the second surface (122) faces the lead frame (110) further, wherein the metal block (120) has a thickness, measured between the first (121) and second (122) surfaces, equal to or greater than 1.5 times the thickness of the lead frame (110) and an area of the first Area (121) is equal to or greater than 4Tm * (Tm + Fc ^0.5 ) + Fc, where Tm is the thickness of the metal block (120) measured between the first (121) and second (122) surfaces, and Fc is a Is the area of a first surface of a semiconductor power chip (130) which is connected to the second surface (122) of the metal block (120); Connecting a first surface (321) of a contact clip (320) to a second surface of the semiconductor power chip (130) opposite the first surface of the semiconductor power chip (130); and encapsulating the semiconductor power chip (130), the metal block (120) and the lead frame (110) in an encapsulation body (310) such that a second side (114) of the lead frame (110) opposite the mounting surface (112) under the semiconductor power chip (120 ) is exposed on the encapsulation body (310). Procedure according to Claim 14 further comprising: depositing a first bonding material on the lead frame (110); Placing the metal block (120) on the first bonding material; Depositing a second bonding material on the semiconductor power chip (130); Placing a contact clip on the second bonding material; and applying energy to mount the metal block (120) to the lead frame (110) and to mount the contact clip to the semiconductor power chip (130).

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