DE102015226641A1 - Current limiting device - Google Patents
Current limiting device Download PDFInfo
- Publication number
- DE102015226641A1 DE102015226641A1 DE102015226641.9A DE102015226641A DE102015226641A1 DE 102015226641 A1 DE102015226641 A1 DE 102015226641A1 DE 102015226641 A DE102015226641 A DE 102015226641A DE 102015226641 A1 DE102015226641 A1 DE 102015226641A1
- Authority
- DE
- Germany
- Prior art keywords
- doped semiconductor
- current
- limiting device
- semiconductor region
- conductive layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 65
- 238000001816 cooling Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HBBGRARXTFLTSG-UHFFFAOYSA-N Lithium ion Chemical compound [Li+] HBBGRARXTFLTSG-UHFFFAOYSA-N 0.000 claims description 3
- 229910001416 lithium ion Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- JDZCKJOXGCMJGS-UHFFFAOYSA-N [Li].[S] Chemical compound [Li].[S] JDZCKJOXGCMJGS-UHFFFAOYSA-N 0.000 claims description 2
- 230000008569 process Effects 0.000 claims description 2
- 238000005476 soldering Methods 0.000 claims description 2
- 238000003466 welding Methods 0.000 claims description 2
- 230000005669 field effect Effects 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- BUHVIAUBTBOHAG-FOYDDCNASA-N (2r,3r,4s,5r)-2-[6-[[2-(3,5-dimethoxyphenyl)-2-(2-methylphenyl)ethyl]amino]purin-9-yl]-5-(hydroxymethyl)oxolane-3,4-diol Chemical compound COC1=CC(OC)=CC(C(CNC=2C=3N=CN(C=3N=CN=2)[C@H]2[C@@H]([C@H](O)[C@@H](CO)O2)O)C=2C(=CC=CC=2)C)=C1 BUHVIAUBTBOHAG-FOYDDCNASA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004146 energy storage Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
- H01L2224/081—Disposition
- H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
- H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/08245—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
- H01L2224/091—Disposition
- H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/09181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M2200/00—Safety devices for primary or secondary batteries
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Electrochemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Secondary Cells (AREA)
Abstract
Strombegrenzungsvorrichtung umfassend eine elektrisch leitfähige Schicht mit einem im Wesentlichen konstanten Widerstand, dadurch gekennzeichnet, dass die Strombegrenzungsvorrichtung ferner umfasst: – ein n-dotiertes Halbleitergebiet mit flächiger Grundform, welches mit der elektrisch leitfähigen Schicht elektrisch verbunden ist, und mindestens ein von p-dotiertes Halbleitergebiet aufweist, – mindestens eine elektrische Leitung zur Kontaktierung des mindestens einen p-dotierten Halbleitergebiets mit einer Stromzuführung der elektrisch leitfähigen Schicht, die von der elektrisch leitfähigen Schicht und dem n-dotierten Halbleitergebiet elektrisch isoliert ist.Current limiting device comprising an electrically conductive layer having a substantially constant resistance, characterized in that the current limiting device further comprises: - an n-doped semiconductor region having a planar basic shape, which is electrically connected to the electrically conductive layer, and at least one of p-doped semiconductor region comprises, - at least one electrical line for contacting the at least one p-doped semiconductor region with a power supply of the electrically conductive layer, which is electrically isolated from the electrically conductive layer and the n-doped semiconductor region.
Description
Die Erfindung geht aus von einer Strombegrenzungsvorrichtung mit einer elektrisch leitfähigen Schicht mit einem im Wesentlichen konstanten Widerstand gemäß dem Oberbegriff der unabhängigen Ansprüche.The invention is based on a current-limiting device having an electrically conductive layer with a substantially constant resistance according to the preamble of the independent claims.
Stand der TechnikState of the art
Eine Batterie muss als Energiequelle sicherstellen, dass
- – keine gefährlichen Ströme durch einen angeschlossenen Stromkreis fließen (Kurzschluss)
- – Batteriezellen der Batterie und andere innerhalb der Batterie angeordnete Komponenten nicht durch zu hohe Ströme beschädigt werden.
- - no dangerous currents flow through a connected circuit (short circuit)
- - Battery cells of the battery and other components located inside the battery should not be damaged by excessive currents.
Eine Absicherung gegen diese Fehlerfälle (Überstrom bzw. Kurzschluss) wird von einem Batteriesystem durch eine redundante Stromerfassung und eine Auswertung mittels einer Software realisiert. Durch eine Kommunikation des eines Batteriesteuergeräts des Batteriesystems mit einem Fahrzeug wird der Batteriestrom geregelt. Bei einer Überschreitung der zulässigen Betriebsgrenze kommt es zu einer Abschaltung mittels Hauptschütze. Zur Trennung sehr hoher Fehlerströme verfügt die Batterie zusätzlich über eine Hauptsicherung, beispielsweise in Form einer Schmelzsicherung.A protection against these fault cases (overcurrent or short circuit) is realized by a battery system by a redundant current detection and an evaluation by means of software. Through a communication of a battery control device of the battery system with a vehicle, the battery current is regulated. If the permissible operating limit is exceeded, the main contactors are switched off. To separate very high fault currents, the battery also has a main fuse, for example in the form of a fuse.
Die Hauptsicherung ist ein teures Bauteil, das im Extremfall auch durch eine mechanische Beanspruchung zu einem Totalausfall der Batterie führen kann. The main fuse is an expensive component, which in extreme cases can also lead to a total failure of the battery due to mechanical stress.
Die redundante Stromerfassung führt zu einem komplexen Systemdesign. In Batteriesystemen, insbesondere Lithium-Ionen-Batteriesystemen sind Strommessgeräte verbaut, die beispielsweise nach dem Shunt-, Hall- oder Flux-Prinzip arbeiten. Der Batteriestrom ist neben Zelltemperaturen und Zellspannungen eine wichtige Messgröße zur Beobachtung und Regelung des Batteriesystems. The redundant current detection leads to a complex system design. In battery systems, in particular lithium-ion battery systems power meters are installed, which operate for example according to the shunt, reverb or flux principle. In addition to cell temperatures and cell voltages, the battery current is an important parameter for monitoring and controlling the battery system.
Die Stromsensoren sind gemäß dem Stand der Technik als externe Strommesseinrichtungen ausgeführt, von den Batteriezellen separiert in Batteriesystemen verbaut und werden von einem Batteriesteuergerät (BMS) ausgelesen. Die Kommunikation zwischen Sensor und Batteriesteuergerät erfolgt beispielsweise über ein Bussystem (LIN-, CAN-Bus) nur in Ausnahmefällen über eine direkte Auslesung eines physikalischen elektrischen Signals.The current sensors are designed according to the prior art as external current measuring devices, separated from the battery cells installed in battery systems and are read by a battery control unit (BMS). The communication between the sensor and the battery control unit takes place, for example, via a bus system (LIN, CAN bus) only in exceptional cases via a direct readout of a physical electrical signal.
Für eine Berechnung einer elektrischen Leistung P = U·I werden in einer Batterie Strom und Spannung miteinander in Berechnung verwendet. Zu diesem Zweck ist es wichtig, dass die kontinuierlich erfassten Werte zum selben Zeitpunkt aufgenommen werden. Beispielsweise wird ein errechneter Leistungswert falsch, wenn der Stromwert zu einem anderen Zeitpunkt als der Spannungswert erfasst wird. Derartige zeitliche Versätze entstehen jedoch insbesondere dann, wenn beispielsweise eine Strommessung in einem Stromsensor verarbeitet wird, über ein Bussystem der verarbeitete Wert an das Batteriesteuergerät gemeldet wird, das Batteriesteuergerät dieses Bussignal wandelt und erst dann mit den Wert zur Berechnung mit einer Spannungsmessung verwenden kann. Die Spannungsmessung selbst kann auch zeitlich entkoppelt sein, wenn beispielsweise Zellüberwachungseinheiten (CSC) zur Spannungsmessung verwendet werden, welche über ein Bussystem mit dem Batteriesteuergerät kommunizieren.For a calculation of an electric power P = U · I, current and voltage are used together in a battery in a battery. For this purpose, it is important that the continuously recorded values be recorded at the same time. For example, a calculated power value becomes false when the current value is detected at a time other than the voltage value. However, such temporal offsets arise in particular when, for example, a current measurement is processed in a current sensor, the processed value is reported to the battery control device via a bus system, the battery control device converts this bus signal and can then use the value for calculation with a voltage measurement. The voltage measurement itself can also be decoupled in time if, for example, cell monitoring units (CSC) are used for voltage measurement, which communicate with the battery control unit via a bus system.
Gemäß dem Stand der Technik werden aufwendige softwaretechnische Filterungen und Glättungen der Strom- und/oder Spannungswerte durchgeführt. Dies verursacht Ungenauigkeiten in Bezug auf die gemessenen Werte. Zur Herstellung einer Synchronität der Strom- und Spannungsmessung tragen die Filterungen nur bedingt bei. Dadurch sind komplexe Kabelbäume, welche verschiedene Instanzen miteinander verbinden, mehrteilige und zum Teil komplexe Stromschienen bzw. Kabel im Hochvoltkreis, um die Sensoren zwischen schalten zu können, notwendig. Diese hohe Komplexität verursacht hohe Kosten. Jeder weitere Sensor benötigt neben Kabelbäumen und Schnittstellen im Hochvoltpfad weiter Bauraum und Gewicht in einem Batteriepack.According to the state of the art, elaborate software-technical filtering and smoothing of the current and / or voltage values are carried out. This causes inaccuracies in the measured values. To create a synchronicity of the current and voltage measurement, the filters contribute only to a limited extent. As a result, complex harnesses, which connect different instances together, multi-part and sometimes complex busbars or cables in the high-voltage circuit in order to switch the sensors between, necessary. This high complexity causes high costs. Each additional sensor requires not only wiring harnesses and interfaces in the high-voltage path but also space and weight in a battery pack.
Des Weiteren werden Temperaturen mittels Temperatursensoren in räumliczher Nähe der Zellen, beispielsweise auf dem Zellverbinder, über den Modulkontroller gemessen und über ein Bussystem an das Batteriesteuergerät gesendet. Dies hat eine weitere Erhöhung der Komplexität zur Folge.Furthermore, temperatures are measured by means of temperature sensors in spatial proximity of the cells, for example on the cell connector, via the module controller and sent to the battery control unit via a bus system. This results in a further increase in complexity.
Die Druckschrift
Die Druckschrift
Die Druckschrift
Die Druckschrift
Die Druckschrift
Die Druckschrift
Offenbarung der ErfindungDisclosure of the invention
Vorteile der ErfindungAdvantages of the invention
Die erfindungsgemäße Vorgehensweise mit den kennzeichnenden Merkmalen der unabhängigen Ansprüche weist demgegenüber den Vorteil auf, dass die Strombegrenzungsvorrichtung ferner ein n-dotiertes Halbleitergebiet mit flächiger Grundform, welches mit der elektrisch leitfähigen Schicht elektrisch verbunden ist, und mindestens ein von p-dotiertes Halbleitergebiet aufweist, wobei mindestens eine elektrische Leitung zur Kontaktierung des mindestens einen p-dotierten Halbleitergebiets mit einer Stromzuführung des elektrischen Widerstands, die von der elektrisch leitfähigen Schicht und dem n-dotierten Halbleitergebiet elektrisch isoliert ist, umfasst. Dadurch kann vorteilhafterweise mittels einer passiven Vorrichtung ohne Verwendung einer Steuerelektronik ein maximaler Stromfluss begrenzt werden. The procedure according to the invention with the characterizing features of the independent claims, on the other hand, has the advantage that the current limiting device further comprises an n-doped semiconductor region having a planar basic shape, which is electrically connected to the electrically conductive layer, and at least one p-doped semiconductor region at least one electrical line for contacting the at least one p-doped semiconductor region with a power supply of the electrical resistance, which is electrically isolated from the electrically conductive layer and the n-doped semiconductor region includes. As a result, a maximum current flow can advantageously be limited by means of a passive device without the use of control electronics.
Weitere vorteilhafte Ausführungsformen sind Gegenstand der Unteransprüche.Further advantageous embodiments are the subject of the dependent claims.
Die Strombegrenzungsvorrichtung umfasst ferner eine weitere elektrische leitfähige Schicht, welche mit dem n-dotierten Halbleitergebiet und/oder des mindestens einen p-dotierten Halbleitergebiets elektrisch verbunden ist. Dadurch wird eine robuste Bauweise der Strombegrenzungsvorrichtung erreicht. Weiter kann durch eine geeignete Materialwahl eine Wärmeabfuhr einer im Inneren der Strombegrenzungsvorrichtung entstehenden Hitzeentwicklung erreicht werden. The current-limiting device further comprises a further electrically conductive layer, which is electrically connected to the n-doped semiconductor region and / or the at least one p-doped semiconductor region. As a result, a robust construction of the current limiting device is achieved. Furthermore, a heat dissipation of a heat development occurring in the interior of the current-limiting device can be achieved by a suitable choice of material.
Die Strombegrenzungsvorrichtung umfasst ferner mindestens eine weitere elektrische Leitung zur Kontaktierung des mindestens einen p-dotierten Halbleitergebiets mit einer Stromzuführung der weiteren elektrisch leitfähigen Schicht, die von der zweiten Schichten und dem n-dotierten Halbleitergebiet elektrisch isoliert ist. Dadurch wird eine Kurzschlussrichtung des Stromes in entgegengesetzter Richtung abgesichert. The current-limiting device further comprises at least one further electrical line for contacting the at least one p-doped semiconductor region with a current supply of the further electrically conductive layer, which is electrically insulated from the second layer and the n-doped semiconductor region. As a result, a short-circuit direction of the current is secured in the opposite direction.
Bei einer Verwendung der erfindungsgemäßen Strombegrenzungsvorrichtung wird so neben einem während eines Entladevorgangs fließenden Stromes auch ein während eines Ladevorgangs fließender Strom begrenzt. When using the current limiting device according to the invention as well as a current flowing during a discharge current and a current flowing during a charging current is limited.
Die Strombegrenzungsvorrichtung umfasst Mittel zur Kühlung der elektrisch leitfähigen Schicht, des n-dotierten Halbleitergebiets und/oder des p-dotierten Halbleitergebiets. Dadurch wird eine Kühlung der Strombegrenzungsvorrichtung erreicht. Die Mittel zur Kühlung sind beispielsweise durch Vorsehen von Kühlrippen und/oder einer aktiven Kühlung beispielsweise in Form eines Kühlkreislaufs möglich. The current-limiting device comprises means for cooling the electrically conductive layer, the n-doped semiconductor region and / or the p-doped semiconductor region. As a result, cooling of the current-limiting device is achieved. The means for cooling are possible, for example, by providing cooling fins and / or active cooling, for example in the form of a cooling circuit.
Vorteilhafterweise wird die erfindungsgemäße Strombegrenzungsvorrichtung in mindestens einem Zellterminal einer Batteriezelle und/oder einem Modulverbinder eines Batteriemoduls eines Batteriesystems zur Begrenzung eines fließenden Stroms zwischen Batteriezellen und/oder Batteriemodulen verwendet. Dadurch ist insbesondere bei prismatischen Batteriezellen eine bauraumoptimierte Integration möglich, wobei ein beispielsweise vorhandenes Zellterminal als elektrisch leitfähige Schicht dient.Advantageously, the current limiting device according to the invention is used in at least one cell terminal of a battery cell and / or a module connector of a battery module of a battery system for limiting a flowing current between battery cells and / or battery modules. As a result, space-optimized integration is possible, in particular in the case of prismatic battery cells, with an existing cell terminal, for example, serving as an electrically conductive layer.
Vorteilhafterweise wird die erfindungsgemäße Strombegrenzungsvorrichtung in Form einer Batteriezelle zur Begrenzung eines fließenden Stroms innerhalb eines Batteriemoduls verwendet. Dadurch ist eine Integration der Strombegrenzungsvorrichtung, beispielsweise zwischen zwei Nutshell-Zellen und/oder als ein Deckel oder ein Boden innerhalb eines Nutshell-Zellenmoduls möglich. Weiter ist vorteilhafterweise eine Ausführung innerhalb einer Nutshell-Zelle möglich, bei der beispielsweise eine n-dotierte Halbleiterbeschichtung innerhalb der Nutshell-Zell eingesetzt wird, durch die ein Strom seriell fließt.Advantageously, the current limiting device according to the invention is used in the form of a battery cell for limiting a flowing current within a battery module. As a result, an integration of the current limiting device, for example, between two Nutshell cells and / or as a lid or a bottom within a Nutshell cell module is possible. Furthermore, an embodiment within a Nutshell cell is advantageously possible in which, for example, an n-doped semiconductor coating is used within the Nutshell cell, through which a current flows in series.
Die Nutshell-Batteriezellen umfassen beispielsweise Lithium-Ionen-, Lithium-Schwefel-, Lithium-Luft-Zellen. Dadurch wird vorteilhafterweise eine Strombegrenzung bei energieintensiven Batteriesystemen ermöglicht.The Nutshell battery cells include, for example, lithium-ion, lithium-sulfur, lithium-air cells. This advantageously allows current limitation in energy-intensive battery systems.
Das Verfahren zur Herstellung einer erfindungsgemäßen Strombegrenzungsvorrichtung umfasst folgende Schritte:
- – Herstellung einer Halbleiterschicht mit mindestens einem p-dotierten Halbleitergebiet und einem n-dotierten Halbleitergebiet umfassend die Schritte: Strukturierung eines n-dotierten Silizium-Wafers, Dotierung des n-dotierten Silizium-Wafers mit P-dotiertem Halbleitermaterial, Anlagen von Kontaktierungen und elektrischen Leitungen,
- – Elektrisches Kontaktieren der Halbleiterschicht mit mindestens einer elektrisch leitfähigen Schicht mittels eines Schweiß-Löt- und/oder Bonding-Vorgangs.
- Production of a semiconductor layer having at least one p-doped semiconductor region and one n-doped semiconductor region, comprising the steps of structuring an n-doped silicon region Wafers, doping of the n-doped silicon wafer with P-doped semiconductor material, systems of contacts and electrical lines,
- - electrically contacting the semiconductor layer with at least one electrically conductive layer by means of a welding soldering and / or bonding process.
Dadurch wird eine kostengünstige und technisch einfache Herstellung der Strombegrenzungsvorrichtung ermöglicht, die mittels Standardverfahren durchgeführt werden kann.This allows a cost-effective and technically simple production of the current-limiting device, which can be carried out by means of standard methods.
Kurzbeschreibung der FigurenBrief description of the figures
Ausführungsbeispiele der Erfindung sind in der Zeichnung dargestellt und in der nachfolgenden Beschreibung näher erläutert.Embodiments of the invention are illustrated in the drawings and explained in more detail in the following description.
Es zeigt:It shows:
Detaillierte Beschreibung der AusführungsbeispieleDetailed description of the embodiments
Gleiche Bezugszeichen bezeichnen in allen Figuren gleiche Vorrichtungskomponenten.The same reference numerals denote the same device components in all figures.
Die erfindungsgemäße Strombegrenzungsvorrichtung
In einer weiteren vorteilhaften Ausführungsform eignet sich eine Multigate-Sperrschicht-Feldeffekttransistorsbauweise, welche eine flächige Grundform hat und mehrere p-dotierte Halbleitergebiete
Die erfindungsgemäße Strombegrenzungsvorrichtung
Durch eine flächige Ausführung kann die erfindungsgemäße Strombegrenzungsvorrichtung
In einer weiteren Ausführungsform ist die erfindungsgemäße Strombegrenzungsvorrichtung
Durch die Verwendung der erfindungsgemäßen Strombegrenzungsvorrichtung
ZITATE ENTHALTEN IN DER BESCHREIBUNG QUOTES INCLUDE IN THE DESCRIPTION
Diese Liste der vom Anmelder aufgeführten Dokumente wurde automatisiert erzeugt und ist ausschließlich zur besseren Information des Lesers aufgenommen. Die Liste ist nicht Bestandteil der deutschen Patent- bzw. Gebrauchsmusteranmeldung. Das DPMA übernimmt keinerlei Haftung für etwaige Fehler oder Auslassungen.This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.
Zitierte PatentliteraturCited patent literature
- DE 102004057690 A1 [0010] DE 102004057690 A1 [0010]
- DE 102012017673 A1 [0011] DE 102012017673 A1 [0011]
- DE 102008011789 A1 [0012] DE 102008011789 A1 [0012]
- DE 102012213053 A1 [0013] DE 102012213053 A1 [0013]
- DE 102006034589 A1 [0014] DE 102006034589 A1 [0014]
- US 2002/0125507 A1 [0015] US 2002/0125507 A1 [0015]
Claims (8)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102015226641.9A DE102015226641A1 (en) | 2015-12-23 | 2015-12-23 | Current limiting device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102015226641.9A DE102015226641A1 (en) | 2015-12-23 | 2015-12-23 | Current limiting device |
Publications (1)
Publication Number | Publication Date |
---|---|
DE102015226641A1 true DE102015226641A1 (en) | 2017-06-29 |
Family
ID=59010518
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE102015226641.9A Pending DE102015226641A1 (en) | 2015-12-23 | 2015-12-23 | Current limiting device |
Country Status (1)
Country | Link |
---|---|
DE (1) | DE102015226641A1 (en) |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000016403A1 (en) * | 1998-09-16 | 2000-03-23 | Siced Electronics Development Gmbh & Co. Kg | Semiconductor device and semiconductor structure with contact |
FR2818013A1 (en) * | 2000-12-13 | 2002-06-14 | St Microelectronics Sa | Junction field effect transistor designed to form a current limiter |
US20020125507A1 (en) | 2001-03-07 | 2002-09-12 | Washburn James Ray | Interruptable high-voltage current limiter suitable for monolithic integration |
DE102004057690A1 (en) | 2004-11-30 | 2006-06-01 | Robert Bosch Gmbh | Charging device for an electrical energy store connected to a source as for motor vehicle airbags has clocked voltage converter and current limiter |
DE102006034589A1 (en) | 2006-07-26 | 2008-01-31 | Siemens Ag | Semiconductor arrangement for limiting over-current e.g. during start-up phase of motor, has limiter unit including dual structure with two lateral current flow channels, where arrangement is integrated in hybrid or monolithic manner |
DE102008011789A1 (en) | 2007-03-01 | 2008-09-04 | Infineon Technologies Ag | Integrated circuit, has multiple partial circuits with substrate, and multiple multi-gate field-effect transistor power supply circuits that are electrically coupled with different voltage of selectable partial circuits |
US20090206438A1 (en) * | 2004-10-06 | 2009-08-20 | Peter Flohrs | Semiconductor component |
DE102012017673A1 (en) | 2012-09-07 | 2013-06-06 | Daimler Ag | Circuit device for coupling high voltage (HV) battery with vehicle network e.g. hybrid vehicle network, has power electronic switch that is connected in series with relay for power interruption between HV battery and vehicle network |
DE102012213053A1 (en) | 2012-07-25 | 2014-01-30 | Robert Bosch Gmbh | Battery for use in motor car, has battery cell which is disengaged from one of the terminals, while lower terminal and upper terminal are conductively connected with each other in secondary switching position |
DE102014107287A1 (en) * | 2014-05-23 | 2015-11-26 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Device and method for bridging an electrical energy storage device |
-
2015
- 2015-12-23 DE DE102015226641.9A patent/DE102015226641A1/en active Pending
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000016403A1 (en) * | 1998-09-16 | 2000-03-23 | Siced Electronics Development Gmbh & Co. Kg | Semiconductor device and semiconductor structure with contact |
FR2818013A1 (en) * | 2000-12-13 | 2002-06-14 | St Microelectronics Sa | Junction field effect transistor designed to form a current limiter |
US20020125507A1 (en) | 2001-03-07 | 2002-09-12 | Washburn James Ray | Interruptable high-voltage current limiter suitable for monolithic integration |
US20090206438A1 (en) * | 2004-10-06 | 2009-08-20 | Peter Flohrs | Semiconductor component |
DE102004057690A1 (en) | 2004-11-30 | 2006-06-01 | Robert Bosch Gmbh | Charging device for an electrical energy store connected to a source as for motor vehicle airbags has clocked voltage converter and current limiter |
DE102006034589A1 (en) | 2006-07-26 | 2008-01-31 | Siemens Ag | Semiconductor arrangement for limiting over-current e.g. during start-up phase of motor, has limiter unit including dual structure with two lateral current flow channels, where arrangement is integrated in hybrid or monolithic manner |
DE102008011789A1 (en) | 2007-03-01 | 2008-09-04 | Infineon Technologies Ag | Integrated circuit, has multiple partial circuits with substrate, and multiple multi-gate field-effect transistor power supply circuits that are electrically coupled with different voltage of selectable partial circuits |
DE102012213053A1 (en) | 2012-07-25 | 2014-01-30 | Robert Bosch Gmbh | Battery for use in motor car, has battery cell which is disengaged from one of the terminals, while lower terminal and upper terminal are conductively connected with each other in secondary switching position |
DE102012017673A1 (en) | 2012-09-07 | 2013-06-06 | Daimler Ag | Circuit device for coupling high voltage (HV) battery with vehicle network e.g. hybrid vehicle network, has power electronic switch that is connected in series with relay for power interruption between HV battery and vehicle network |
DE102014107287A1 (en) * | 2014-05-23 | 2015-11-26 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Device and method for bridging an electrical energy storage device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP2732295B1 (en) | Current measuring device | |
EP0582913B1 (en) | Switching device | |
DE102013218077A1 (en) | Battery cell device and method for determining a complex impedance of a battery cell arranged in a battery cell device | |
DE102015002061B4 (en) | Electrical busbar with sensor unit | |
DE102012209615A1 (en) | Battery condition reporting unit, busbar module, battery pack and battery condition monitoring system | |
DE102010028626A1 (en) | Electric charging device for an electric vehicle | |
DE102015114398A1 (en) | Thermal conditioning of a vehicle traction battery | |
DE112011101833T5 (en) | Inverter device | |
DE102013218081A1 (en) | Battery module device and method for determining a complex impedance of a battery module arranged in a battery module | |
DE102013111463B4 (en) | SWITCH ARRANGEMENTS AND BATTERY ARRANGEMENTS | |
DE102014221272A1 (en) | Monitoring device for a battery, a lithium-ion battery and method for monitoring a battery | |
US10850618B2 (en) | Connection module for an electrical energy storage device, and power supply system | |
DE102014200304A1 (en) | Battery pack with a plurality of electrochemical battery cells with a device for measuring a difference between two cell currents of two different battery cells | |
DE102017221857A1 (en) | Voltage Detection Structure and Voltage Detection Module | |
EP2865068B1 (en) | Batterymanagementsystem with improved robustness against negative voltages | |
WO2015090926A1 (en) | Method for monitoring a battery, evaluation device and measurement system | |
DE112018002844T5 (en) | PROTECTIVE DEVICE FOR ENERGY STORAGE DEVICE | |
DE102015200276A1 (en) | Device and method for discharging a battery cell and battery module Battery, battery system, vehicle, computer program and computer program product | |
DE102012215074A1 (en) | Battery e.g. lithium-ion battery used in e.g. motor vehicle, has securing device which secures several interconnected battery cells by separating battery cells from output terminals, when fault is occurred in output terminals | |
DE102015226641A1 (en) | Current limiting device | |
DE102015223088A1 (en) | Device for measuring high and medium high voltage currents | |
DE102017205612A1 (en) | Method for controlling a separator of an electrochemical energy store | |
DE102012210595A1 (en) | Battery cell for lithium-ion battery of e.g. hybrid vehicle, has switch integrated in battery sensor, controlled by sensor, and connected with electrical connection, where switch is actuated based on variables detected by sensor | |
DE102021004146A1 (en) | Method for operating a high-voltage system and high-voltage system | |
DE102020124737A1 (en) | Detection device, measuring arrangement, battery cell unit, motor vehicle and method for detecting a voltage |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
R163 | Identified publications notified | ||
R012 | Request for examination validly filed |