DE102015114583A1 - Process for the production of optoelectronic semiconductor chips and optoelectronic semiconductor chip - Google Patents

Abstract

The method for producing optoelectronic semiconductor chips (1) comprises the following steps in the stated sequence: A) providing a semiconductor layer sequence (2), B) applying an electrical second contact structure (33) to a side of the semiconductor layer sequence facing away from a growth substrate (20) ( 2), C) applying at least one electrical insulating layer (41, 42) to the second contact structure (33) and the semiconductor layer sequence (2), D) applying a first contact structure (31), so that the first contact structure (31) electrically with a E) applying a further electrical insulating layer (43) locally at least to the first contact structure (31), F) generating electrical contact surfaces (51, 53), so that with the step F) an extension of the contact surfaces (51, 53) in the direction away from the semiconductor layer sequence (2) with a he tolerance of maximum 5 microns is defined.

Description

A process for the production of optoelectronic semiconductor chips is specified. In addition, an optoelectronic semiconductor chip is specified.

An object to be solved is to provide a method with which a spatially compact and mechanically stable semiconductor chip can be produced.

This object is achieved inter alia by a method having the features of patent claim 1. Preferred developments are the subject of the other claims.

In accordance with at least one embodiment, the method produces optoelectronic semiconductor chips. The semiconductor chips are preferably processed in parallel in a composite, in particular still on a wafer. The finished semiconductor chips are, for example, light-emitting diodes, in short LEDs, or also laser diodes, in short LDs.

In accordance with at least one embodiment, the method comprises the step of providing a semiconductor layer sequence. The semiconductor layer sequence comprises at least one active zone which is set up to generate ultraviolet radiation, visible light and / or infrared radiation. In particular, the semiconductor chips are set up to produce visible light, such as blue light, during normal operation.

The semiconductor layer sequence is preferably based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material such as Al _n In _{1 nm} Ga _m N or a phosphide compound semiconductor material such as Al _n In _{1 nm} Ga _m P or an arsenide compound semiconductor material such as Al _n In _1-nm Ga _m As, where 0 ≦ n ≦ 1, 0 ≦ m ≦ 1 and n + m ≦ 1, respectively. In this case, the semiconductor layer sequence may have dopants and additional constituents. For the sake of simplicity, however, only the essential constituents of the crystal lattice of the semiconductor layer sequence, that is to say Al, As, Ga, In, N or P, are indicated, even if these may be partially replaced and / or supplemented by small amounts of further substances.

In accordance with at least one embodiment, the semiconductor layer sequence is provided on a growth substrate. The semiconductor layer sequence is produced in particular epitaxially on the growth substrate. Thus, the semiconductor layer sequence can be in direct contact with the growth substrate. The growth substrate is, for example, a semiconductor substrate such as a silicon substrate or a germanium substrate or a compound semiconductor substrate such as GaN, GaAs or GaP. Other materials such as SiC are also suitable for the growth substrate. However, the growth substrate is preferably sapphire.

In accordance with at least one embodiment, the method comprises the step of applying a second electrical contact structure. In this case, the second contact structure is applied to a side of the semiconductor layer sequence facing away from the growth substrate, preferably applied directly. The second contact structure preferably covers only a part of this side of the semiconductor layer sequence. The second contact structure is, in particular, a p-contact for current injection into a p-doped p-region of the semiconductor layer sequence. In this case, the second contact structure may have a plurality of partial layers.

In accordance with at least one embodiment, at least one electrical insulating layer is applied to the second contact structure and / or to the semiconductor layer sequence. It is possible that the insulating layer directly and completely covers the second contact structure and the semiconductor layer sequence.

In accordance with at least one embodiment, a first electrical contact structure is applied. The first contact structure is electrically connected to a region of the semiconductor layer sequence facing the growth substrate. In particular, the first contact structure is an n-contact, so that electrical current is impressed into an n-type n-region of the semiconductor layer sequence via the first contact structure. The first contact structure can also be composed of several partial layers. Like the second contact structure, the first contact structure is preferably in direct physical and electrical contact with the semiconductor layer sequence.

In accordance with at least one embodiment, at least one further electrical insulating layer is applied in places at least to the first contact structure and optionally also to regions of the semiconductor layer sequence. It is possible that the further insulating layer is first applied over the entire surface and subsequently removed in places again.

In accordance with at least one embodiment, the method comprises the step of generating electrical contact surfaces. The electrical contact surfaces are set up for external electrical contacting of the finished semiconductor chips. In particular, stand the electrical Contact surfaces in direct electrical contact with the respective associated electrical contact structure.

According to at least one embodiment, with the generation of the electrical contact surfaces, an expansion of the contact surfaces themselves and of the finished semiconductor chip in the direction away from the semiconductor layer sequence is defined, in particular with a tolerance of at most 5 μm or 0.5 μm or 0.1 μm or exactly. After the contact areas have been generated, an expansion of the contact areas and / or of the semiconductor chip, calculated from the active zone up to a boundary surface of the electrical contact areas facing away from the active zone, preferably no longer changes. In particular, only additional material is applied during the production of the contact surfaces, and later no material is removed from the contact surfaces.

According to at least one embodiment, the contact structures, optionally together with the contact surfaces, contribute to a mechanical stability of the finished semiconductor chip of at least 30% or 60% or 80% or 90%. The contribution to the mechanical stability can be determined, for example, by a determination of the individual materials and their layer thicknesses and a subsequent simulation calculation. In other words, the contact structures and the contact surfaces taken together represent a substantial, in particular the decisive part of a mechanical stabilization of the semiconductor chips. This makes it possible that an additional carrier can be omitted or that the additional carrier serves only for a further stabilization, but not the is the decisive stability-giving component of the semiconductor chip. As a result, the semiconductor chip can be realized in a compact design. In addition, an efficient removal of waste heat via the contact structures and the contact surfaces is possible.

• A) Bereitstellen einer Halbleiterschichtenfolge zur Lichterzeugung auf einem Aufwachssubstrat,
• B) Aufbringen einer elektrischen zweiten Kontaktstruktur auf eine dem Aufwachssubstrat abgewandte Seite der Halbleiterschichtenfolge,
• C) Aufbringen mindestens einer elektrischen Isolierschicht auf die zweite Kontaktstruktur und auf die Halbleiterschichtenfolge,
• D) Aufbringen einer elektrischen ersten Kontaktstruktur, sodass die erste Kontaktstruktur elektrisch mit einem dem Aufwachssubstrat abgewandten Bereich der Halbleiterschichtenfolge verbunden wird,
• E) Aufbringen einer weiteren elektrischen Isolierschicht stellenweise zumindest auf die erste Kontaktstruktur, und
• F) Erzeugen von elektrischen Kontaktflächen zur externen elektrischen Kontaktierung der fertigen Halbleiterchips, sodass mit dem Schritt F) eine Ausdehnung der Kontaktflächen und bevorzugt auch der fertigen Halbleiterchips in Richtung weg von der Halbleiterschichtenfolge definiert wird, mit einer Toleranz von höchsten 5 µm. Besonders geht hierbei eine mechanische Stabilität der fertigen Halbleiterchips zu mindestens 60% auf die Kontaktstrukturen zusammen mit den Kontaktflächen zurück.

In at least one embodiment, the method for producing optoelectronic semiconductor chips is set up and comprises the following steps, preferably in the order indicated:

• A) providing a semiconductor layer sequence for generating light on a growth substrate,
• B) applying an electrical second contact structure to a side of the semiconductor layer sequence facing away from the growth substrate,
• C) applying at least one electrical insulating layer to the second contact structure and to the semiconductor layer sequence,
• D) applying an electrical first contact structure such that the first contact structure is electrically connected to a region of the semiconductor layer sequence facing away from the growth substrate,
• E) applying a further electrical insulating layer in places, at least on the first contact structure, and
• F) generating electrical contact surfaces for the external electrical contacting of the finished semiconductor chips, so that an expansion of the contact surfaces and preferably also of the finished semiconductor chips in the direction away from the semiconductor layer sequence is defined with the step F), with a tolerance of the highest 5 microns. In particular, at least 60% of the mechanical stability of the finished semiconductor chips is attributable to the contact structures together with the contact surfaces.

In the case of semiconductor chips, in particular with light-emitting diode chips which are free of a growth substrate, mechanical stability is typically ensured by a further carrier. Such a carrier is applied, for example, by injection molding, also known as molding. In this case, back electrical contact surfaces are usually covered by a material for the carrier. The electrical contact surfaces are subsequently exposed by a back grinding of the shaped as a potting body carrier. Thus, one or more additional process steps are required to define in particular solderable contact surfaces. In the method described here, however, such a back grinding of the carrier is dispensable, since a thickness of the semiconductor chips is already defined with the generation of the electrical contact surfaces.

In accordance with at least one embodiment, the electrical contact surfaces are applied with the desired thickness present in the finished semiconductor chip. Thus, subsequently no material of the electrical contact surfaces must be removed. In this case, the contact surfaces are preferably also surmounted by no further component of the finished semiconductor chip, in the direction away from the semiconductor layer sequence.

In accordance with at least one embodiment, the contact surfaces have a smaller average thickness than the electrical contact structures. In other words, it may be the case that the decisive mechanically stabilizing component of the finished semiconductor chips is formed by the electrical contact structures, in particular by the first electrical contact structure. For example, the first contact structure is at least a factor of 1.5 or 3 or 5 thicker than the contact surfaces.

In accordance with at least one embodiment, the electrical contact surfaces have a greater average thickness than the electrical contact structures. This mechanical stabilization is essentially given by the contact surfaces. In this Case, the average thickness of the contact surfaces, for example, by at least a factor of 1.5 or 3 or 5 or 10 over the average thickness of the contact structures, in particular the first contact structure.

In accordance with at least one embodiment, step C) comprises the substep of applying a first insulating layer to the second contact structure. The insulating layer is preferably applied directly to the second contact structure. Furthermore, the first insulating layer preferably also covers the semiconductor layer sequence in all the areas that are not covered by the second contact structure. The first insulating layer may in turn be composed of a plurality of directly successive partial layers, for example of silicon dioxide and / or silicon nitride. It is likewise possible for the first insulating layer to be a layer applied by means of atomic layer deposition, or ALD for short. In this case, the first insulating layer is made of about alumina.

In accordance with at least one embodiment, step C) comprises a partial step in which at least one side of the semiconductor layer sequence facing away from the growth substrate is patterned. In particular, the p-type p-region of the semiconductor layer sequence is locally removed during patterning. This structuring defines the later semiconductor chips. Likewise, structuring preferably produces contact regions for an n-contact, so that the n-conducting n-region of the semiconductor layer sequence is exposed in places. In particular, this step of structuring takes place after the application of the first insulating layer.

In accordance with at least one embodiment, step C) comprises a substep in which a second insulating layer is applied. In this case, the second insulating layer preferably completely covers the semiconductor layer sequence together with the second contact structure. The second insulating layer is applied in particular after a structuring of the semiconductor layer sequence has been carried out. After the full-surface application of the second insulating layer, the second insulating layer in the region of the n-contact is locally removed again. In other words, the second insulating layer then completely covers the second contact structure and the semiconductor layer sequence only partially.

According to at least one embodiment, at least one of the contact surfaces or both contact surfaces by plating, by physical vapor deposition, short PVD, by chemical vapor deposition, short CVD, by electroless plating, also referred to as electroless plating, by setting solder balls, English solder balls , caused by the doctoring of a solder paste, by printing with an ink or by the application of an anisotropically conductive adhesive film. The contact surfaces are preferably formed by one or more of the following materials, in particular if at least one contact surface is produced by electroplating in combination with electroless plating: TiAu, PtAu, PdAu, AuSn, NiAu, CuSnAg, SnPb.

In accordance with at least one embodiment, step D) comprises the application of a first partial layer of the first contact structure. The first sub-layer is preferably located directly at the n-type n-region of the semiconductor layer sequence. For example, the first sub-layer includes or consists of ZnO and / or Ag.

In accordance with at least one embodiment, step D) comprises the sub-step of applying a second partial layer of the first contact structure. The second partial layer is applied in particular directly to the first partial layer. A thickness of the second sub-layer may be greater than a thickness of the first sub-layer, for example by at least a factor of 2 or 5. For example, the second sub-layer comprises or consists of nickel and / or copper.

In accordance with at least one embodiment, the second contact structure remains partially free of the partial layers of the first contact structure. This makes it possible for the second contact structure to be electrically contactable through the first contact structure, in particular by means of the electrical contact surfaces.

In accordance with at least one embodiment, step D) comprises the partial exposure of the second contact structure. In particular, the second contact structure is exposed by removing the electrical insulating layer or layers applied in step C). This step of exposing the second contact structure preferably takes place after the first contact structure and / or all sub-layers of the first contact structure have been generated.

In accordance with at least one embodiment, a region in which the first sub-layer directly adjoins the n-region is located in a center of the semiconductor layer sequence. In particular, this area is located centrally in the semiconductor layer sequence, calculated per semiconductor chip and seen in plan view. This area is surrounded all around by the p-type p-region of the semiconductor layer sequence and / or by the second contact structure. In other words, a current injection takes place in the n-type n region of the semiconductor layer sequence only via this region in the center of the semiconductor layer sequence.

In accordance with at least one embodiment, in the finished semiconductor chip, the first contact structure and the two electrical contact surfaces in the direction away from the semiconductor layer sequence are located at least partially over the second contact structure. In this case, the contact surfaces, in the direction away from the semiconductor layer sequence, preferably follow the first contact structure. In other words, the first contact structure then lies in places between the contact surfaces and the second contact structure.

In accordance with at least one embodiment, the contact surfaces are in each case in direct contact with the associated contact structure. An n-contact surface thus contacts the n-contact structure and a p-contact surface contacts only the p-contact structure. Preferably, an electrically insulating layer is located in places between the corresponding contact surface and the associated contact structure.

In accordance with at least one embodiment, all contact surfaces are made of the same material or of the same materials. Likewise, the contact surfaces are preferably produced simultaneously with the same method and also in the same method step.

In accordance with at least one embodiment, the contact surfaces each have a first partial layer. The first part-layer is produced, for example, by electroplating. Likewise, the contact surfaces each have a second sub-layer. The second sub-layer is preferably made of a solder or forms an intended for a solder contact interface. In other words, the second sub-layer is solderable or contactable by means of a solder as intended. The partial layers of the contact surfaces can be applied in directly successive process steps. Alternatively, it is possible that further method steps are carried out between the application of the partial layers.

In accordance with at least one embodiment, the first part-layer of the contact surfaces has a greater thickness than the second part-layer. For example, the thickness of the first partial layer exceeds that of the second partial layer by at least a factor of 5 or 10 or 100 or 1000.

In accordance with at least one embodiment, the contact surfaces in step F) are structured such that the contact surfaces, seen in plan view, are interlocked with one another. That is, the contact surfaces are not simply rectangular in shape, seen in plan view, but for example fork-like, with tines interlock. As a result, an improved mechanical stabilization of the semiconductor chip through the contact surfaces can be achieved. Likewise, it is possible for one of the contact surfaces to partially or completely circulate in the manner of a frame like another of the contact surfaces in plan view.

In accordance with at least one embodiment, the two contact structures each have a layer or partial layer that is reflective for the light generated during operation of the semiconductor chips. A reflectivity of the contact structures for the light generated during operation is, for example, at least 80% or 90% or 95%. In particular, the contact structures for this purpose include a metal mirror, such as silver or aluminum.

In accordance with at least one embodiment, the contact structures each have at least one partial layer consisting of a metal or a metal alloy. Optionally, the contact layers may also include a layer formed of a transparent conductive oxide such as zinc oxide or indium tin oxide. Preferably, the contact structures consist entirely of metals and optionally additionally of transparent conductive oxides.

In accordance with at least one embodiment, the first contact structure in step D) is applied completely to outer side surfaces of the semiconductor layer sequence. In other words, the side surfaces of the semiconductor layer sequence can be completely and completely covered by the first contact structure. Thus, it can be achieved that no light emerges from the semiconductor layer sequence on the side surfaces.

In accordance with at least one embodiment, the method comprises a step G). In step G), the growth substrate is removed from the semiconductor layer sequence, preferably completely removed. This removal takes place, for example, with a laser lifting method, English laser lift off or LLO for short. Alternatively, the growth substrate can be removed by etching or mechanical material removal.

According to at least one embodiment, a roughening is produced on a main radiation side of the semiconductor layer sequence, which is preferably remote from the contact surfaces. Over the roughening an improved light extraction from the semiconductor layer sequence out can be achieved.

In accordance with at least one embodiment, step G) follows step F). In particular, it is possible that no further method steps are carried out between steps G) and F).

In accordance with at least one embodiment, in a step H) at least one phosphor is attached to the semiconductor layer sequence. The at least one phosphor can be directly on the roughening and / or the main radiation side are applied. The phosphor may be present in pure form or embedded in a matrix material. The light generated during operation of the semiconductor layer sequence is partially or completely converted into light of another, preferably longer wavelength via the phosphor. For example, the semiconductor layer sequence generates blue light and green, yellow and / or red light is generated via the phosphor, so that the semiconductor chip as a whole emits white light.

According to at least one embodiment, step H) follows step G). Alternatively, it is possible that step G) precedes step H).

In accordance with at least one embodiment, the finished semiconductor chips are free of a plastic. This can mean that the semiconductor chips have no potting body. It is thus possible for the semiconductor chips to consist of semiconducting materials, of metals, of glasses and / or of ceramics. In other words, the finished semiconductor chip may be free of organic matter.

In accordance with at least one embodiment, the method has a step I). In step I), a potting body is produced. In particular, the potting body is formed from at least one plastic or comprises at least one plastic. For example, the potting body is made of a paint, an epoxy or a silicone. The potting body can have additional components, for example light-scattering, light-absorbing or heat-conducting particles. Likewise, a thermal expansion coefficient of the potting body can be adjusted via such additives. Preferably, the potting body is opaque.

In accordance with at least one embodiment, the potting body is in direct contact with the contact surfaces. In particular, the contact surfaces are surrounded all around by the potting body, seen in plan view. Alternatively or additionally, the potting body can be in direct contact with the further insulating layer, which is applied in step E).

In accordance with at least one embodiment, the potting body is spaced apart from the semiconductor layer sequence and the contact structures. In other words, the potting body and the semiconductor layer sequence as well as the potting body and the contact structures do not touch.

According to at least one embodiment, the potting body in step I) is applied in a highly fluid state. For example, thin liquid means that a viscosity of the potting body during application is less than 100 Pa · s or 10 Pa · s or 1 Pa · s or 0.2 Pa · s. After application of the potting body in a highly fluid state, the potting body is cured. This can be done thermally or photochemically or by the evaporation of a solvent.

According to at least one embodiment, a surface of the potting body adjusts immediately after application due to the action of gravity. The surface of the potting body is then aligned in particular horizontally. This does not necessarily exclude the possibility of locally forming menisci on the edges, which are the result of wettability and / or surface tension. Preferably, however, the surface of the potting body is not or not significantly influenced by effects due to surface tensions.

In accordance with at least one embodiment, the contact surfaces project beyond the potting body. This means, for example, that the semiconductor layer sequence facing away from the boundary surfaces of the contact surfaces are completely free of a material of the potting. For example, the contact surfaces are at least 2 μm or 5 μm and / or at most 20 μm or 15 μm or 10 μm or 6 μm over the potting body. Alternatively, it is possible for the contact surfaces and the potting body to terminate flush with one another, in the direction away from the semiconductor layer sequence. Furthermore, alternatively, it is possible that the contact surfaces are slightly surmounted by the potting body, for example by at most 4 microns or 2 microns or 0.5 microns.

In accordance with at least one embodiment, step I) precedes step G). That is, the growth substrate is removed prior to creating the potting body. Alternatively, the potting body is created before the growth substrate is removed. The creation of the potting body can be done before or after the attachment of the phosphor.

In accordance with at least one embodiment, the semiconductor layer sequence has approximately the same lateral extent as the entire finished semiconductor chip. By way of example, the lateral extent of the semiconductor layer sequence is at least 80% or 90% or 95% or 98% of the lateral extent of the finished semiconductor chips.

In accordance with at least one embodiment, the finished semiconductor chip has only a small overall thickness. The total thickness is in particular at least 5 .mu.m or 10 .mu.m or 15 .mu.m and / or at most 50 .mu.m or 30 .mu.m or 20 .mu.m. In this case, the semiconductor chip is preferably self-supporting and mechanically rigid. In this case, a mean edge length of the semiconductor chip, seen in plan view, at least 0.9 mm or 0.5 mm or 0.3 mm and / or at most 2.5 mm or 1.5 mm or 0.8 mm.

In addition, an optoelectronic semiconductor chip is specified. The semiconductor chip is preferably made by a method as recited in connection with one or more of the above embodiments. Features of the method are therefore also disclosed for the semiconductor chip and vice versa.

Hereinafter, a method described herein and a semiconductor chip described herein with reference to the drawings using exemplary embodiments will be explained in more detail. The same reference numerals indicate the same elements in the individual figures. However, there are no scale relationships shown, but individual elements can be shown exaggerated for better understanding.

Show it:

1 to 5 schematic sectional views of method steps of manufacturing method according to the invention for optoelectronic semiconductor chips described here, with the exception of the schematic plan view in 1C , and

6 schematic sectional views of embodiments of optoelectronic semiconductor chips described herein.

In 1 schematically is a manufacturing method for an optoelectronic semiconductor chip 1 shown. In the 1 and 2 is to simplify the presentation ever a single semiconductor chip 1 illustrated. The method is preferred in the wafer composite for a multiplicity of semiconductor chips 1 carried out simultaneously.

According to 1A becomes a semiconductor layer sequence 2 provided, based for example on the AlInGaN material system. The semiconductor layer sequence 2 becomes epitaxially on a growth substrate 20 generated. In the growth substrate 20 it is preferably a sapphire substrate. Directly on the growth substrate 20 there is an n-area 21 made of n-type semiconductor material. At one of the growth substrate 20 remote side of the semiconductor layer sequence 2 there is a p-area 23 from a p-type semiconductor material. Between the two areas 21 . 23 there is an active zone 22 in the operation of the finished semiconductor chip 1 is generated via electroluminescence radiation.

In the process step of 1B is in places on the p-range 23 a second contact structure 33 applied. The second contact structure 33 is located directly on the p-area 23 and is for current injection in the p-range 23 intended.

Optionally, the second contact structure comprises 33 several sublayers. A first sub-layer 33a directly at the p-area 23 is for example made of silver or zinc oxide. A second sub-layer 33b is in particular a layer or layer sequence of platinum, titanium, gold. Between the two sublayers 33a . 33b may have an optional barrier layer 33c located, for example, zinc oxide and / or platinum. The sublayers 33a . 33b . 33c follow each other directly.

Furthermore, according to 1B over the entire surface of the semiconductor layer sequence 2 and thus on the second contact structure 33 an electrically insulating first insulating layer 41 applied. For example, the first insulating layer 41 formed of layers of silicon dioxide and silicon nitride and has a thickness of about 200 nm. Alternatively, the first insulating layer may be 41 is an aluminum oxide layer produced via atomic layer deposition, for example with a thickness of approximately 40 nm.

The sectional views are preferably a section through a center of the semiconductor chip 1 , compare 1C , The cutting plane is in 1C symbolized by a dashed line. The second contact structure 33 thus surrounds a frame-shaped area, which is intended for a n-contact. The area as well as the second contact structure 33 could be seen in plan view square or rectangular shaped.

According to the method step of 1D becomes the semiconductor layer sequence 2 structured. Here, the p-range 23 as well as the active zone 22 removed in places, so that in some areas the n-range 21 is exposed. This creates side surfaces 25 ,

Further, a second electrical insulating layer 42 produced, for example, from a stack of silicon nitride layers and silicon dioxide layers. The second insulating layer 42 has, for example, a thickness of about 400 nm. Preferably, the second insulating layer covers 42 all areas, except for the area centered in the second contact structure 33 for the n-contact.

Furthermore, a first partial layer 31a for a first contact structure 31 applied. The first sub-layer 31a is preferably formed from zinc oxide and / or silver. Like the second contact structure 33 is the first contact structure 31 preferred as Mirror for those in the active zone 22 generated radiation formed. The first sub-layer 31a the first contact structure 31 covers the second contact structure 33 only partially, seen in plan view. In the n-contact area, the first sub-layer contacts 31a the n-range 21 ,

In the process step of 1E is on the first sub-layer 31a a second sub-layer 31b applied, in particular galvanic. At the second sub-layer 31b it is preferably a nickel layer. The in 1E right area of the second contact structure 33 gets completely from the first contact structure 31 covered. On the in 1E left area of the second contact structure 33 becomes the second sublayer 31b only partially applied, wherein the second sub-layer 31b a larger share of this second contact structure 33 covered as the first sublayer 31a ,

A thickness of the semiconductor layer sequence 2 is for example at least 3 microns and / or at most 10 microns. The insulating layers 41 . 42 each have a small thickness of preferably at most 0.5 microns or 0.2 microns. A total thickness of the second contact structure 33 is preferably also comparatively low and is for example at least 100 nm or 200 nm and / or at most 1 .mu.m or 500 nm or 200 nm. The first contact structure and in this case in particular the second part layer 31b has a relatively large thickness, in particular at least 1 micron or 3 microns or 6 microns and / or at most 50 microns or 20 microns or 10 microns. The second sub-layer 31b preferably represents the finished semiconductor chip 1 most mechanically stabilizing component.

In the process step of 1F become the insulating layers 41 . 42 partially removed, leaving the second contact structure 33 partially exposed.

In the subsequent process step, see 1G , becomes a third electrical insulating layer 43 applied, for example of silicon dioxide and, for example, with a thickness of less than 250 nm. Of the other, third insulating layer 43 stays in the 1F exposed second contact structure 33 also free. Furthermore, in the area above the in 1G right second contact structure 33 an opening in the third insulating layer 43 available.

Over these two openings of the third insulating layer 43 become electrical contact surfaces 51 . 53 generated. About the contact surfaces 51 . 53 is the finished semiconductor chip 1 externally electrically contactable. The contact layers 51 . 53 close in the direction away from the semiconductor layer sequence 2 flush with each other. This makes it possible to achieve that the semiconductor chip 1 is surface mountable. An average thickness of the contact surfaces 51 . 53 in total, for example, is at least 0.5 microns or 2 microns and / or at most 100 microns or 40 microns or 10 microns.

Optionally have the contact surfaces 51 . 53 in each case at least two partial layers. First sublayers 51a . 53a are for example made of nickel or of nickel and gold. These sublayers 51a . 53a preferably have a relatively large thickness. This is followed by second sub-layers 51b . 53b For example, from AuPd or from a lot. About the second sublayers 51b . 53b is the finished semiconductor chip 1 attachable via soldering.

According to the method step of 1H becomes the growth substrate 20 removed, leaving a main radiation side 26 the semiconductor layer sequence 2 results. In the main radiation side 26 will be below, see 1I , a roughening 27 generated.

The following will be, see 1y , on the main radiation side 26 and optionally on side surfaces of the n-region 21 a phosphor 6 appropriate. One of the contact surfaces 51 . 53 opposite side of the phosphor 6 can be designed just.

In particular, by the comparatively thick second sub-layer 31b the first contact structure 31 and by the metallic, preferably also comparatively thick contact surfaces 51 . 53 is a mechanical stabilization of the semiconductor chip 1 achievable. Thus, a potting body for mechanical stabilization of the semiconductor chip 1 dispensable. Likewise, the contact surfaces 51 . 53 applied with a thickness such that a target thickness is achieved. As a result, a subsequent thinning, such as in connection with a photographic technique and a separate application of the contact surfaces, not required. Likewise, an extremely small total thickness of the semiconductor chip 1 of for example at most 20 microns feasible.

In 2 a further embodiment of the manufacturing method is illustrated. Deviating from 1 , see in particular 1D , is used in this method in structuring the semiconductor layer sequence 2 also the n-range 21 structured, see 2C , The n-range remains 21 preferably with a small thickness of, for example, at most 2 μm or 0.5 μm in a region laterally adjacent to the p-region 23 , This area is the n-range 21 between the growth substrate 20 and the second insulating layer 42 ,

The process steps of 2D to 2G are preferably carried out analogously to 1 , When creating the roughening, see 2H , becomes the n-range 21 preferably from the second insulating layer 42 away. On the side surfaces 25 close the n-range 21 and the p-range 23 flush with each other around. The side surfaces 25 are thus completely around the second insulating layer 42 and the first contact structure 31 covered. Because the first contact structure 31 is impermeable to the generated light, no light passes laterally from the semiconductor layer sequence 2 out.

Analogous to 1y is finally according to 2I the phosphor 6 applied. At a peripheral outer edge of the phosphor 6 directly on the second insulating layer 42 be upset.

The first contact structure 31 forms according to 2 in other words, a tub, at the bottom of which the contact surfaces 51 . 53 are located. In a center of this tub, a column is formed, which leads to the n-range 21 enough. Seen in cross section, the first contact structure 31 thus E-shaped, with the legs of the E towards the semiconductor layer sequence 2 point.

In the embodiment of the method of 3 are each two units for the semiconductor chips 1 drawn side by side. These units are symbolically separated by a dash-and-dot line. The process steps of 3A to 3C take place analogously to the method steps of 1A to 1I , Unlike in 3 can also be the method according to the 2A to 2H be used.

In the process step of 3D becomes a potting body 7 made of a plastic. Deviating from the illustration, the processing can also be carried out on an auxiliary carrier in the form of a film or in the form of a film in conjunction with a hard carrier. Is the first contact structure 31 in conjunction with the contact surfaces 51 . 53 already mechanically stable enough, it can be dispensed with on a subcarrier.

A material for the potting body 7 is poured, for example, and then cured. This makes it possible to achieve that the contact surfaces 51 . 53 in the direction away from the semiconductor layer sequence 2 flush with the potting body 7 conclude or, preferably, from the potting body 7 protrude.

Unlike shown in the figures, it is also possible that the second sub-layers 51b . 53b the contact surfaces 51 . 53 only after the production of the potting body 7 on the first sublayers 51a . 53a be applied. In this case, the potting closes 7 preferably flush with the first partial layers 51a . 53a with a tolerance of at most 2 μm, and the second partial layers 51b . 53b protrude from the potting body 7 out. It is therefore not absolutely necessary that the production of the entire contact surfaces 51 . 53 in a single, coherent process step.

In the process step of 3E becomes the phosphor 6 Applied, compare the 1y and 2I , Then a singulation takes place, see 3F by sawing or laser treatment.

In the process of 4 becomes, deviating from 3 , the luminescent material 6 in front of the potting body 7 appropriate.

In the procedure, as in 5 illustrated, the potting body 7 before detaching the growth substrate 20 shaped, see 5A , The remaining process steps, see the 5B to 5D , are analogous to the 3 and 4 ,

In 6 are further embodiments of the semiconductor chip 1 shown. According to 1A dominates the potting 7 the contact surfaces 51 . 53 slightly, in the direction away from the semiconductor layer sequence 2 , A degree of coverage and a coverage thickness of the contact surfaces 51 . 53 with the potting body 7 preferably result exclusively from a wettability of the contact surfaces 51 . 53 and due to surface tension effects in creating the potting body 7 out of a liquid phase. A thickness of the potting body 7 on the contact surfaces 51 . 53 is then for example at most 5 microns or 1 micron.

In the embodiment of 6B is the potting body 7 relatively thin, so the contact surfaces 51 . 53 from the casting 7 protrude. In 6C it is shown that no phosphor is present.

Also in all embodiments with a potting 7 is it possible for the entire side surfaces 25 the semiconductor layer sequence 2 from the first contact structure 31 are covered, see 6D , Here, the phosphor 6 also be omitted. Unlike in 6D shown, the potting body 7 over the contact surfaces 51 . 53 protrude or vice versa.

The invention described here is not limited by the description based on the embodiments. Rather, the invention encompasses any novel feature as well as any combination of features, including in particular any combination of features in the claims, even if this feature or combination itself is not explicitly stated in the patent claims or exemplary embodiments.

LIST OF REFERENCE NUMBERS

1

 optoelectronic semiconductor chip

2

 Semiconductor layer sequence

20

 growth substrate

21

 n-region

22

 active zone

23

 p-type region

25

 side surface

26

 Radiation main page

27

 roughening

31

 first electrical contact structure for the n-region

33

 second electrical contact structure for the p-region

41

 first electrical insulating layer

42

 second electrical insulating layer

43

 third electrical insulating layer

51

 first electrical contact surface for the n-region

53

 second electrical contact surface for the p-region

6

 fluorescent

7

 potting

Claims (16)

Method for producing optoelectronic semiconductor chips ( 1 ) comprising the following steps in the order given: A) providing a semiconductor layer sequence ( 2 ) for generating light on a growth substrate ( 20 ), B) applying an electrical second contact structure ( 33 ) on a growth substrate ( 20 ) side facing away from the semiconductor layer sequence ( 2 C) applying at least one electrical insulating layer ( 41 . 42 ) to the second contact structure ( 33 ) and on the semiconductor layer sequence ( 2 ), D) application of an electrical first contact structure ( 31 ), so that the first contact structure ( 31 ) electrically with a growth substrate ( 20 ) facing area ( 21 ) of the semiconductor layer sequence ( 2 E) applying a further electrical insulating layer ( 43 ) at least to the first contact structure ( 31 ), and F) generating electrical contact surfaces ( 51 . 53 ) for external electrical contacting of the finished semiconductor chips ( 1 ), so that with the step F) an expansion of the contact surfaces ( 51 . 53 ) in the direction away from the semiconductor layer sequence ( 2 ) is defined with a tolerance of the highest 5 μm. Method according to the preceding claim, in which the electrical contact surfaces ( 51 . 53 ) are applied in the desired thickness, so that subsequently no material of the electrical contact surfaces ( 51 . 53 ), the electrical contact surfaces ( 51 . 53 ) have a smaller average thickness than the electrical contact structures ( 31 . 33 ), wherein with step F) an expansion of both the contact surfaces ( 51 . 53 ) as well as the finished semiconductor chips ( 1 ) in the direction away from the semiconductor layer sequence ( 2 ) is defined exactly, with a mechanical stability of the finished semiconductor chips ( 1 ) at least 60% on the contact structures ( 31 . 33 ) together with the contact surfaces ( 51 . 53 ) goes back. Method according to one of the preceding claims, in which step C) comprises the following substeps, in the order indicated: C1) application of a first insulating layer ( 41 ), the second contact structure ( 33 ) and the semiconductor layer sequence ( 2 completely covered, C2) structuring at least one of the growth substrate ( 20 ) remote area ( 23 ) of the semiconductor layer sequence ( 2 ), and C3) applying a second insulating layer ( 43 ), the second contact structure ( 33 ) completely and the semiconductor layer sequence ( 2 partially covered. Method according to one of the preceding claims, in which step D) comprises the following substeps, in the order given: D1) application of a first part-layer ( 31a ) with or from ZnO and / or Ag directly at an n-region ( 21 ) of the semiconductor layer sequence ( 2 ), D2) application of a thicker second partial layer ( 31b ) with or from Ni and / or Cu directly onto the first partial layer ( 31a ), wherein the second contact structure ( 33 ) remains partially free of the sublayers ( 31a . 31b ), and D3) exposing the second contact structure ( 33 ), where seen in plan view an area in which the first sub-layer ( 31a ) directly to the n-area ( 21 ) borders, in the middle in the semiconductor layer sequence ( 2 ) and this area around the second contact structure ( 31 ) is surrounded. Method according to one of the preceding claims, in which in the finished semiconductor chips ( 1 ) the first contact structure ( 31 ) and the two contact surfaces ( 51 . 53 ) in the direction away from the semiconductor layer sequence ( 2 ) at least in part over the second contact structure ( 33 ), the contact surfaces ( 51 . 53 ) in each case in direct contact with the associated contact structure ( 31 . 33 ), and wherein the contact surfaces ( 51 . 53 ) are made of the same materials and each have a thicker first sublayer ( 51a . 53a ), which is produced by electroplating, and in each case a thinner second partial layer ( 51a . 51b ), which is made of a solder or provided for a solder contact material. Method according to one of the preceding claims, in which the contact surfaces ( 51 . 53 ) in step F) are structured so that they are interlocked seen in plan view. Method according to one of the preceding claims, wherein the two contact structures ( 31 . 33 ) for the operation of the finished semiconductor chips ( 1 ) have a reflectivity of at least 90%, the contact structures ( 31 . 33 ) each comprise a sub-layer consisting of a metal or metal alloy and consist overall of metals and optionally of transparent conductive oxides. Method according to one of the preceding claims, in which the first contact structure ( 31 ) in step D) completely on external side surfaces ( 25 ) of the semiconductor layer sequence ( 2 ) is applied so that on the side surfaces ( 25 ) no light from the semiconductor layer sequence ( 2 ) can emerge. Method according to one of the preceding claims, in which, in a step G), the growth substrate ( 20 ) of the semiconductor layer sequence ( 2 ) and on the side where the growth substrate was located, a roughening ( 27 ) is generated to improve a light extraction, wherein step G) follows step F). Process according to the preceding claim, in which in a step H) at least one phosphor ( 6 ) directly on the semiconductor layer sequence ( 2 ), step H) following step G). Method according to one of the preceding claims, in which the finished semiconductor chips ( 1 ) are free of a plastic. Method according to one of claims 1 to 10, further comprising step I), wherein in step I) a potting body ( 7 ) which is in direct contact with the contact surfaces ( 51 . 53 ) and to the further insulating layer ( 43 ), wherein the potting body ( 7 ) is opaque, is made of a plastic and of the semiconductor layer sequence ( 2 ) as well as the contact structures ( 31 . 33 ) is spaced. Method according to the preceding claim, in which the potting body ( 7 ) is applied in a thin liquid state in step I), wherein a surface of the potting body ( 7 ) due to gravity, so that the contact surfaces ( 51 . 53 ) the potting body ( 7 protrude, and wherein subsequently the potting body ( 7 ) is cured. Method according to one of claims 12 or 13 and according to claim 10, wherein step G) precedes step I). Method according to one of the preceding claims, in which - the semiconductor layer sequence ( 2 ) has a thickness of between 3 microns and 10 microns, - the first contact structure ( 31 ) is produced with an average thickness of between 3 μm and 50 μm, and this thickness remains unchanged, - the insulating layers ( 41 . 42 . 43 ) each have a thickness of at most 0.5 μm, - the contact surfaces ( 51 . 53 ) are each produced with an average thickness of between 0.5 microns and 100 microns, - a total thickness of the finished semiconductor chip ( 1 ) is at least 10 microns and at most 30 microns, and - a lateral extent of the semiconductor layer sequence ( 1 ) in the finished semiconductor chips ( 1 ) at least 90% of a total lateral extent of the semiconductor chips ( 1 ) lies. Optoelectronic semiconductor chip ( 1 ) with - a semiconductor layer sequence ( 2 ) for light generation with an n-region ( 21 ), a p-domain ( 23 ) and an intermediate active zone ( 22 ), - an electrical second contact structure ( 33 ) locally and directly on the p-region ( 22 ), - an electrical insulating layer ( 41 . 42 ) in places and directly on the second contact structure ( 33 ) and on the semiconductor layer sequence ( 2 ), - an electrical first contact structure ( 31 ), which is electrically connected directly to the n-region and through the second contact structure ( 33 ) and the p-region ( 23 ) and the n-range ( 21 ) does not penetrate, - another electrical insulating layer ( 43 ) in places and directly on the first contact structure ( 31 ), and - electrical contact surfaces ( 51 . 53 ) for external electrical contacting of the semiconductor chip ( 1 ), which are free of traces of material removal, wherein the semiconductor chip ( 1 ) is free from a growth substrate ( 20 ) of the semiconductor layer sequence ( 2 ) and a mechanical stability of the semiconductor chip ( 1 ) at least 60% on the contact structures ( 31 . 33 ) together with the contact surfaces ( 51 . 53 ) goes back.

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